JP6425532B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6425532B2 JP6425532B2 JP2014255608A JP2014255608A JP6425532B2 JP 6425532 B2 JP6425532 B2 JP 6425532B2 JP 2014255608 A JP2014255608 A JP 2014255608A JP 2014255608 A JP2014255608 A JP 2014255608A JP 6425532 B2 JP6425532 B2 JP 6425532B2
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Description
本実施の形態1および以下の実施の形態の半導体装置(半導体集積回路装置)は、例えば複数の半導体素子と、複数の半導体素子の上部に形成された複数層の配線(多層配線)と、複数層の内の最上層の配線に接続された複数の再配線を有する半導体チップを有し、複数の半導体素子を前記多層配線および複数の再配線により接続して構成される。
図1は、半導体装置の回路ブロック図である。図1に示すように、半導体装置は、例えば半導体チップ1Aのデバイス面に形成された入出力(I/O)回路、アナログ回路、CMIS−ロジック回路、パワーMIS回路、およびメモリ回路を備え、半導体装置を構成している。
以下に、本実施の形態1の半導体装置の主な特徴を説明する。
次に、本実施の形態1の半導体装置の製造方法について説明するが、本実施の形態1の特徴である再配線の製造方法を中心に説明する。再配線の製造方法は、図4に示した断面に対応している。
以下に、本実施の形態1の半導体装置の製造方法の主な特徴を説明する。
実施の形態2は、実施の形態1の側壁バリア膜11aの構造および製法に関する変形例である。実施の形態1と異なる部分に異なる符号を付して説明をする。同様の符号を付した部分は実施の形態1と同様である。実施の形態1と区別するために、本実施の形態2では、半導体チップ1Bとした。
実施の形態3は、実施の形態1の下地金属膜UM、側壁バリア膜11aおよびキャップ金属膜CMの構造および製法に関する変形例である。実施の形態1と異なる部分に異なる符号を付して説明をする。同様の符号を付した部分は実施の形態1と同様である。実施の形態1と区別するために、本実施の形態3では、半導体チップ1Cとした。
実施の形態4は、実施の形態3の変形例であるが、キャップ金属膜CMd構造および製法、さらに、表面保護膜10の上面に凹部を有する点が実施の形態3とは異なっている。実施の形態3と異なる部分に異なる符号を付して説明をする。同様の符号を付した部分は実施の形態3と同様である。実施の形態3と区別するために、本実施の形態4では、半導体チップ1Dとした。
CM1、CM1c、CM1d、CM2、CM2c、CM2d、CM3、CM3c キャップバリア膜
PP 張り出し部
PR1、PR2、PR3、PR4、PR5 レジストマスク
PR1a 側面
p1、p2、p3 プラグ
P1 第1平面パターン
P2 第2平面パターン
Qn nチャネル型MISトランジスタ
Qp pチャネル型MISトランジスタ
RM、RMa、RMb、RMc、RMd、RMS、RMV 再配線
RM1 シード膜
RM2 メッキ膜
UM、UMc、UMd 下地金属膜
UM1、UM1c、UM1d、UM2、UM2c、UM2d、UM3、UM3c、UM3d 下地バリア膜
1A、1B、1C、1D 半導体チップ
1P 半導体基板
2P p型ウエル
2N n型ウエル
3 素子分離溝
3a 素子分離絶縁膜
4、6、8 層間絶縁膜
5、7、9 配線層(Al配線)
9a パッド電極
10 表面保護膜
10a パッド開口
11 無機絶縁膜
11a、11b、11c、11d 側壁バリア膜
12 保護膜
13 開口
14 凹部
18 外部パッド電極
25D ダイパッド部
25L リード
26 封止体
27 ワイヤ
Claims (8)
- 半導体基板と、
前記半導体基板上に形成された複数の配線層と、
前記複数の配線層の最上層に形成されたパッド電極と、
前記パッド電極上に開口を有する第1保護膜と、
前記第1保護膜上および前記パッド電極上に形成された下地金属膜と、
前記下地金属膜上に形成され、上面と側面を有する、銅膜からなる再配線と、
前記再配線の前記側面を覆う絶縁膜からなるバリア膜と、
前記再配線の前記上面と、前記再配線の前記側面と、前記第1保護膜の上面とを連続的に覆うように形成されており、かつ前記バリア膜との重なり部を有するキャップ金属膜と、
前記バリア膜および前記キャップ金属膜を覆うように前記第1保護膜上に形成された、有機膜からなる第2保護膜と、
を有し、
前記キャップ金属膜は、前記再配線の前記側面上に位置する前記バリア膜を覆っている、半導体装置。 - 請求項1に記載の半導体装置であって、
前記バリア膜は、前記下地金属膜の側壁を覆っている、半導体装置。 - 請求項1に記載の半導体装置であって、
前記再配線は、前記上面に対向する下面を有し、前記上面における前記再配線の幅は、前記下面における前記再配線の幅よりも大きい、半導体装置。 - 請求項3に記載の半導体装置であって、
前記再配線の幅は、前記上面から前記下面に向かって狭くなる、半導体装置。 - 請求項1に記載の半導体装置であって、
前記バリア膜は、窒化シリコン膜または酸化シリコン膜からなる、半導体装置。 - 請求項1に記載の半導体装置であって、
前記キャップ金属膜は、前記再配線に接する、チタン膜、タンタル膜、タングステン膜、ニッケル膜、窒化チタン膜、窒化タンタル膜、窒化タングステン膜または窒化ニッケル膜を含む、半導体装置。 - 請求項1に記載の半導体装置であって、
前記第1保護膜と前記バリア膜は、窒化シリコン膜からなる、半導体装置。 - 請求項1に記載の半導体装置であって、
前記再配線とは異なる領域において、前記第1保護膜上に形成された銅膜からなる再配線をさらに有する、半導体装置。
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| CN201510940548.9A CN105720027A (zh) | 2014-12-17 | 2015-12-16 | 半导体器件以及其制造方法 |
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