JP6428003B2 - Writing apparatus, writing method, writing processing program, and information storage medium - Google Patents

Description

  The present invention relates to a technique such as an apparatus for writing a program in a memory provided in an information storage medium such as an IC chip capable of executing a plurality of execution codes constituting a predetermined program.

Conventionally, for example, many IC chips mounted on an IC card are compatible with Java (registered trademark) Card. A programming language such as Java (registered trademark) is different from a language that is converted from source code to native code (machine language) by compiling, such as C language, in order to absorb hardware dependency. It is converted into an intermediate code (byte code) which is an execution format called. The intermediate code is a data string including instructions such as arithmetic and branch. This intermediate code is a virtual machine (Virtual Machine
) Is interpreted and executed. In an IC chip having such a virtual machine, the instruction interpreting unit of the virtual machine is realized by an array of the start address (that is, the start address in the memory) of the implementation (execution code) of each instruction (intermediate code). There are many. In addition, many existing IC chips record programs (executable codes including instruction interpreting units) in ROM (the arrangement of executable codes is determined during the semiconductor manufacturing process). Recently, however, the ROM capacity has been reduced, Many IC chips have a large capacity nonvolatile memory such as a flash memory, and an increasing number of IC chips record the above-described programs in the nonvolatile memory (the execution code and its arrangement are determined after shipping from a semiconductor vendor). ).

  By the way, SCA (Side Channel Analysis) is widely known as an attack technique for inferring secret information that is only inside the IC chip by analyzing changes in the power consumption and radiated electromagnetic field of the IC chip. . Of particular note is an attack method that analyzes side channel information of readily available sample cards, learns their characteristics in advance, and infers secret information from distribution cards (for example, credit cards) that use the same IC chip. Has been. This is because the side channel information obtained from each of the sample card and the distribution card used for learning (attack preparation) is very similar. As a technique related to such SCA countermeasures, there is known a cryptographic processing apparatus that introduces noise in power consumption measurement by calculating an unpredictable amount of power during cryptographic processing operations (for example, Patent Documents). 1).

US Pat. No. 7,599,488

  However, the cryptographic processing device described in Patent Document 1 has a problem that the processing becomes complicated and the circuit scale increases. Further, in the cryptographic processing apparatus described in Patent Document 1, attention is not paid to protection of a program itself written in an information storage medium such as an IC chip as a countermeasure against SCA.

  The present invention provides a writing device, a writing method, and a writing method that can efficiently protect a program written in an information storage medium such as an IC chip with a configuration that does not complicate the processing as a countermeasure against SCA. It is an object to provide a processing program and an information storage medium.

In order to solve the above problem, the invention according to claim 1 writes information in an information storage medium including a virtual machine that interprets and executes intermediate codes corresponding to each of a plurality of execution codes constituting a predetermined program. A writing device, wherein the plurality of execution codes are arranged in the memory of the information storage medium, the sorting means rearranging the default arrangement, and the arrangement is rearranged by the sorting means. Write control means for writing a plurality of execution codes to the memory of the information storage medium, the intermediate code for identifying the execution code, and address information indicating an address in the memory to which the execution code is written A reference table for each execution code, wherein the pair after the array is rearranged by the rearranging means. A generating means for generating the reference table showing the relationship, characterized in that it comprises a transmitting means for transmitting a reference table generated by the generation unit to the information storage medium.

The invention according to claim 2 is an information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program, and at least of the plurality of execution codes A writing device for writing information to the information storage medium in which a plurality of execution codes in which any one execution code is duplicated is stored in a memory, the intermediate code identifying the execution code, A reference table showing a correspondence relationship with address information indicating an address in the memory in which an execution code is written, for each execution code, and the at least duplicated execution code is selected from these execution codes the intermediate code that identifies one of executable code that, the notes which the execution code is stored Characterized in that it comprises generation means for generating a reference table showing the correspondence between the address information indicating an address, and transmission means for transmitting a reference table generated by the generation unit to the information storage medium in.

The invention according to claim 3 is an information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program, the memory and the plurality of execution codes A plurality of execution codes obtained by rearranging the default arrangement of the plurality of execution codes in the memory, and writing means for writing to the memory; and the intermediate code for identifying the execution code A reference table showing a correspondence relationship with address information indicating an address in the memory in which the execution code is written for each execution code, the reference table showing the correspondence relationship after the array is rearranged Generating means for generating.

According to a fourth aspect of the present invention, there is provided an information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program, and stores the plurality of execution codes A memory, rearrangement means for rearranging the arrangement of the plurality of execution codes stored in the memory in the memory, and writing the plurality of execution codes in which the arrangement is rearranged by the rearrangement means; A reference table for each execution code showing a correspondence relationship between a writing means, the intermediate code for identifying the execution code, and address information indicating an address in the memory in which the execution code is written, wherein the array is Generating means for generating the reference table indicating the correspondence relationship after being rearranged.

The invention according to claim 5 is an information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program, and at least of the plurality of execution codes A memory for storing the plurality of execution codes in which any one execution code is duplicated; the intermediate code for identifying the execution code; and address information indicating an address in the memory in which the execution code is written; A reference table for each of the execution codes, and for the at least duplicated execution code, the intermediate code for identifying any one execution code selected from these execution codes ; Correspondence with address information indicating an address in the memory in which the execution code is written Characterized in that it comprises a generation means for generating a reference table showing the.

The invention according to claim 6 is an information storage medium executed by a computer that writes information in an information storage medium including a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program And a rearrangement step of rearranging the default arrangement of the plurality of execution codes in the memory of the information storage medium, and the arrangement is rearranged by the rearrangement step. A correspondence relationship between a write control step for writing the plurality of execution codes to the memory of the information storage medium, the intermediate code for identifying the execution code, and address information indicating an address in the memory to which the execution code is written. A reference table for each execution code, wherein the reordering step Characterized in that it comprises a generation step of generating the reference table indicating the correspondence relationship after the array is sorted, and transmitting the lookup table generated by the generation step to the information storage medium, the .

The invention according to claim 7 is an information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program, and at least of the plurality of execution codes a method of writing one of the execution code is executed by a computer to write information to the plurality of execution codes at least doubled in the information storage medium which stores in a memory, said identifying the execution code A reference table for each execution code showing a correspondence relationship between an intermediate code and address information indicating an address in the memory in which the execution code is written, and the execution code for the at least duplex execution code the intermediate code that identifies any one of the execution code that is selected from among, the real A generation step of generating a reference table indicating a correspondence relationship with address information indicating an address in the memory in which a code is stored; and a transmission step of transmitting the reference table generated by the generation step to the information storage medium. It is characterized by including.

According to an eighth aspect of the present invention, there is provided a computer for writing information in an information storage medium including a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program. Rearrangement means for rearranging the default arrangement in the memory of the information storage medium, and the plurality of execution codes in which the arrangement is rearranged by the rearrangement means in the memory of the information storage medium A reference table for each execution code showing a correspondence relationship between write control means for writing, the intermediate code for identifying the execution code, and address information indicating an address in the memory in which the execution code is written, The reference table showing the correspondence after the arrangement is rearranged by the rearranging means Generating means for generating, and wherein the lookup table generated by the generating means is caused to function as transmission means for transmitting to said information storage medium.

The invention according to claim 9 is an information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program, and at least of the plurality of execution codes The intermediate code for identifying the execution code and the execution code are written in a computer for writing information to the information storage medium in which the plurality of execution codes in which any one execution code is duplicated is stored in a memory. A reference table showing a correspondence relationship with address information indicating an address in the memory for each execution code, wherein the at least duplicated execution code is selected from these execution codes. One of said intermediate code identifying the execution code, the memory where the execution code is stored A generating means for generating a reference table showing the correspondence between the address information indicating the definitive address, and wherein the lookup table generated by the generating means is caused to function as transmission means for transmitting to said information storage medium.

  According to the present invention, it is possible to efficiently protect a program written in an information storage medium such as an IC chip with a configuration that does not complicate the processing.

It is a figure showing an example of outline composition of IC card issue system S. (A), (B) is a flowchart which shows the process example of the control part 21 in the IC card issuing machine 2. FIG. (A) is a figure which shows the reference table and mounting arrangement | sequence of IC card 1 which were issued by the process of Example 1 and the sample card, and (B) is issued by the process of Example card and Example 2. It is a figure which shows the reference table and mounting arrangement | sequence of IC card 1. (C) is a diagram showing an example of the contents of the duplicated execution code “ADD” (01 and 02).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiment described below is an embodiment when the present invention is applied to an IC card issuing system. In this specification, “issue” means writing predetermined information (program, data, etc.) in an information storage medium such as an IC chip.

  First, with reference to FIG. 1, the configuration and functional overview of an IC card issuing system according to the present embodiment will be described. FIG. 1 is a diagram showing a schematic configuration example of the IC card issuing system S. As shown in FIG. 1, the IC card issuing system S includes an IC card 1 to be issued and an IC card issuing machine 2.

  An IC chip 1a is mounted on the IC card 1 as shown in FIG. The IC card 1 is used as a cash card, credit card, employee card or the like. Alternatively, the IC card 1 is incorporated into a communication device such as a smartphone or a mobile phone. The IC chip 1a constitutes the information storage medium in the present invention. However, the IC chip 1a may be directly incorporated on the circuit board of the communication device.

  The IC chip 1a includes a CPU (Central Processing Unit) 10, a RAM (Random Access Memory) 11, a ROM (Read Only Memory) 12, a nonvolatile memory 13, and an I / O circuit 14, and constitutes a predetermined program. It is possible to execute multiple executable codes. For example, a flash memory is applied to the nonvolatile memory 13. The nonvolatile memory 13 may be “Electrically Erasable Programmable Read-Only Memory”. The I / O circuit 14 serves as an interface with the IC card issuer 2. The I / O circuit 14 is provided with eight terminals C1 to C8 defined by, for example, ISO / IEC7816. For example, the C1 terminal is a power supply terminal, the C2 terminal is a reset terminal, the C3 terminal is a clock terminal, the C5 terminal is a ground terminal, and the C7 terminal is a terminal that performs data communication with an external terminal such as the IC card issuer 2.

  The CPU 10 is an arithmetic device that executes various programs stored in the ROM 12, the nonvolatile memory 13, or the RAM 11. The various programs include an OS (Operating System), a virtual machine, and an application program, and the application program is executed via the virtual machine as described later. The OS and the virtual machine are described by a plurality of execution codes (execution code groups). The OS is software that directly controls the operation of the IC chip 1a. The virtual machine interprets and executes intermediate code obtained by compiling source code of an application program described in a program language such as Java (registered trademark). The application program of the present embodiment is an application program that is installed in the IC chip 1a after the IC card 1 issuance process, for example. Such an application program is composed of a plurality of intermediate codes located between the source code and the execution code, and is written at a predetermined address in the nonvolatile memory 13. The intermediate code is identification information (index) that identifies an execution code corresponding to the intermediate code. For example, the intermediate code “03” indicates an execution code “ADD” (addition). The intermediate code “04” indicates an execution code “MOV” (data write). The intermediate code “05” indicates the execution code “SUB” (subtraction). When interpreting and executing the intermediate code, the virtual machine indicates the correspondence between the intermediate code and address information indicating an address (for example, the start address of the execution code) in the nonvolatile memory 13 in which the execution code is written for each execution code. Reference the reference table. As a result, the CPU 10 executes the execution code stored at the specified address. That is, this reference table is referred to when the execution code written in the nonvolatile memory 13 is executed. This reference table may be generated by the IC card issuing machine 1 or generated by the IC chip 1a.

  The IC card issuer 2 communicates with the control unit 21 including a CPU, RAM, and nonvolatile memory, the storage unit 22 including a hard disk drive, and the IC card 1 via a reader / writer. The communication unit 23 is configured to be performed. The IC card issuer 2 is an example of the writing device of the present invention. The storage unit 22 stores the OS and the write processing program of the present invention. The control unit 21 functions as a rearrangement unit, a write control unit, a generation unit, and a transmission unit in the present invention by executing the write processing program of the present invention. During the manufacturing process of the IC card 1, the IC card 1 Issue processing for issuing 1 is performed. The storage unit 22 stores a program to be written to the IC card 1.

  FIGS. 2A and 2B are flowcharts showing a processing example of the control unit 21 in the IC card issuing machine 2. FIG. 2A shows the processing of the first embodiment, and FIG. 2B shows the processing of the second embodiment. The processes shown in FIGS. 2A and 2B are executed at the time of issuing process during the manufacturing process of the IC card 1.

(Example 1)
The first embodiment is an effective embodiment when applied to the IC card 1 having a small storage capacity of the ROM 12 and a large storage capacity of the nonvolatile memory 13. In the process of the first embodiment, as illustrated in FIG. 2A, the control unit 21 acquires a program to be written to the nonvolatile memory 13 of the IC chip 1a from the storage unit 22 (step S1).

  Next, the control unit 21 uses an array (a mounting array), which is an array in the nonvolatile memory 13 of a plurality of execution codes constituting the acquired program and is set as a default, based on, for example, random numbers or information unique to the IC chip 1a. And rearrange (step S2). For example, a code that is interpreted and executed by the IC chip 1a (for example, a state in which the boundary of implementation of the intermediate code can be identified by a lump of characters or numerical values generated by a compiler or a linker) is input, and a random number, manufacturing history, IC chip 1a The execution code array corresponding to the intermediate code is rearranged based on the identification information. Thus, during the issuance process during the manufacturing process, the arrangement of the intermediate code implementation (execution code) is changed for each IC chip 1a used for the same purpose (data including the same program is written). It is desirable to individualize based on the identification information and manufacturing history of the IC chip 1a so that it can be individualized for all the IC chips 1a used for the same application. However, sample cards and distribution cards (used in the market) May be distinguished only in two ways.

  Subsequently, the control part 21 produces | generates the reference table which shows the said correspondence after the arrangement | sequence was rearranged in step S2 (step S3). That is, the reference table is generated along the rearrangement in step S2.

  Next, the control unit 21 transmits a program including a plurality of execution codes whose arrangement is rearranged in step S2 and the reference table generated in step S3 to the IC chip 1a, and the plurality of execution codes are nonvolatile. Write to the memory 13 (step S4). Thus, the IC card 1 on which the IC chip 1a having the reference table and the program stored in the nonvolatile memory 13 is generated as a distribution card.

  FIG. 3A is a diagram illustrating a sample card and a reference table and mounting arrangement of the IC card 1 issued in the processing of the first embodiment. As shown in FIG. 3A, the arrangement order of the intermediate codes in both reference tables is the same, but the address information associated with the intermediate code (in this example, the start address of the execution code) is different. Yes. That is, the arrangement of the execution code written in the nonvolatile memory 13 is different between the sample card and the IC card 1 issued in the processing of the first embodiment. As a result, it is possible to change the manner in which power is consumed when the execution code is read from the nonvolatile memory 13 by referring to the reference table. For example, even if the same execution code “ADD” is arranged at addresses 8000 and 8026, the address Hamming weight (the number of bits indicating 1 in binary number, 8000 is 1 and 8026 is 4). Because of the difference, there is a difference in power consumption caused by the address bus. That is, although the same execution code “ADD” is being executed, the power consumption value can be varied for each IC chip. Therefore, it is possible to reduce the correlation between the side channel information of the sample card used for learning in the SCA and the IC card 1 issued in the processing of the first embodiment. Further, according to the configuration of the first embodiment, there is no special additional element in the processing inside the IC chip 1a, and only “refers to the reference table in which the start address of the implementation corresponding to the intermediate code is recorded” as in the past. Good. That is, the above effect can be obtained by dealing with the IC card issuing machine 2 side.

  As a modification of the first embodiment, the reference code may be generated on the IC chip 1a side. In this case, the IC chip 1a includes a plurality of execution codes in which the arrangement of the plurality of execution codes in the nonvolatile memory 13 and the default arrangement is rearranged based on, for example, random numbers or information unique to the IC chip 1a. Is acquired from the IC card issuer 2 and written to the nonvolatile memory 13. Then, the IC chip 1a generates a reference table indicating the correspondence relationship after the arrangement of the execution codes is rearranged by the IC card issuer 2.

  As a modification of the first embodiment, the arrangement of the execution code array may be rearranged on the IC chip 1a side. In this case, the IC chip 1 a writes the execution codes in, for example, the backup area of the nonvolatile memory 13 in the order determined at the time of compilation. Next, the IC chip 1a rearranges the arrangement of the plurality of execution codes stored in the nonvolatile memory 13 in the nonvolatile memory 13 based on, for example, random numbers or information unique to the IC chip 1a. Next, the IC chip 1a writes (that is, transfers) a plurality of execution codes in which the arrangement is rearranged in an arrangement in which the non-volatile memory 13 is rearranged from, for example, a backup area to a normal area. Then, the IC chip 1a generates a reference table indicating the correspondence relationship after the arrangement of the execution code is rearranged by the IC chip 1a.

(Example 2)
The second embodiment is effective in the case where the nonvolatile memory 13 has a small storage capacity, and is particularly effective when applied to the IC card 1 in which the execution code is stored in the ROM in which the IC card issuer 2 cannot change the mounting order. is there. In this case, the ROM 12 of the IC chip 1a stores a plurality of execution codes in which at least one of the plurality of execution codes is duplicated (may be triple or more). It shall be. In the processing of the second embodiment, as shown in FIG. 2B, the control unit 21 selects any one of these execution codes from among the execution codes in the reference table described above. A reference table indicating a correspondence relationship between an intermediate code for identifying one execution code and address information indicating an address in the ROM 12 in which the execution code is stored is generated (step S11). Here, which execution code is selected from at least the duplicated execution code is determined by a random number, for example. And the control part 21 transmits the reference table produced | generated by step S11 to IC chip 1a (step S12).

  FIG. 3B is a diagram illustrating a sample card and a reference table and mounting arrangement of the IC card 1 issued in the processing of the second embodiment. As shown in FIG. 3B, the arrangement order of the intermediate codes in both reference tables is the same, but the address information associated with the intermediate code (in this example, the start address of the execution code) is different. Yes. That is, the execution code selected from the duplicated execution code is different between the sample card and the IC card 1 issued in the processing of the second embodiment. As a result, as in the first embodiment, it is possible to change the manner in which power is consumed when the execution code is read from the ROM 12 by referring to the reference table. Further, according to the configuration of the second embodiment, there is no special additional element in the processing inside the IC chip 1a, and only “refers to the reference table in which the start address of the implementation corresponding to the intermediate code is recorded” as in the past. Good. That is, the above effect can be obtained by dealing with the IC card issuing machine 2 side. Further, even when the execution code is stored in the ROM whose arrangement of mounting cannot be changed, the power consumption when the execution code is read from the ROM can be changed for each IC card 1.

  As a modification of the second embodiment, the reference code may be generated on the IC chip 1a side. In this case, the IC chip 1a includes an intermediate code for identifying any one execution code selected from these execution codes in the reference table described above, and the execution code. A reference table indicating a correspondence relationship with address information indicating an address in the ROM 12 is generated. Further, in the case where execution codes that are processed in the same way are at least duplicated, the order of execution codes and the registers used may be changed. FIG. 3C is a diagram showing an example of the contents of the duplicated execution code “ADD” (01 and 02). In ADD01 shown in FIG. 3C, the data at address 0003 is first transferred to register R0, then the data at address 0058 is transferred to register R1, and then the data in registers R0 and R1 are added. . On the other hand, in ADD02 shown in FIG. 3C, the data at address 0058 is first transferred to register R1, the data at address 0003 is then transferred to register R0, and then the data of registers R0 and R1 are added. ing. As described above, the processing results of ADD01 and ADD02 are the same, but by changing the reading order from the address, the tendency of the power consumption when the execution code is read from the ROM 12 can be further changed.

  As described above, according to the above-described embodiment, the arrangement of a plurality of execution codes written in the IC chip 1a is rearranged, or at least two execution codes are selected to select any execution code. Therefore, it is possible to change the way in which power is consumed when the execution code is read from the nonvolatile memory 13, and to efficiently protect the program written in the IC chip 1a with a configuration that does not complicate the processing. It can be carried out.

1 IC card 2 IC card issuing machine 1a IC chip 10 CPU
11 RAM
12 ROM
13 Non-volatile memory 14 I / O circuit

Claims (9)

A writing device for writing information to an information storage medium including a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program,
Rearrangement means for rearranging the default arrangement of the plurality of execution codes in the memory of the information storage medium;
Write control means for writing the plurality of execution codes in which the arrangement is rearranged by the rearranging means to a memory of the information storage medium;
A reference table showing a correspondence relationship between the intermediate code for identifying the execution code and address information indicating an address in the memory in which the execution code is written, for each execution code, and the array is arranged by the rearranging unit. Generating means for generating the reference table indicating the correspondence after the rearrangement;
Transmitting means for transmitting the reference table generated by the generating means to the information storage medium;
A writing device comprising: An information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program, wherein at least one execution code of the plurality of execution codes is at least 2 A writing device for writing information to the information storage medium in which the plurality of execution codes that have been duplicated are stored in a memory,
A reference table for each execution code showing a correspondence relationship between the intermediate code for identifying the execution code and address information indicating an address in the memory in which the execution code is written, wherein the execution code is at least duplicated For the code, a reference table indicating a correspondence relationship between the intermediate code for identifying any one execution code selected from these execution codes and address information indicating an address in the memory in which the execution code is stored Generating means for generating
Transmitting means for transmitting the reference table generated by the generating means to the information storage medium;
A writing device comprising: An information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program,
Memory,
A writing means for acquiring the plurality of execution codes from the writing device and writing the plurality of execution codes in the memory, wherein the plurality of execution codes are arranged in the memory and the default arrangement is rearranged;
A reference table for each execution code showing a correspondence relationship between the intermediate code for identifying the execution code and address information indicating an address in the memory in which the execution code is written, and after the array is rearranged Generating means for generating the reference table indicating the correspondence relationship of:
An information storage medium comprising: An information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program,
A memory for storing the plurality of execution codes;
Rearrangement means for rearranging an array in the memory of the plurality of execution codes stored in the memory;
Writing means for writing the plurality of executable codes in which the arrangement is rearranged by the rearranging means to the memory;
A reference table for each execution code showing a correspondence relationship between the intermediate code for identifying the execution code and address information indicating an address in the memory in which the execution code is written, and after the array is rearranged Generating means for generating the reference table indicating the correspondence relationship of:
An information storage medium comprising: An information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program,
A memory for storing the plurality of execution codes in which at least any one of the plurality of execution codes is duplicated;
A reference table for each execution code showing a correspondence relationship between the intermediate code for identifying the execution code and address information indicating an address in the memory in which the execution code is written, wherein the execution code is at least duplicated For the code, a reference table showing a correspondence relationship between the intermediate code for identifying any one of the execution codes and the address information indicating the address in the memory in which the execution code is written. Generating means for generating;
An information storage medium comprising: An information storage medium writing method executed by a computer that writes information to an information storage medium including a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program,
A rearrangement step of rearranging the default arrangement of the plurality of execution codes in the memory of the information storage medium;
A write control step for writing the plurality of execution codes in which the arrangement is rearranged in the rearrangement step into a memory of the information storage medium;
A reference table for each execution code showing a correspondence relationship between the intermediate code for identifying the execution code and address information indicating an address in the memory in which the execution code is written, and the array is arranged by the rearrangement step. A generation step of generating the reference table indicating the correspondence after the rearrangement;
Transmitting the reference table generated by the generating step to the information storage medium;
A writing method comprising: An information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program, wherein at least one execution code of the plurality of execution codes is at least 2 A writing method executed by a computer that writes information to the information storage medium in which the plurality of execution codes that have been overlapped are stored in a memory,
A reference table for each execution code showing a correspondence relationship between the intermediate code for identifying the execution code and address information indicating an address in the memory in which the execution code is written, wherein the execution code is at least duplicated For the code, a reference table indicating a correspondence relationship between the intermediate code for identifying any one execution code selected from these execution codes and address information indicating an address in the memory in which the execution code is stored A generation step for generating
A transmission step of transmitting the reference table generated by the generation step to the information storage medium;
A writing method comprising: A computer for writing information to an information storage medium including a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program;
Rearrangement means for rearranging the default arrangement of the plurality of execution codes in the memory of the information storage medium;
Write control means for writing the plurality of execution codes in which the arrangement is rearranged by the rearranging means to a memory of the information storage medium ;
A reference table showing a correspondence relationship between the intermediate code for identifying the execution code and address information indicating an address in the memory in which the execution code is written, for each execution code, and the array is arranged by the rearranging unit. Generating means for generating the reference table indicating the correspondence after the rearrangement;
A writing processing program that functions as a transmission unit that transmits the reference table generated by the generation unit to the information storage medium . An information storage medium comprising a virtual machine that interprets and executes an intermediate code corresponding to each of a plurality of execution codes constituting a predetermined program, wherein at least one execution code of the plurality of execution codes is at least 2 A computer for writing information to the information storage medium in which the multiple execution codes are stored in a memory;
A reference table for each execution code showing a correspondence relationship between the intermediate code for identifying the execution code and address information indicating an address in the memory in which the execution code is written, wherein the execution code is at least duplicated For the code, a reference table indicating a correspondence relationship between the intermediate code for identifying any one execution code selected from these execution codes and address information indicating an address in the memory in which the execution code is stored Generating means for generating
A writing processing program that functions as a transmission unit that transmits the reference table generated by the generation unit to the information storage medium.

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