JP6430274B2 - Phase difference detection method - Google Patents

Description

  The present invention relates to a method for detecting a phase difference.

  In general, it is known to use a PLL (phase-locked loop) circuit to control the phase. The PLL circuit controls the phase of the output signal by detecting the phase difference between the reference signal and the output signal to be controlled.

JP-A-2005-3530

  However, for example, when a single-phase PLL circuit is configured, a phase shift circuit that performs dq axis conversion or the like is required to detect a phase difference, and the circuit becomes complicated.

  Accordingly, an object of the present invention is to provide a phase difference detection method applicable to a PLL circuit with a simple circuit.

  A phase difference detection method according to an embodiment of the present invention is a phase difference detection method for detecting a phase difference between a reference phase obtained by shifting a predetermined phase from a reference wave and a target phase of the target wave, and is constant. The first count value of the first counter is increased at a time interval of, the first count value is reset at the zero point of the reference wave, and the first waveform is output from the first counter, A value based on the first count value by the first counter for a predetermined phase and one period of the reference wave is compared with the first waveform output from the first counter, and a second , The second count value of the second counter is incremented at the predetermined time interval, the second count value is reset by the output second waveform, and the second counter To output a third waveform from the second waveform. Based on the third waveform output from the counter, the fourth waveform having the reference phase of zero is calculated, the calculated fourth waveform is sampled at the target phase, and the phase difference is detected. Including doing.

The block diagram which shows the structure of the PLL circuit to which the phase difference detection circuit which concerns on the 1st Embodiment of this invention is applied. FIG. 4 is a waveform diagram showing waveforms in the PLL circuit according to the first embodiment. The block diagram which shows the structure of the PLL circuit to which the phase difference detection circuit which concerns on the 2nd Embodiment of this invention is applied. The wave form diagram which shows each waveform in the PLL circuit which concerns on 2nd Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a configuration diagram showing a configuration of a PLL circuit 10 to which the phase difference detection circuit 1 according to the first embodiment of the present invention is applied. FIG. 2 is a waveform diagram showing each waveform in the PLL circuit 10 according to the present embodiment. In the following, the same parts in the drawings are denoted by the same reference numerals, detailed description thereof is omitted, and different parts are mainly described.

  The PLL circuit 10 includes a phase difference detection circuit 1, a comparator 2, a controller 3, an adder 4, and an integrator 5.

  The reference sine wave Wr is input to the comparator 2. The reference sine wave Wr is, for example, a sine wave single-phase AC voltage. Note that the waveform input to the comparator 2 may not be a sine wave. Any waveform such as a rectangular wave or a triangular wave may be used as long as the waveform repeats at a constant cycle. However, the zero point that changes from negative to positive needs to be once per cycle. If the zero occurs multiple times due to noise or the like, the waveform needs to be adjusted by a filter.

  The comparator 2 outputs 1 if the instantaneous value of the input reference sine wave Wr is 0 or more, and outputs 0 if it is less than 0. That is, if the instantaneous value input to the comparator 2 is a and 0 is the reference value of the comparison of the comparator 2 and b is b, if a ≧ b holds, the comparator 2 outputs 1; In this case, the comparator 2 outputs 0. Thereby, the comparator 2 converts the reference sine wave Wr into a pulse waveform W1 as shown in FIG. The rising edge of the pulse waveform W1 indicates the phase at which the reference sine wave Wr becomes 0 ° (zero point from negative to positive). The comparator 2 outputs the converted pulse waveform W1 to the phase difference detection circuit 1.

  The phase difference detection circuit 1 receives the pulse waveform W1 output from the comparator 2 and the phase θ of the target wave (for example, a sine wave) to be controlled by the PLL circuit 10. The phase difference detection circuit 1 includes a reference phase that is shifted by an arbitrary synchronization phase θs (−180 ° ≦ θs ≦ + 180 °) set in advance from the phase of the reference sine wave Wr (or pulse waveform W1). A phase difference Δθ with respect to the phase θ is calculated. The synchronization phase θs indicates a phase width for shifting the phase synchronized with the phase θ from the phase of the reference sine wave Wr. When the synchronous phase θs is a positive value, it represents a delayed phase with respect to the reference sine wave Wr, and when the synchronous phase θs is a negative value, it represents a lead phase with respect to the reference sine wave Wr. The phase difference detection circuit 1 outputs the calculated phase difference Δθ to the controller 3.

  The controller 3 performs PI (proportional-plus-integral control) based on the input phase difference Δθ. The controller 3 outputs the angular frequency correction value ωh calculated as a control result to the adder 4. When the phase θ is delayed by the angular frequency correction value ωh of the controller 3, control is performed to increase the frequency of the sine wave of the phase θ, and when the phase θ is advanced, the frequency of the sine wave of the phase θ. Control to lower.

  The adder 4 receives a preset reference angular frequency ωr and an angular frequency correction value ωh output from the controller 3. For example, the reference angular frequency ωr is an average frequency of a waveform that synchronizes the phase θ. The adder 4 adds the angular frequency correction value ωh from the reference angular frequency ωr to obtain the angular frequency ω. The adder 4 outputs the calculated angular frequency ω to the integrator 5. Instead of providing the adder 4 in the PLL circuit 10, the angular frequency correction value ωh output from the controller 3 may be directly input to the integrator 5.

  The integrator 5 integrates the angular frequency ω input from the adder 4 and outputs a phase θ. The phase θ output from the integrator 5 is input to the phase difference detection circuit 1.

  Next, the configuration of the phase difference detection circuit 1 will be described. Here, the description will be made mainly assuming that the synchronization phase θs is 90 °, but the same applies to values other than 90 ° of the synchronization phase θs.

  The phase difference detection circuit 1 includes a counter 11, a comparator 12, a counter 13, a subtracter 14, and a sample / hold circuit 15.

  The counter 11 receives the clock signal Sc and the pulse waveform W1 output from the comparator 2. The clock signal Sc is a signal generated (becomes 1) at regular time intervals. For example, the clock signal Sc is a signal output from a timer built in the computer. The counter 11 increases the count value at regular time intervals by the clock signal Sc. The count value is the output of the counter 11. Thereby, the output waveform W2 of the counter 11 increases in a slope shape as shown in FIG. When the pulse waveform W1 changes from 0 to 1, the counter 11 resets the count value. That is, the counter 11 is reset at the rising edge of the pulse waveform W1. As a result, the output waveform W2 of the counter 11 becomes zero. The generated waveform W2 is input to the comparator 12.

  In the comparator 12, a reference value based on the synchronization phase θs is set in advance. The reference value is obtained by Ct × (180 ° + θs) / 360 °, where Ct is a count value for one cycle of the pulse waveform W1 (reference sine wave Wr) by the counter 11. When the synchronization phase θs is 90 °, the reference value is 0.75 × Ct. The comparator 12 compares the instantaneous value of the waveform W2 input from the counter 11 with the reference value, and generates the waveform W3 shown in FIG. The comparator 12 outputs 1 if the instantaneous value of the input waveform W3 is greater than or equal to the reference value, and outputs 0 if it is less than the reference value. The generated pulse waveform W3 is output to the counter 13.

  The counter 13 receives the clock signal Sc and the pulse waveform W3 output from the comparator 12. The counter 13 operates in the same manner as the counter 11. That is, the output waveform W4 of the counter 13 increases in a slope shape by the clock signal Sc and is reset at the rising edge of the pulse waveform W3. Thereby, the counter 13 generates the waveform W4 shown in FIG. The generated waveform W4 is output to the subtractor 14.

  In the subtractor 14, a value (Ct / 2) that is a half of the count value for one cycle of the pulse waveform W1 (reference sine wave Wr) by the counter 13 is set in advance. The count value for one cycle by the counter 13 is the same as the count value for one cycle by the counter 11. The subtracter 14 subtracts the aforementioned preset value from the waveform W4 output from the counter 13. Thereby, the subtractor 14 generates the waveform W5 shown in FIG. The PLL circuit 10 performs control so that the phase of the zero point of the target wave to be controlled is positioned at the zero point of the waveform W5 thus generated. The generated waveform W5 is output to the sample / hold circuit 15.

  The sample / hold circuit 15 receives the waveform W5 output from the subtractor 14 and the phase θ of the target wave. The sample / hold circuit 15 samples and holds the instantaneous value of the waveform W5 when the phase θ is 0 [rad] (when the phase θ is a zero phase from negative to positive). As a result, the sample / hold circuit 15 samples once per period. The sample / hold circuit 15 detects the value thus calculated as a phase difference Δθ. The detected phase difference Δθ is output to the controller 3. Since the phase θ shown in FIG. 2 indicates a completely synchronized phase θ, the phase difference Δθ is always 0. If a deviation occurs in the timing at which the phase θ becomes 0 [rad], the phase difference Δθ becomes a positive value because it does not coincide with the zero point of the waveform W5.

  According to the present embodiment, the phase difference Δθ in the PLL can be detected by the phase difference detection circuit 1 configured with a simple logic circuit.

  Further, the phase difference detection circuit 1 can accurately detect the phase difference Δθ even in a single-phase PLL without using a phase shift circuit or the like.

  Furthermore, the phase difference detection circuit 1 can detect the phase difference Δθ with high accuracy even in a high-frequency PLL that is difficult to ensure with a general phase detection circuit.

  Further, since the phase difference detection circuit 1 can set the synchronization phase θs to an arbitrary phase, the PLL to which the phase difference detection circuit 1 is applied synchronizes the phase θ of the target wave to be controlled with the arbitrary phase. Can be made.

(Second Embodiment)
FIG. 3 is a configuration diagram showing a configuration of a PLL circuit 10A to which the phase difference detection circuit 1A according to the second embodiment of the present invention is applied. FIG. 4 is a waveform diagram showing each waveform in the PLL circuit 10A according to the present embodiment.

  The PLL circuit 10A is the same as the PLL circuit 10 according to the first embodiment shown in FIG. 1, except that the phase difference detection circuit 1 is replaced with the phase difference detection circuit 1A, a comparator 2A is added, and the output voltage Vi of the inverter 21 is compared with the comparator. This is configured to be input to the phase difference detection circuit 1A via 2A. The phase difference detection circuit 1A is obtained by replacing the sample / hold circuit 15 of the phase difference detection circuit 1 according to the first embodiment with a sample / hold circuit 15A. Others are the same as those of the PLL circuit 10 according to the first embodiment.

  The inverter 21 outputs the single-phase AC voltage Vi with the phase θ output from the integrator 5. The output voltage Vi of the inverter 21 is input to the comparator 2A as a tracking sine wave Wi. The follow-up sine wave Wi is a target wave to be controlled whose phase is synchronized (follow-up).

  The comparator 2A has the same configuration as the comparator 2 described in the first embodiment. That is, the comparator 2A outputs 1 if the instantaneous value of the tracking sine wave Wi is 0 or more, and outputs 0 if it is less than 0. Thereby, the comparator 2A generates a pulse waveform W6 shown in FIG. The generated pulse waveform W6 is output to the sample / hold circuit 15A of the phase difference detection circuit 1A.

  When the pulse waveform W6 changes from 0 to 1, the sample / hold circuit 15A samples and holds the instantaneous value of the waveform W5. That is, the sample / hold circuit 15A performs sampling and holding at the rising edge of the pulse waveform W6. Thereby, the sample / hold circuit 15A detects the phase difference Δθ shown in FIG. The other points are the same as those of the sample / hold circuit 15 according to the first embodiment.

  According to the present embodiment, by using the output voltage Vi of the inverter 21 as the tracking sine wave Wi, it is possible to obtain the same operational effects as in the first embodiment.

  Further, by providing the PLL circuit 10A, it is possible to control the output voltage Vi of the inverter 21 so as to follow a phase shifted by an arbitrary synchronization phase θs with respect to the reference sine wave Wr. For example, by making the reference sine wave Wr a single-phase AC voltage, the output voltage of the inverter 21 can be controlled so as to synchronize with the phase shifted by an arbitrary synchronization phase θs with respect to the single-phase AC voltage. it can. The reference sine wave Wr and the follow-up sine wave Wi are not limited to voltages, and may be currents or waveforms of other elements.

  In each embodiment, the calculation for detecting the phase difference Δθ may be changed in various manners as long as the same phase difference Δθ is detected as the calculation result. For example, even if the definition of the synchronization phase θs and the phase of the reference sine wave Wr as 0 ° (in the embodiment, the phase of the zero point from negative to positive) is changed, various parameters are also changed, so that each embodiment is changed. The same function and effect can be obtained.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Phase difference detection circuit, 2 ... Comparator, 3 ... Controller, 4 ... Adder, 5 ... Integrator, 10 ... PLL circuit, 11 ... Counter, 12 ... Comparator, 13 ... Counter, 14 ... Subtractor, 15: Sample / hold circuit.

Claims (5)

A phase difference detection method for detecting a phase difference between a reference phase obtained by shifting a predetermined phase from a reference wave and a target phase of the target wave,
Increasing the first count value of the first counter at a fixed time interval, resetting the first count value at the zero point of the reference wave, and outputting the first waveform from the first counter;
A value based on the first count value by the first counter for one cycle of the predetermined phase and the reference wave is compared with the first waveform output from the first counter, 2 waveform is output,
The second count value of the second counter is increased at the predetermined time interval, the second count value is reset by the output second waveform, and the third waveform is output from the second counter. Output,
Based on the third waveform output from the second counter, a fourth waveform in which the reference phase is zero is calculated,
A phase difference detection method comprising sampling the calculated fourth waveform at the target phase and detecting the phase difference. Converting the reference wave to a first pulse wave by setting the reference wave to 1 when the reference wave is positive and 0 when the reference wave is negative;
The phase difference detection method according to claim 1, wherein the first counter is reset with the converted first pulse wave. Converting the target wave to a second pulse wave by setting the target wave to 1 when the target wave is positive, and setting to 0 when the target wave is negative;
The phase difference detection method according to claim 1 or 2, wherein the phase difference is detected by sampling the fourth waveform with the converted second pulse wave. A phase difference detector that detects a phase difference between a reference phase obtained by shifting a predetermined phase from a reference wave and a target phase of the target wave,
A first counter that increases a first count value at a constant time interval, resets the first count value at a zero point of the reference wave, and outputs a first waveform;
A value based on the first count value by the first counter for one cycle of the predetermined phase and the reference wave is compared with the first waveform output from the first counter, Comparing means for outputting two waveforms;
A second counter that increases a second count value at the predetermined time interval, resets the second count value by the second waveform output from the comparison means, and outputs a third waveform; ,
Based on the third waveform output from the second counter, waveform calculating means for calculating a fourth waveform in which the reference phase is a zero point;
A phase difference detector comprising: a phase difference detection unit configured to sample the fourth waveform calculated by the waveform calculation unit with the target phase and detect the phase difference. A phase control circuit that controls a phase of the target wave based on a phase difference between a reference phase obtained by shifting a predetermined phase from the reference wave and a target phase of the target wave;
A first counter that increases a first count value at a constant time interval, resets the first count value at a zero point of the reference wave, and outputs a first waveform;
A value based on the first count value by the first counter for one cycle of the predetermined phase and the reference wave is compared with the first waveform output from the first counter, Comparing means for outputting two waveforms;
A second counter that increases a second count value at the predetermined time interval, resets the second count value by the second waveform output from the comparison means, and outputs a third waveform; ,
Based on the third waveform output from the second counter, waveform calculating means for calculating a fourth waveform in which the reference phase is a zero point;
Sampling the fourth waveform calculated by the waveform calculating means at the target phase, and detecting the phase difference;
A phase control circuit comprising: phase control means for controlling the phase of the target wave based on the phase difference detected by the phase difference detection means.

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