JP6432232B2 - Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device .

Research and development of next-generation semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) using a silicon carbide (SiC) substrate are underway. Since silicon carbide can form an insulating film on the surface of silicon carbide by thermal oxidation like silicon (Si), silicon carbide MOS type semiconductor devices are promising as next-generation MOS type power devices, for example ( For example, see Patent Document 1). As a method for forming a gate insulating film on a silicon carbide substrate, for example, there is a wet oxidation method using water vapor (H ₂ O) (see, for example, Patent Document 2).

JP 2013-102106 A JP 2013-157539 A

An insulating film can be formed on the silicon carbide substrate also by an oxynitriding method using a compound gas containing nitrogen (N) such as nitrogen dioxide (NO ₂ ) or nitrogen monoxide (NO). In the oxynitridation method, nitridation occurs simultaneously with oxidation, and nitrogen contributes to the termination of dangling bonds existing in the oxide film or at the interface between the oxide film and silicon carbide. Therefore, there is an effect of reducing the interface state density. It is said that. After the oxidation treatment by the oxynitriding method, annealing may be performed in an atmosphere containing hydrogen (H) as a POA (Post Oxidation Annealing) treatment. Since the dangling bonds are terminated with hydrogen by the POA treatment, an effect of further reducing the interface state density can be obtained.

  One of the indexes for alternatively evaluating channel mobility is interface state density. In general, it is known that the channel mobility tends to increase as the interface state density at the interface between the gate insulating film and the silicon carbide semiconductor decreases. Therefore, by performing the POA treatment after the oxidation treatment by the oxynitriding method, the interface state density is reduced, so that high channel mobility can be obtained.

  However, as the characteristics of the MOSFET, not only the channel mobility but also the threshold voltage is important. If the threshold voltage changes after being exposed to stress such as electric field application, the device will not perform a desired operation, which is a serious problem. In the conventional wet oxidation method, there are many electron traps related to hydroxyl groups and other water at the interface between the oxide film, that is, the gate insulating film and silicon carbide, so that the threshold voltage becomes unstable. There is a point.

  Here, in this specification, in the notation of Miller index, “−” means a bar attached to the index immediately after that, and “−” is added before the index to indicate a negative index. .

FIG. 16 is a diagram showing the atmosphere and temperature change of the heat treatment when manufacturing the MOS capacitor or MOSFET of the comparative example. After thermally oxidizing the (000-1) plane or the (11-20) plane of the silicon carbide substrate in a gas atmosphere of a compound containing nitrogen such as nitrous oxide (N ₂ O) or nitric oxide, hydrogen is removed. It is assumed that POA treatment is performed in a gas atmosphere containing the gas to reduce the interface state density and improve channel mobility. In this case, in order to prevent the hydrogen terminating the dangling bonds from desorbing, as shown in FIG. 16, it is desirable that the atmosphere at the time of temperature reduction of the POA treatment is an atmosphere containing hydrogen. However, since the number of electron traps increases in the oxide film that takes in excessive hydrogen, the threshold voltage may become unstable.

  In order to prevent excess hydrogen from being taken into the oxide film, it is preferable to purge the hydrogen with an inert gas when necessary and sufficient hydrogen is introduced into the interface between the oxide film and silicon carbide. However, when hydrogen is purged with an inert gas at the same temperature as the POA treatment, hydrogen terminated at the dangling bond is desorbed and the interface state density is increased, so that the channel mobility is decreased. The hydrogen introduced by the POA treatment is preferably present at the interface between the oxide film and silicon carbide in order to effectively terminate the interface state. In other words, hydrogen introduced by the POA process causes an electron trap, and therefore it is desirable that the amount of hydrogen in the gate insulating film is as small as possible.

In order to eliminate the above-described problems caused by the prior art, the present invention can improve the threshold voltage stability while maintaining the channel mobility without increasing the interface state density. An object is to provide a device and a method for manufacturing a silicon carbide semiconductor device .

In order to solve the above-described problems and achieve the object, a silicon carbide semiconductor device according to the present invention has an insulating film made of an oxynitride film on a silicon carbide semiconductor, and the silicon carbide semiconductor, the insulating film, Nitrogen is present at a peak concentration of 2 × 10 ²¹ / cm ³ or more in a region within 5 nm from the interface, and hydrogen is present at a concentration of 1 × 10 ²⁰ / cm ³ or more at the interface, and The hydrogen concentration does not exceed 5 × 10 ¹⁹ / cm ³ in the region of the insulating film 5 nm or more from the interface , and the insulating film is a gate insulating film of a MOSFET.

According to the present invention, since nitrogen and hydrogen necessary and sufficient for terminating the interface state are present at the interface between the silicon carbide semiconductor and the insulating film, the interface state existing at the interface between the silicon carbide semiconductor and the insulating film is present. Is terminated. The reason why the concentration of nitrogen and hydrogen existing at the interface between the silicon carbide semiconductor and the insulating film is 1 × 10 ²⁰ / cm ³ or more is that the interface state is sufficiently terminated when the concentration is lower than 1 × 10 ²⁰ / cm ^3. Because you can't. In addition, it is possible to suppress the presence of excess hydrogen that causes an electron trap in the insulating film. The reason why the hydrogen concentration in the insulating film is 5 × 10 ¹⁹ / cm ³ or less is that when it exceeds 5 × 10 ¹⁹ / cm ³ , excessive hydrogen causes an electron trap and makes the threshold voltage unstable. It is a cause.

According to the present invention, even in a MOSFET made of silicon carbide, the interface state existing at the interface between the silicon carbide semiconductor and the gate insulating film is terminated. It is possible to suppress the presence of excess hydrogen that causes an electron trap in the gate insulating film.

A silicon carbide semiconductor device according to the present invention is a vertical MOSFET in the above-described invention.

According to the present invention, even in a vertical MOSFET made of silicon carbide, the interface state existing at the interface between the silicon carbide semiconductor and the gate insulating film is terminated. It is possible to suppress the presence of excess hydrogen that causes an electron trap in the gate insulating film.

In order to solve the above-described problems and achieve the object, a method for manufacturing a silicon carbide semiconductor device according to the present invention includes a first step of forming an insulating film made of an oxynitride film on a silicon carbide semiconductor, and the insulation. A second step of performing a POA treatment on the film, and a third step of lowering the temperature to a furnace discharge temperature in a nitrogen atmosphere after the temperature is lowered to 50 ° C. or lower than the processing temperature of the POA treatment . Thereafter, nitrogen exists at a peak concentration of 2 × 10 ²¹ / cm ³ or more in a region within 5 nm from the interface between the silicon carbide semiconductor and the insulating film, and hydrogen exists at the interface at 1 × 10 ²⁰ / exist in cm ³ or more concentrations, and the hydrogen concentration in the region of 5nm or more of the insulating film from the surface does not exceed 5 × 10 ¹⁹ / cm ^3, wherein the insulating film is the gate insulating film of the MOSFET It is characterized by.

According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention, the stability of the threshold voltage can be improved while maintaining the channel mobility without increasing the interface state density. it can.

It is a figure which shows an example of the MOS capacitor concerning embodiment of this invention. It is a figure which shows distribution of the interface state density obtained by measuring the MOS capacitor concerning embodiment of this invention, and the MOS capacitor of a comparative example. It is sectional drawing which shows an example of the silicon carbide semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment of this invention. FIG. 5 is a cross-sectional view showing a continuation of FIG. 4. FIG. 6 is a cross-sectional view showing a continuation of FIG. 5. It is sectional drawing which shows the state of a continuation of FIG. FIG. 8 is a cross-sectional view illustrating a continuation of FIG. 7. FIG. 9 is a cross-sectional view illustrating a continuation of FIG. 8. FIG. 10 is a cross-sectional view showing a continuation of FIG. 9. It is sectional drawing which shows the state of a continuation of FIG. It is a figure which shows the gate voltage dependence of the field effect channel mobility obtained by measuring MOSFET concerning Embodiment of this invention and MOSFET of a comparative example. It is a figure which shows the stress application time dependence of the threshold voltage shift amount obtained by measuring MOSFET concerning Embodiment of this invention and MOSFET of a comparative example. It is a figure which shows the atmosphere and temperature change of heat processing in the manufacturing method of the silicon carbide semiconductor device concerning embodiment of this invention. It is a figure which shows the atmosphere and temperature change of heat processing at the time of manufacturing the MOS capacitor of a comparative example. It is a figure which shows the atmosphere and temperature change of heat processing at the time of manufacturing the MOS capacitor or MOSFET of a comparative example. It is a figure which shows the secondary ion mass spectrometry result of the silicon carbide semiconductor device concerning embodiment of this invention. It is sectional drawing which shows another example of the silicon carbide semiconductor device concerning embodiment of this invention.

Exemplary embodiments of a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached thereto. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

Experimental example for verifying that interface state density does not increase First, in order to verify that the interface state density does not increase according to the present invention, an experimental example using a MOS capacitor is shown in FIGS. 2. It demonstrates using FIG. 14 ~ FIG. FIG. 1 is a diagram showing an example of a MOS capacitor according to an embodiment of the present invention.

This MOS capacitor is manufactured as follows.
(1) Step 1
First, an n-type epitaxial film 102 having a donor density of about 1 × 10 ¹⁶ / cm ^{3 is formed} on an n-type 4H—SiC (000-1) substrate 101 (0 to 8 degrees off substrate from the (000-1) plane). Grow 10 μm. Note that the 4H—SiC substrate alone or the 4H—SiC substrate 101 and the epitaxial film 102 are collectively referred to as a 4H—SiC semiconductor.

(2) Step 2
After cleaning the 4H—SiC semiconductor, an oxynitriding treatment in an atmosphere containing nitrous oxide at 1300 ° C. is performed for 100 minutes to form the insulating film 103 with a thickness of 50 nm. Insulating in an atmosphere of nitrous oxide or nitric oxide diluted with an inert gas after forming an insulating film of about 50 nm by dry oxidation in a dry oxygen atmosphere, wet oxidation using pyrogenic, deposited film by CVD method, etc. The insulating film 103 may be formed by oxynitriding the interface between the film and SiC.

(3) Process 3
FIG. 14 is a diagram showing a heat treatment atmosphere and temperature changes in the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present invention. As the POA treatment, as shown in FIG. 14, the temperature was raised to 1100 ° C. in an atmosphere containing hydrogen, and then heat treatment was performed by holding for 30 minutes. After the temperature was lowered to a predetermined temperature, the atmosphere was purged with nitrogen to form an inert gas atmosphere. After holding in an inert gas atmosphere for 60 minutes, the temperature was lowered to the furnace discharge temperature. The temperature for purging with nitrogen and maintaining in an inert gas atmosphere was 1000 ° C. and 1050 ° C. The temperature of the heat treatment in the atmosphere containing hydrogen is set to 800 to 1200 ° C, preferably 900 to 1100 ° C. The heat treatment time is preferably 10 minutes to 180 minutes. The reason is that the reaction does not proceed at a temperature lower than 800 ° C., and the dangling bond cannot be sufficiently terminated with hydrogen, and the insulating film may be etched by hydrogen at a temperature higher than 1200 ° C. The temperature range for purging and holding with an inert gas is 700 ° C. to 1050 ° C., preferably 700 to 1000 ° C. The temperature for purging and holding with an inert gas during cooling is preferably lower by 50 ° C. or more than the heat treatment temperature of the atmosphere containing hydrogen. The reason is that when purging with an inert gas at the same temperature as the heat treatment in an atmosphere containing hydrogen, hydrogen terminated with dangling bonds is desorbed. Moreover, it is because excess hydrogen cannot be expelled efficiently at the temperature below 700 degreeC. The time for purging and holding with an inert gas is preferably 10 minutes to 180 minutes. The atmosphere at the time of temperature rise may be an inert gas atmosphere, and after the temperature rise, the atmosphere may be switched from an inert gas atmosphere to an atmosphere containing hydrogen. Further, in the heat treatment atmosphere, hydrogen may be diluted with an inert gas. The inert gas may be nitrogen, helium (He), or argon (Ar).

(4) Step 4
On the insulating film 103, a dot-shaped aluminum gate electrode 104 was deposited at room temperature, and a MOS capacitor composed of an aluminum back electrode 105 in which aluminum was deposited on the entire back surface of the 4H-SiC semiconductor was fabricated.

  FIG. 15 is a diagram showing the atmosphere and temperature change of the heat treatment when manufacturing the MOS capacitor of the comparative example. Here, in order to verify the MOS interface state according to this experimental example, as a comparative example, the POA process in Step 3 is performed with a nitrogen purge at 1100 ° C. for 60 minutes, which is the same as the heat treatment in an atmosphere containing hydrogen, as shown in FIG. A retained MOS capacitor was fabricated. In addition, as shown in FIG. 16, a MOS capacitor was produced in which the temperature was lowered to the furnace discharge temperature in an atmosphere containing hydrogen. Further, a MOS capacitor that did not perform the POA process in step 3 was also produced. Each completed MOS capacitor was measured with a C-V meter 106, and the interface state density was calculated and compared.

FIG. 2 is a diagram showing the distribution of interface state density obtained by measuring the MOS capacitor according to the embodiment of the present invention and the MOS capacitor of the comparative example. In FIG. 2, the vertical axis represents the interface state density (unit: / cm ² / eV), and the horizontal axis represents the energy from the conduction band (unit: eV). As shown in FIG. 2, there are a MOS capacitor having a nitrogen purge temperature of 1000 ° C. (plotted with ○) and 1050 ° C. (plotted with ◇), and a MOS capacitor that has been cooled in a hydrogen atmosphere (plotted with a Δ mark). There is no significant difference in the interface state density, and there is no deterioration of the MOS interface characteristics due to nitrogen purge. On the other hand, a MOS capacitor purged with nitrogen at 1100 ° C. (plotted with □), which is the same as the heat treatment in a hydrogen atmosphere, is not as large as a MOS capacitor without POA treatment (plotted with x), but the interface state density increases, and the MOS capacitor Interface characteristics are degraded. Thus, by purging nitrogen at a temperature lower by 50 ° C. or more after the heat treatment in an atmosphere containing hydrogen, hydrogen terminating the dangling bonds is not desorbed, and the interface state density does not increase. I was able to confirm.

FIG. 3 is a cross-sectional view showing an example of the silicon carbide semiconductor device according to the embodiment of the present invention. As shown in FIG. 3, the silicon carbide semiconductor device includes a p ⁺ silicon carbide substrate 1 and a p epitaxial film 2.

The p ⁺ silicon carbide substrate 1 may be, for example, a silicon carbide single crystal substrate obtained by doping silicon carbide with a p-type impurity. The p ⁺ silicon carbide substrate 1 may be, for example, a p-type 4H—SiC (000-1) substrate. The p ⁺ silicon carbide substrate 1 has, for example, a (000-1) plane front surface, and an off angle from the (000-1) plane is 0 to 8 degrees, preferably 0 to 4 degrees. May be. The front surface of the p ⁺ silicon carbide substrate 1 may be, for example, a (11-20) plane.

The p epitaxial film 2 is provided on the front surface of the p ⁺ silicon carbide substrate 1. The impurity concentration of p epitaxial film 2 is lower than that of p ⁺ silicon carbide substrate 1. The acceptor density of the p epitaxial film 2 may be, for example, about 1 × 10 ¹⁶ / cm ³ . The p epitaxial film 2 may be an epitaxial film in which, for example, silicon carbide is doped with a p-type impurity. The p epitaxial film 2 is an example of a silicon carbide semiconductor.

The silicon carbide semiconductor device has, for example, an n ⁺ drain region 3, an n ⁺ source region 4, a p ⁺ ground region 5, a gate insulating film 6, and a gate electrode on the front surface side of the p ⁺ silicon carbide substrate 1 as a MOS structure. 7. Reaction layers 8 and 9 are provided.

The n ⁺ drain region 3 is selectively provided in the surface region of the p epitaxial film 2. The n ⁺ drain region 3 includes, for example, phosphorus (P) as an n-type impurity.

The n ⁺ source region 4 is selectively provided in the surface region of the p epitaxial film 2 away from the n ⁺ drain region 3. The n ⁺ source region 4 includes, for example, phosphorus as an n-type impurity.

The p ⁺ ground region 5 is selectively provided in the surface region of the p epitaxial film 2 away from the n ⁺ drain region 3 and in contact with the n ⁺ source region 4. The impurity concentration of p ⁺ ground region 5 is higher than that of p epitaxial film 2. The p ⁺ ground region 5 includes, for example, aluminum (Al) as a p-type impurity.

The gate insulating film 6 is provided on the surface of a region sandwiched between the n ⁺ drain region 3 and the n ⁺ source region 4 of the p epitaxial film 2. The gate insulating film 6 may be made of one layer or two or more layers. The gate insulating film 6 may include a nitride film. The gate insulating film 6 may include an oxynitride film. The gate insulating film 6 may include a nitride film and an oxynitride film. The thickness of the gate insulating film 6 may be about 50 nm, for example. The gate insulating film 6 is an example of an insulating film.

Both nitrogen and hydrogen are present at a concentration of 1 × 10 ²⁰ / cm ³ or more at the interface between the gate insulating film 6 and the p epitaxial film 2. The hydrogen concentration in the gate insulating film 6 is 5 × 10 ¹⁹ / cm ³ or less.

  The gate electrode 7 is provided on the surface of the gate insulating film 6. The gate electrode 7 may be made of, for example, polycrystalline silicon. The thickness of the gate electrode 7 may be about 0.3 μm, for example.

The reaction layer 8 on the n ⁺ drain region 3 is in contact with the surface of the n ⁺ drain region 3. The reaction layer on the n ⁺ drain region 3 8 is electrically connected to the n ⁺ drain region 3.

n ⁺ reaction layer 9 over the source region 4 is in contact with the surface of the n ⁺ source region 4 and p ⁺ ground region 5. n ⁺ reaction layer 9 over the source region 4 is electrically connected to the n ⁺ source region 4 and p ⁺ ground region 5.

  The reaction layers 8 and 9 are insulated from the gate electrode 7 by an interlayer insulating film (not shown). The reaction layers 8 and 9 are layers formed by the reaction of contact metal and silicon carbide. The contact metal may be made of, for example, a nickel (Ni) layer laminated on an aluminum layer.

  The silicon carbide semiconductor device includes pad electrodes 10, 11, 12, a field oxide film 13, and a back electrode 14.

  The pad electrode 10 is provided on the gate electrode 7, for example. The pad electrode 10 on the gate electrode 7 is electrically connected to the gate electrode 7. The pad electrode 10 may be made of aluminum, for example. The thickness of the pad electrode 10 may be about 300 nm, for example.

The pad electrode 11 is provided on the reaction layer 8 on the n ⁺ drain region 3, for example. The pad electrode 11 on the reaction layer 8 is electrically connected to the reaction layer 8. The pad electrode 11 may be made of aluminum, for example. The thickness of the pad electrode 11 may be about 300 nm, for example.

The pad electrode 12 is provided on the reaction layer 9 on the n ⁺ source region 4, for example. The pad electrode 12 on the reaction layer 9 is electrically connected to the reaction layer 9. The pad electrode 12 may be made of aluminum, for example. The thickness of the pad electrode 12 may be about 300 nm, for example.

  The field oxide film 13 is provided outside the active region 15. The thickness of the field oxide film 13 may be about 0.5 μm, for example.

The silicon carbide semiconductor device includes a back electrode 14 on the back surface of the p ⁺ silicon carbide substrate 1. The back electrode 14 is in ohmic contact with the p ⁺ silicon carbide substrate 1. The back electrode 14 may be made of aluminum, for example. The thickness of the back electrode 14 may be about 100 nm, for example.

  Next, an embodiment of the present invention will be described with reference to FIGS.

Example 1
FIG. 4 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment of the present invention. FIG. 5 is a cross-sectional view showing a continuation of FIG. 6 is a cross-sectional view showing a continuation of FIG. FIG. 7 is a cross-sectional view showing a continuation of FIG. FIG. 8 is a sectional view showing a continuation of FIG. FIG. 9 is a cross-sectional view showing a continuation of FIG. FIG. 10 is a cross-sectional view showing a continuation of FIG. FIG. 11 is a cross-sectional view showing a continuation of FIG.

(1) Step 1
First, as shown in FIG. 4, a p ⁺ silicon carbide substrate 1 is prepared. The p ⁺ silicon carbide substrate 1 is a p-type 4H—SiC (000-1) substrate (0 to 8 degrees off substrate from the (000-1) plane, preferably 0 to 4 degrees off substrate). A p epitaxial film 2 having an acceptor density of about 1 × 10 ¹⁶ / cm ³ is grown on the front surface of the p ⁺ silicon carbide substrate 1.

(2) Step 2
Next, as shown in FIG. 5, a SiO ₂ film having a thickness of, for example, about 1 μm is deposited on the surface of the p epitaxial film 2 by, for example, a low pressure CVD method. Then, the SiO ₂ film is patterned by photolithography to form a mask 21. Thereafter, for example, phosphorus ions 22 are ion-implanted into the surface of the p epitaxial film 2 through the mask 21. The conditions at the time of ion implantation may be, for example, that the substrate temperature is about 500 ° C., the acceleration energy is about 40 keV to about 250 keV, and the implantation amount is about 2 × 10 ²⁰ / cm ³ . As a result of this ion implantation, a part of the surface region of the p epitaxial film 2 becomes the first ion implantation region 23 and the second ion implantation region 24 as indicated by broken lines in FIG. The first ion implantation region 23 and the second ion implantation region 24 become, for example, an n ⁺ drain region 3 and an n ⁺ source region 4 through heat treatment to be described later.

(3) Process 3
Next, after removing the mask 21, as shown in FIG. 6, a SiO ₂ film having a thickness of about 1 μm, for example, is deposited on the surface of the p epitaxial film 2 by, for example, a low pressure CVD method. Then, this SiO ₂ film is patterned by photolithography to form a mask 25. Thereafter, for example, aluminum ions 26 are ion-implanted into the surface of the p epitaxial film 2 through the mask 25. The conditions at the time of ion implantation may be, for example, a multi-stage where the substrate temperature is about 500 ° C., the acceleration energy is about 40 keV to 200 keV, and the implantation amount may be 2 × 10 ²⁰ / cm ³ . As a result of this ion implantation, a part of the surface region of the p epitaxial film 2 becomes the third ion implantation region 27 as indicated by a broken line in FIG. The third ion implantation region 27 becomes the p ⁺ ground region 5 through, for example, a heat treatment described later.

(4) Step 4
Next, after removing the mask 25, activation annealing is performed in an inert gas atmosphere such as an argon atmosphere, for example, so that the first ion implantation region 23, the second ion implantation region 24, and the third ion implantation region 27 are formed. Activate. Accordingly, as shown in FIG. 7, the first ion implantation region 23 becomes the n ⁺ drain region 3. The second ion implantation region 24 becomes the n ⁺ source region 4. The third ion implantation region 27 becomes the p ⁺ ground region 5. The temperature of the heat treatment may be about 1600 ° C., for example. The heat treatment time may be, for example, about 5 minutes.

(5) Process 5
Next, as shown in FIG. 8, a field oxide film 13 having a thickness of, for example, about 0.5 μm is deposited on the surface of the p epitaxial film 2 by, for example, a low pressure CVD method. Then, a part of the field oxide film 13 is removed by photolithography and wet etching to form an active region 15. In the active region 15, the n ⁺ drain region 3, the n ⁺ source region 4 and the p ⁺ ground region 5 are exposed.

(6) Step 6
Next, as shown in FIG. 9, for example, oxynitridation is performed for about 100 minutes in an atmosphere containing nitrous oxide (N ₂ O) at a temperature of about 1300 ° C., for example, and a gate insulating film having a thickness of, for example, about 50 nm. 6 is formed. Subsequently, as shown in FIG. 14, as POA treatment, the temperature is raised to 1100 ° C. in a hydrogen atmosphere and then heat-treated by holding for 30 minutes. After the temperature is lowered to 1000 ° C., the atmosphere is purged with nitrogen to form an inert gas atmosphere. did. And after hold | maintaining in inert gas atmosphere for 60 minutes, it temperature-falls to the furnace discharge temperature. Thereafter, for example, polycrystalline silicon having a thickness of about 0.3 μm is deposited on the gate insulating film 6 by, for example, a low pressure CVD method. Then, the polycrystalline silicon is patterned by photolithography to form the gate electrode 7.

(7) Step 7
Next, as shown in FIG. 10, contact holes 28 are formed on the n ⁺ drain region 3, the n ⁺ source region 4 and the p ⁺ ground region 5 by photolithography and hydrofluoric acid etching. Subsequently, for example, aluminum having a thickness of about 10 nm is deposited on the entire surface on the side where the gate electrode 7 is provided, and nickel having a thickness of about 60 nm is further deposited. Then, nickel and aluminum are patterned by lift-off to form a contact metal 29 in the contact hole 28.

(8) Step 8
Next, as shown in FIG. 11, as the ohmic contact annealing, annealing is performed in an inert gas atmosphere at a temperature of, for example, about 950 ° C. for a time of, for example, about 2 minutes, and the reaction between the contact metal 29 and silicon carbide is performed. Layers 8 and 9 are formed. The inert gas may be nitrogen, helium, or argon.

(9) Step 9
Next, for example, aluminum having a thickness of about 300 nm is deposited on the entire surface on the side where the gate electrode 7 is provided. Then, as shown in FIG. 3, pad electrodes 10, 11 and 12 are formed on the gate electrode 7 and the reaction layers 8 and 9 by photolithography and phosphoric acid (H ₃ PO ₄ ) etching. Further, the back electrode 14 is formed on the back surface of the p ⁺ silicon carbide substrate 1 by vapor-depositing, for example, aluminum having a thickness of about 100 nm. In this way, the silicon carbide MOSFET shown in FIG. 3 is completed.

Example 2
A silicon carbide MOSFET was manufactured by the same manufacturing method as in Example 1 except that the temperature purged with nitrogen and maintained in the inert gas atmosphere in Step 6 of Example 1 was 700 ° C.

Comparative Example In the above-described Step 6 of Example 1, the POA treatment is the same as in Example 1 except that the furnace temperature is lowered to 600 ° C. in an atmosphere containing hydrogen as shown in FIG. A silicon carbide MOSFET was manufactured.

Evaluation of Field Effect Channel Mobility FIG. 12 is a diagram showing the gate voltage dependence of the field effect channel mobility obtained by measuring the MOSFET according to the embodiment of the present invention and the MOSFET of the comparative example. In FIG. 12, the vertical axis represents field effect channel mobility (unit: cm ² / Vs), and the horizontal axis represents gate voltage (unit: V). As shown in FIG. 12, the maximum value of channel mobility is slightly higher in Example 1 and Example 2 than in the comparative example. Therefore, even if nitrogen purge is performed in the middle of the temperature lowering of the heat treatment in an atmosphere containing hydrogen, hydrogen that terminates the interface state is not desorbed and the interface state density does not increase.

Evaluation of threshold voltage shift amount As an indicator of threshold voltage stability, the threshold voltage shift amount after applying a 3 MV / cm stress to the gate insulating film for a predetermined time was evaluated.

  FIG. 13 is a diagram showing the stress application time dependence of the threshold voltage shift amount obtained by measuring the MOSFET according to the embodiment of the present invention and the MOSFET of the comparative example. In FIG. 13, the vertical axis represents the threshold voltage shift amount (unit: V), and the horizontal axis represents the stress application time (unit: sec). As shown in FIG. 13, since the shift amount of the threshold voltage is smaller in Example 1 and Example 2 than in the comparative example, Example 1 and Example 2 are more effective than the comparative example. The threshold voltage is stable. Further, the threshold voltage shift amount is larger in Example 2 purged at 700 ° C. than in Example 1 purged at 1000 ° C. Therefore, there is a tendency that excessive hydrogen cannot be expelled by purging at a low temperature. The furnace temperature in the comparative example is 600 ° C., whereas the 700 ° C. purge in Example 2 is effective in improving the stability of the threshold voltage, so the temperature for purging with an inert gas is 700 ° C. It is preferable that the temperature is not lower than ° C.

  In each of the embodiments described above, a (000-1) substrate (0 to 8 degrees off substrate) having a crystal structure of 4H—SiC was used, but a (11-20) substrate having a crystal structure of 4H—SiC was used. However, the same effect can be obtained.

・ Evaluation of nitrogen concentration and hydrogen concentration in the vicinity of the SiO ₂ / SiC interface POA treatment in an atmosphere containing hydrogen Stability of threshold voltage while maintaining channel mobility without increasing interface state density The nitrogen concentration and the hydrogen concentration in the vicinity of the SiO ₂ / SiC interface that were able to be obtained were measured by secondary ion mass spectrometry (SIMS).

FIG. 17 is a diagram showing a result of secondary ion mass spectrometry of the silicon carbide semiconductor device according to the embodiment of the present invention. FIG. 17 shows the result of SIMS analysis on the SiO ₂ film formed on the (000-1) -SiC substrate according to Step 6 of Example 1 described above. In FIG. 17, the vertical axis on the left is the concentration of nitrogen (N) and hydrogen (H) (unit: atoms / cm ³ ), and the vertical axis on the right is the secondary ion intensity (unit: count) of oxygen and carbon. Yes, the horizontal axis represents the depth of analysis (unit: nm). Cesium (Cs) was used as the primary ion species of SIMS. As shown in FIG. 17, the left half has a high secondary ion intensity of oxygen and the right half has a high carbon secondary ion intensity. Therefore, the left region is SiO ₂ and the right region is SiC. In the vicinity of the SiO ₂ / SiC interface, it was confirmed that both hydrogen and nitrogen had a peak with a concentration of 1 × 10 ²⁰ / cm ³ or more. It was also confirmed that the hydrogen concentration in the SiO ₂ film was a low value of 5 × 10 ¹⁹ / cm ³ or less.

Nitrogen or hydrogen that terminates the interface state is preferably present only at the SiO ₂ / SiC interface, and preferably has a concentration of 1 × 10 ²⁰ atoms / cm ³ or more. This is because if the concentration of nitrogen or hydrogen is lower than 1 × 10 ²⁰ atoms / cm ³ , the interface state cannot be terminated sufficiently.

The hydrogen concentration in the SiO ₂ film is preferably 5 × 10 ¹⁹ atoms / cm ³ or less. This is because if the hydrogen concentration in the SiO ₂ film exceeds 5 × 10 ¹⁹ atoms / cm ³ , excess hydrogen causes electron trapping and the threshold voltage becomes unstable.

  As described above, according to the embodiment, since nitrogen and hydrogen necessary and sufficient for terminating the interface state exist at the interface between the p epitaxial film 2 and the gate insulating film 6, The interface state existing at the interface with the gate insulating film 6 is terminated. In addition, since it is possible to suppress the presence of excessive hydrogen that causes an electron trap in the gate insulating film 6, the threshold voltage is stabilized. Therefore, the stability of the threshold voltage can be improved while maintaining the channel mobility without increasing the interface state density.

As described above, the present invention is not limited to the embodiment described above, and various modifications can be made. For example, the numerical values described in the embodiments are examples, and the present invention is not limited to these values. Further, the present invention is not limited to a lateral silicon carbide semiconductor device using the p ⁺ silicon carbide substrate 1. For example, the present invention can be applied to a semiconductor device having a high breakdown voltage structure, such as a vertical silicon carbide semiconductor device using an n ⁺ silicon carbide substrate, or a silicon carbide semiconductor device having a trench gate structure or a complicated MOS gate structure. .

  An example of a complex MOS gate structure is an element structure that forms a channel in the vicinity of the surface of a SiC epitaxial substrate in the on state, as shown in FIG. 18, for example.

FIG. 18 is a cross-sectional view showing another example of the silicon carbide semiconductor device according to the embodiment of the present invention. As shown in FIG. 18, the silicon carbide semiconductor device includes an n ⁺ silicon carbide substrate 31 and an n epitaxial film 32. The n ⁺ silicon carbide substrate 31 may be, for example, a silicon carbide single crystal substrate obtained by doping silicon carbide with an n-type impurity. The n ⁺ silicon carbide substrate 31 becomes a drain region, for example.

The n epitaxial film 32 is provided on the front surface of the n ⁺ silicon carbide substrate 31. The impurity concentration of n epitaxial film 32 is lower than that of n ⁺ silicon carbide substrate 31. The n epitaxial film 32 becomes, for example, an n-type drift region.

The silicon carbide semiconductor device has, for example, a p region 33, a pSiC layer 34, an n ⁺ source region 35, a p ⁺ contact region 36, a gate insulating film 37, a gate electrode 38, on the front surface side of the n ⁺ silicon carbide substrate 31. A source electrode 39 and an n region 40 are provided. The silicon carbide semiconductor device includes a back electrode to be a drain electrode 41 on the back surface side of the n ⁺ silicon carbide substrate 31, for example.

  The p region 33 is provided in a part of the surface region of the n epitaxial film 32. The p region 33 may be provided so as to sandwich another part of the surface region of the n epitaxial film 32, for example. In other words, there may be a region of the n epitaxial film 32 between the adjacent p region 33 and p region 33.

The p SiC layer 34 is provided on the surface of the p region 33 and the region of the n epitaxial film 32 existing between the adjacent p region 33 and the p region 33. The impurity concentration of the p SiC layer 34 is lower than that of the p region 33. In the p SiC layer 34, a portion excluding the n ⁺ source region 35, the p ⁺ contact region 36, and the n region 40 becomes a p-type base region together with the p region 33. The pSiC layer 34 is an example of a silicon carbide semiconductor.

  The n region 40 is provided on the surface of the region between the adjacent p region 33 and the p region 33 of the n epitaxial film 32. The n region 40 penetrates the p SiC layer 34 and is in contact with the n epitaxial film 32. The impurity concentration of the n region 40 is preferably higher than that of the n epitaxial film 32. For example, the n region 40 may be a region obtained by inverting the conductivity type of a part of the p SiC layer 34 by ion implantation of n type impurities and heat treatment. For example, the n region 40 becomes an n type drift region together with the n epitaxial film 32.

The n ⁺ source region 35 is provided in the surface region of the pSiC layer 34 on the p region 33. The n ⁺ source region 35 is provided away from the n region 40.

The p ⁺ contact region 36 is provided on the opposite side of the n region 40 across the n ⁺ source region 35. The p ⁺ contact region 36 is in contact with the p SiC layer 34 and the n ⁺ source region 35. The p ⁺ contact region 36 penetrates the p SiC layer 34 and contacts the p region 33. The impurity concentration of the p ⁺ contact region 36 is higher than that of the pSiC layer 34.

Gate insulating film 37 is provided on the surface of the region sandwiched between n region 40 and n ⁺ source region 35 of pSiC layer 34. The gate insulating film 37 may be provided on the surface of the p SiC layer 34 and the n region 40 between the adjacent n ⁺ source region 35 and the n ⁺ source region 35, for example. The gate insulating film 37 is an example of an insulating film.

  The gate electrode 38 is provided on the surface of the gate insulating film 37.

The source electrode 39 is provided in contact with the surfaces of the n ⁺ source region 35 and the p ⁺ contact region 36. The source electrode 39 is electrically connected to the n ⁺ source region 35 and the p ⁺ contact region 36. The source electrode 39 is insulated from the gate electrode 38 by an interlayer insulating film (not shown).

Drain electrode 41 is provided in contact with the back surface of n ⁺ silicon carbide substrate 31. Drain electrode 41 is in ohmic contact with n ⁺ silicon carbide substrate 31.

As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are not limited to lateral MOSFETs, but also semiconductor devices having a high breakdown voltage structure such as vertical MOSFETs, trench gate structures, and complex MOSs. The present invention can be applied to a MOSFET having a gate structure, and the same effect can be obtained. Therefore, the present invention can be applied to various silicon carbide semiconductor devices and silicon carbide semiconductor device manufacturing methods without departing from the scope of the present invention described in the claims.

1 p ⁺ silicon carbide substrate 2 p epitaxial film 3 n ⁺ drain region 4, 35 n ⁺ source region 5 p ⁺ ground region 6, 37 gate insulating film 7, 38 gate electrode 8, 9 reaction layer 10, 11, 12 pad electrode 13 Field oxide film 14 Back electrode 15 Active region 21, 25 Mask 22 Phosphorus ion 23 First ion implantation region 24 Second ion implantation region 26 Aluminum ion 27 Third ion implantation region 28 Contact hole 29 Contact metal 31 n ⁺ carbonization Silicon substrate 32 n epitaxial film 33 p region 34 p SiC layer 36 p ⁺ contact region 39 source electrode 40 n region 41 drain electrode 101 n-type 4H—SiC (000-1) substrate 102 n-type epitaxial film 103 insulating film 104 aluminum gate electrode 105 Aluminum back electrode 10 6 C-V meter

Claims (3)

Having an insulating film made of an oxynitride film on the silicon carbide semiconductor;
Nitrogen is present at one peak concentration of 2 × 10 ²¹ / cm ³ or more in a region within 5 nm from the interface between the silicon carbide semiconductor and the insulating film, and hydrogen is 1 × 10 ²⁰ / cm ^{3 at the} interface. And the hydrogen concentration does not exceed 5 × 10 ¹⁹ / cm ³ in the region of the insulating film 5 nm or more from the interface .
The silicon carbide semiconductor device, wherein the insulating film is a gate insulating film of a MOSFET.   The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is a vertical MOSFET. A first step of forming an insulating film made of an oxynitride film on the silicon carbide semiconductor;
A second step of performing POA treatment on the insulating film;
A third step in which the temperature is lowered to a temperature lower than the processing temperature of the POA treatment by 50 ° C. or more and then lowered to a furnace discharge temperature in a nitrogen atmosphere;
Including
After the three steps,
Nitrogen is present at one peak concentration of 2 × 10 ²¹ / cm ³ or more in a region within 5 nm from the interface between the silicon carbide semiconductor and the insulating film, and hydrogen is 1 × 10 ²⁰ / cm ^{3 at the} interface. And the hydrogen concentration does not exceed 5 × 10 ¹⁹ / cm ³ in the region of the insulating film 5 nm or more from the interface .
The method for manufacturing a silicon carbide semiconductor device, wherein the insulating film is a gate insulating film of a MOSFET.

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