JP6432472B2 - Power switching device - Google Patents

Description

  The present invention relates to a power supply switching device for alternately switching two AC power supplies and supplying power to a load.

    In general, when power is supplied to a load from an AC power source including an inverter, the AC power source including the inverter is switched from the AC power source including the inverter to a commercial AC power source when the inverter is broken or inspected, and power is supplied from the commercial AC power source to the load.

    Thus, when switching between two power supplies instantaneously, the voltage fluctuation accompanying a load fluctuation generate | occur | produces and a cross current flows between power supplies.

Conventionally, devices disclosed in Patent Documents 1 and 2 are known as power supply switching devices for suppressing such voltage fluctuations and cross currents. However, this conventional power source switching device includes a synchronous switching unit that performs switching by synchronizing the voltage of the power source including the inverter with the voltage of the other commercial AC power source, a cross current suppressing unit that suppresses the cross current, and the like. Therefore, there is a problem that the configuration becomes complicated.

Japanese Patent Laid-Open No. 09-019065 Japanese Patent Publication No. 07-004052

  In order to solve the problems in the above-described conventional device, the present invention has a configuration that can reliably prevent the occurrence of a cross current at the time of power switching without providing a synchronous switching means or a cross current suppressing means for suppressing a cross current. It is an object to provide a simple power supply switching device.

  In order to solve the above-described problems, the present invention provides a power supply switch in each of two power supply circuits that supply power to a common load from each of the first and second AC power supplies, and by switching these power supply switches. In the power supply switching device for switching the power supply for supplying power to the load, the two power supply switches are configured by connecting two thyristor elements in parallel with opposite polarities, respectively, and are switched on when switching the power supply by switching the two power supply switches. A gate-off signal is given to each thyristor of one feeding switch that is turned on, a gate-on signal is given to each thyristor of the other feeding switch that is turned off after each thyristor of the feeding switch on the turned-on side is turned off, Each thyristor is turned on.

  In the present invention, as means for detecting that each thyristor in the on-side power supply switch is turned off, polarity determination means for determining inversion of the polarity of the current flowing through the power supply switch, and the power supply switch And a zero current detector for detecting that the flowing current is almost zero.

  According to the present invention, when switching the power supply by switching on and off the power supply switch composed of thyristor elements provided in the two power supply circuits that supply power to the common load from the two AC power supplies, the power supply is switched on. Since the off command is given to one of the power supply switches, and the thyristor is turned off, the on command is given to the thyristor of the other power feed switch that is turned off, so that the thyristor is turned on. Without providing a special cross current suppressing device, it is possible to prevent a cross current from flowing between the power sources when the power source is switched. For this reason, the configuration of the switching device can be simplified.

It is a circuit block diagram which shows the Example of this invention. It is an operation | movement waveform diagram of the Example of this invention.

  Embodiments of the present invention will be described with reference to the embodiments shown in the drawings.

  FIG. 1 shows an embodiment of a power supply switching device according to the present invention, and is a configuration diagram showing one phase of a three-phase AC circuit.

  In FIG. 1, reference numerals 1 and 2 denote first and second AC power supplies. From each of the two AC power sources, the power supply paths 11 and 21 are switched to supply power to the common load 5. The power feed paths 11 and 21 are provided with current detectors 12 and 22 and power feed switches 3 and 4 for selectively switching power feed paths to the load 5, respectively. The power feeding switches 3 and 4 are each configured by connecting two thyristors in parallel with 3P, 3N and 4P, 4N in reverse polarity.

  Switching control circuits 30 and 40 are attached to the power supply switches 3 and 4, respectively. The switching control circuits 30 and 40 are configured so that when one power feeding switch is turned on by an external switching command, the other power feeding switch is turned off and the two power feeding switches 3 and 4 are not turned on at the same time. The power supply switches 3 and 4 are turned on and off.

  The switching control circuit 30 turns on (“1”) the gate signals G3P and G3N to the thyristors 3P and 3N of the power supply switch 3 in response to an ON command ON3 to the power supply switch 3, and gates the power supply switch 4 to the thyristors 4P and 4N. The operation of turning off the signals G4P and G4N (“0”) is performed. Then, the switching control circuit 40 turns on (“1”) the gate signals G4P and G4N to the thyristors 4P and 4N of the power supply switch 4 in response to an ON command ON4 to the power supply switch 4 to the thyristors 3P and 3N of the power supply switch 3. The gate signals G3P and G3N are turned off (“0”).

  Since the switching control circuits 30 and 40 have the same configuration, the configuration of the switching control circuit 30 will be described, and the reference numerals of the same components of the switching control circuit 40 are also shown in parentheses.

  The polarity discriminators 31P and 31N (41P and 41N) discriminate the polarity reversal of the current by comparing the alternating current I2 (I1) of the power feeding path 22 (12) with a preset reference value 0. The polarity discriminator 31P (41P) of the switching control circuit 30 (40) is connected to the AC current I2 (I1) of the power supply path 21 (11) detected by the current detector 22 (12) on the other AC power supply 2 (1) side. ) Outputs a determination signal that is “1” when the polarity is inverted from positive to negative, and outputs a determination signal that is “0” otherwise. In the polarity discriminator 31N (41N), the AC current I2 (I1) of the power supply path 21 (11) detected by the current detector 22 (12) on the other party AC power supply 2 (1) side is inverted from negative to positive. When it is determined that it has been performed, a determination signal that is “1” is output, and in other cases, a determination signal that is “0” is output. The discrimination outputs of the polarity discriminators 31P and 31N (41P and 41N) are applied to one input terminals of AND gates 32P and 32N (42P and 42N), respectively.

  On the other input terminal of the AND gates 32P, 32N (42P, 42N), an ON command ON4 (ON3) for the power supply switch 4 (3) applied to the command input terminal S41 (S31) of the counterpart switching control circuit 40 (30). ) Is added via the knot circuit 38 (48). Therefore, when the ON command ON4 (ON3) is OFF (“0”), the outputs of the polarity discriminators 31P and 31N (41P and 41N) are taken out from the AND gates 32P and 32N (42P and 42N).

  In the flip-flops 34P and 34N (44P and 44N), the discrimination outputs of the polarity discriminators 31P and 31N (41P and 41N) are “1” to the set input terminal S added via the AND gates 32P and 32N (42P and 42N). Set when. When the flip-flops 34P and 34N (44P and 44N) are set, the gate-on permission signals GA3P and GA3N (GA4P and GA4N) are set to “1” and held. When the gate-on permission signals GA3P and GA3N (GA4P and GA4N) output from the flip-flops 34P and 34N are turned on (“1”), the AND gates 35P and 35N (45P and 45N) are opened, and the power supply switch 3 (4) An ON command ON3 (ON4) is applied to the gates of thyristors 3P and 3N (4P and 4N) as gate signals G3P and G3N (G4P and G4N).

  Since the ON command ON3 (ON4) for the feed switch 3 (4) is applied to the reset input terminal R of the flip-flops 34P and 34N (44P and 44N) via the knot circuit 37 (47), the flip-flops 34P and 34N (44P, 44N) is reset when the ON command ON3 (ON4) is turned off ("0"), and turns off the held gate-on permission signals GA3P, GA3N (GA4P, GA4N). As a result, the AND gates 35P and 35N (45P and 45N) are closed, and the gate signals G3P and G3N (G4P and G4N) applied to the gates of the thyristors of the switch 3 (4) are turned off (“0”).

  The switching control circuit 30 (40) further includes a switch-off detector 36 (46) that detects that the power feeding switch 3 (4) is turned off. The switch-off detector 36 (46) outputs a detection signal that becomes “1” when the current I2 (I1) of the power supply path 21 (11) detected by the current detector 22 (12) becomes almost zero. The generated zero current detector 36I (46I) and a delay circuit 36D (46D) that delays the output signal of the zero current detector 36I (46I) by a predetermined time α.

  The output of the switch-off detector 36 (46) is applied to the set input terminal S of the flip-flops 34P and 34N (44P and 44N) via the AND gate 36A (46A) and the OR gates 33P and 33N (43P and 43N). . An ON command ON4 (ON3) for the other power supply switch 4 (3) is applied to the other input terminal of the AND gate 36A (46A) via a knot circuit 38 (48). For this reason, the AND gate 36A (46A) is opened together with the AND gates 32P and 32N (42P and 42N) when the ON command ON4 (ON3) for the other power supply switch 4 (3) is OFF (“0”). For this reason, only when the ON command ON4 (ON3) of the power supply switch 4 (3) is OFF (“0”), the output signal DI3 (DI4) of the zero current detector 36 (46) is OR gates 33P and 33N (43P). 43N) to the set input terminal S of the flip-flops 34P, 34N (44P, 44N).

  Next, the operation of the power supply switching device of the present invention configured as described above will be described with reference to the operation waveform diagram shown in FIG.

  At time t0 in FIG. 2, the ON command ON3 for the power supply switch 3 on the power source 1 side applied to the command input terminal S31 of the switching control circuit 30 is ON (“1”), and the command input terminal S41 of the switching control circuit 40 is ON. The ON command ON4 for the power supply switch 4 on the power source 2 side added to is OFF (“0”) (see FIGS. 2C and 2D).

  For this reason, in the switching control circuit 30, the flip-flops 34P and 34N are set, the AND gates 35P and 35N are opened, and the gate signals G3P and G3N of the thyristors 3P and 3N of the feed switch 3 are turned on (“1”). Thus, the power supply switch 3 is turned on, and power is supplied from the power source 1 to the load 5.

  On the other hand, in the switching control circuit 40, the flip-flops 44P and 44N are reset, the AND gates 45P and 45N are closed, and the gate signals G4P and G4N to the thyristors 4P and 4N of the power feeding switch 4 are turned off (“0 ]) And the power feed switch 4 is turned off. For this reason, the power supply from the power source 2 to the load 5 is stopped.

  At time t1, in order to switch the power supply to the load 5 from the power supply 1 to the power supply 2, as shown in FIGS. 2C and 2D, the ON command ON3 to the power supply switch 3 is turned off (“0”). In addition, the on command ON4 to the power supply switch 4 is switched on ("1").

  As a result, in the switching control circuit 30, the flip-flops 34P and 34N are reset by inverting the ON command ON3 turned off ("0") by the knot circuit 37, and the held gate-on permission signals GA3P and GA3N are turned off. ("0") (see FIGS. 2 (k) and (l)). At the same time, when the ON command ON3 is turned off ("0"), the gate signals G3P and G3N applied from the AND gates 35P and 35N to the thyristors 3P and 3N of the power supply switch 3 are turned off ("0"). The thyristors 3P and 3N are not immediately turned off if the current I1 still flows even when the gate signal is turned off. Here, since the thyristor 3N is turned off and the thyristor 3P is turned on, the gate signal G3P is turned off at the time t2 when the gate signal G3P is turned off and the current I1 passes through the zero point and reverses the polarity. Turn off. As a result, the power supply switch 3 is turned off and the current I1 is cut off.

  In the switching control circuit 40, the polarity discriminator 41P that discriminates the polarity reversal of the current I1 on the power source 1 side discriminates that the polarity is reversed by the current I1 becoming zero at the time t2, and the discrimination output signal D41P is set to “0” (off) (see FIG. 2G). This discrimination output signal D41P is applied to the set input terminal S of the flip-flop 44P through the AND gate 42P and the OR gate 43P which are opened by the ON command ON3 of “0” (off) to the power supply switch 3, and the flip-flop 44P is set. As a result, the flip-flop 44P sets the gate-on permission signal GA4P to “1” (on) and holds it. The gate-on permission signal GA4P opens the AND gate 45P, and an ON command ON4 for the power supply switch 4 is applied to the gate of the thyristor 4P of the power supply switch 4 as a gate-on signal G4P. Thereby, the thyristor 4P is immediately turned on.

  During the period from t1 to t2, an ON signal is given only to the conversion destination thyristor 4P, but whether or not power is supplied from the power source 2 to the load 5 is determined by the conduction state of the N-side thyristor of the other phase of the conversion destination. Since the current I1 becomes zero after t2, the polarity discriminator 41N that permits the gate-on of the N-side thyristor does not output.

  Instead of the polarity discriminator 41N, the zero current detector 46I detects this at the time t2 when the current I1 becomes zero, and generates a detection signal which becomes “1”. This signal is delayed by a predetermined time α by the delay circuit 46D, and at time t3, a detection signal DS4 is generated in which the switch-off detector 46 becomes “1” indicating that the power supply switch 3 is turned off (FIG. 2 ( j)). This signal DS4 is supplied via an AND gate 46A which is opened when the ON command ON3 for the power supply switch 3 which is “0” is inverted through the knot circuit 48 and OR gates 43P and 43N. Applied to the set terminal S of the flip-flops 44P and 44N. As a result, the lip flop 44N is also set, and the gate on permission signal GA4N is set to “1” (on) and held (see FIG. 2 (n)).

  The set gate ON permission signal GA4N which is held “1” (ON) held by the flip-flop 44N is applied to the AND gate 45N, and the AND gate 45N is opened. As a result, the ON command ON4 for the power supply switch 4 from the command input terminal S41 is applied to the gate of the thyristor 4N of the power supply switch 4 as the gate signal G4N (see FIG. 2 (n)). At time t3, both the P-side and N-side gate signals are applied to the thyristors 4P and 4N that are the conversion destinations.

  Thus, the thyristor 4N of the feed switch 4 to which the gate signal G4N is applied is turned on from the time t4 when the current I2 becomes negative, and the feed switch 4 is turned on. Thereafter, both thyristors 4P and 4N of the power supply switch 4 are alternately turned on according to the polarity of the current I2 to supply power to the load 5 (see FIGS. 2B and 2T).

  The switch-off detector 46 delays the output for a predetermined time α from the detection of the current zero because the thyristor 4N of the power supply switch 4 is turned on simultaneously with the thyristor 3P when switching to the power supply switch 4. This is to prevent cross current from flowing from the first side to the power source 2 side. For this reason, the time α for delaying the output is set to a time that can prevent the thyristors 3P and 4N from conducting simultaneously.

  Next, the operation when the power source for supplying power to the load 5 is switched from the power source 2 to the power source 1 will be described.

  In order to switch the power supply from the power supply 2 to the power supply 1, as shown in FIGS. 2C and 2D, the ON command ON4 for the power supply switch 4 of the switching control circuit 40 is set to “1” (ON) as shown in FIGS. ) To “0” (off), the on command ON3 for the power supply switch 3 of the switching control circuit 30 is switched from “0” (off) to “1” (on).

  As a result, the gate signals G4P and G4N to the power supply switch 4 in the switching control circuit 40 immediately become “0” (off), but since a negative current of the current I2 flows through the thyristor 4N of the power supply switch 4, Conduction continues and current I2 continues to flow (see FIG. 2B). Further, since the ON command ON4 that has become “0” (OFF) is applied to the reset input terminal R via the knot circuit 47, the flip-flops 44P and 44N are reset, as shown in FIGS. 2 (q) and (r). Thus, the gate-on permission signals GA4P and GA4N are “0” (off).

  In the period from t10 to t11 when the current I2 decreases to zero, the current polarity discriminator 31N of the switching control circuit 30 discriminates the negative polarity of the current I2 and sets the discrimination signal D31N to “1” (ON) (FIG. 2 (f)). The discrimination signal from the polarity discriminator 31N is applied to the set input terminal S via the AND gate 32N and the OR gate 33N, the flip-flop 34N is set, and the gate on permission signal GA3N is set to “1” (on) and held. The gate-on permission signal GA3N opens the AND gate 35N, and the ON command ON3 is applied as the gate signal G3N to the gate of the negative side thyristor 3N of the power supply switch 3. As a result, the thyristor thyristor 3N is turned on (turned on).

  During the period from t10 to t11, an ON signal is given only to the conversion destination thyristor 3N, but whether or not power is supplied from the power source 1 to the load 5 is determined by the conduction state of the P-side thyristor of the other phase of the conversion destination. After t11, since the current I2 becomes zero, the polarity discriminator 31P that permits gate-on of the P-side thyristor does not output.

  Instead of the polarity discriminator 31P, the current I2 decreases to zero at time t11, and this is detected by the zero current detector 36I of the switching control circuit 30. This detection signal is output from the delay circuit 36D as the OFF detection signal DS3 of the power feeding switch 3 after a predetermined time α (see FIG. 2 (i)). Since the switch-off detection signal DS3 is applied to the set input terminal S of the flip-flops 34P and 34N via the AND gate 32A and the OR gates 34P and 34N, the flip-flop 34P is also set and the gate-on permission signal GA3P is turned on (“1 )) And hold (see FIG. 2 (k)).

  The gate-on permission signal GA3P opens the AND gate 35P, and the ON command ON3 is applied to the gate of the positive side thyristor 3P of the power supply switch 3 as the gate signal G3P. Thereby, at t13 when the current I1 becomes positive, the negative thyristor 3N is turned off and the positive thyristor 3P is turned on. Thereafter, the thyristors 3P and 3N of the power supply switch 3 are alternately turned on according to the polarity of the current I1 until the on command ON3 is turned off (“0”), and power is supplied to the load 3.

  As described above, in the present invention, each of the power supply circuits for supplying power to one load from two AC power supplies is provided with a power supply switch configured by connecting thyristors in reverse polarity in parallel, and this power supply switch is switched. At this time, since the power supply switch on the side that is turned on is turned on after the power supply switch on the side that is turned on is completely turned off, it is possible to prevent the cross current that flows between the power supplies when the power supply is switched.

1, 2: AC power supply 11, 21: Feed path 12: 22: Current detector 3, 4: Feed switch 3P, 3N, 4P, 4N: Thyristor 30, 40: Switching control circuit 31P, 31N, 41P, 41N: Polarity Discriminators 32A, 32P, 32N, 35P, 35N, 42A, 42P, 42N, 45P, 45N: AND gates 33P, 33N, 43P, 43N: OR gates 34P, 34N, 44P, 44N: flip-flops 36, 46: switch-off detection Units 37, 38, 47, 48: Knot circuits S 31 and S 41: Opening / closing command input terminal ON 3: ON command ON for power feed switch 3 4: ON command for power feed switch 4.

Claims (1)

The two power supply circuits that supply power to the common load from each of the first and second AC power supplies are each provided with a power supply switch composed of a reverse polarity parallel connection circuit of thyristor elements. In the power supply switching device that switches the power supply for supplying power to the load,
A current detector that detects the alternating currents of the two power supply circuits, and a gate signal to the thyristor of the power supply switch according to an ON command to one power supply switch, and a gate to the thyristor of the other power supply switch A switching control circuit for turning off the signal,
The switching control circuit determines polarity reversal of current based on the alternating current detected by the current detector and outputs a polarity determination signal, and switch-off detecting that the power supply switch is turned off A detector,
The switch-off detector generates a detection signal when the alternating current detected by the current detector becomes zero, and a switch that delays the detection signal of the zero current detector by a predetermined time A delay circuit for generating an off detection signal,
When switching the power supply by switching the two power supply switches, by switching off the on command to one power switch that is turned on and to turn on the command to turn on the other power switch that is turned off, Turn off the gate signals to the thyristors of the power supply switch of one being the on,
After the thyristors of one power supply switches that the on is turned off, on the basis of the polarity determination signal, to turn on the gate signal to one of the thyristors of the other power supply switches and said off, said switch A power supply switching device characterized in that, based on an off detection signal, a gate signal to the other thyristor of the other power supply switch that is turned off is turned on to turn on each thyristor.

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