JP6438839B2 - Semiconductor device and power conversion device using the same - Google Patents

Description

  The present invention relates to a semiconductor device and a power conversion device using the same, and more particularly to a semiconductor device using an insulated gate bipolar transistor and a power conversion device using the same.

  As a large-capacity power converter, for example, a thyristor has been mainly used in a power frequency converter, but in recent years, an insulated gate bipolar transistor (hereinafter referred to as an IGBT) having a current blocking capability as a power element. The replacement of is being considered. In particular, in a DC converter, a modular multilevel converter (hereinafter referred to as MMC), which is one of multilevel converters, has been actively researched, and the demand for a pressure-welded IGBT having features such as short-circuit failure and explosion-proof is increasing.

  A chip mounted on the pressure-contact IGBT is composed of a central active region and an outer-side termination region, and has a structure in which a pressure-contact electrode is in contact with a part of the active region and is vertically connected. In order to clarify the comparison with the present invention, the configuration and function of a conventional pressure welding IGBT will be described below with reference to FIGS.

  First, FIG. 12 shows an example of a top view and a sectional view of a conventional pressure contact tip. As shown in a top view of FIG. 12 (upper part of FIG. 12), emitter electrodes 204 and 205 and a gate pad 212 are formed on the upper surface of the IGBT chip 211.

  Further, as shown in a cross-sectional view showing the AA cross section of the top view (lower part of FIG. 12), the collector electrode 210 is disposed on one surface of the semiconductor substrate 250, and the emitter electrodes 204 and 205 having a two-stage configuration are disposed on the other surface. Has been. The emitter electrode 205 positioned at the upper stage of the two-stage configuration is formed inside the region of the emitter electrode 204 positioned at the lower stage of the two-stage configuration. Reference numeral 213 denotes an insulating film formed at the end of the emitter electrode 204. In the press-contact IGBT shown in this cross-sectional view, an almost entire region of the upper emitter electrode 205 is an electrode region 260 to be press-contacted, and a peripheral region 261 excluding a region occupied by the emitter electrode 205 is a region occupied by the lower emitter electrode 204. This is a non-pressure contact electrode region 261.

  As described above, in the pressure-contact IGBT illustrated in FIG. 12, pressure contact is made from above and below, and the emitter electrode 205 and the collector electrode 210 are electrically connected. In addition, by inputting an on / off signal to the gate electrode 212, the conduction of the semiconductor substrate 250 between the emitter electrode 205 and the collector electrode 210 is controlled.

  Here, as shown in FIG. 12, the electrode of the chip 211 for pressure contact has two stages, ie, an emitter electrode 205 and an emitter electrode 204, which is more than the electrode of the chip mounted without pressure for pressure relaxation or the like. It was adopted to increase the total thickness. Further, the electrode area 260 to be pressed and the electrode area 261 to be non-pressure-contacted are determined by the shape and area of the electrodes that are in contact with the emitter electrode 205 and the collector electrode 210. When the two-stage structure as shown in FIG. The emitter electrode 205 coincides with the maximum pressure contact region. That is, there is an advantage that the electrode region 260 to be pressed can be arbitrarily limited by the layout of the emitter electrode 205.

  FIG. 13 shows a schematic example of the basic structure of a planar IGBT. As shown in FIG. 13, in the planar IGBT, IGBT cells 227 are repeated in an array, and each IGBT cell 227 has an n-substrate 201 and a p-type base formed on one main surface of the n-substrate 201. The gate oxide film 206 is formed on the surface of the layer 202, the n-type source layer 203 formed on a part of the p-type base layer 202, and the p-type base layer 202 between the n-substrate 201 and the n-type source layer 203. , The first emitter electrode 204 connected to the n-type source layer 203 and the p-type base layer 202, and the p-type formed on the other main surface of the n-substrate 201. It comprises an emitter layer 209 and a collector electrode 210 connected to the p-type emitter layer 209. Reference numeral 208 denotes an n buffer layer. In the figure, reference numeral 290 denotes a pressing force applied to the IGBT cell 227 from above and below in the electrode region 260 to be pressed.

  FIG. 14 shows a schematic diagram of the basic operation of the IGBT. In the IGBT cell 227, by applying a voltage of 5 to 20 V to the gate electrode 207, electrons 224 are injected from the n-type source layer 203 toward the n-substrate 201 and shift to the on state. Depending on the amount of injected electrons, holes 225 are injected from the p-type emitter layer 209 toward the n-substrate 201 to cause conductivity modulation, and the resistance is lowered. The injected holes 225 pass through the p-type base layer 202. Then, it flows to the emitter electrodes 204 and 205 and is electrically connected to the collector electrode 210. Reference numeral 226 denotes a post electrode.

  FIG. 15 is a sectional view of a conventional pressure contact type chip mounting example. The IGBT chip 211 for pressure contact is sandwiched between the emitter side metal plate 214 and the collector side metal plate 215 via the emitter electrode 205 and the collector electrode 210, and is pressed by the external pressure between the emitter terminal plate 216 and the collector terminal plate 217. As shown, mount multiple chips in parallel according to the rated current. At this time, by providing a sense emitter in each chip, the controllability of the current balance of the parallel chips can be improved.

  16 and 17 show conventional examples provided with a sense emitter disclosed in Patent Document 1. FIG. According to FIG. 16, the semiconductor chip 10 having the gate electrode 13 and the emitter electrode 12 and the emitter sense electrode 12a, which are insulated and separated from each other and having the same potential, formed on the top surface and the collector electrode formed on the back surface, and the emitter electrode An emitter pressure contact plate that is in pressure contact with the collector electrode, a collector pressure contact plate that is in pressure contact with the collector electrode, a gate electrode lead-out lead wire that has one end pressed into contact with the gate electrode and the other end taken out to the outside, and one end in pressure contact with the emitter sense electrode; The intermediate portion is provided so as to pass through a gap portion electrically insulated from the emitter pressure contact plate, and the other end includes an emitter sense electrode lead wire that is taken out to the outside.

  The IGBT shown in FIG. 17 has a number of IGBT elements sharing the emitter electrode array 12 and the collector electrode 10a, and an emitter sense electrode 12a connected to the emitter electrode array 12, and a base is provided below the emitter sense electrode 12a. Although the region 33 is formed, the emitter region is not formed, and the emitter sense electrode 12a is not in contact with the emitter region.

  That is, in FIG. 17, 31 is a P-type semiconductor layer (collector layer), 32 is an N− type semiconductor layer on the collector layer, and 33 is a P + type partially formed on the surface layer portion of the N− type semiconductor layer. A semiconductor layer (base region), 34 is a gate insulating film (oxide film) formed on a part of the surface of the N− type semiconductor layer, 35 is a gate electrode (wiring) formed on the gate insulating film, and 36 is an interlayer. An insulating film (oxide film), 37 is an emitter electrode using, for example, an aluminum film formed on the interlayer insulating film, 11 is an insulating film partially formed on the emitter electrode, and 38 is a surface layer portion of the base region. N + type semiconductor layers (emitter regions) 10a partially diffused in the collector layer 10a are collector electrodes using, for example, an aluminum film formed on the lower surface of the collector layer.

  According to Patent Document 1, the emitter voltage can be accurately detected even if the inductance component of the emitter pressure contact plate exists between the emitter terminal and the emitter electrode, and the influence of induced noise or the like can be suppressed. Yes.

JP 9-1335023 A

  However, according to the structure of the IGBT disclosed in Patent Document 1, the sense emitter connection portion on the chip has a problem that there is a concern that the heat contact due to the increase in thermal resistance may cause a heat-concentrated breakdown because the press contact is insufficient. doing.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of preventing heat concentration destruction due to heat generation at the sense emitter connection portion and a power conversion device using the same.

  As described above, the present invention includes the first electrode layer formed on one main surface of the semiconductor substrate and the second electrode layer formed on the other main surface of the semiconductor substrate, A semiconductor device configured to be electrically connected to the outside by press-contacting the second electrode layer from a direction perpendicular to the layer, wherein the electrical conduction can be actively switched by an external signal, the first electrode layer A first region that is press-contacted and a second region that extracts a sense potential at a portion outside the first region that is press-contacted, and the second region is a conduction suppressing portion in a conductive state. This is a semiconductor device.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can prevent the heat concentration destruction by the heat_generation | fever in a sense emitter connection part, and a power converter device using the same can be provided.

FIG. 3 is a diagram illustrating an example of a top view and a cross-sectional view of an example of mounting the IGBT chip according to the first embodiment. The figure which shows the upper side figure and sectional drawing of the example of mounting of the conventional IGBT chip | tip. The figure which shows the expanded cross section of the conduction | electrical_connection suppression part 263 part of the structural example of the IGBT chip | tip which concerns on Example 1. FIG. FIG. 6 is a diagram illustrating an example of a top view and a cross-sectional view of a mounting example of an IGBT chip according to the second embodiment. The figure which shows the expanded cross section of the conduction | electrical_connection suppression part 263 part of the structural example of the IGBT chip | tip which concerns on Example 2. FIG. FIG. 10 is a diagram illustrating an example of a top view and a cross-sectional view of a mounting example of an IGBT chip according to a third embodiment. FIG. 10 is a diagram illustrating an example of a top view and a cross-sectional view of a mounting example of an IGBT chip according to a fourth embodiment. FIG. 10 is a diagram illustrating an example of a top view and a cross-sectional view of a mounting example of an IGBT chip according to a fifth embodiment. FIG. 10 is a diagram illustrating an example of a top view and a cross-sectional view of a mounting example of an IGBT chip according to a sixth embodiment. The figure which shows the expanded cross section of the conduction | electrical_connection suppression part 263 part of the structural example of the IGBT chip | tip which concerns on Example 6. FIG. FIG. 18 is a diagram illustrating an example of a top view and a cross-sectional view of a mounting example of an IGBT chip according to a seventh embodiment. The figure which shows an example of the upper side figure and sectional drawing of the conventional chip | tip for press-contacting. The figure which shows the schematic example of the basic structure of the conventional planar type IGBT. The figure which shows the model of the basic operation | movement of the conventional planar type IGBT. The figure which shows the cross section of the conventional pressure-contact type chip | tip mounting example. The figure which shows the pattern layout on the chip | tip of the press-contact type IGBT of patent document 1. FIG. The figure which shows the device structure of the press-contact type IGBT of patent document 1. As shown in FIG. FIG. 10 is a diagram illustrating an example of an MMC circuit to which the IGBT according to the first to seventh embodiments is applied. The figure which shows an example of the unit cell circuit of MMC to which IGBT which concerns on Example 1-7 is applied. The figure which shows an example of the three-phase inverter to which IGBT of Example 1- Example 8 of this invention is applied.

  The semiconductor device of the present invention will be described in detail below based on the illustrated embodiments. In all the drawings for explaining the embodiments, the same reference numerals are given to the same members in principle, and the repeated explanation thereof is omitted.

  FIG. 1 shows a top view and a cross-sectional view of a mounting example of an IGBT chip according to Embodiment 1 of the present invention. As a comparative example of the structure of the present invention, FIG. 2 shows a top view and a cross-sectional view of a conventional IGBT chip mounting example.

  First, according to the top view (upper part of FIG. 2) of the conventional mounting example of the IGBT chip of FIG. 2, the emitter electrode 204, the gate pad 212, and the sense emitter pin 270 are formed on the upper surface of the IGBT chip 211. According to the cross-sectional view (lower part of FIG. 2) showing the AA cross section of the top view of FIG. 2, the portion of the sense emitter pin 270 is not pressed by the pressing force 290 in the emitter electrode 204. A portion 204 is an electrode region 260 to be pressed. Further, the lower part of the electrode region 260 to be pressed and the whole region of the non-pressure-contacted electrode region 261 around the lower part of the sense emitter pin 270 are the main current region (main conductive portion) 262. In this method, a drive signal is input from the gate pad 212, and the IGBT chip 211 is pressed and conducted through the emitter-side metal plate 214 and the collector-side metal plate 215.

  On the other hand, in FIG. 1 showing the first embodiment of the present invention, as is clear by comparing FIG. 1 and FIG. 2, the non-pressure contact electrode region 261 around the lower portion of the sense emitter pin 270 is a current suppression region (conduction suppression). Part) 263 is different from the conventional configuration of FIG. 2, and the effect of the present invention is expected. That is, since the lower peripheral region of the sense emitter pin 270 has insufficient pressure contact, in the conventional example, there is a concern that heat concentration is caused by heat generation due to an increase in thermal resistance, but the current in this region is suppressed in the first embodiment of the present invention. This improves the breakdown resistance.

  FIG. 3 is an enlarged cross-sectional view of the conduction suppressing portion 263 portion of the structure example of the IGBT chip according to the first embodiment of the present invention. This part corresponds to the circuit board constituent part of FIG. 14 described as a conventional example.

  14 and FIG. 3 according to the present invention, the source layer 203 is entirely formed in FIG. 14, whereas in the present invention, the electrode region 260 and the non-contact electrode region 260 are not formed. After the pressure-contact electrode region 261 is divided, the source layer 203 is formed only in the electrode region 260 to be pressed, and is not formed in the non-pressure-contact electrode region 261. In other words, the source layer 203 in the region immediately below the sense emitter pin 270 is reduced.

  As shown in FIG. 3, the current limitation of the present invention can be realized only by reducing the source layer 203 in the region immediately below the sense emitter pin 270. This is because if the source layer is reduced, electrons are not injected from the emitter into the n-substrate 201, so that the resistance is not lowered by the conductivity modulation and the current is suppressed.

  Here, the current limit can be adjusted by the reduction rate of the source layer 203. The larger the current limit, the higher the breakdown resistance. On the contrary, if the current limit is reduced, the breakdown resistance decreases, but the resistance of the entire chip is reduced. And reduce the voltage drop. In particular, when the current density of the conduction suppressing portion 263 is 1/100 or less of the current density of the main conducting portion 262, a clear effect of improving the breakdown resistance can be obtained.

  The reason for this is as follows. In the first place, the main cause of destruction is temperature rise due to heat generation. The amount of heat generation is voltage drop × current. When the current density is 1/100, the heat generation density is also 1/100. In a switch operation for a short time of about 10 μs, the temperature rise is considered to be a calorific value / heat capacity, and the temperature rise is 1 / 100th. For example, since the semiconductor is operated from room temperature to about 200 ° C., the temperature rise of the conduction suppression unit 263 is in a sufficiently negligible range with respect to the temperature rise of the main conduction unit 262, and the heat concentration breakdown due to the high thermal resistance and low heat dissipation. It becomes possible to suppress.

  In FIG. 17 showing the conventional example, the base layer 38 under the sense emitter is not formed. At first glance, it seems that the configuration of this embodiment is disclosed, but the conventional configuration of FIG. The electrode 12a is fundamentally different from the present embodiment in that it does not contact the emitter region. Paragraph 0023 of Patent Document 1 has a similar purpose.

  In order to improve the breakdown tolerance, it is advantageous that the electrode of the emitter sensing portion is also in contact with the emitter region as in the present invention because the effect of heat radiation is increased.

In short, the first embodiment of the present invention described above adopts the following configuration. The configuration of Example 1 is “provided with the first electrode layer formed on one main surface of the semiconductor substrate and the second electrode layer formed on the other main surface of the semiconductor substrate, In the semiconductor device that is configured to take electrical continuity with the outside by pressing the second electrode layer in a direction perpendicular to the layer, and the electrical continuity can be actively switched by an external signal,
A first region that is press-contacted among the regions of the first electrode layer; and a second region that extracts a sense potential at a portion outside the first region that is press-contacted. A semiconductor device characterized by that. ".

In addition, the configuration of Example 1 is described as follows: “A third electrode layer having an area smaller than that of the first electrode layer is provided on the upper surface side and on the inner side of the first electrode layer. And the above-mentioned semiconductor device configured to take electrical continuity with the outside by pressing the second electrode layer in a direction perpendicular to the layer,
A first region of the first electrode layer that is press-contacted via the third electrode layer; and a second region that extracts a sense potential at a portion outside the press-contacted first region; The semiconductor device, wherein the second region is a conduction suppressing portion. ".

  Further, the configuration of the first embodiment is “a semiconductor device characterized in that the source layer in the second region is reduced in order to make the second region a conduction suppressing portion in the conductive state”. .

  In addition, the configuration of Example 1 is “a semiconductor device in which the current density of the second region is 1/100 or less of the current density of the first region.”

  A second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a diagram illustrating an example of a top view and a cross-sectional view of the mounting example of the IGBT chip according to the second embodiment, and corresponds to FIG. 1 of the first embodiment. FIG. 5 is an enlarged cross-sectional view of the conduction suppressing portion 263 portion of the structure example of the IGBT chip according to the second embodiment, and corresponds to FIG. 3 of the first embodiment.

  1 and 3 of the first embodiment, the sense emitter pin 270 is formed on the emitter electrode 204, whereas in the second embodiment of FIGS. 4 and 5, current suppression from the emitter electrode 204 via the emitter-side metal plate 214 is performed. It differs in that it is formed in the upper part of the region 263.

  As shown in FIGS. 4 and 5, the sense emitter probe (sense emitter pin) 270 can achieve the same effect even when the contact is formed at the upper part of the current suppression region 263 via the emitter-side metal plate 214. The sense emitter probe 270 is connected to the emitter potential via the emitter-side metal plate 214. Similarly, since the non-pressure contact electrode region 261 has a high thermal resistance, an effect of improving the breakdown resistance can be obtained by reducing the n-type source layer 203 directly below.

  FIG. 6 shows a top view and a sectional view of a mounting example of an IGBT chip according to the third embodiment of the present invention.

  FIG. 6 shows an example in which the sense emitter pin 270 is replaced with a wire connected one such as the sense emitter wire 271. Even when the sense emitter pin 270 has a wire connection such as the sense emitter wire 271, the same effect as the above-described embodiment of the present invention can be obtained.

  FIG. 7 shows a top view and a sectional view of a mounting example of an IGBT chip according to the fourth embodiment of the present invention.

  FIG. 7 shows an example in which the sense emitter pin 270 is replaced with a plate-connected one such as the sense emitter plate 272. As in the sense emitter plate 272 of FIG. 7, the same effect as in the above-described embodiment of the present invention can be obtained even when the sense emitter is a ribbon or plate connection.

  FIG. 8 shows a top view and a sectional view of a mounting example of an IGBT chip according to the fifth embodiment of the present invention. The difference from the other embodiments such as FIG. 1 is that the IGBT chip 211 and the collector-side metal plate 215 are metal-bonded by the metal-bonding portion 280.

  In FIG. 8, when the IGBT chip 211 and the collector-side metal plate 215 are metal-bonded by the metal bonding portion 280, the current resistance in the peripheral region under the sense emitter probe is ½ that of the main conduction portion 262 because the thermal resistance is lowered. The effect similar to the above-mentioned embodiment can be obtained only by narrowing down to the following current density. For metal bonding, a bonding material containing metal capable of reducing resistance, such as various solders and Ag paste, can be used.

  In the fifth embodiment, the main conduction portion 262 connects the emitter-side metal plate 214 and the collector-side metal plate 215 with low thermal resistance, whereas the conduction suppression portion 263 has only the collector-side metal plate 215 with low thermal resistance. Since it is connected, the thermal resistance is doubled, and by making the current density of the conduction suppressing portion 263 ½ or less, the heat generation amount can be ½ or less, and the temperature rise can be equivalent to the main conduction portion 262. it can.

  As described above, the fifth embodiment of the present invention is basically “the second electrode layer is bonded to the electrode substrate by a conductive material, and the current density of the second region is half of the current density of the first region. The semiconductor device is characterized in that it is 1 or less. "

  FIG. 9 shows a top view and a sectional view of a mounting example of an IGBT chip according to the sixth embodiment of the present invention.

  In the sixth embodiment, it is assumed that the heat generation of the emitter spreads at 45 degrees in consideration of heat propagation, and the pressure contact region is narrowed inward by the same width a as the chip thickness a to reduce the heat to the sense emitter region having high thermal resistance. The inflow is suppressed and the effect of improving the fracture resistance is great.

  FIG. 10 is an enlarged cross-sectional view of the conduction suppressing portion 263 portion of the structural example of the IGBT chip according to the sixth embodiment of the present invention. This embodiment differs from FIG. 1 of the first embodiment in that a current suppressing emitter layer 228 is provided.

  As shown in FIG. 10, the collector p-emitter layer 209 in the region immediately below the sense emitter is a p-type low-dose current-suppressing emitter layer 228, so that the effect of this embodiment can be obtained. The conductivity modulation is a reduction in resistance by a bipolar operation in which electrons are injected from the emitter into the n-substrate 201 and holes which are minority carriers are injected from the p-type emitter layer 209, so that the current suppressing emitter layer 228 is sensed. By providing it in the region directly under the emitter, hole injection directly above is suppressed, and conduction can be suppressed.

  It should be noted that a similar effect can be obtained for improving the breakdown resistance of the IGBT operation when an n-type layer is formed instead of the p-type current suppressing emitter layer 228 to form a reverse conducting IGBT.

  The sixth embodiment of the present invention described above is basically “in order to make the second region a conduction suppressing portion in the conductive state, the current of the first conductivity type instead of the emitter layer of the first conductivity type of the second region. A semiconductor device characterized in that a suppression emitter layer or a second conductivity type current suppression layer is formed. "

  FIG. 11 shows a top view and a cross-sectional view of a mounting example of an IGBT chip according to the seventh embodiment of the present invention. In FIG. 1 of the first embodiment, the collector-side metal plate 215 is disposed on the lower front surface of the IGBT chip 211. However, in FIG. 11 of the seventh embodiment, the collector-side metal plate 215 is provided only in the electrode region that is in pressure contact. It is different in that the lower part of is removed.

  Thus, even when the collector-side metal plate 215 is shaved in the peripheral region below the sense emitter pin 270 in the same manner as the emitter-side metal plate 214, the current flowing immediately below the sense emitter is suppressed, and the same effect as described above can be obtained. can get.

  18 and 19 show the configuration of a converter according to Embodiment 8 of the present invention.

  FIG. 18 shows an example of an MMC circuit to which the IGBT according to the first to seventh embodiments of the present invention is applied. In FIG. 18, a unit cell 106 including switching elements such as the phase arms 101 to 103, the input terminal 104, the output terminal 105, and an IGBT is shown.

  FIG. 19 shows an example of an MMC unit cell circuit to which the IGBT according to the first to seventh embodiments of the present invention is applied. In FIG. 19, a power source 110, a gate drive circuit 107, and a diode 109 are used, and the IGBT according to the first to seventh embodiments of the present invention is applied to the IGBT 108.

  As described above, by applying the element mounted with the IGBT chip according to the embodiment of the present invention to the power conversion device, the breakdown tolerance of the IGBT chip is improved, and high reliability of the power conversion device can be realized.

  Although the MMC circuit has been described in the eighth embodiment, the same effect can be obtained with other power conversion devices such as a converter, a chopper, and an inverter. FIG. 20 shows an example of a three-phase inverter to which the IGBT according to the first to seventh embodiments of the present invention is applied.

  According to the present invention described above, the following effects can be obtained. First, in the conventional structure, the temperature immediately below the sense emitter connection portion is overheated due to an increase in thermal resistance. However, according to the semiconductor device of the present invention and the power conversion device using the same, heat is generated to suppress the current immediately below the sense emitter connection portion. Is reduced and the heat distribution becomes uniform.

  In addition, when the active is narrowed, the withstand current resistance decreases due to the increase in current density. However, in the present invention, the heat distribution becomes uniform and the local overheated portion is eliminated, so that the withstand capacity is improved. Furthermore, since no current flows, the voltage drop is suppressed, the potential sensing accuracy is improved and stabilized, and the original function of the sense emitter is improved.

  The invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the gate electrode of Example 1 may be a trench type instead of a planar type. The IGBT of the above embodiment may invert the p-type and n-type, and the emitter electrode may have two or more stages and the collector electrode may be similarly thick and have two or more stages. The effect is the same even if the sense emitter electrode is separated from the main emitter electrode and a sense emitter pad is provided.

  Further, for example, the semiconductor material of the above embodiment may be silicon or silicon carbide, and can be widely applied to other semiconductor devices.

  The present invention relates to a semiconductor device and a power conversion device using the semiconductor device, and particularly to an IGBT and a power conversion device using the same, thereby contributing to miniaturization and high output by suppressing heat generation. Is possible.

101: u-phase arm 102: v-phase arm 103: w-phase arm 104: input terminal 105: output terminal 106: unit cell 107: gate drive circuit 108: pressure contact IGBT
109: pressure contact diode 110: capacitor 201: n ^- substrate 202: p-type base layer 203: n-type source layer 204: emitter electrode 205: emitter electrode 206: gate oxide film 207: gate electrode 208: n buffer layer 209: p-type Emitter layer 210: Collector electrode 211: IGBT chip 212: Gate pad 213: Insulating film 214: Emitter side metal plate 215: Collector side metal plate 216: Emitter terminal plate 217: Collector terminal plate 224: Electron 225: Hole 226: Post Electrode 227: IGBT cell 228: Low-concentration p-type emitter layer 230: Insulating film 250: Semiconductor substrate 260: Pressure contact electrode region 261: Non-pressure contact electrode region 262: Main conduction part 263: Conduction suppression part 270: Sense emitter pin 280: Metal joint

Claims (14)

A first electrode layer formed on one main surface of a semiconductor substrate and a second electrode layer formed on the other main surface of the semiconductor substrate, the first electrode layer and the second electrode layer being layers A semiconductor device configured to be electrically connected to the outside by being pressed from a direction perpendicular to the semiconductor device, wherein the electrical conduction is actively switchable by an external signal,
A first region that is press-contacted among the regions of the first electrode layer; and a second region that extracts a sense potential at a portion outside the first region that is press-contacted. And including an emitter layer of a first conductivity type in the semiconductor substrate,
In order to use the second region as a conduction suppressing portion in the conductive state, a first conductivity type current suppressing emitter layer or a second conductivity type current suppressing layer is used instead of the first conductivity type emitter layer in the second region. the semiconductor device is characterized in that the formed. A first electrode layer formed on one main surface of a semiconductor substrate and a second electrode layer formed on the other main surface of the semiconductor substrate, the first electrode layer and the second electrode layer being layers A semiconductor device configured to be electrically connected to the outside by being pressed from a direction perpendicular to the semiconductor device, wherein the electrical conduction is actively switchable by an external signal,
A first region that is press-contacted among the regions of the first electrode layer; and a second region that extracts a sense potential at a portion outside the first region that is press-contacted. And including a metal plate outside the second electrode layer,
A semiconductor device according to claim 1, wherein a metal plate outside the second electrode layer is not provided in the second region in order to make the second region a conduction suppressing portion in the conductive state . A third electrode layer having a smaller area than the first electrode layer is provided on the upper surface and inside of the first electrode layer, and the third electrode layer and the second electrode layer are formed in layers instead of the first electrode layer. The semiconductor device according to claim 1 or 2 , wherein the semiconductor device is configured to be electrically connected to the outside by being pressed from a vertical direction.
A first region of the first electrode layer that is press-contacted via the third electrode layer; and a second region that extracts a sense potential at a portion outside the press-contacted first region; The semiconductor device, wherein the second region is a conduction suppressing portion. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor substrate includes a source layer.
A semiconductor device characterized in that the source layer in the second region is reduced in order to make the second region a conduction suppressing portion in a conductive state. The semiconductor device according to any one of claims 1 to 4 , wherein:
The semiconductor device, wherein the second electrode layer is bonded to an electrode substrate with a conductive material, and the current density of the second region is less than or equal to half the current density of the first region. A semiconductor device according to any one of claims 1 to 5 ,
A semiconductor device, wherein the current density of the second region is 1/100 or less of the current density of the first region. A second conductivity type base layer formed at equal intervals on the main surface of the first conductivity type semiconductor substrate; a first conductivity type source layer formed intermittently on the surface of the second conductivity type base layer; A gate electrode formed on a surface of the second conductivity type base layer sandwiched between the one conductivity type semiconductor substrate and the first conductivity type source layer via a gate oxide film; the second conductivity type base layer; A first electrode layer electrically connected to both of the one conductivity type source layer and formed on the surface of the first conductivity type source layer, and on the other main surface of the first conductivity type semiconductor substrate. Comprises a second conductivity type emitter layer, and a second electrode layer electrically connected to the second conductivity type emitter layer and formed on a surface of the second conductivity type emitter layer, Electrical contact with the outside is achieved by pressing the second electrode layer in a direction perpendicular to the layer. A semiconductor device configured to take,
A first region that is press-contacted among the regions of the first electrode layer; and a second region that extracts a sense potential at a portion outside the first region that is press-contacted, and the first electrode layer of the second region includes contacting said first conductivity type source layer in contact with the first electrode layer of the first region Ri der less than 1/100 of the density of the first conductivity type source layer, the emitter of the first conductivity type in a semiconductor substrate Including layers,
In order to use the second region as a conduction suppressing portion in the conductive state, a first conductivity type current suppressing emitter layer or a second conductivity type current suppressing layer is used instead of the first conductivity type emitter layer in the second region. the semiconductor device is characterized in that the formed. A second conductivity type base layer formed at equal intervals on the main surface of the first conductivity type semiconductor substrate; a first conductivity type source layer formed intermittently on the surface of the second conductivity type base layer; A gate electrode formed on a surface of the second conductivity type base layer sandwiched between the one conductivity type semiconductor substrate and the first conductivity type source layer via a gate oxide film; the second conductivity type base layer; A first electrode layer electrically connected to both of the one conductivity type source layer and formed on the surface of the first conductivity type source layer, and on the other main surface of the first conductivity type semiconductor substrate. Comprises a second conductivity type emitter layer, and a second electrode layer electrically connected to the second conductivity type emitter layer and formed on a surface of the second conductivity type emitter layer, Electrical contact with the outside is achieved by pressing the second electrode layer in a direction perpendicular to the layer. A semiconductor device configured to take,
A first region that is press-contacted among the regions of the first electrode layer; and a second region that extracts a sense potential at a portion outside the first region that is press-contacted, and the first electrode layer of the second region includes The first conductivity type source layer in contact is less than or equal to one hundredth of the density of the first conductivity type source layer in contact with the first electrode layer in the first region, and a metal plate is disposed outside the second electrode layer. Including
A semiconductor device according to claim 1, wherein a metal plate outside the second electrode layer is not provided in the second region in order to make the second region a conduction suppressing portion in the conductive state . A second conductivity type base layer formed on the main surface of the first conductivity type semiconductor substrate; a trench gate electrode formed on the second conductivity type base layer; and a surface formed on the surface of the second conductivity type base layer. A first conductivity type source layer in contact with the trench gate electrode, electrically connected to both the second conductivity type base layer and the first conductivity type source layer, and formed on a surface of the first conductivity type source layer. And a second conductivity type emitter layer electrically connected to the second conductivity type emitter layer on the other main surface of the first conductivity type semiconductor substrate, and the second conductivity type emitter layer. A second electrode layer formed on the surface of the conductive type emitter layer, and configured to be electrically connected to the outside by pressing the first electrode layer and the second electrode layer in a direction perpendicular to the layer; A semiconductor device,
A first region that is press-contacted among the regions of the first electrode layer; and a second region that extracts a sense potential at a portion outside the first region that is press-contacted, and the first electrode layer of the second region includes contacting said first conductivity type source layer in contact with the first electrode layer of the first region Ri der less than 1/100 of the density of the first conductivity type source layer, the emitter of the first conductivity type in a semiconductor substrate Including layers,
In order to use the second region as a conduction suppressing portion in the conductive state, a first conductivity type current suppressing emitter layer or a second conductivity type current suppressing layer is used instead of the first conductivity type emitter layer in the second region. the semiconductor device is characterized in that the formed. A second conductivity type base layer formed on the main surface of the first conductivity type semiconductor substrate; a trench gate electrode formed on the second conductivity type base layer; and a surface formed on the surface of the second conductivity type base layer. A first conductivity type source layer in contact with the trench gate electrode, electrically connected to both the second conductivity type base layer and the first conductivity type source layer, and formed on a surface of the first conductivity type source layer. And a second conductivity type emitter layer electrically connected to the second conductivity type emitter layer on the other main surface of the first conductivity type semiconductor substrate, and the second conductivity type emitter layer. A second electrode layer formed on the surface of the conductive type emitter layer, and configured to be electrically connected to the outside by pressing the first electrode layer and the second electrode layer in a direction perpendicular to the layer; A semiconductor device,
A first region that is press-contacted among the regions of the first electrode layer; and a second region that extracts a sense potential at a portion outside the first region that is press-contacted, and the first electrode layer of the second region includes The first conductivity type source layer in contact is less than or equal to one hundredth of the density of the first conductivity type source layer in contact with the first electrode layer in the first region, and a metal plate is disposed outside the second electrode layer. Including
A semiconductor device according to claim 1, wherein a metal plate outside the second electrode layer is not provided in the second region in order to make the second region a conduction suppressing portion in the conductive state . A third electrode layer having a smaller area than the first electrode layer is provided above and inside the first electrode layer, and the third electrode layer and the second electrode layer are perpendicular to the layer instead of the first electrode layer. The semiconductor device according to any one of claims 7 to 10, wherein the semiconductor device is configured to be electrically connected to the outside by being pressed from any direction.
A first region that is press-contacted via the third electrode layer in a region of the first electrode layer; and a second region that extracts a sense emitter potential at a portion outside the first region to be pressed. The first conductivity type source layer in contact with the first electrode layer in two regions is 1/100 or less of the density of the first conductivity type source layer in contact with the first electrode layer in the first region. A semiconductor device. The semiconductor device according to any one of claims 7 to 11 ,
The semiconductor device, wherein the second electrode layer is bonded to an electrode substrate with a conductive material, and the current density of the second region is less than or equal to one half of the current density of the first region. The semiconductor device according to any one of claims 1 to 12 ,
The semiconductor device is configured by parallel connection of a plurality of semiconductor chips. An input terminal; an arm connected to the input terminal, wherein a plurality of unit cells each composed of a semiconductor switching element and a semiconductor rectifier element are connected in series; and an output terminal connected to the arm, wherein the semiconductor switching element is turned on A power conversion device that converts power by turning off,
Wherein each of the semiconductor switching element or the semiconductor rectifying element, a power conversion device which is a semiconductor device according to any one of claims 13 claim 1.

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