JP6439463B2 - Semiconductor memory device and method for controlling semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device and a method for controlling the semiconductor memory device.

  There is known a technique of storing parity data together with data in a semiconductor memory device, and detecting or correcting an error in data read from the semiconductor memory device using the parity data. For example, by providing a plurality of error detection circuits corresponding to the bit positions of a plurality of memory elements that respectively store a plurality of bits of data, a memory element that has caused a burst error is detected (see, for example, Patent Document 1). ). Further, in a semiconductor memory device that selectively outputs one of two data groups read from the memory cell array, the error correction circuit can be configured to correct errors using parity data common to the data groups after the data groups are selected. The circuit scale is reduced (see, for example, Patent Document 2).

Japanese Patent Laid-Open No. 11-65944 JP-A-5-2898

  When correcting an error in data read from the memory cell array, the error correction time is included in the data read time from when the data read request is received until the data is output. For this reason, the data read time of the semiconductor memory device having the error correction circuit is longer than the data read time of the semiconductor memory device having no error correction circuit.

  Further, when an error correction circuit is mounted on a serial memory that converts parallel data read from the memory cell array into serial data and outputs the data, the head data is output from the output terminal after error correction of the parallel data is executed. . Therefore, the output timing of the head data changes depending on the error correction time by the error correction circuit.

  In one aspect, a semiconductor memory device and a method for controlling the semiconductor memory device disclosed herein are intended to shorten a data read time in a semiconductor memory device that includes an error correction circuit and outputs data in series.

According to one aspect, the semiconductor memory device includes a first data group, a first parity data group corresponding to the first data group, a second data group different from the first data group, A memory unit that outputs in parallel a second parity data group corresponding to two data groups, and correcting the error in the first data group using the first parity data group, A first error correction circuit for generating, a second error correction circuit for correcting a second data group error using the second parity data group to generate a second correction data group, and data contained in the correction data group, possess an output circuit for outputting the data included in the second correction data group sequentially, the number of bits of the first data group, the number of bits of the second data group Less .
According to another aspect, the semiconductor memory device includes a first data group, a first parity data group corresponding to the first data group, a second data group different from the first data group, A memory unit that outputs in parallel a second parity data group corresponding to two data groups, and correcting the error in the first data group using the first parity data group, A first error correction circuit for generating, a second error correction circuit for correcting a second data group error using the second parity data group to generate a second correction data group, An output circuit that sequentially outputs data included in the correction data group and data included in the second correction data group, and the error correction time of the first data group by the first error correction circuit is: It is shorter than the error correction time of the second data group by the second error correction circuit .

According to another aspect, a method for controlling a semiconductor memory device includes a first data group, a first parity data group corresponding to the first data group, and a second data different from the first data group. A data group and a second parity data group corresponding to the second data group are output in parallel from the memory unit, and an error in the first data group is corrected using the first parity data group. The first correction data group is generated, the second parity data group is used to correct the error of the second data group, and the second correction data group is generated. The first correction data group And the data included in the second correction data group are sequentially output, and the number of bits of the first data group is smaller than the number of bits of the second data group .
According to another aspect, a method for controlling a semiconductor memory device includes a first data group, a first parity data group corresponding to the first data group, and a second data different from the first data group. A data group and a second parity data group corresponding to the second data group are output in parallel from the memory unit, and an error in the first data group is corrected using the first parity data group. The first correction data group is generated, the second parity data group is used to correct the error of the second data group, and the second correction data group is generated. The first correction data group And the data included in the second correction data group are sequentially output, and the error correction time of the first data group is shorter than the error correction time of the second data group.

  The semiconductor memory device and the method for controlling the semiconductor memory device disclosed herein have an error correction circuit, and can shorten the data read time in the semiconductor memory device that outputs data in series.

It is a figure which shows one Embodiment of the control method of a semiconductor memory device and a semiconductor memory device. FIG. 3 is a diagram illustrating an example of a read operation of the semiconductor memory device illustrated in FIG. 1. It is a figure which shows another embodiment of a semiconductor memory device and a semiconductor memory device. FIG. 4 is a diagram illustrating an example of an input / output control circuit illustrated in FIG. 3. It is a figure which shows an example of the parity control circuit 40 shown in FIG. FIG. 6 is a diagram illustrating an example of a parity check matrix used in the read parity generation circuit, the write parity generation circuit, the syndrome generation circuit, and the syndrome decoder illustrated in FIG. 5. FIG. 6 is a diagram illustrating an example of a read parity generation circuit, a syndrome generation circuit, a syndrome decoder, and an error correction circuit illustrated in FIG. 5. FIG. 8 is a diagram illustrating an example in which the read parity generation circuit and the syndrome generation circuit illustrated in FIG. 7 are merged and exclusive OR gates are arranged in parallel. FIG. 6 is a diagram illustrating an example of a replacement circuit and a write parity generation circuit illustrated in FIG. 5. FIG. 4 is a diagram illustrating an example of a parity control circuit 50 illustrated in FIG. 3. FIG. 11 is a diagram illustrating an example of a parity check matrix used in the read parity generation circuit, the write parity generation circuit, the syndrome generation circuit, and the syndrome decoder illustrated in FIG. 10. It is a figure which shows an example of the error correction circuit shown in FIG. It is a figure which shows an example of the replacement circuit shown in FIG. FIG. 4 is a diagram illustrating an example of a read operation of the semiconductor memory device illustrated in FIG. 3. It is a figure which shows an example of the principal part of the read-out operation | movement shown in FIG. FIG. 4 is a diagram showing an example of a write operation of the semiconductor memory device shown in FIG. 3. It is a figure which shows another embodiment of the control method of a semiconductor memory device and a semiconductor memory device. FIG. 18 is a diagram illustrating an example of an input / output control circuit illustrated in FIG. 17. FIG. 18 is a diagram illustrating an example of a read operation of the semiconductor memory device illustrated in FIG. 17. FIG. 18 is a diagram showing an example of a write operation of the semiconductor memory device shown in FIG. 17.

  Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals as the signal names are used for signal lines through which signals are transmitted. A signal prefixed with “/” indicates negative logic. Double square marks in the figure indicate external terminals. The external terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored. For the signal supplied via the external terminal, the same symbol as the terminal name is used.

  FIG. 1 is a diagram illustrating an embodiment of a semiconductor memory device and a method for controlling the semiconductor memory device. A semiconductor memory device MEM1 illustrated in FIG. 1 includes a memory unit 1, error correction circuits 2, 3 and an output circuit 4. In FIG. 1, elements for reading data from the memory unit 1 are shown, and elements for writing data to the memory unit 1 are not shown.

  The memory unit 1 includes a plurality of memory cells that store a data group RDG1, a parity data group RPG1 corresponding to the data group RDG1, a data group RDG2 different from the data group RDG1, and a parity data group RPG2 corresponding to the data group RDG2. Have For example, the data group RDG1 has m + 1 bits (m is an integer of 0 or more), and the data group RDG2 has n + 1 bits (n is an integer of 0 or more).

  The memory unit 1 outputs the data groups RDG1, RDG2 and the parity data groups RPG1, RPG2 in parallel in response to the read request. For example, the memory unit 1 stores a plurality of data blocks each including data groups RDG1, RDG2 and parity data groups RPG1, RPG2. When the memory unit 1 stores a plurality of data blocks, each data block is identified by an address supplied from the outside of the semiconductor memory device MEM1.

  In the read operation based on the read request, the error correction circuit 2 corrects the error of the data group RDG1 using the parity data group RPG1, and generates a corrected data group CRDG1. The error correction circuit 3 corrects an error in the data group RDG2 using the parity data group RPG2, and generates a corrected data group CRDG2. By correcting errors in the data stored in the memory unit 1 for each of the data groups RDG1 and RDG2, the correction time can be shortened compared to correcting errors in the data groups RDG1 and RDG2 collectively.

  In the read operation, the output circuit 4 first selects the head data CRDG1 [m] from the correction data group CRDG1, and outputs the selected head data CRDG1 [m] to the outside of the semiconductor memory device via the external terminal. Next, the output circuit 4 sequentially outputs data CRDG1 [m−1],..., CRDG1 [0] excluding the head data CRDG1 “m” in the correction data group CRDG1. When the correction data group CRDG1 is 1 bit, the output circuit 4 outputs the 1-bit correction data group CRDG1 as the top data, and does not output because there is no data other than the top data.

  The output circuit 4 sequentially outputs data CRDG2 [n], CRDG2 [n−1],..., CRDG2 [0] included in the correction data group CRDG2 following the output of the correction data group CRDG1. As described above, the output circuit 4 converts the parallel correction data groups CRDG1 and CRDG2 in series so that the output order is the order of the correction data groups CRDG1 and CRDG2, and sequentially outputs the converted serial data to the external terminal. To do.

  FIG. 2 shows an example of the read operation of the semiconductor memory device MEM1 shown in FIG. The rectangle shown in FIG. 2 indicates the operation of each circuit of the semiconductor memory device. FIG. 2A shows the operation when the data group RDG1 is 1 bit and the data group RDG2 is 7 bits. When the Hamming code method is employed, the 2-bit parity data group RPG1 is used for error correction of the data group RDG1, and the 4-bit parity data group RPG2 is used for error correction of the data group RDG2.

  FIG. 2B shows the operation when the data groups RDG1 and RDG2 each have 4 bits. When the Hamming code method is adopted, 3-bit parity data groups RPG1 and RPG2 are used for error correction of the data groups RDG1 and RDG2, respectively. FIG. 2C shows an operation (comparative example) when an 8-bit data group RDG is corrected by one error correction circuit to generate a corrected data group CRDG. When the Hamming code method is employed, a 4-bit parity data group RPG is used to correct an error in the data group RDG.

  2A and 2B, the semiconductor memory device MEM1 operates the memory unit 1 based on the read request RRQ. The memory unit 1 outputs data groups RDG1 and RDG2 and parity data groups RPG1 and RPG2. The error correction circuit 2 corrects an error in the data group RDG1 using the parity data group RPG1, and outputs a corrected data group CRDG1 (1 bit). The error correction circuit 3 corrects the error of the data group RDG2 using the parity data group RPG2, and sequentially outputs the corrected data group CRDG2 (7 bits) following the correction data group CRDG1.

  In FIG. 2A, the code length (1 + 2 bits) processed by the error correction circuit 2 is smaller than the code length (7 + 4 bits) processed by the error correction circuit 3. For this reason, the error correction time of the data group RDG1 by the error correction circuit 2 is shorter than the error correction time of the data group RDG2 by the error correction circuit 3. Therefore, the output circuit 4 can start outputting the first data while the error correction circuit 3 is executing the correction of the error of the data group RDG2. That is, by setting the head data output from the output circuit 4 as the correction data group CRDG1, the read access time tRD, which is the time from when the read request RRQ is received until the first data is output, is shown in FIG. ), Which can be shortened compared to FIG. Note that shortening the read access time tRD is shortened by shortening the generation time of the correction data group CRDG1, but not shortening by shortening the generation time of the correction data group CRDG2. For this reason, shortening the generation time of the correction data group CRDG1 output at the head is important for reducing the read access time tRD.

  In FIG. 2B, since the code lengths (7 bits) processed by the error correction circuits 2 and 3 are the same, the error correction time of the data group RDG1 by the error correction circuit 2 is the data by the error correction circuit 3. It is the same as the error correction time of the group RDG2. However, the 8-bit data read from the memory unit 1 is divided into two data groups RDG1 and RDG2, and each error is corrected by the error correction circuits 2 and 3, so that the read access time tRD can be obtained as shown in FIG. ) Can be shortened.

  As described above, in the embodiment shown in FIGS. 1 and 2, the error correction circuits 2 and 3 correct errors in the data groups RDG1 and RDG2 output in parallel from the memory unit 1, respectively. As a result, the time for outputting the head data of the serial data to the external terminal can be shortened compared with the case where the error of the data groups RDG1 and RDG2 is corrected by one error correction circuit. That is, the read access time tRD from when the read request is received until the head data is output can be shortened as compared with the case where the error of the data groups RDG1 and RDG2 is corrected by one error correction circuit. As a result, the performance of the semiconductor memory device MEM1 can be improved.

  FIG. 3 is a diagram illustrating another embodiment of the semiconductor memory device and the semiconductor memory device. The semiconductor memory device MEM2 shown in FIG. 3 is an SPI (Serial Peripheral Interface) type serial memory, stores data supplied in series to the input terminal SI, and outputs the stored data in series from the output terminal SO. To do. For example, the data input unit and output unit are 8 bits, and the 8-bit data is stored in one of four 8-bit storage areas (32 bits) according to the addresses A0 to A1. Examples of the read operation and the write operation of the semiconductor memory device MEM2 will be described with reference to FIGS.

  The semiconductor memory device MEM2 includes a memory cell array 10, an address decoder 20, a read / write control circuit 30, parity control circuits 40 and 50, and an input / output control circuit 60.

  The memory cell array 10 has a plurality of memory cells that hold 64 data groups D0 to D31 (that is, 2048 bits) according to 6-bit addresses IA0 to IA5. The memory cell is a memory cell such as a ferroelectric memory, SRAM (Static Random Access Memory), or DRAM (Dynamic Random Access Memory). The memory cell may be an MRAM (Magnetoresistive Random Access Memory) memory cell. The memory cell array 10 has a storage area M1 that holds 4-bit data D7, D15, D23, and D31 for each of the addresses IA0 to IA5. The memory cell array 10 has a storage area M2 for holding 28-bit data D0-D6, D8-D14, D16-D22, D24-D30 for each address IA0-IA5. The memory cell array 10 also has a storage area MP1 for storing 3-bit parity data P0-P2 for correcting errors in the data D7, D15, D23, D31 for each address IA0-IA5. Further, the memory cell array 10 stores a 6-bit parity data P3-P8 for correcting errors in the data D0-D6, D8-D14, D16-D22, D24-D30 for each address IA0-IA5. Have

  Note that each of the storage areas M1 and M2 may not be physically provided collectively. For example, the memory cell array 10 has four storage areas of data D0-D7, D8-D15, D16-D23, and D24-D31, and the storage areas M1 and M2 are distributed and arranged in the four storage areas. Also good. The memory cell array 10 is an example of a memory unit. Data D7, D15, D23, and D31 are examples of the first data group, and data D0-D6, D8-D14, D16-D22, and D24-D30 are examples of the second data group. Parity data P0-P2 is an example of a first parity data group, and parity data P3-P8 is an example of a second parity data group.

  The address decoder 20 decodes the addresses IA0 to IA5 in synchronization with the internal clock ICK, and depending on the value of the addresses IA0 to IA5, either of the 64 data groups D0 to D31 and the 64 parity data groups P0. -Select one of P8.

  The read / write control circuit 30 operates based on the control signal RCNT during a read operation for reading data from the memory cell array 10. The read / write control circuit 30 receives data D0-D31 and parity data P0-P8 selected by the address decoder 30 and output in parallel from the memory cell array 10. The read / write control circuit 30 outputs the data D7, D15, D23, D31 from the memory cell array 10 to the parity control circuit 40 as read data RD7, RD15, RD23, RD31. The read / write control circuit 30 reads the parity data P0-P2 from the memory cell array 10 and outputs the read parity data RP0-RP2 to the parity control circuit 40. The read / write control circuit 30 reads data D0-D6, D8-D14, D16-D22, D24-D30 from the memory cell array 10 as read data RD0-RD6, RD8-RD14, RD16-RD22, RD24-RD30. Output to 50. The read / write control circuit 30 reads the parity data P3-P8 from the memory cell array 10 and outputs it to the parity control circuit 50 as parity data RP3-RP8.

  On the other hand, the read / write control circuit 30 operates based on the control signal WCNT during a write operation for writing data into the memory cell array 10. The read / write control circuit 30 receives the write data WD7, WD15, WD23, WD31 and the write parity data WP0-WP2 from the parity control circuit 40. The read / write control circuit 30 receives write data WD0-WD6, WD8-WD14, WD16-WD22, WD24-WD30 and write parity data WP3-WP8 from the parity control circuit 50.

  The read / write control circuit 30 outputs the write data WD0-WD31 as data D0-D31 to the memory cell array 10, and outputs the write parity data WP0-WP8 as parity data P0-P8 to the memory cell array 10. The read / write control circuit 30 that writes data to the memory cell array 10 is an example of a write circuit. Write data WD7, WD15, WD23, and WD31 are examples of the first write data group, and write data WD0-WD6, WD8-WD14, WD16-WD22, and WD24-WD30 are examples of the second write data group. is there.

  In FIG. 3, for the sake of easy understanding, all the control signals for executing the read operation are shown as the control signal RCNT, but the control signal RCNT includes a plurality of timing signals. The control signal RCNT supplied to the read / write control circuit 30 is different from the control signal RCNT supplied to the parity control circuits 40 and 50. Similarly, all the control signals for executing the write operation are shown as the control signal WCNT, but the control signal WCNT includes a plurality of timing signals. The control signal WCNT supplied to the read / write control circuit 30 is different from the control signal WCNT supplied to the parity control circuits 40 and 50.

  The parity control circuit 40 operates during the read operation and the write operation, and corrects errors in the read data RD7, RD15, RD23, and RD31 using the read parity data RP0 to RP2. The parity control circuit 40 outputs the corrected read data RD7, RD15, RD23, RD31 as output data DO7, DO15, DO23, DO31. The output data DO7, DO15, DO23, and DO31 are an example of a first correction data group, and each of the output data DO7, DO15, DO23, and DO31 is an example of a first partial data group.

  The parity control circuit 40 operates based on the control signal WCNT during the write operation, and receives the input data DI07. The parity control circuit 40 replaces any of the output data DO7, DO15, DO23, and DO31 whose error has been corrected with the input data DI07 according to the value of the address A0-A1, and replaces the write data WD7, WD15, WD23, and WD31. Generate. That is, the input data DI07 is written into the memory cell array 10 as any of the write data WD7, WD15, WD23, and WD31.

  The parity control circuit 40 generates write parity data WP0-WP2 by using the generated write data WD7, WD15, WD23, WD31. Then, the parity control circuit 40 outputs the write data WD7, WD15, WD23, WD31 and the write parity data WP0-WP2 to the read / write control circuit 30.

  The parity control circuit 50 operates during a read operation and a write operation, and corrects errors in the read data RD0-RD6, RD8-RD14, RD16-RD22, and RD24-RD30 using the read parity data RP3-RP8. The parity control circuit 50 outputs the corrected read data RD0-RD6, RD8-RD14, RD16-RD22, RD24-RD30 as output data DO0-DO6, DO8-DO14, DO16-DO22, DO24-DO30. The output data DO0-DO6, DO8-DO14, DO16-DO22, and DO24-DO30 are an example of the second correction data group. Each of the output data DO0-DO6, DO8-DO14, DO16-DO22, DO24-DO30 is an example of the second partial data group.

  The parity control circuit 50 operates based on the control signal WCNT during a write operation, and receives 7-bit input data DI00 to DI06. The parity control circuit 50 converts any one of the output data DO0-DO6, DO8-DO14, DO16-DO22, and DO24-DO30 in which the error is corrected into the input data DI00-DI06 according to the value of the address A0-A1. replace. Then, the parity control circuit 50 generates write data WD0 to WD6, WD8 to WD14, WD16 to WD22, and WD24 to WD30. That is, the input data DI00-DI06 is written into the memory cell array 10 as any of the write data WD0-WD6, WD8-WD14, WD16-WD22, WD24-WD30.

  The parity control circuit 50 generates write parity data WP3-WP8 using the generated write data WD0-WD6, WD8-WD14, WD16-WD22, WD24-WD30. Then, the parity control circuit 50 outputs WD0-WD6, WD8-WD14, WD16-WD22, WD24-WD30, and write parity data WP3-WP8 to the read / write control circuit 30.

  The input / output control circuit 60 becomes valid during the period when the chip select / CS is at the low level, and operates in synchronization with the clock SCK. The input / output control circuit 60 receives a command (read command or write command) and an address via the input terminal SI, and outputs a part of the received address to the address decoder 20 as addresses IA0 to IA5. When receiving the read command, the input / output control circuit 60 generates a plurality of control signals RCNT, and converts the 8 bits of the 32-bit output data DO0 to DO31 output from the parity control circuits 40 and 50 to 2 bits. Selection is made according to addresses A0-A1. The input / output control circuit 60 converts the selected data into serial and sequentially outputs from the output terminal SO.

  When the output data DO0-DO7 is selected, the input / output control circuit 60 outputs the output data DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 to the output terminal SO in this order. When the output data DO8-DO15 is selected, the input / output control circuit 60 outputs the output data DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8 to the output terminal SO in this order. When the output data DO16-23 is selected, the input / output control circuit 60 outputs the output data DO23, DO22, DO21, DO20, DO19, DO18, DO17, and DO16 to the output terminal SO in this order. When the output data DO24-DO31 is selected, the input / output control circuit 60 outputs the output data DO31, DO30, DO29, DO28, DO27, DO26, DO25, DO24 to the output terminal SO in this order. That is, the input / output control circuit 60 outputs the data whose error has been corrected by the parity control circuit 40 before the data whose error has been corrected by the parity control circuit 50.

  When receiving a write command, the input / output control circuit 60 sequentially receives 8-bit serial data (write data) following the address via the input terminal SI and generates a plurality of control signals WCNT. The input / output control circuit 60 outputs the first 1-bit data received via the input terminal SI as the input data DI07 to the parity control circuit 40, and the remaining 7-bit data as the input data DI06-DI00. Output to 50.

  The semiconductor memory device MEM2 may adopt another serial interface method such as I2C (Inter-Integrated Circuit). In the I2C method, bidirectional input / output terminals for inputting / outputting data in series are provided in place of the input terminal SI and the output terminal SO. In the I2C method, a device address terminal that receives a device address code for identifying the semiconductor memory device MEM2 is provided instead of the chip select terminal / CS. The semiconductor memory device MEM2 includes a decoder that decodes the device address code and recognizes access to itself.

  FIG. 4 shows an example of the input / output control circuit 60 shown in FIG. The input / output control circuit 60 includes an input control circuit 62, an internal clock generation circuit 64, a selection circuit 66 and an output control circuit 68. The input control circuit 62 operates during a read operation and a write operation. The internal clock generation circuit 64 operates based on control from the input control circuit 62. The selection circuit 66 and the output control circuit 68 operate during a read operation.

  The input control circuit 62 operates during a period in which the chip select / CS is at a low level, and receives information (command, address, data, etc.) supplied via the input terminal SI in synchronization with the clock SCK. The input control circuit 62 has a shift register SFTRI and a command decoder CDEC. The shift register SFTRI has an 8-bit storage area for sequentially holding information supplied to the input terminal SI from the lower bit LSB side to the upper bit MSB side. The shift register SFTRI outputs the held information as a command CMD, internal addresses IA0 to IA5, addresses A0 to A1, and input data DI00 to DI07. The input control circuit 62 is an example of an input circuit.

  The command decoder CDEC receives, as a command CMD (opcode), 8 bits held in the shift register SFTRI first after the chip select / CS becomes low level. The command decoder CDEC generates a plurality of control signals RCNT when the command CMD indicates a read command (read request), and generates a plurality of control signals WCNT when the command CMD indicates a write command (write request).

  The internal clock generation circuit 64 generates the internal clock ICK after a predetermined clock cycle after receiving a read command or a write command. The clock cycle in which the internal clock ICK is generated is set according to the reception timing of the control signals RNCT and WNCT. As described with reference to FIG. 3, the clock cycle in which the internal clock ICK is generated indicates the timing at which the address decoder 20 starts its operation.

  The selection circuit 66 operates in the read operation, selects 8 bits of the output data DO0 to DO31 output from the parity control circuits 40 and 50 according to the addresses A0 to A1, and selects the selected data as the output data DOUT. Output to the output control circuit 68. For example, the selection circuit 66 selects the output data DO0-DO7 when the value of the address A0-A1 is “0”, and selects the output data DO8-DO15 when the value of the address A0-A1 is “1”. . The selection circuit 66 selects the output data DO16-DO23 when the value of the address A0-A1 is “2”, and selects the output data DO24-DO31 when the value of the address A0-A1 is “3”.

  The output control circuit 68 includes a shift register SFTR that holds 8-bit output data DOUT. The shift register SFTR outputs the held output data DOUT to the output terminal SO in synchronization with the clock SCK in the order from the upper bit MSB to the lower bit LSB. For example, when the output data DOUT is output data DO0 to DO7, the data DO7, DO6, DO5, DO4, DO3, DO2, DO1, and DO0 are output to the output terminal SO in this order. The output control circuit 68 is an example of an output circuit.

  FIG. 5 shows an example of the parity control circuit 40 shown in FIG. The parity control circuit 40 has a function of detecting any one bit error of the read data RD7, RD15, RD23, and RD31 and correcting the detected error. The parity control circuit 40 includes a read parity generation circuit 41, a syndrome generation circuit 42, a syndrome decoder 43, an error correction circuit 44, a replacement circuit 45, and a write parity generation circuit 46. The read parity generation circuit 41, the syndrome generation circuit 42, the syndrome decoder 43, and the error correction circuit 44 are an example of a first error correction circuit.

  The read parity generation circuit 41 generates 3-bit read parity data RP00 to RP02 using the 4-bit read data RD7, RD15, RD23, and RD31. Then, the read parity generation circuit 41 outputs the generated read parity data RP00 to RP02 to the syndrome generation circuit 42. The syndrome generation circuit 42 calculates an exclusive OR of the read parity data RP0-RP2 and the read parity data RP00-RP02 read from the memory cell array 10 via the read / write control circuit 30, and generates syndromes S0-S2. The syndrome generation circuit 42 outputs the generated syndromes S0 to S2 to the syndrome decoder 43.

  The syndrome decoder 43 decodes the logical value indicated by the syndromes S0 to S2, and generates any one of error bit information E7, E15, E23, and E31 indicating the bit in which an error has occurred. The syndrome decoder 43 outputs any one of the generated error bit information E7, E15, E23, E31 to the error correction circuit 44. Each of the error bit information E7, E15, E23, E31 indicates that there is an error in each of the read data RD7, RD15, RD23, RD31.

  The error correction circuit 44 corrects any error of the read data RD7, RD15, RD23, RD31 indicated by the error bit information E7, E15, E23, E31, and outputs data DO7, DO15, DO23, including the corrected data. DO31 is output.

  The replacement circuit 45 replaces any of the output data DO7, DO15, DO23, and DO31 corresponding to the value of the address A0-A1 with the input data DI07 (write data) in the write operation. Then, the replacement circuit 45 outputs write data WD7, WD15, WD23, and WD31 including the replaced data. The write data WD7, WD15, WD23, and WD31 are output to the read / write control circuit 30 shown in FIG.

  The replacement circuit 45 replaces the output data DO7 with the input data DI07 when the value of the address A0-A1 is “0”, and replaces the output data DO15 with the input data DI07 when the value of the address A0-A1 is “1”. . The replacement circuit 45 replaces the output data DO23 with the input data DI07 when the value of the address A0-A1 is “2”, and replaces the output data DO31 with the input data DI07 when the value of the address A0-A1 is “3”. .

  The write parity generation circuit 46 generates 3-bit write parity data WP0-WP2 using the 4-bit write data WD7, WD15, WD23, and WD31. The write parity generation circuit 46 outputs the generated write parity data WP0-WP2 to the read / write control circuit 30 shown in FIG. The write parity generation circuit 46 is an example of a parity generation circuit that generates write parity data WP0 to WP2.

  FIG. 6 shows an example of a parity check matrix used in the read parity generation circuit 41, the write parity generation circuit 46, the syndrome generation circuit 42, and the syndrome decoder 43 shown in FIG. The parity check matrix shown in FIG. 6 is used for parity check by the Hamming code method.

  The read parity generation circuit 41 generates the read parity data RP00 to RP02 of the read data RD7, RD15, RD23, and RD31 using the logic of columns (a) to (d) of the parity check matrix. The write parity generation circuit 46 generates write parity data WP0 to WP2 of the write data WD7, WD15, WD23, and WD31 using the logic of the columns (a) to (d).

  The syndrome generation circuit 42 generates syndromes S0 to S2 from the read parity data RP00 to RP02 and the read parity data RP0 to RP2, using the logic of the columns (e) to (g). The syndrome decoder 43 identifies the bit in which an error has occurred from the syndromes S0 to S2 using the logic of the columns (a) to (d).

  FIG. 7 shows an example of the read parity generation circuit 41, syndrome generation circuit 42, syndrome decoder 43, and error correction circuit 44 shown in FIG.

  The read parity generation circuit 41 has an exclusive OR gate corresponding to the logic of the parity check matrix of columns (a) to (d) shown in FIG. The read data RD7, RD15, RD23, and RD31 correspond to the columns (a) to (d), respectively, and the read parity data RP00 to RP02 correspond to the first to third rows of the parity check rows. The read parity generation circuit 41 calculates an exclusive OR of read data (any three of RD7, RD15, RD23, and RD31) corresponding to the column indicated by logic 1 in each row. Then, the read parity generation circuit 41 outputs the obtained exclusive OR logic as read parity data RP00 to RP02.

  The syndrome generation circuit 42 has an exclusive OR gate corresponding to the logic of the parity check matrix of columns (e) to (g) shown in FIG. The read parity data RP0, RP1, and RP2 correspond to the columns (e) to (g), respectively, and the read parity data RP00, RP01, and RP02 correspond to the first to third rows of the parity check row. The syndrome generation circuit 42 performs an exclusive OR of the read parity data (any one of RP0 to RP2) and the read parity data (any one of RP00 to RP02) corresponding to the logic 1 in the columns (e) to (g). Is calculated. Then, the syndrome generation circuit 42 outputs the obtained exclusive OR logic as syndromes S0 to S2.

  The syndrome decoder 43 has a decoding circuit corresponding to the logic of the parity check matrix of columns (a) to (d) shown in FIG. The error bit information E7, E15, E23, E31 corresponds to each of the columns (a) to (d), and the syndromes S0, S1, S2 correspond to the first to third rows of the parity check row. The syndrome decoder 43 generates error bit information E7 using (a) column logic, (b) generates error bit information E15 using column logic, and (c) error bit using column logic. Information E23 is generated, and error bit information E31 is generated using the logic of (d) column.

  The error correction circuit 44 has four exclusive OR gates for receiving the read data RD7, RD15, RD23, RD31 and the error bit information E7, E15, E23, E31, respectively. Then, when the error bit information E7 (or E15, E23, E31) is logic 1, the error correction circuit 44 inverts the logic of the read data RD7 (or RD15, RD23, RD31) to correct the error. correct. The error correction circuit 44 outputs the corrected data as output data DO7, DO15, DO23, DO31.

  In the read operation, there is a case in which a method of writing output data DO7, DO15, DO23, and DO31 back to the memory cell array 10 with corrected data is applied to the semiconductor memory device MEM2. In this case, errors in the read parity data RP0-RP2 are also corrected and written back to the memory cell array 10. In order to correct errors in the read parity data RP0 to RP2, a decode circuit corresponding to the logic of the parity check matrix of the columns (a) to (g) shown in FIG. In addition, an exclusive OR gate that inverts any bit of the read parity data RP0 to RP2 in which an error is detected by the syndrome decoder 43 is provided in the error correction circuit 44. The output data DO7, DO15, DO23, DO31 and the read parity data RP0-RP2 in which the error is corrected are written back to the memory cell array 10 without passing through the replacement circuit 45 and the write parity generation circuit 46 shown in FIG.

  In FIG. 7, the read parity generation circuit 41 and the syndrome generation circuit 42 have exclusive OR gates arranged in series corresponding to the logic of the parity check matrix shown in FIG. May be arranged in parallel.

  FIG. 8 shows an example in which the read parity generation circuit 41 and the syndrome generation circuit 42 shown in FIG. 7 are merged and exclusive OR gates are arranged in parallel. By arranging the exclusive OR gates in parallel, the number of exclusive OR gates connected in series to generate each of the syndromes S0 to S2 can be changed from three to two in FIG. it can.

  Consider a case where a 1-bit error in 32-bit read data RD0 to RD31 is corrected by a Hamming code method using one error correction circuit. In this case, the maximum number of exclusive OR gates provided in the error correction circuit is 18 in the case of serial connection and 5 in the case of parallel connection. Therefore, the maximum number of connection stages of exclusive OR gates can be reduced from 18 to 3 in the case of series connection compared to the case of using one error correction circuit, and 5 in the case of parallel connection. The number of stages can be reduced to two. As a result, the effect of shortening the error correction time becomes a time corresponding to 15 stages or 3 stages of the exclusive OR gate, and the error correction time of the read data RD7, RD15, RD23, RD31 is reduced to one. This can be shortened compared to the case of using an error correction circuit.

  FIG. 9 shows an example of the replacement circuit 45 and the write parity generation circuit 46 shown in FIG. The replacement circuit 45 includes a decoder DEC and a selector SEL. The decoder DEC obtains a bit position for writing the input data DI07 (write data) according to the logic of the addresses A0 to A1.

  The selector SEL has four switch circuits that replace any of the output data DO7, DO15, DO23, and DO31 with the input data DI07 based on the bit position obtained by the decoder DEC. For example, each switch circuit has a pair of complementary metal oxide semiconductor (CMOS) transmission gates. Then, the selector SEL outputs the write data WD7, WD15, WD23, and WD31 including the replaced input data DI07 to the write parity generation circuit 46.

  The write parity generation circuit 46 has the same logic as the read parity generation circuit 41 shown in FIG. Write data WD7, WD15, WD23, and WD31 correspond to columns (a) to (d) of the parity check matrix shown in FIG. 6, and write parity data WP0-WP2 are from the first row of the parity check rows. Corresponds to the third row. The write parity generation circuit 46 calculates an exclusive OR of write data (any three of WD7, WD15, WD23, and WD31) corresponding to the column indicated by logic 1 in each row. Then, the write parity generation circuit 46 outputs the obtained exclusive OR logic as write parity data WP0-WP2.

  FIG. 10 shows an example of the parity control circuit 50 shown in FIG. The parity control circuit 50 has a function of detecting any one bit error of the read data RD0 to RD6, RD8 to RD14, RD16 to RD22, and RD24 to RD30, and correcting the detected error. The parity control circuit 50 has a circuit similar to the parity control circuit 40 shown in FIG. That is, the parity control circuit 50 includes a read parity generation circuit 51, a syndrome generation circuit 52, a syndrome decoder 53, an error correction circuit 54, a replacement circuit 55, and a write parity generation circuit 56. The read parity generation circuit 51, the syndrome generation circuit 52, the syndrome decoder 53, and the error correction circuit 54 are examples of a second error correction circuit.

  The read parity generation circuit 51 generates 6-bit read parity data RP03-RP08 using 28-bit read data RD0-RD6, RD8-RD14, RD16-RD22, and RD24-RD30. The syndrome generation circuit 52 calculates the exclusive OR of the read parity data RP3-RP8 and the read parity data RP03-RP08 read from the memory cell array 10 via the read / write control circuit 30, and generates syndromes S3-S8.

  The syndrome decoder 53 decodes the logical value indicated by the syndromes S3-S8, and generates any one of error bit information E0-E6, E8-E14, E16-E22, E24-E30 indicating the bit in which an error has occurred. Each of the error bit information E0-E6, E8-E14, E16-E22, E24-E30 indicates that each of the read data RD0-RD6, RD8-RD14, RD16-RD22, RD24-RD30 has an error.

  The error correction circuit 54 detects any error of the read data RD0-RD6, RD8-RD14, RD16-RD22, RD24-RD30 indicated by the error bit information E0-E6, E8-E14, E16-E22, E24-E30. correct. Then, the error correction circuit 54 outputs the corrected data as output data DO0-DO6, DO8-DO14, DO16-DO22, DO24-DO30.

  In the write operation, the replacement circuit 55 converts any set of the output data DO0-DO6, DO8-DO14, DO16-DO22, DO24-DO30 corresponding to the value of the address A0-A1 to the input data DI00-DI06 (write data). Replace with Then, the replacement circuit 45 outputs write data WD0 to WD6, WD8 to WD14, WD16 to WD22, and WD24 to WD30 including the replaced data. Write data WD0 to WD6, WD8 to WD14, WD16 to WD22, and WD24 to WD30 are output to the read / write control circuit 30 shown in FIG.

  The replacement circuit 55 replaces the output data DO0-DO6 with the input data DI00-DI06 when the value of the address A0-A1 is “0”, and the output data DO8-DO14 when the value of the address A0-A1 is “1”. Is replaced with input data DI00-DI06. The replacement circuit 55 replaces the output data DO16-DO22 with the input data DI00-DI06 when the value of the address A0-A1 is “2”, and the output data WD24-WD30 when the value of the address A0-A1 is “3”. Is replaced with input data DI00-DI06.

  The write parity generation circuit 56 generates 6-bit write parity data WP3-WP8 using 28-bit write data WD0-WD6, WD8-WD14, WD16-WD22, and WD24-WD30. The write parity generation circuit 56 outputs the generated write parity data WP3-WP8 to the read / write control circuit 30 shown in FIG. The write parity generation circuit 56 is an example of a parity generation circuit that generates the write parity data WP3-WP8.

  FIG. 11 shows an example of a parity check matrix used in the read parity generation circuit 51, the write parity generation circuit 56, the syndrome generation circuit 52, and the syndrome decoder 53 shown in FIG. The parity check matrix shown in FIG. 11 is used for parity check by the Hamming code method.

  The read parity generation circuit 51 uses the logic of 28 columns from the (a) column to the (b1) column of the parity check matrix to read the read parity data of the read data RD0 to RD6, RD8 to RD14, RD16 to RD22, and RD24 to RD30. RP03-RP08 are generated. Similar to the read parity generation circuit 41 shown in FIG. 7, the read parity generation circuit 51 includes an exclusive OR gate corresponding to the logic of the parity check matrix from the (a) column to the (b1) column. That is, read data RD0-RD6, RD8-RD14, RD16-RD22, and RD24-RD30 correspond to columns (a) to (b1), respectively, and read parity data RP03-RP08 are the first in the parity check row. Corresponds to the sixth line. The read parity generation circuit 51 calculates a predetermined number of exclusive ORs of read data RD0 to RD6, RD8 to RD14, RD16 to RD22, and RD24 to RD30 corresponding to the column indicated by logic 1 in each row. Then, the read parity generation circuit 51 outputs the obtained exclusive OR logic as read parity data RP03 to RP08.

  The syndrome generation circuit 52 generates syndromes S3-S8 from the read parity data RP3-RP8 and RP03-RP08 using the logic of six columns from the (c1) column to the (h1) column. Similar to the syndrome generation circuit 42 shown in FIG. 7, the syndrome generation circuit 52 has an exclusive OR gate corresponding to the logic of the parity check matrix from the (c1) column to the (h1) column. That is, the read parity data RP3 to RP8 correspond to each of the columns (c1) to (h1), and the read parity data RP03 to RP08 correspond to the first to sixth rows of the parity check row. The syndrome generation circuit 52 performs exclusive OR of read parity data (any one of RP3 to RP8) and read parity data (any one of RP03 to RP08) corresponding to the logic 1 in the columns (c1) to (h1). Is calculated. Then, the syndrome generation circuit 52 outputs the obtained exclusive OR logic as syndromes S3 to S8.

  The syndrome decoder 53 identifies the bit in which an error has occurred from the syndromes S3 to S8 using the logic of 28 columns from the (a) column to the (b1) column. The circuit configuration of the syndrome decoder 53 is the same as that of the syndrome decoder 43 shown in FIG. That is, error bit information E0-E6, E8-E14, E16-E22, E24-E30 corresponds to each of columns (a) to (b1), and syndromes S3-S8 are the first row of parity check rows. To 6th line. The syndrome decoder 53 generates (a) error bit information E0 using the column logic, (b) generates error bit information E1 using the column logic,. . . , (B1) The error bit information E30 is generated using the logic of the column.

  The write parity generation circuit 56 uses the logic of 28 columns from the (a) column to the (b1) column to write the write parity data WP3-WP8 of the write data WD0-WD6, WD8-WD14, WD16-WD22, WD24-WD30. Generate. The logic of the write parity generation circuit 56 is the same as the logic of the read parity generation circuit 51. Write data WD0-WD6, WD8-WD14, WD16-WD22, and WD24-WD30 correspond to columns (a) to (b1), respectively, and write parity data WP3-WP8 starts from the first row of the parity check row. Corresponds to the sixth line.

  When designing the logic of the read parity generation circuit 51 and the syndrome generation circuit 52 according to the logic of the parity check matrix shown in FIG. 10, the number of stages of exclusive OR gates connected in series is as follows. The maximum is 17 steps. The number of exclusive OR gates connected in series is the number obtained by subtracting “1” from the number of logic 1s in each row of the parity check matrix. Similarly to FIG. 8, when the read parity generation circuit 51 and the syndrome generation circuit 52 are merged and the exclusive OR gates are arranged in parallel, the maximum number of stages of the exclusive OR gate is changed from 17 to 5 stages. Reduced.

  FIG. 12 shows an example of the error correction circuit 54 shown in FIG. The error correction circuit 54 receives the read data RD0-RD6, RD8-RD14, RD16-RD22, RD24-RD30 and bit information E0-E6, E8-E14, E16-E22, E24-E30, respectively. Has a gate. Then, similarly to the error correction circuit 44 shown in FIG. 7, the error correction circuit 54 inverts the logic of the read data (for example, RD0) when the error bit information (for example, E0) is the logic 1, Correct the error. The error correction circuit 54 outputs the corrected data as output data DO0-DO6, DO8-DO14, DO16-DO22, DO24-DO30.

  In the read operation, there is a case where a method of writing back the corrected data in the output data DO0-DO6, DO8-DO14, DO16-DO22, DO24-DO30 to the memory cell array 10 in the semiconductor memory device MEM2. . In this case, the error in the read parity data RP3-RP8 is also corrected and written back to the memory cell array 10. In order to correct errors in the read parity data RP3 to RP8, the syndrome decoder 53 is provided with a decode circuit corresponding to the logic of the parity check matrix of the columns (c1) to (h1) shown in FIG. In addition, an exclusive OR gate that inverts any bit of the read parity data RP <b> 3 to RP <b> 8 in which an error is detected by the syndrome decoder 53 is provided in the error correction circuit 54. Then, the output data DO0-DO6, DO8-DO14, DO16-DO22, DO24-DO30 and the read parity data RP3-RP8 in which the error is corrected are written back to the memory cell array 10. At this time, the replacement circuit 55 and the write parity generation circuit 56 shown in FIG. 10 are not used for data write-back.

  FIG. 13 shows an example of the replacement circuit 55 shown in FIG. The replacement circuit 55 includes a decoder DEC and a selector SEL similarly to the replacement circuit 45 shown in FIG. The decoder DEC is the same as the decoder DEC shown in FIG.

  The selector SEL replaces any of the output data DO0, DO8, DO16, and DO24 with the input data DI00 based on the bit position obtained by the decoder DEC, and replaces any of the output data DO1, DO9, DO17, and DO25 with the input data DI01. Replace with The selector SEL replaces any of the output data DO2, DO10, DO18, and DO26 with the input data DI02, and replaces any of the output data DO3, DO11, DO19, and DO27 with the input data DI03. The selector SEL replaces any of the output data DO4, DO12, DO20, and DO28 with the input data DI04, and replaces any of the output data DO5, DO13, DO21, and DO29 with the input data DI05. Then, the selector SEL replaces any of the output data DO6, DO14, DO22, and DO30 with the input data DI06.

  FIG. 14 shows an example of the read operation of the semiconductor memory device MEM2 shown in FIG. First, the command decoder CDEC shown in FIG. 4 receives 8-bit data “00000011” via the input terminal SI in the first 8 clock cycles after the chip select / CS changes to the low level (FIG. 14A). . The command decoder CDEC recognizes the read command based on the data “00000011” and outputs the control signal RCNT (FIG. 14B).

  Next, the shift register SFTRI shown in FIG. 4 receives the address A7-A2 via the input terminal SI in the eighth to thirteenth clock cycles (FIG. 14 (c)). The internal clock generation circuit 64 shown in FIG. 4 outputs the internal clock ICK in the 14th clock cycle (FIG. 14 (d)).

  The address decoder 20 receives the address A7-A2 as the internal address IA5-IA0 in synchronization with the internal clock ICK, and starts the decoding operation (FIG. 14 (e)). The memory cell array 10 starts a read operation based on the result of decoding by the address decoder 20. The read / write control circuit 30 shown in FIG. 3 outputs read data RD0-RD31 and read parity data RP0-RP8 read from the storage area indicated by the internal addresses IA5-IA0 during the fourteenth clock cycle (FIG. 3). 14 (f)). The shift register SFTRI receives addresses A1 and A0 for selecting 8 bits of 32-bit read data RD0 to RD31 in the 14th and 15th clock cycles (FIG. 14 (g)).

  The parity control circuit 40 shown in FIG. 3 corrects errors in the read data RD7, RD15, RD23, and RD31 using the read parity data RP0 to RP2 in the 14th clock cycle. The parity control circuit 40 outputs the read data RD7, RD15, RD23, and RD31 corrected for errors as output data DO7, DO15, DO23, and DO31 (FIG. 14 (h)).

  The parity control circuit 50 shown in FIG. 3 corrects errors in the read data RD0-RD6, RD8-RD14, RD16-RD22, and RD24-RD30 using the read parity data RP3-RP8 in the 14th clock cycle. The parity control circuit 50 outputs the read data RD0 to RD6, RD8 to RD14, RD16 to RD22, and RD24 to RD30 whose errors are corrected as output data DO0 to DO6, DO8 to DO14, DO16 to DO22, and DO24 to DO30 (FIG. 14 (i)). Here, the error correction time by the parity control circuit 40 is shorter than the error correction time by the parity control circuit 50. For this reason, the output time of the output data DO7, DO15, DO23, DO31 is earlier than the output time of the output data DO0-DO6, DO8-DO14, DO16-DO22, DO24-DO30.

  The selection circuit 66 shown in FIG. 4 selects 8 bits from the read data RD0 to RD31 in which the error is corrected based on the addresses A1 to A0 from the 14th to the 15th clock cycles, and stores them in the shift register SFTR. Transfer (FIG. 14 (j)). In the example shown in FIG. 14, the selection circuit 66 selects read data RD0-RD7 (data D0-D7) based on the address A1-A0 = "00".

  For example, the transfer of the read data RD7-RD0 from the selection circuit 66 to the shift register SFTR changes according to the error correction time. Since the read data RD7 has a shorter error correction time than the read data RD6-RD0, the transfer time to the shift register SFTR is earlier than the transfer time of the read data RD6-RD0. In FIG. 14, the timing at which the read data RD6-RD0 is transferred to the shift register SFTR is indicated by hatched rectangles.

  The shift register SFTR0 outputs the data D7 to the output terminal SO in the 16th clock cycle (FIG. 14 (k)). Thereafter, the shift register SFTR0 sequentially outputs data D6-D0 to the output terminal SO in the 17th to 23rd clock cycles (FIG. 14 (l)). Then, the clock SCK stops, the chip select / CS changes to high level, and the read operation is completed.

  Note that the data D6-D0 corresponding to the read data RD6-RD0 may not be stored in the shift register SFTR at the timing when the data D7 is output from the output terminal SO7. The data D6-D0 only needs to be stored in the shift register SFTR by the rising edge of the 16th clock SCK.

  For example, it is assumed in advance that the storage timing of the data D6-D0 in the shift register SFTR is not in time for the rising edge of the 16th clock SCK. In this case, the selection circuit 66 may store the data D6 to D0 at a position shifted by 1 bit on the most significant bit side in the shift register SFTR. In order to shift the bit position, in FIG. 4, for example, a switching circuit for shifting the output data DOUT corresponding to the data D6-D0 by one bit to the most significant bit side in synchronization with the rising edge of the 16th clock SCK is provided. It is done.

  FIG. 15 shows an example of a main part of the read operation shown in FIG. The upper waveform in FIG. 15 shows the operation of the semiconductor memory device MEM2 shown in FIG. 3 (that is, the operation in FIG. 14), and the lower waveform in FIG. 15 detects errors in the read data RD0 to RD31 as one error detection. An operation (comparative example) of a semiconductor memory device in which correction is performed at once by a circuit will be described.

  The address decoder 20 starts an operation of decoding the addresses IA0 to IA5 in the 14th clock cycle in synchronization with the rising edge of the internal clock ICK. The first data D7 is output to the output terminal SO in the 16th clock cycle. Therefore, the frequency of the clock SCK is set so that the total of the operation period of the address decoder 20 and the memory cell array 10, the error correction period of the read data RD7, RD15, RD23, and RD31 and the selection period of the data D7 is two clock cycles or less. Is set. Hereinafter, the total of the operation period of the address decoder 20 and the memory cell array 10, the error correction period of the read data RD7, RD15, RD23, and RD31 and the selection period of the data D7 is referred to as an internal operation period.

  The period of two clock cycles is represented by “2 / f”, where the frequency of the clock SCK is “f”. Since the internal operation period satisfies the cycle 2 / f or less (2 / f ≧ internal operation period), the maximum frequency fmax of the clock SCK of the semiconductor memory device MEM2 becomes “2 / internal operation period”. For example, when the internal operation period is 80 nanoseconds, the maximum frequency fmax of the clock SCK is 25 MHz (megahertz).

  On the other hand, when errors in 32-bit read data RD0-RD31 output from the memory cell array 10 are corrected at one time by one error detection circuit, the circuit scale of the error detection circuit is the parity control circuit shown in FIGS. More than 40 circuit scales. For example, in the read parity generation circuit and the syndrome generation circuit provided in the error detection circuit, the number of exclusive OR gates connected in series increases. As a result, the error correction period of the read data RD0 to RD31 becomes longer than the upper waveform in FIG. The total of the operation period of the address decoder, the memory cell array, the error correction period of the read data RD0 to RD31, and the selection period of the data D7 is also limited to 2 clock cycles or less in the upper waveform of FIG. As a result, the cycle of the clock SCK is longer than the upper waveform in FIG. 15, and the frequency of the clock SCK is lower than the upper waveform in FIG. In other words, in the semiconductor memory device MEM2 shown in FIG. 3, the frequency of the clock SCK can be increased as compared with the conventional case, and the data read time can be shortened.

  In the semiconductor memory device MEM2 shown in FIG. 3, read data RD0-RD31 that is four times the 8-bit data D7-D0 sequentially output from the output terminal SO is output from the memory cell array 10. Addresses A0-A1 received sequentially at input terminal SI are used to select 8 bits of 32-bit read data RD0-RD31, and are not used by address decoder 20. For this reason, the two clock cycles to which the addresses A0 to A1 are supplied are allocated to the internal operation period.

  For example, in a semiconductor memory device that selects 8 bits out of 64-bit read data RD0 to RD63 output from the memory cell array and outputs the selected data from the output terminal SO, 3 clock cycles can be assigned to the internal operation period. In a semiconductor memory device that selects 8 bits out of 16-bit read data RD0 to RD15 output from the memory cell array and outputs the selected data from the output terminal SO, one clock cycle can be allocated to the internal operation period. When the number of bits of read data output from the memory cell array is “2 to the power of n” (n is an integer of 4 or more) and 8-bit data is sequentially output from the output terminal SO, the maximum frequency of the clock SCK is , “(N−3) / internal operation period”.

  FIG. 16 shows an example of the write operation of the semiconductor memory device MEM2 shown in FIG. Detailed description of operations similar to those in FIG. 14 is omitted.

  The write command for executing the write operation is recognized by 8-bit data “00000010” received via the input terminal SI in the first 8 clock cycles after the chip select / CS changes to the low level (FIG. 16A). ). The command decoder CDEC recognizes the write command based on the data “00000010” and outputs the control signal WCNT (FIG. 16B).

  Next, the shift register SFTRI receives the address A7-A2 from the input terminal SI in the eighth to thirteenth clock cycles, and outputs the received address A7-A2 to the address decoder 20 as the internal address IA5-IA0 (FIG. 16). (C)). The internal clock generation circuit 64 outputs the internal clock ICK in the 14th clock cycle (FIG. 16 (d)).

  The address decoder 20 starts a decoding operation in synchronization with the internal clock ICK, and the memory cell array 10 starts a writing operation based on the decoding result by the address decoder 20 (FIG. 16 (e)). Thereafter, as in FIG. 14, the parity control circuits 40 and 50 correct the errors of the read data RD7, RD15, RD23, and RD31 and the read data RD0-RD6, RD8-RD14, RD16-RD22, and RD24-RD30, respectively. The The parity control circuits 40 and 50 output the output data DO7, DO15, DO23, and DO31 and the output data DO0-DO6, DO8-DO14, DO16-DO22, and DO24-DO30, respectively, in which errors are corrected (FIG. 16 (f)). (G)).

  The shift register SFTRI receives addresses A1 and A0 indicating which 8-bit write data is written in 32 bits in the 14th and 15th clock cycles (FIG. 16 (h)).

  Thereafter, the shift register SFTRI sequentially receives 8-bit write data D7-D0 in the 16th to 23rd clock cycles (FIG. 16 (i)). The replacement circuit 45 shown in FIG. 5 replaces any of the output data DO7, DO15, DO23, and DO31 with data DI00 received from the shift register SFTRI, and generates write data WD7, WD15, WD23, and WD31 (FIG. 16 (j)). ). The write parity circuit 46 shown in FIG. 5 generates write parity data WP0 to WP2 of the write data WD7, WD15, WD23, and WD31.

  On the other hand, replacement circuit 55 shown in FIG. 10 replaces any 7 bits of output data DO0-DO6, DO8-DO14, DO16-DO22, and DO24-DO30 with data DI00-DI06 received from shift register SFTRI. Then, the replacement circuit 55 generates write data WD0-WD6, WD8-WD14, WD16-WD22, and WD24-WD30 (FIG. 16 (k)). The write parity circuit 56 shown in FIG. 10 generates write parity data WP3-WP8 of the write data WD0-WD6, WD8-WD14, WD16-WD22, and WD24-WD30.

  Then, write data WD 0 -WD 31 and write parity data WP 0 -WP 8 are written into the memory cell array 10. After the write data D0 is supplied to the input terminal SI, the clock SCK stops, the chip select / CS changes to high level, and the write operation is completed. Note that the writing of the write data WD0-WD31 and the write parity data WP0-WP8 to the memory cell array 10 may be completed after the chip select / CS changes to high level.

  As described above, in the embodiment shown in FIGS. 3 to 16 as well, in the same way as the embodiment shown in FIGS. Can be shortened. As a result, the performance of the semiconductor memory device MEM2 can be improved.

  Further, in the embodiment shown in FIGS. 3 to 16, the error correction circuit 44 corrects an error of 4-bit data (D7, D15, D23, D31), which is the head data output from the output terminal SO, and corrects the error. The circuit 54 corrects an error in 28-bit data following the head data. Thereby, the circuit scale of the error correction circuit 44 for correcting the error of the head data can be made smaller than the circuit scale of the error correction circuit 54, and the error correction time by the error correction circuit 44 is reduced by the error correction circuit 54. Can be shorter than the correction time. As a result, the output timing of the first data (for example, D7) output from the output terminal SO can be made faster than before.

  In the semiconductor memory device MEM2 that selects 8 bits of the 32-bit data output from the memory cell array 10 by the selection circuit 66, the output timing of the head data from the output terminal SO can be made earlier than before. it can. At this time, the error correction circuit 44 corrects errors in the read data RD7, RD15, RD23, and RD31 that are the head data output from the output terminal SO. Thereby, irrespective of the head data selected by the addresses A0 to A1, the output timing of the head data can be made earlier than in the prior art.

  The replacement circuits 45 and 55 replace a part of the read data whose error is corrected with the write data received at the input terminal SI. Thereby, even when data D0-D31 having a bit width larger than the write data received at the input terminal SI is stored in the memory cell array 10, the consistency between the write data and the parity data can be maintained.

  The replacement circuit 45 and the write parity generation circuit 46 generate write parity data WP0 to WP2 of the write data WD7, WD15, WD23, and WD31 corresponding to the head data. The replacement circuit 55 and the write parity generation circuit 56 generate write parity data WP3-WP8 of the write data WD0-WD6, WD8-WD14, WD16-WD22, WD24-WD30 corresponding to the subsequent data following the head data. Thereby, each of the parity data P0 to P2 and P3 to P8 used for error correction by the error correction circuits 44 and 54 can be held in the memory cell array 10, and the error correction by the error correction circuits 44 and 54 is normally executed. can do.

  FIG. 17 shows another embodiment of the semiconductor memory device and the method for controlling the semiconductor memory device. The same or similar elements as those described in the embodiment shown in FIGS. 3 to 16 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The semiconductor memory device MEM3 of this embodiment includes 8-bit data D0-D7, parity data P0-P1 for correcting an error in the data D7, and parity data P2- for correcting an error in the data D0-D6. A memory cell array 10a for storing P5. For example, the memory cell array 10a includes a plurality of memory cells that hold 64 data groups D0 to D7 (that is, 512 bits) according to 6-bit addresses IA0 to IA5.

  The address decoder 20 is the same as the address decoder 20 of FIG. The read / write control circuit 30a has the same function as that of the read / write control circuit 30 shown in FIG. 3 except that the bit width of data input / output to / from the memory cell array 10a is 14 bits.

  The parity control circuit 40a is a circuit similar to the parity control circuit 40 shown in FIG. 5 except that it does not have the replacement circuit 45 shown in FIG. The parity control circuit 50a is a circuit similar to the parity control circuit 50 shown in FIG. 10 except that the parity control circuit 50a does not have the replacement circuit 55 shown in FIG. In the semiconductor memory device MEM3, the number of bits of data D0 to D7 input / output to / from the memory cell array 10a is equal to the number of bits of write data received at the input terminal SI and the number of bits of read data output to the output terminal SO. . For this reason, the parity control circuit 40a does not have the replacement circuit 45 shown in FIG. 5, and the parity control circuit 50a does not have the replacement circuit 55 shown in FIG. Since the parity control circuits 40a and 50a do not synthesize read data and write data, they do not receive the addresses A0 to A1 shown in FIG.

  During the read operation, the parity control circuit 40a corrects an error in the read data RD7 using the read parity data RP0 to RP1, generates output data DO7, and outputs it as output data to the output terminal SO. The parity control circuit 40a generates write parity data WP0-WP1 of the first input data DI07 received through the input terminal SI during the write operation, and outputs the input data DI07 and the write parity data WP0-WP1 to the memory cell array 10a. To do.

  During the read operation, the parity control circuit 50a corrects errors in the read data RD0 to RD6 using the read parity data RP2 to RP5 to generate output data DO0 to DO6, and outputs the output data SO following the head data (D7). Output to. The parity control circuit 50a generates write parity data WP2-WP5 of the input data DI06-DI00 received following the input data DI07 via the input terminal SI during the write operation. Then, the parity control circuit 50a outputs the input data DI06-DI00 and the write parity data WP2-WP5 to the memory cell array 10a.

  The input / output control circuit 60a is the same circuit as the selection circuit 66 shown in FIG. 4 except that it does not have the selection circuit 66 shown in FIG. An example of the input / output control circuit 60a is shown in FIG.

  FIG. 18 shows an example of the input / output control circuit 60a shown in FIG. The input / output control circuit 60a is the same as the input / output control circuit 60 shown in FIG. 4 except that the selection circuit 66 is not provided. That is, shift register SFTR directly receives output data DO0-DO7 output from parity control circuit 50a shown in FIG. Further, since the address A0-A1 shown in FIG. 4 is not supplied to the input terminal SI, the shift register SFTRI does not output the address A0-A1.

  FIG. 19 shows an example of the read operation of the semiconductor memory device MEM3 shown in FIG. Detailed description of operations similar to those in FIG. 14 is omitted. The read operation of the semiconductor memory device MEM3 is the same as the read operation shown in FIG. 14 except that the clock cycle that receives the addresses A1-A0 is omitted. The operation up to the 13th clock cycle is the same as in FIG.

  Since the clock cycle for receiving the addresses A1-A0 is omitted, error correction of the read data RD7 (D7) output from the memory cell array 10a is executed by the end of the 14th clock cycle in which the internal clock ICK is generated. The Then, output data DO7 in which the error is corrected is generated (FIG. 19A). Data D7 corresponding to the output data DO7 is output to the output terminal SO in the fifteenth clock cycle (FIG. 19 (b)).

  Further, by the end of the fifteenth clock cycle, errors in the read data RD0-RD6 are corrected, and output data DO0-DO6 are generated (FIG. 19 (c)). The data D6-D0 corresponding to the output data DO6-DO0 are sequentially output to the output terminal SO in the 16th to 22nd clock cycles (FIG. 19 (d)). That is, the time required for error correction of data D6-D0 output after head data D7 may be longer than the time required for error correction of head data D7. In other words, by correcting the error of the head data D7 by the parity control circuit 40a and correcting the error of the remaining data D6-D0 by the parity control circuit 50a, the time until the head data D7 is output is compared with the conventional time. Can be shortened.

  FIG. 20 shows an example of the write operation of the semiconductor memory device MEM3 shown in FIG. Detailed description of the same operations as those in FIG. 16 is omitted. The operation up to the 13th clock cycle is the same as in FIG.

  Since the semiconductor memory device MEM3 does not replace the read data with the write data, it does not read data from the memory cell array 10a during the write operation, and does not correct errors in the read data. For this reason, the address decoder 20 only needs to operate in accordance with the data writing to the memory cell array 10a, and the internal clock ICK is generated in the 21st clock cycle (FIG. 20A). The addresses IA0 to IA5 output from the shift register SFTRI in the thirteenth clock cycle are held in the address decoder 20 until the twenty-first clock cycle (FIG. 20B). The address decoder 20 starts a decoding operation in synchronization with the internal clock ICK, and the memory cell array 10a starts a writing operation based on the decoding result by the address decoder 20 (FIG. 20 (c)).

  The internal clock ICK may be generated in the 14th clock cycle, as in FIG. In this case, the address decoder 20 starts the decoding operation at the 14th clock cycle, and the memory cell array 10a starts the writing operation based on the decoding result by the address decoder 20. However, from the viewpoint of reducing the power consumption of the memory cell array 10a, it is desirable to generate the internal clock ICK in the 21st clock cycle.

  The shift register SFTRI sequentially receives 8-bit write data D7-D0 in the 14th to 21st clock cycles (FIG. 20 (d)). The parity control circuit 40a shown in FIG. 17 generates write parity data WP0-WP1 of the write data WD7 corresponding to the data D7, and outputs the write data WD7 and the write parity data WP0-WP1 to the memory cell array 10a (FIG. 20 ( e)). The parity control circuit 50a illustrated in FIG. 17 generates write parity data WP2-WP5 of the write data WD0-WD6 corresponding to the data D0-D6. The parity control circuit 50a outputs the write data WD0-WD6 and the write parity data WP2-WP5 to the memory cell array 10a (FIG. 20 (f)). Then, write data WD0-WD7 and write parity data WP0-WP5 are written into the memory cell array 10a. Note that the writing of the write data WD0 to WD7 and the write parity data WP0 to WP5 to the memory cell array 10a may be completed after the chip select / CS changes to high level.

  As described above, also in the embodiment shown in FIGS. 17 to 20, the same effect as that of the embodiment shown in FIGS. 1 to 16 can be obtained. That is, the time from receiving the read command to outputting the leading data (for example, D7) can be shortened compared to the conventional case, and the performance of the semiconductor memory device MEM3 can be improved. Further, by reducing the number of bits for error correction by the parity control circuit 40a to be smaller than the number of bits for error correction by the parity control circuit 50a, the output timing of the first data D7 output from the output terminal SO is made earlier than before. be able to.

  The embodiment shown in FIGS. 1 to 20 shows an example of a semiconductor memory device (serial memory) that outputs read data from one terminal. However, for example, a 2-bit serial memory that outputs two read data from two terminals may be designed by combining two configurations of the semiconductor memory device MEM1 illustrated in FIG. Similarly, a serial memory that outputs a plurality of bits of data may be designed by combining a plurality of semiconductor memory devices MEM2 and MEM3 shown in FIG.

  Further, the embodiment shown in FIGS. 1 to 20 can be applied to a semiconductor memory device such as a FIFO (First In First Out) memory that continuously stores data in a storage unit without inputting a command and an address. . In this case, data is written using two write circuits included in each of the parity control circuits 40a and 40b shown in FIG. For example, when data D7-D0 is input in series to the input terminal SI, one writing circuit generates parity data of data D7-D1 based on the input of data D7-D1, and data D7 Write D1 and parity data to the memory cell array. The other writing circuit generates parity data of the data D0 based on the input of the last data D0, and writes the data D0 and the parity data in the memory cell array. Thus, the parity time of the data D7-D0 is generated based on the input of all the data D7-D0, and the write time is reduced compared with the case where the data D7-D0 and the parity data are written to the memory cell array. It can be shortened.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  DESCRIPTION OF SYMBOLS 1 ... Memory part; 2, 3 ... Error correction circuit; 4 ... Output circuit; 10, 10a ... Memory cell array; 20 ... Address decoder; 30, 30a ... Read / write control circuit; 40, 40a ... Parity control circuit; 42: Syndrome generation circuit; 43 ... Syndrome decoder; 44 ... Error correction circuit; 45 ... Replacement circuit; 46 ... Write parity generation circuit; 50, 50a ... Parity control circuit; 51 ... Read parity generation circuit; 53: Syndrome decoder; 54 ... Error correction circuit; 55 ... Replacement circuit; 56 ... Write parity generation circuit; 60, 60a ... Input / output control circuit; 62 ... Input control circuit; Selection circuit; 68 ... Output control circuit; A0-A1 ... Address; CRDG , CRDG2 ... correction data group; / CS ... chip select; D0-D31 ... data; DEC ... decoder; DI00-DI07 ... input data; DO0-DO31 ... output data; E0-E31 ... error bit information; IA0-IA5 ... address ICK: Internal clock; MEM1, MEM2, MEM3: Semiconductor memory device; P0-P8: Parity data; RCNT ... Control signal; RD0-RD31 ... Read data; RP00-RP08 ... Read parity data; RP0-RP8 ... Read parity data RPG1, RPG2 ... Parity data group; RDG1, RDG2 ... Data group; S0-S8 ... Syndrome; SCK ... Clock; SEL ... Selector; SI ... Input terminal; SO ... Output terminal; WCNT ... Control signal; WD0-WD31 ... Write Data; WP -WP8 ... writing parity data

Claims (7)

A first data group; a first parity data group corresponding to the first data group; a second data group different from the first data group; and a second data group corresponding to the second data group. A memory unit that outputs a parity data group in parallel,
A first error correction circuit that corrects an error in the first data group using the first parity data group to generate a first corrected data group;
A second error correction circuit that corrects an error in the second data group using the second parity data group to generate a second corrected data group;
E Bei and data contained in the first correction data group, and an output circuit for outputting the data included in the second correction data group sequentially,
The number of bits of the first data group is smaller than the number of bits of the second data group . A first data group; a first parity data group corresponding to the first data group; a second data group different from the first data group; and a second data group corresponding to the second data group. A memory unit that outputs a parity data group in parallel,
A first error correction circuit that corrects an error in the first data group using the first parity data group to generate a first corrected data group;
A second error correction circuit that corrects an error in the second data group using the second parity data group to generate a second corrected data group;
An output circuit for sequentially outputting data included in the first correction data group and data included in the second correction data group ;
The semiconductor memory device , wherein an error correction time of the first data group by the first error correction circuit is shorter than an error correction time of the second data group by the second error correction circuit . The first error correction circuit corrects an error of the head data among the data output from the output circuit,
3. The semiconductor memory device according to claim 1, wherein the second error correction circuit corrects an error in remaining data excluding the head data among data output from the output circuit. 4. A selection circuit configured to select one of a plurality of first partial data groups included in the first correction data group and one of a plurality of second partial data groups included in the second correction data group; ,
The output circuit sequentially outputs the one of the plurality of first partial data groups selected by the selection circuit and the one of the plurality of second partial data groups. The semiconductor memory device according to claim 3. An input circuit for sequentially receiving data included in a write data group to be written to the memory unit;
The one of the plurality of first partial data groups is replaced with data corresponding to the first data group among the write data groups to generate a first write data group, and the plurality of second partial data groups A replacement circuit that generates a second write data group by replacing any one of the partial data groups with data corresponding to the second data group of the write data;
A parity generation circuit for generating the first parity data group corresponding to the first write data group and generating the second parity data group corresponding to the second write data group;
A write circuit for writing the first write data group, the second write data group, and the first parity data group and the second parity data group generated by the parity generation circuit to the memory unit; The semiconductor memory device according to claim 4, further comprising: A first data group; a first parity data group corresponding to the first data group; a second data group different from the first data group; and a second data group corresponding to the second data group. Output the parity data group from the memory unit in parallel,
Correcting the error of the first data group using the first parity data group to generate a first corrected data group;
Correcting the error of the second data group using the second parity data group to generate a second corrected data group;
A method for controlling a semiconductor memory device, which sequentially outputs data included in the first correction data group and data included in the second correction data group ,
The number of bits of the first data group is smaller than the number of bits of the second data group . A first data group; a first parity data group corresponding to the first data group; a second data group different from the first data group; and a second data group corresponding to the second data group. Output the parity data group from the memory unit in parallel,
Correcting the error of the first data group using the first parity data group to generate a first corrected data group;
Correcting the error of the second data group using the second parity data group to generate a second corrected data group;
A method for controlling a semiconductor memory device, which sequentially outputs data included in the first correction data group and data included in the second correction data group ,
The method of controlling a semiconductor memory device , wherein an error correction time of the first data group is shorter than an error correction time of the second data group .

Images