JP6443065B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine.

  As a kind of gaming machine, a pachinko gaming machine, a slot machine, and the like are known. These gaming machines include a control element such as a CPU, a read-only storage element such as a ROM, and a read / write storage element such as a RAM. The control element executes processing in accordance with a program read from the read-only storage element while writing information to the read / write storage element and reading information from the storage element. When executing this processing, information is input from the sensor or the like to the control element, and information is output from the control element to the electric actuator, the light emitting element, or the like (see, for example, Patent Document 1). It is also known that a control element, a read-only memory element, a read / write memory element, and the like are integrated into one chip.

JP 2009-261415 A

  Here, in the gaming machine such as the above-described example, a configuration capable of suitably performing control is required, and there is still room for improvement in this respect.

  The present invention has been made in view of the above-mentioned circumstances and the like, and an object thereof is to provide a gaming machine capable of suitably performing control.

In order to solve the above-mentioned problem, the invention according to claim 1 comprises a storage means for storing instructions in advance,
Control execution means for executing the instructions read from the storage means;
In a gaming machine equipped with
The control execution means includes
First signal output means for outputting a first instruction corresponding signal when executing the first instruction;
A second signal output means for outputting a second command corresponding signal when executing a second command having a different amount of information from the first command;
With
The gaming machine is
A specific output means for outputting a specific signal at least in the case where the first command corresponding signal is output and in the case where the second command corresponding signal is output;
When the specific signal is output, an operation means that is in a specific operation state that is at least one of information input and output; and
It is characterized by having.

  According to the present invention, control can be suitably performed.

It is a perspective view which shows the pachinko machine in 1st Embodiment. It is a perspective view which decomposes | disassembles and shows the main structures of a pachinko machine. It is a front view which shows the structure of a game board. It is a block diagram which shows the electric constitution of a pachinko machine. It is explanatory drawing for demonstrating the content of the various counters used for a success or failure lottery. It is a flowchart which shows the main process performed in MPU of a main controller. It is a flowchart which shows the timer interruption process performed in MPU of a main controller. It is a block diagram for demonstrating the electrical structure of CPU provided in MPU. (A) It is a block diagram of an input latch circuit, (b) It is a block diagram of an output latch circuit. It is explanatory drawing for demonstrating the area where the instruction | command is memorize | stored in ROM. (A) It is explanatory drawing for demonstrating the in instruction and out instruction which are 2 byte instructions, (b) It is explanatory drawing for demonstrating the load instruction which is 3 byte instructions. It is a block diagram for demonstrating IO space and memory space. It is explanatory drawing for demonstrating memory space. It is a block diagram showing an electrical configuration for outputting a chip select signal from a chip select terminal corresponding to an input latch circuit for inputting data from an input port. (A)-(h) It is a time chart which shows a mode that a chip select signal is output from a chip select terminal. It is a flowchart which shows the command execution process performed with a CPU core. It is a flowchart which shows the process for 3 byte instructions performed with a CPU core. It is explanatory drawing for demonstrating the electrical structure of CPU in 2nd Embodiment. 3 is a block diagram showing an output circuit for outputting a chip select signal to an output latch circuit in a CPU and an input circuit for outputting a chip select signal to an input latch circuit in a CPU. FIG. (A) It is a front view of a special figure display part, (b) It is explanatory drawing for demonstrating an output area. (A1)-(a8) It is explanatory drawing for demonstrating the content of the data set to the output area, (b1)-(b8) Explanation for demonstrating the light emission aspect of the 1st-8th light emission part. FIG. It is a flowchart which shows the control processing of the special figure display part performed with MPU of a main control apparatus. It is a block diagram which shows the electric constitution of CPU in 3rd Embodiment. FIG. 3 is a block diagram showing an electrical configuration for outputting a chip select signal to a corresponding input latch circuit when data is read from a RAM.

<First Embodiment>
Hereinafter, a first embodiment of a pachinko gaming machine (hereinafter referred to as “pachinko machine”), which is a type of gaming machine, will be described in detail with reference to the drawings. FIG. 1 is a perspective view of the pachinko machine 10, and FIG. 2 is an exploded perspective view showing the main configuration of the pachinko machine 10. As shown in FIG. In FIG. 2, the configuration in the game area of the pachinko machine 10 is omitted for convenience.

  As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 that forms an outer shell of the pachinko machine 10, and a gaming machine body 12 that is rotatably attached to the outer frame 11. . The outer frame 11 is configured by connecting wooden plates to four sides and has a rectangular frame shape. The pachinko machine 10 is installed in the game hall by attaching and fixing the outer frame 11 to the island facility. In the pachinko machine 10, the outer frame 11 is not an essential configuration, and may be configured such that the outer frame 11 is provided in the island facility of the game hall.

  As shown in FIG. 2, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. ing. The inner frame 13 of the gaming machine main body 12 is supported so as to be rotatable with respect to the outer frame 11. Specifically, the inner frame 13 can be rotated forward with the left side as a rotation base end side and the right side as a rotation front end side in front view.

  A front door frame 14 is rotatably supported by the inner frame 13 and can be rotated forward with the left side as a rotation base end side and the right side as a rotation front end side in a front view. Further, the back pack unit 15 is rotatably supported on the inner frame 13, and can be rotated backward with the left side as a rotation base end side and the right side as a rotation front end side in a front view.

  The gaming machine main body 12 is provided with a locking device at the rotating tip, and has a function of locking the gaming machine main body 12 to the outer frame 11 so that it cannot be opened. The door frame 14 has a function of locking the door frame 14 to the inner frame 13 so as not to be opened. Each of these locked states is released by performing an unlocking operation using the unlocking key on the cylinder lock 17 that is exposed on the front surface of the pachinko machine 10.

  Next, the configuration of the front side of the gaming machine body 12 will be described.

  The inner frame 13 is mainly composed of a resin base 21 whose outer shape is substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed at the center of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and the game area PA formed on the front surface of the game board 24 is exposed to the front surface side of the inner frame 13 through the window hole 23 of the resin base 21.

  Here, the structure of the game board 24 is demonstrated based on FIG. FIG. 3 is a front view of the game board 24.

  An inner rail portion 25 and an outer rail portion 26 are attached to the game board 24 so as to partition a part of the outer edge of the game area PA. The inner rail portion 25 and the outer rail portion 26 provide guidance means. As a guide rail, it is configured. A game ball launched from a game ball launching mechanism 27 (see FIG. 2) attached below the window hole 23 in the resin base 21 is guided to the upper part of the game area PA by a guide rail.

  Incidentally, the game ball launching mechanism 27 includes a launch rail 27a extending toward the guide rail, a ball feeding device 27b for supplying game balls stored in an upper plate 55a, which will be described later, onto the launch rail 27a, and the launch rail 27a. And a solenoid 27c which is an electric actuator for firing the game ball supplied to the guide rail. When the launch operation device (or operation handle) 28 provided on the front door frame 14 is rotated, the solenoid 27c is driven and controlled, and a game ball is launched.

  The game board 24 has a plurality of large and small openings penetrating in the front-rear direction. Each opening is provided with a general winning port 31, a special electricity winning device 32, a first operating port 33, a second operating port 34, a through gate 35, a variable display unit 36, a special drawing unit 37, a universal drawing unit 38, and the like. ing.

  Even if a ball enters the through gate 35, the game ball is not paid out. On the other hand, when a ball enters the general winning port 31, the special electricity winning device 32, the first operating port 33, and the second operating port 34, a predetermined number of game balls are paid out. Specifically, with respect to the number of prize balls, when a ball enters the first working port 33 or a ball enters the second working port 34, three prize balls are paid out. When a ball is entered into the general winning port 31, 10 prize balls are paid out. When a ball is entered into the special electric prize device 32, 15 prize balls are paid out. Executed.

  The number of prize balls may be arbitrary. For example, the second actuation port 34 may have a smaller number of prize balls than the first actuation port 33, and the second actuation port 34 may be configured as the first actuation port. The number of prize balls may be larger than 33.

  In addition, an out port 24a is provided at the bottom of the game board 24, and game balls that have not entered various winning ports etc. are discharged from the game area PA through the out port 24a. In addition, the game board 24 is provided with a large number of nails 24b and various members such as a windmill in order to disperse and adjust the falling direction of the game ball as appropriate.

  Here, the entry ball means that the game ball passes through a predetermined opening, and not only the mode of discharging from the game area PA after passing through the opening, but also from the game area PA after passing through the opening. A mode in which the game area PA continues to flow down without being discharged is also included. However, in the following description, in order to clearly distinguish the game ball from entering the out port 24a, the general winning port 31, the special prize winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 are provided. Entering a game ball into is also expressed as a prize.

  The first operating port 33 and the second operating port 34 are unitized as operating port devices and are installed in the game board 24. Both the first working port 33 and the second working port 34 are opened upward. Further, both the operation ports 33 and 34 are arranged in the vertical direction so that the first operation port 33 is located on the upper side. The second operating port 34 is provided with a general electric utility 34a as a guide piece composed of a pair of left and right movable pieces. In the closed state of the utility wire 34a, the game ball cannot win the second operating port 34, and the winning of the second operating port 34 becomes possible when the universal power 34a is opened.

  A through gate 35 is provided on the upstream side in the flow-down direction of the game ball from the second working port 34. The through gate 35 has a through hole (not shown) penetrating in the vertical direction, and the game ball that has won the through gate 35 flows down the game area PA after winning. As a result, the game ball that has won the through gate 35 can win the second working port 34.

  Based on the winning of the through gate 35, the common utility 34 a of the second operating port 34 is switched from the closed state to the open state. Specifically, an internal lottery is performed with a winning at the through gate 35 as a trigger, and a normal display of a general-purpose unit 38 provided at the lower right corner, which is a region where game balls do not pass in the game region PA, is displayed. In the part 38a, the change display of the pattern is performed. Then, when the result of the internal lottery is the electrification opening winning, the stop result corresponding to the result is displayed, and the fluctuation display of the general map display unit 38a is finished, the state shifts to the public power open state. In the public power open state, the general electric utility 34a is opened in a predetermined manner.

  The general map display unit 38a is constituted by a segment display in which a plurality of segment light emitting units are arranged in a predetermined manner, but is not limited to this, and is not limited to this. A liquid crystal display device, an organic EL display device , Or other types of display devices such as CRT or dot matrix display. In addition, as a pattern variably displayed on the general map display unit 38a, a configuration in which a plurality of types of characters are variably displayed, a configuration in which a plurality of types of symbols are variably displayed, a configuration in which a plurality of types of characters are variably displayed, or A configuration in which a plurality of colors are switched and displayed is conceivable.

  In the universal map unit 38, a universal map hold display section 38b is provided at a position adjacent to the universal map display section 38a. A maximum of four game balls won in the through gate 35 are reserved, and the number of the reserved balls is displayed by turning on the general-purpose display unit 38b.

  A lottery is performed with the winning of the first working port 33 or the second working port 34 as a trigger. The lottery result is clearly shown through display effects in the symbol display device 41 of the special figure unit 37 and the variable display unit 36.

  Specifically, the special figure unit 37 is provided with a special figure display unit 37a. The display area of the special figure display unit 37 a is narrower than the display surface 41 a of the symbol display device 41. In the special figure display part 37a, a winning change to the first working port 33 or a winning to the second working port 34 is used as a trigger, and a lottery is performed to display a variation display or a predetermined display. Then, a result corresponding to the lottery result is displayed. In addition, although the special figure display part 37a is comprised by the segment display by which several segment light emission parts are arranged in the predetermined | prescribed aspect, it is not limited to this, A liquid crystal display device, an organic electroluminescence display device , Or other types of display devices such as CRT or dot matrix display. In addition, as a picture displayed on the special figure display unit 37a, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a plurality of types of colors A configuration in which is displayed is conceivable.

  In the special figure unit 37, a special figure holding display part 37b is provided at a position adjacent to the special figure display part 37a. A maximum of four game balls won in the first operation port 33 or the second operation port 34 are reserved, and the reserved number is displayed by lighting the special figure reservation display portion 37b.

  Specifically, the symbol display device 41 is configured as a liquid crystal display device including a liquid crystal display, and the display content is controlled by a display control device described later. The symbol display device 41 is not limited to a liquid crystal display device, and may be another display device having a display screen such as a plasma display device, an organic EL display device, or a CRT, and is a dot matrix display. May be.

  In the symbol display device 41, when a special symbol display unit 37a displays a change or predetermined display of a pattern based on a winning in the first operating port 33 or a winning in the second operating port 34, the symbol is displayed accordingly. A variable display or a predetermined display is performed. For example, on the display surface 41a of the symbol display device 41, three symbol rows of upper, middle, and lower rows are set as a plurality of display areas, and numbers “1” to “9” are attached to the symbol rows. The symbols are scrolled and displayed with the symbols arranged in ascending or descending order. In this scroll display, the scroll display in all the symbol sequences is started first, and the display is switched from the scroll display to the standby display in the order of the upper symbol sequence → the lower symbol sequence → the middle symbol sequence. The process ends with the symbols still displayed. For example, in the game times in which the game result is a jackpot result, a predetermined combination of symbols is stopped and displayed on the active line set in advance on the display surface 41a of the symbol display device 41.

  In addition, the symbol display device 41 performs not only a display effect triggered by winning a prize to the first operating port 33 or the second operating port 34, but also a display effect in the opening / closing execution mode that shifts after winning the winning combination. Is called. In addition, based on the winning in one of the operation ports 33 and 34, the display is started on the special symbol display unit 37a and the symbol display device 41, and until a predetermined result is displayed and ended, the game number is 1 Equivalent to times. Further, the variation display mode of the symbol in the symbol display device 41 is not limited to the above, and is arbitrary, such as the number of symbol columns, the direction of symbol variation display in the symbol column, the number of symbols in each symbol column, etc. Can be appropriately changed. Also, the pattern that is variably displayed on the symbol display device 41 is not limited to the above-described pattern, and for example, only numbers may be variably displayed as the pattern.

  When the big win is won in the winning lottery based on the winning to the first operating port 33 or the winning to the second operating port 34, the mode shifts to an opening / closing execution mode in which the special electric winning device 32 can be won. The special electric prize winning device 32 is provided with a large winning opening (not shown) leading to the back side of the game board 24 and an open / close door 32a for opening and closing the large winning opening. The open / close door 32a is arranged in either a closed state or an open state. Specifically, the open / close door 32a is normally in a closed state in which game balls cannot be won, and can be switched to an open state in which game balls can be won when winning the transition to the open / close execution mode in the internal lottery. It has become. Incidentally, the opening / closing execution mode is a mode that shifts when a hit result is obtained. Note that, in the closed state, winning may not be impossible, but it may be configured such that winning is less likely to occur than in the open state.

  As shown in FIG. 2, the front door frame 14 is provided so as to cover the entire front side of the inner frame 13 in which the game board 24 having the above configuration is attached to the resin base 21. As shown in FIG. 1, the front door frame 14 is formed with a window portion 51 so that almost the entire game area PA can be viewed from the front. The window part 51 has a substantially elliptical shape, and the window panel 52 is fitted therein. The window panel 52 is formed of colorless and transparent with glass, but is not limited to this, and may be formed of colorless and transparent with synthetic resin. The game area PA is defined through the window panel 52 from the front of the pachinko machine 10. As long as it is visible, it may be colored and transparent.

  A display light emitting unit 53 is provided above the window unit 51. In addition, a pair of left and right speaker portions 54 that output sound effects according to the gaming state are provided. Further, below the window portion 51, an upper bulging portion 55 and a lower bulging portion 56 that bulge to the near side are arranged in parallel vertically. An upper plate 55a that opens upward is provided inside the upper bulge portion 55, and a lower plate 56a that also opens upward is provided inside the lower bulge portion 56. The upper plate 55a has a function of temporarily storing game balls paid out from a payout device described later and guiding them to the game ball launching mechanism 27 side while aligning them in a row. In addition, the lower tray 56a has a function of storing game balls that are surplus in the upper tray 55a.

  Next, the configuration on the back side of the gaming machine main body 12 will be described.

  As shown in FIG. 2, a main controller 60 that controls the main game is mounted on the back of the inner frame 13 (specifically, the game board 24). The main control device 60 has a main control board accommodated in a board box. In addition, you may provide the trace structure for giving the trace means for leaving the trace of the opening to the board | substrate box, or leaving the trace of the open. As the trace means, a plurality of case bodies constituting the substrate box are unseparably coupled, and a configuration of a coupling portion that requires destruction of a predetermined part at the time of separation, or an adhesive layer that remains on an adhesion target at the time of peeling is peeled off. A configuration is conceivable in which a seal seal that leaves a trace of what has been done is pasted so as to straddle the boundaries between the plurality of case bodies. Moreover, as a trace structure, the structure which apply | coats an adhesive agent with respect to the boundary between the some case bodies which comprise a board | substrate box can be considered.

  The back pack unit 15 is installed so as to cover the back side of the inner frame 13 including the main controller 60. The back pack unit 15 includes a back pack 72 formed of a synthetic resin having transparency, and a payout mechanism unit 73 and a controller assembly unit 74 are attached to the back pack 72.

  The payout mechanism unit 73 includes a tank 75 in which game balls supplied from the island equipment of the game hall are sequentially replenished, and a payout device 76 for paying out the game balls stored in the tank 75. The game balls paid out from the payout device 76 are discharged to the upper plate 55a or the lower plate 56a through a payout passage provided on the downstream side of the payout device 76. The payout mechanism unit 73 is provided with a backpack substrate having a power switch for performing ON and OFF operations of the power supply, for example, while supplying a main power of AC 24 volts.

  The control device assembly unit 74 generates and outputs predetermined power required by the payout control device 77 having a function of controlling the payout device 76 and various control devices, and is accompanied by an operation of the launch operation device 28 by the player. And a power source / launch control device 78 for controlling the launch of the game ball. The payout control device 77 and the power supply / launch control device 78 are arranged so as to overlap each other so that the payout control device 77 is behind the pachinko machine 10.

<Electric configuration of pachinko machine 10>
FIG. 4 is a block diagram showing an electrical configuration of the pachinko machine 10.

  The main control device 60 includes a main control board 61 that controls the main control of the game, and a power failure monitoring board 65 that monitors the power supply. An MPU 62 is mounted on the main control board 61. The MPU 62 includes a ROM 63 that stores various control programs executed by the MPU 62 and fixed value data, and a memory that temporarily stores various data when the control program stored in the ROM 63 is executed. A RAM 64, an interrupt circuit, a timer circuit, a data input / output circuit, various counter circuits as a random number generator, and the like are incorporated. Note that it is not essential that the ROM 63 and the RAM 64 are made into one chip with respect to the MPU 62, but each may be made into a chip individually. The same applies to the MPUs of control devices other than the main control device 60.

  The MPU 62 is provided with an input port 62a and an output port 62b. The input port 62a is provided with 24 connection terminals, and the output port 62b is provided with 40 connection terminals. A power failure monitoring board 65 and a payout controller 77 provided in the main controller 60 are connected to the input port 62 a of the MPU 62. The power failure monitoring board 65 is connected to a power source / launch control device 78 having a function of supplying operating power, and the MPU 62 is supplied with power via the power failure monitoring board 65.

  Further, various sensors such as various winning detection sensors 66a to 66e are connected to the input port 62a of the MPU 62. Each of the various winning detection sensors 66a to 66e is provided on a one-to-one basis with respect to the winning-corresponding pitching portions such as the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35. The detection sensor is included, and the MPU 62 makes a winning determination for each winning part. Further, in the MPU 62, various lotteries are executed on the basis of winning in the first operating port 33, and various lotteries are executed on the basis of winning in the second operating port 34.

  A power failure monitoring board 65, a payout control device 77, and a sound emission control device 80 are connected to the output port 62b of the MPU 62. To the payout control device 77, for example, a winning ball command is output based on the winning determination result to the winning corresponding winning portion. Various commands such as a change command, a type command, and an opening command are output to the sound emission control device 80. Details of these various commands will be described later. The MPU 62 transmits a command to the sound emission control device 80 by parallel communication.

  Further, the output port 62b of the MPU 62 includes a special electric drive unit 32b for opening / closing the open / close door 32a of the special electric prize device 32, and a general electric drive unit for opening / closing the electric utility 34a of the second operating port 34. 34b, special figure unit 37 and universal figure unit 38 are connected. Incidentally, the special figure unit 37 is provided with a special figure display part 37 a and a special figure holding display part 37 b, all of which are connected to the output side of the MPU 62. Similarly, the universal map unit 38 is provided with a universal map display unit 38 a and a universal map hold display unit 38 b, all of which are connected to the output side of the MPU 62. The main control board 61 is provided with various driver circuits, and the MPU 62 performs drive control of various drive units and various display units through the driver circuits.

  That is, in the opening / closing execution mode, the MPU 62 performs drive control of the special electricity driving unit 32b so that the special electricity prize winning device 32 is opened and closed. In addition, when the power utility item 34a is won, the MPU 62 performs drive control of the power unit 34b so that the power utility item 34a is opened and closed. In each game round, the display control of the special figure display unit 37a is executed in the MPU 62. In addition, when the lottery result indicating whether or not to open the electric utility item 34a is clearly indicated, the MPU 62 performs display control of the normal display portion 38a. In addition, when winning is awarded to the first working port 33 or the second working port 34, or when the variable display is started in the special figure display unit 37a, the display control of the special figure holding display unit 37b is executed in the MPU 62. When the winning to the through gate 35 is generated or when the variable display is started in the general map display unit 38a, the display control of the general map hold display unit 38b is executed in the MPU 62.

  The power failure monitoring board 65 relays between the main control board 61 and the power / fire control device 78, and monitors a DC stable voltage of 24 volts, which is the maximum voltage output from the power / fire control device 78. The payout control device 77 performs payout control of prize balls and rental balls by the payout device 76 based on the prize ball command received from the main control device 60.

  The power / launch control device 78 is connected to, for example, a commercial power source (external power source) in a game hall or the like. And based on the external electric power supplied from the commercial power supply, necessary operating power is generated for each of the main control board 61, the payout control device 77, etc., and the generated operating power is supplied. Incidentally, the power supply / launch control device 78 is provided with a power supply unit for power interruption such as a backup capacitor, and even when the power of the pachinko machine 10 is in an OFF state, the power supply unit for power interruption is connected to the main power supply unit. Electric power for storing and holding is supplied to the RAM 64 of the control device 60. In addition, the power source / launch control device 78 is responsible for launch control of the game ball launch mechanism 27, and the game ball launch mechanism 27 is driven when predetermined launch conditions are met.

  The sound light emission control device 80 controls the display control device 90 while driving and controlling the display light emitting portion 53 and the speaker portion 54 provided on the front door frame 14 based on various commands received from the main control device 60. It is. The display control device 90 executes display control of the symbol display device 41 based on the command received from the sound emission control device 80.

<Electrical configuration for performing various lotteries in the MPU 62 of the main controller 60>
Next, an electrical configuration for performing various lotteries in the MPU 62 of the main controller 60 will be described with reference to FIG.

  The MPU 62 uses lots of counter information in the game to perform winning occurrence lottery, setting of display of the special symbol display unit 37a, setting of symbol display of the symbol display device 41, setting of display of the general symbol display unit 38a, and the like. More specifically, as shown in FIG. 5, when the winning random number counter C1 used for winning lottery, the big hit type counter C2 used for determining the big hit type, and the symbol display device 41 fluctuate and change. Reach random number counter C3 used for the reach generation lottery, random number initial value counter CINI used for setting the initial value of the hit random number counter C1, and the variation type for determining the display duration in the special figure display unit 37a and the symbol display unit 41 The counter CS is used. Further, the utility power release counter C4 used for the lottery to determine whether or not the utility power item 34a of the second working port 34 is set to the utility power release state is used. The counters C1 to C3, CINI, CS, and C4 are provided in various counter areas 64b of the RAM 64.

  Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value every time it is updated and returns to “0” after reaching the maximum value. Each counter is updated at short intervals. Information corresponding to the hit random number counter C1, the big hit type counter C2 and the reach random number counter C3 is provided as an acquisition information storage means in the RAM 64 when a winning to the first operating port 33 or the second operating port 34 occurs. It is stored in the reserved storage area 64a.

  The holding storage area 64a includes a holding area RE and an execution area AE. The holding area RE includes a first holding area RE1, a second holding area RE2, a third holding area RE3, and a fourth holding area RE4. In the winning history to the first operating port 33 or the second operating port 34, In addition, combinations of numerical information of the hit random number counter C1, the big hit type counter C2, and the reach random number counter C3 are stored as hold information in any of the hold areas RE1 to RE4.

  In this case, in the first reservation area RE1 to the fourth reservation area RE4, when a winning to the first operation port 33 or the second operation port 34 occurs continuously a plurality of times, the first reservation area RE1 → second Each numerical information is stored in time series in the order of the reserved area RE2 → the third reserved area RE3 → the fourth reserved area RE4. By providing the four holding areas RE1 to RE4 as described above, up to four game balls winning histories to the first operating port 33 or the second operating port 34 are stored and stored. .

  Note that the number that can be reserved and stored is not limited to four, but may be any other number such as two, three, or five or more.

  The execution area AE is an area for moving each numerical information stored in the first holding area RE1 of the holding area RE when starting the variable display of the special figure display section 37a, and starting one game round At this time, determination of success or failure is performed based on various numerical information stored in the execution area AE.

  Each of the counters will be described in detail.

  First, the general electric utility release counter C4 will be described. For example, the utility power release counter C4 is incremented by 1 in the range of 0 to 250 and returns to “0” after reaching the maximum value. The general electric utility release counter C4 is periodically updated and stored in the general electric power holding area 64c of the RAM 64 at a timing when a game ball wins the through gate 35. Then, at a predetermined timing, a lottery is performed as to whether or not to control the general utility 34a to the open state based on the stored value of the general utility release counter C4.

  In the pachinko machine 10, a plurality of types of support modes are set so that the modes of support by the electric utility 34 a are different from each other. Specifically, in the support mode, when the game ball PA is continuously fired in the same manner with respect to the game area PA, the power utility 34a of the second working port 34 is per unit time. The high frequency support mode and the low frequency support mode are set so that the frequency of the open state is relatively high.

  In the high frequency support mode and the low frequency support mode, the probability of winning the electric power open state in the electric power open lottery using the electric power utility opening counter C4 is the same (for example, both 4/5). In the high frequency support mode, the number of times that the power utility 34a is in the open state is set more frequently than in the low frequency support mode, and one open time is set longer. Has been. In this case, in the high frequency support mode, when the open state of the public electric power is selected and the open state of the general electric utility 34a is generated a plurality of times, from the end of one open state to the start of the next open state. The closing time is set shorter than one opening time. Furthermore, in the high frequency support mode, the minimum reserved time (i.e., the normal map) is required for the next open train lottery after the first open train lottery than in the low frequency support mode. The display duration time for the display unit 38a is set short.

  As described above, in the high frequency support mode, the probability of winning a prize to the second operating port 34 is higher than in the low frequency support mode. In other words, in the low frequency support mode, there is a higher probability of winning the first operating port 33 than in the second operating port 34, but in the high frequency support mode, the second operation is performed more than in the first operating port 33. The probability of winning a prize in the mouth 34 is increased. When a winning is made to the second operation port 34, a predetermined number of game balls are paid out. Therefore, in the high frequency support mode, the player plays a game while not reducing the number of possessed balls so much. It can be carried out.

  Note that the configuration for increasing the frequency at which the high frequency support mode is set to the normal power open state per unit time as compared to the low frequency support mode is not limited to the above, for example, in the general power open lottery It is good also as a structure which raises the probability that it will be elected in an open state of a public train. In addition, a reserved time (for example, executed in the general map display unit 38a based on a winning to the through gate 35) is secured after the next public train opening lottery is performed. In a configuration in which a plurality of types of variable display time) are prepared, the high frequency support mode is set so that a short securing time is easily selected or the average secure time is shorter than the low frequency support mode. Also good. Furthermore, increase the number of times of opening, lengthen the opening time, and shorten the reserved time that will be secured when the next public train opening lottery is performed after the first public train opening lottery is performed, the reserved time concerned The advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one condition or any combination of conditions among shortening the average time and increasing the winning probability.

  Next, the winning random number counter C1 will be described. For example, the winning random number counter C1 is incremented by 1 within a range of 0 to 599, and returns to “0” after reaching the maximum value. In particular, when the winning random number counter C1 makes one round, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is periodically updated, and stored in the holding storage area 64a of the RAM 64 at the timing when the game ball wins the first operation port 33 or the second operation port 34.

  The random number value for winning the jackpot is stored in the ROM 63 as a success / failure table. As the success / failure table, a success / failure table for the low probability mode and a success / failure table for the high probability mode are set. That is, in the pachinko machine 10, the low probability mode and the high probability mode are set as the lottery modes in the success / failure lottery means.

  In the gaming state in which the winning / failing table for the low probability mode is referred to at the time of the lottery, the number of random numbers that win the jackpot is two. On the other hand, in the gaming state in which the winning / failing table for the high probability mode is referred to at the time of the lottery, the number of random numbers that will win the jackpot is 20. If the winning probability in the high probability mode is higher than that in the low probability mode, the number of random numbers to be won is arbitrary.

  The jackpot type counter C2 is incremented one by one within the range of 0 to 29, and returns to “0” after reaching the maximum value. The big hit type counter C2 is periodically updated and stored in the holding storage area 64a at the timing when the game ball wins the first operation port 33 or the second operation port 34.

  In the pachinko machine 10, a plurality of jackpot results are set. The plurality of jackpot results are as follows: (1) a mode of opening / closing control of the special prize winning device 32 in the opening / closing execution mode, (2) lottery mode in the winning lottery means after the opening / closing execution mode ends, (3) A plurality of jackpot results are set by making a difference in the three conditions of the support mode in the general electric utility 34a of the two operation ports 34.

  As an aspect of the opening / closing control of the special electricity prize winning device 32 in the opening / closing execution mode, the occurrence frequency of winning in the special electricity prize winning device 32 from the start to the end of the opening / closing execution mode is relatively high. A frequency winning mode and a low frequency winning mode are set. Specifically, in any of the high-frequency winning mode and the low-frequency winning mode, the game is executed with a predetermined number of round games as an upper limit.

  Here, the round game is continued until either one of a predetermined upper limit continuation time elapses and a predetermined upper limit number of game balls win the special electric prize winning device 32 is satisfied. It is a game to play. In addition, the number of round games in the opening / closing execution mode triggered by the jackpot result is the same for a fixed number of rounds regardless of the type of jackpot result triggered by the transition. Specifically, the upper limit number of round games is set to 15 rounds regardless of which jackpot result is obtained.

  Moreover, in this pachinko machine 10, a plurality of types of opening modes of the special electricity prize winning device 32 are set with different opening durations from when the special electricity prize winning device 32 is opened until it is closed. Specifically, a long-time mode set to 29 sec, which is a long open duration, and a short-time mode set to 0.06 sec, which is a short time shorter than the above long time, are set. Has been.

  In the present pachinko machine 10, when the launch operation device 28 is operated by the player, the game ball launching mechanism 27 is driven and controlled so that one game ball is launched toward the game area every 0.6 sec. The In the round game, the upper limit number of end conditions is set to nine. Then, in the long time mode among the above open modes, the open duration time is set longer than the product of the game ball firing period and one round game. On the other hand, in the short-time mode, an opening continuation time is set that is shorter than the product of the game ball launch cycle and one round game, more specifically, shorter than the game ball launch cycle. Therefore, when the opening is performed once in the long-time mode, it is expected that the special electric prize winning device 32 will receive the maximum number of winnings in one round game. When the number of times is released, it is expected that no prize will be given to the special electric prize winning device 32 or that there will be about one even if a prize is generated.

  In the high-frequency winning mode, the special electric prize winning device 32 is opened once in a long-time manner in each round game. On the other hand, in the low-frequency winning mode, the special prize winning device 32 is opened once in each round game in a short time mode.

  In addition, the number of times of opening / closing the special electric prize device 32 in the high frequency winning mode and the low frequency winning mode, the number of round games, the opening duration for one opening, and the upper limit number in one round game are those in the high frequency winning mode. However, the value is not limited to the above value as long as the occurrence frequency of the winning to the special electricity winning device 32 is higher than the low-frequency winning mode until the opening / closing execution mode starts and ends. It is.

  The game result distribution destination for the big hit type counter C2 is stored in the ROM 63 as a distribution table. And as such a distribution destination, a low probability big hit result, a low winning high probability big hit result, and the most advantageous big hit result are set.

  The low probability big hit result is a big hit result in which the open / close execution mode becomes the high-frequency winning mode, and after the open / close execution mode ends, the win / fail lottery mode becomes the low probability mode and the support mode becomes the high frequency support mode. However, the high-frequency support mode shifts to the low-frequency support mode when the number of games reaches the end reference number (specifically, 100 times) after the shift.

  The low-winning high-probability jackpot result is a jackpot result in which the opening / closing execution mode becomes the low-frequency winning mode, and after the opening / closing execution mode ends, the success / failure lottery mode becomes the high probability mode and the support mode becomes the high-frequency support mode. is there. These high-probability mode and high-frequency support mode continue until the lottery result in the success / failure lottery wins a big win, and the operation shifts to the opening / closing execution mode.

  The most advantageous jackpot result is a jackpot result in which the opening / closing execution mode becomes the high-frequency winning mode, and after the opening / closing execution mode ends, the winning / raising lottery mode becomes the high probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the success / failure lottery wins a big win, and the operation shifts to the opening / closing execution mode.

  Note that the normal game state in relation to each of the above-described game states refers to a state in which the success / failure lottery mode is the low probability mode and the support mode is the low frequency support mode, not the open / close execution mode. Moreover, it is good also as a structure in which the low prize-winning high probability hit result is not set as a game result.

  In the distribution table, among the values of the big hit type counter C2 of “0 to 29”, “0 to 9” corresponds to the low probability big hit result, and “10 to 14” corresponds to the low winning high probability big hit result. “15 to 29” corresponds to the most favorable jackpot result.

  Next, the reach random number counter C3 will be described. The reach random number counter C3 is, for example, incremented by 1 within a range of 0 to 238, and returns to “0” after reaching the maximum value. Here, in the pachinko machine 10, an expected effect is set as a kind of display effect in the symbol display device 41. The expected effect includes a symbol display device 41 that can display a variation of symbols, and in a gaming machine in which a final stop result is an assignment corresponding result in a game round that results in a predetermined jackpot result, the symbol display device 41 This is a display state for making the player think that it is a variable display state that is likely to be the above-mentioned giving correspondence result at the stage before the stop result is derived and displayed after the symbol variable display is started. In addition, about the provision corresponding | compatible result, the combination of the symbol to which the same number was attached | subjected on one of the effective lines is stopped and displayed.

  In the expected effect, two types of reach display and a notice display for expecting the occurrence of reach display and the generation of the result of giving correspondence at a stage before the reach display occurs are set.

  In the reach display, a combination of reach symbols composed of the same symbols is displayed by stopping and displaying symbols for some of the symbol sequences displayed on the display surface 41a of the symbol display device 41. In the state, a display state in which the variable display of symbols is displayed in the remaining symbol rows is included. In addition, in the state where the combination of reach symbols is displayed as described above, the variation of the symbols is displayed in the remaining symbol rows, and a predetermined character or the like is displayed as a moving image on the background screen, and the reach effect is performed. In addition, there are those that perform a reach effect by displaying a predetermined character or the like as a moving image on substantially the entire display surface 41a after reducing or not displaying a combination of reach symbols.

  The notice display includes a plurality of symbol strings in a situation where symbols are variably displayed in all symbol columns after the symbol variable display is started on the display surface 41a of the symbol display device 41. In the situation where the symbols are variably displayed in the symbol row, a mode in which the character is displayed separately from the symbols on the symbol row is included. Moreover, what makes a background screen the predetermined aspect different from the previous aspect, and what makes the symbol on a symbol row the predetermined aspect different from the previous aspect are also included. Such a notice display can occur in any game times when reach display is performed and when reach display is not performed, but the case where reach display is performed is higher than the case where reach display is not performed. It is set to occur with probability.

  The reach display is executed regardless of the value of the reach random number counter C3 in the game times in which the combination of the same symbols is finally stopped. In addition, the game times corresponding to the jackpot result in which the same symbol combination is not stopped and displayed are not executed regardless of the value of the reach random number counter C3. Also, in the game times corresponding to the result of losing, it is executed when the reach random number counter C3 acquired at a predetermined timing with reference to the reach table stored in the ROM 63 corresponds to the occurrence of reach display.

  On the other hand, the determination as to whether or not to perform the notice display is performed not by the main control device 60 but by the sound emission control device 80. In this case, the sound emission control device 80 is more likely to generate a notice display and a notice display with a low appearance rate in the game times corresponding to any of the jackpot results compared to the game times corresponding to the missed results. A lottery process for displaying a notice is executed so as to satisfy at least one of the conditions of being easily generated. Incidentally, the lottery result is reflected when the game display effect is executed on the symbol display device 41.

  Next, the variation type counter CS will be described. For example, the variation type counter CS is incremented one by one within a range of 0 to 198, and returns to “0” after reaching the maximum value. The variation type counter CS is used when the MPU 62 determines the display continuation time in the special symbol display section 37a and the symbol display continuation time in the symbol display device 41. The variation type counter CS is updated once every time a normal process to be described later is executed once, and is repeatedly updated even within the remaining time in the normal process. Then, the buffer value of the variation type counter CS is acquired when the variation pattern is determined at the start of variation display in the special symbol display unit 37a and at the time of symbol variation start by the symbol display device 41.

<Processing configuration of main controller 60>
Next, each process performed in order to advance a game in MPU62 of the main controller 60 is demonstrated. The processing of the MPU 62 is roughly divided into main processing that is started when the power is turned on and timer interrupt processing that is started periodically (in the present embodiment at a cycle of 4 msec).

<Main processing>
First, the main process will be described with reference to the flowchart of FIG.

  In step S101, power-on wait processing is executed. In the power-on wait process, for example, the process waits without progressing to the next process until a predetermined time for wait (specifically 1 sec) elapses after the main process is activated. The operation start and initial setting of the symbol display device 41 are completed during the execution period of the power-on wait process. In the subsequent step S102, access to the RAM 64 is permitted, and in step S103, the internal function register of the MPU 62 is set.

  Thereafter, in step S104, it is determined whether or not the RAM erase switch provided in the power / fire control device 78 is manually operated. In subsequent step S105, whether or not “1” is set in the power failure flag of the RAM 64 is determined. Determine whether. In step S106, a checksum calculation process for calculating a checksum is executed. In subsequent step S107, whether or not the checksum matches the checksum stored when the power is turned off, that is, the validity of the stored data is checked. judge.

  In the pachinko machine 10, for example, when RAM data is initialized when the power is turned on, such as when a game hall starts business, the power is turned on while the RAM erase switch is pressed. Therefore, if the RAM erase switch is pressed, the process proceeds to step S108. Similarly, when the information on occurrence of power shutdown is not set, or when an abnormality of data stored and held is confirmed by the checksum, the process proceeds to step S108. In step S108, the RAM 64 is cleared. Thereafter, the process proceeds to step S109.

  On the other hand, if the RAM erase switch has not been pressed, step S109 is executed without executing step S108 on condition that the power failure flag is set to “1” and the checksum is normal. Proceed to In step S109, a power-on setting process is executed. In the power-on setting process, a predetermined area of the RAM 64 such as initialization of a power failure flag is set to an initial value, and a command corresponding to the current gaming state is transmitted to the sound emission control device 80 in order to recognize the current gaming state. To do.

  Then, it progresses to the residual process of step S110-step S113. That is, the MPU 62 is configured to periodically execute the timer interrupt process, but a remaining time is generated between one timer interrupt process and the next timer interrupt process. The remaining time varies depending on the processing completion time of each timer interrupt process, but the remaining processes in steps S110 to S113 are repeatedly executed using such irregular time. In this regard, it can be said that the remaining processes in steps S110 to S113 are non-periodic processes that are performed irregularly.

  In the remaining process, first, in step S110, an interrupt prohibition setting is performed in order to prohibit the generation of the timer interrupt process. In the subsequent step S111, a random number initial value update process for updating the random number initial value counter CINI is executed, and a change counter update process for updating the change type counter CS is executed in step S112. In these update processes, the current numerical information is read from the corresponding counter of the RAM 64, the process of adding 1 to the read numerical information is executed, and then the process of overwriting the read-out counter is executed. In this case, each counter value is cleared to “0” when it reaches the maximum value. Thereafter, in step S113, an interrupt permission setting for switching from a state in which the generation of the timer interrupt process is prohibited to a state in which the timer interrupt process is permitted is performed. If the process of step S113 is performed, it will return to step S110 and will repeat the process of step S110-step S113.

<Timer interrupt processing>
Next, timer interrupt processing will be described with reference to the flowchart of FIG. The timer interrupt process is executed periodically (for example, at a cycle of 4 msec).

  First, in step S201, a power failure information storage process is executed. In the power outage information storage process, it is monitored whether or not a power outage signal corresponding to the occurrence of power interruption is received from the power outage monitoring board 65, and when the occurrence of a power outage is specified, the process during power outage is executed.

  In subsequent step S202, a lottery random number update process is executed. In the lottery random number update process, the winning random number counter C1, the big hit type counter C2, the reach random number counter C3, and the universal utility release counter C4 are updated. Specifically, the current numerical information is sequentially read from the hit random number counter C1, the big hit type counter C2, the reach random number counter C3, and the general electric utility release counter C4, and a process of adding 1 to each of the read numerical information is executed. Later, a process of overwriting the reading source counter is executed. In this case, each counter value is cleared to “0” when it reaches the maximum value.

  Thereafter, in step S203, the random number initial value update process is executed in the same manner as in step S111, and in step S204, the variation counter update process is executed in the same manner as in step S112.

  In subsequent step S205, a fraud detection process for monitoring whether or not a predetermined event set as a fraud monitoring target has occurred is executed. In the fraud detection process, occurrence of a plurality of types of events is monitored, and by confirming that a predetermined event has occurred, “1” is set to a game stop flag provided in the RAM 64.

  In the subsequent step S206, it is determined whether or not the progress of the game is stopped by determining whether or not “1” is set in the game stop flag. If a negative determination is made in step S206, the processing after step S207 is executed.

  In step S207, port output processing is executed. In the port output processing, when output information is set in the previous timer interrupt processing, processing for performing output corresponding to the output information to the various drive units 32b and 34b through the output port 62b of the MPU 62 is performed. Run. For example, when information for switching the special electric prize winning device 32 to the open state is set, output of a drive signal to the special electric drive unit 32b is started, and information for switching to the closed state is set. Stops the output of the drive signal. In addition, when the information for switching the general utility 34a of the second working port 34 to the open state is set, output of the drive signal to the general power drive unit 34b is started, and the closed state should be switched to. When the information is set, the output of the drive signal is stopped.

  In a succeeding step S208, a reading process is executed. In the reading process, signals other than the power failure signal and the winning signal are read through the input port 62a of the MPU 62, and the read information is stored for use in future processing.

  In subsequent step S209, a winning detection process is executed. In the winning detection process, the signals received from the winning detection sensors 66a to 66e are read through the input port 62a of the MPU 62, and the general winning port 31, the special prize winning device 32, the first operating port 33, and the second operating port are read. The process which specifies the presence or absence of the winning to 34 and the through gate 35 is performed.

  In the subsequent step S210, timer update processing for updating the numerical information of a plurality of types of timer counters provided in the RAM 64 is executed. In this case, the timer counter that is updated by subtracting the stored numerical information is handled in an integrated manner. However, both the updating of the subtracting timer counter and the updating of the adding timer counter are performed collectively. It is good also as a structure.

  In the subsequent step S211, a launch control process for controlling the launch of the game ball is executed. In a situation where the launch operation to the launch operation device 28 is continued, as described above, one game ball is launched at a predetermined launch period of 0.6 sec.

  In the subsequent step S212, as input state monitoring processing, disconnection confirmation of the winning detection sensors 66a to 66e and opening confirmation of the gaming machine body 12 and the front door frame 14 are confirmed based on the information read in the reading processing in step S208. Do.

  In the subsequent step S213, a special figure special electric control process for performing execution control of the game times and execution control of the opening / closing execution mode is executed. In the special figure special power control process, when a winning to the first operation port 33 or the second operation port 34 occurs in a situation where the number of the hold information stored in the hold storage area 64a is less than the upper limit number, A process of storing the numerical information of the hit random number counter C1, the big hit type counter C2 and the reach random number counter C3 at the time as the hold information in the hold storage area 64a in time series is executed. Also, in the special figure special electric control process, whether or not the hold information corresponds to the big win is determined on the condition that the hold information is not stored during the game rotation and the opening / closing execution mode and is stored. If it corresponds to the process and the jackpot winning, a distribution determination process for determining which jackpot result the hold information corresponds to is executed. In addition, in the special figure special power control process, not only the success / failure determination process and the distribution determination process, but if the hold information does not correspond to the big win, whether the hold information corresponds to the occurrence of reach. A reach determination process is performed, and a process of selecting a game time duration using the numerical information of the variation type counter CS at that time is executed. Then, the change command including the duration information according to the result of each process and the type command including the game result information are transmitted to the sound emission control device 80, and the pattern in the special figure display unit 37a is displayed. Start the variable display. As a result, one game round is started, and an effect for game round is started on the special figure display unit 37a and the symbol display device 41.

  Also, in the special figure special electric control process, during the execution of one game round, it is determined whether or not it is the end timing of the game round. If it is the end timing, the display corresponding to the game result is performed. Then, the process of ending the game round is executed. In this case, a final stop command indicating that the game round should be ended is transmitted to the sound emission control device 80. Further, in the special figure special electric control process, when the result of the game times is a result corresponding to the transition to the opening / closing execution mode, a process for starting the opening / closing execution mode is executed. At the start, an opening command indicating that the opening / closing execution mode is started is transmitted to the sound emission control device 80. In the special figure special electric control process, a process for starting each round game and a process for ending each round game are executed. In each of these processes, an open command indicating that the round game is started is transmitted to the sound emission control device 80, and a close command indicating that the round game is ended is transmitted to the sound emission control device 80. Further, in the special figure special electric control process, when the opening / closing execution mode is ended, an ending command indicating that is sent to the sound emission control device 80, and the success / failure lottery mode and the support mode after the opening / closing execution mode are set. Execute the process.

  After executing the special figure special electric control process of step S213 in the timer interruption process, the normal figure electric power control process is executed in step S214. In the ordinary map / electric power control process, when a winning to the through gate 35 is generated, a process for acquiring the retained information on the ordinary map side is executed and the retained information on the ordinary map side is stored. In addition, a release determination is performed on the hold information, and a process for performing an effect for a normal diagram is executed using the release determination as a trigger. Further, based on the result of the opening determination, a process for opening and closing the utility wire 34a of the second working port 34 is executed.

  In the subsequent step S215, based on the processing results of the immediately preceding steps S213 and S214, output information is set for reflecting the increase / decrease number of the hold information related to the special figure display unit 37a in the special figure hold display unit 37b. The output information for reflecting the increase / decrease number of the hold information related to the general map display unit 38a to the general map hold display unit 38b is set. In step S215, the output information for updating the display content of the special figure display unit 37a is set based on the processing results of the immediately preceding steps S213 and S214, and the display content of the general map display unit 38a is set. Set the output information to be updated. The setting of the output information in step S215 is performed through the output port 62b of the MPU 62.

  In the following step S216, the contents of the command and signal received from the payout control device 77 are confirmed, and a payout state receiving process for performing a process corresponding to the confirmation result is executed. In step S217, a payout output process for setting a prize ball command as an output target is executed. In the subsequent step S218, an external information setting process for controlling the start and end of the output of the external signal according to the processing results of the various processes executed in the current timer interrupt process is executed. Thereafter, the timer interrupt process is terminated.

<Electrical Configuration for Reading Data etc. in MPU 62>
Next, an electrical configuration for reading commands and data and writing data in the MPU 62 will be described. FIG. 8 is a block diagram for explaining the electrical configuration of the CPU 101 provided in the MPU 62.

  The CPU 101 is built in the MPU 62. The CPU core 102 incorporated in the CPU 101 reads out various instructions from the ROM 83 incorporated in the MPU 62, and executes arithmetic processing, input data analysis processing, and data output processing according to a program corresponding to the instructions. Specifically, the CPU core 102 reads an instruction from the area of the address corresponding to the value of the program counter incorporated in the CPU core 102 and updated as the processing of the CPU core 102 progresses, and processes corresponding to the instruction To execute various processes according to the program.

  The CPU core 102 includes a Vcc terminal, a GND terminal, an INT terminal, an NMI terminal, data terminals D0 to D7, address terminals A0 to A15, an RD terminal, a WR terminal, an IREQ terminal, an MREQ terminal, and the like. Hereinafter, the data terminals D0 to D7, the address terminals A0 to A15, the RD terminal, the WR terminal, the IREQ terminal, and the MREQ terminal will be described in detail. Note that description of the Vcc terminal, the GND terminal, the INT terminal, and the NMI terminal is omitted. The Vcc terminal, the GND terminal, the INT terminal, and the NMI terminal are also provided in the CPU 101, but the description thereof is also omitted.

  The data terminals D0 to D7 read instructions in the CPU core 102, read data to be referred to when executing processing in the CPU core 102 according to the program corresponding to the instructions, and CPU core 102 according to the program corresponding to the instructions. This is a terminal for writing data derived as a result of the processing in. A plurality of data terminals D0 to D7 are provided, and are electrically connected to data terminals D10 to D17 provided in the CPU 101. Specifically, eight data terminals D0 to D7 of the CPU core 102 are provided, and eight data terminals D10 to D17 of the CPU 101 are also associated with the data terminals D0 to D7 of the CPU core 102 on a one-to-one basis. Is provided. The data terminals D0 to D7 of the CPU core 102 are electrically connected to the data terminals D10 to D17 of the CPU 101 through the data bus DB built in the CPU 101, and the data terminals D10 to D17 of the CPU 101 are provided inside the MPU 62. The data bus DB is electrically connected. With this configuration, the CPU core 102 can collectively read 8-bit (that is, 1 byte) data through the data bus DB, and can read 8-bit (that is, 1 byte) data to the data bus DB. Can be written together.

  Address terminals A0 to A15 are used for designating addresses of areas in which the instructions or data exist when reading instructions from the ROM 63 in the CPU core 102 and reading data from the ROM 63 or the RAM 64 in the CPU core 102. Terminal. Further, the address terminals A0 to A15 are terminals for designating addresses of areas in which data is written when the CPU core 102 writes data to the ROM 63 or the RAM 64. A plurality of address terminals A0 to A15 are provided, and are electrically connected to address terminals A20 to A35 provided in the CPU 101. Specifically, 16 address terminals A0 to A15 of the CPU core 102 are provided, and 16 address terminals A20 to A35 of the CPU 101 are also associated with the address terminals A0 to A15 of the CPU core 102 on a one-to-one basis. Is provided. The address terminals A0 to A15 of the CPU core 102 are electrically connected to the address terminals A20 to A35 of the CPU 101 through the address bus AB built in the CPU 101, and the address terminals A20 to A35 of the CPU 101 are provided inside the MPU 62. The address bus AB is electrically connected. With this configuration, the CPU core 102 can perform address designation for the ROM 63 and the RAM 64.

  The address terminals A0 to A15 are used not only when addressing the ROM 63 and the RAM 64 but also when outputting a chip select signal from the chip select terminals CS0 to CS12 provided in the CPU 101. Here, the chip select terminals CS0 to CS12 specify an operation target input latch circuit 103 (see FIG. 9A) when reading instructions in the CPU core 102 and reading data in the CPU core 102. This is a terminal for designating the output latch circuit 104 (see FIG. 9B) to be operated when data is written in the CPU core 102.

  A plurality of input latch circuits 103 are built in the MPU 62. As the plurality of input latch circuits 103, an input latch circuit for designating the ROM 63 as a read target when reading instructions and reading data, an input latch circuit for designating the RAM 64 as a read target when reading data, And an input latch circuit for designating an area in which the input data is stored as a read target when the data input to the input port 62a of the MPU 62 is read. The input latch circuit for designating the area where the input data is stored as the reading target when reading the data input to the input port 62a of the MPU 62 makes the area specified as the reading target in the input port 62a different. Are provided.

  A plurality of output latch circuits 104 are built in the MPU 62. As the plurality of output latch circuits 104, an output latch circuit for designating the RAM 64 as a write target when writing data, and an area for storing the output data when outputting data to the output port 62b of the MPU 62 are set as write targets. Is provided as an output latch circuit. When outputting data to the output port 62b of the MPU 62, a plurality of output latch circuits for designating an area for storing the output data as a write target are provided with different areas designated as read targets in the output port 62b. Yes.

  A plurality of chip select terminals CS0 to CS12 are provided, and each of the chip select terminals CS0 to CS12 is electrically connected to a select signal line provided in the MPU 62. Specifically, 13 chip select terminals CS0 to CS12 are provided, and 13 select signal lines are provided in one-to-one correspondence with the chip select terminals CS0 to CS12. A plurality of chip select terminals CS0 to CS4 which are a part of the chip select terminals CS0 to CS12 are for outputting the CS0 signal to CS4 signal as chip select signals to the input latch circuit 103, and the remaining plurality of chips. The select terminals CS5 to CS12 are for outputting the CS5 signal to the CS12 signal as chip select signals to the output latch circuit 104.

  The input latch circuit 103 will be described by taking as an example one used in the CPU 101 when predetermined data is input from the input port 62 a of the MPU 62. FIG. 9A is a block diagram of the input latch circuit 103. As shown in FIG. 9A, the input latch circuit 103 receives the data stored in the input latch circuit 103 through the input terminals Q0 to Q7 and the input terminals Q0 to Q7 for receiving data from the input port 62a. Data terminals D20 to D27 for supplying to the bus DB, a CK terminal to which the CS0 signal output from the chip select terminal CS0 of the CPU 101 is input, and the like are provided. When the CS0 signal is input to the CK terminal from the chip select terminal CS0 of the CPU 101, the input latch circuit 103 receives the data stored in the input latch circuit 103 through the input terminals Q0 to Q7 as data terminals D20 to D20. The data is supplied to the data bus DB through D27. The input latch circuit 103 includes a Vcc terminal, a GND terminal, a CLR terminal, and the like in addition to these terminals.

  The output latch circuit 104 will be described with reference to an example used in the CPU 101 when predetermined data is output to the output port 62b of the MPU 62. FIG. 9B is a block diagram of the output latch circuit 104. As shown in FIG. 9B, the output latch circuit 104 outputs data stored in the output latch circuit 104 through the data terminals D30 to D37 and data terminals D30 to D37 for receiving data from the data bus DB. Output terminals Q10 to Q17 for supplying to the port 62b, a CK terminal to which the CS5 signal output from the chip select terminal CS5 of the CPU 101 is input, and the like are provided. The output latch circuit 104 receives the data provided to the data bus DB through the data terminals D30 to D37 in the output latch circuit 104 when the CS5 signal is input to the CK terminal from the chip select terminal CS5 of the CPU 101. Thereafter, the captured data is output from the output terminals Q10 to Q17 to the output port 62b. Note that the output latch circuit 104 includes a Vcc terminal, a GND terminal, a CLR terminal, and the like in addition to these terminals.

  While the chip select terminals CS0 to CS12 of the CPU 101 have the above functions, the address data output from the address terminals A0 to A15 (see FIG. 8) of the CPU core 102 is a chip select for outputting a chip select signal. This is used when selecting the terminals CS0 to CS12. Further, when selecting the chip select terminals CS0 to CS12 for outputting the chip select signal, signals output from the RD terminal, WR terminal, IREQ terminal and MREQ terminal of the CPU core 102 are used.

  The RD terminal is a terminal for outputting an RD signal designating that the CPU core 102 reads an instruction or reads data. The WR terminal is a terminal for outputting a WR signal designating that the CPU core 102 writes data. The IREQ terminal receives an IREQ signal for designating that the CPU core 102 executes an in-command for inputting data from the input port 62a or an out-command for outputting data to the output port 62b. This is a terminal for output. The MREQ terminal receives an MREQ signal for designating that the CPU core 102 executes a load instruction for reading an instruction or data from the ROM 63, writing data to the RAM 64, or reading data from the RAM 64. This is a terminal for output.

  Next, various instructions executed in the CPU core 102 will be described. FIG. 10 is an explanatory diagram for explaining an area where instructions are stored in the ROM 63.

  In the ROM 63, a 1-byte instruction, a 2-byte instruction, and a 3-byte instruction are stored in advance as instructions. Among these instructions, the in instruction and the out instruction already described correspond to a 2-byte instruction, and the load instruction corresponds to a 3-byte instruction. Incidentally, the 2-byte instruction includes instructions other than the in instruction and the out instruction, and the 3-byte instruction includes instructions other than the load instruction. Further, the number of bytes of the instruction is not limited to these, and a 4-byte instruction may be stored in advance in addition to or instead of the instruction having the number of bytes.

  FIG. 11A is an explanatory diagram for explaining an in instruction and an out instruction which are 2-byte instructions. The in instruction and the out instruction include an address code shown in FIG. 11 (a1) and an IO identification code shown in FIG. 11 (a2). The address code has a 1-byte data structure and is set to the first byte in the in instruction and out instruction. Depending on the contents set in the address code, the type of the input latch circuit 103 to be operated when inputting data from the input port 62a and the operation target when outputting data to the output port 62b. The type of the output latch circuit 104 is specified. In this case, since the address code has a 1-byte data configuration, 256 addresses can be designated as addresses for specifying the types of latch circuits 103 and 104 to be operated. However, in this pachinko machine 10, since the number of chip select terminals CS0 to CS12 of the CPU 101 is 13 as already described, the number of types of addresses actually specified is 13 or less.

  The IO identification code has a 1-byte data configuration, and the content set in the IO identification code specifies whether the type of the 2-byte instruction is an in instruction or an out instruction. Incidentally, in the case of an out instruction, the next value of the program counter value corresponding to the out instruction corresponds to a 1-byte instruction, and the 1-byte instruction includes 1-byte output data to be output to the output port 62b. Is set.

  FIG. 11B is an explanatory diagram for explaining a load instruction which is a 3-byte instruction. The load instruction includes a first address code shown in FIG. 11 (b1), a second address code shown in FIG. 11 (b2), and an execution code shown in FIG. 11 (b3). Each of the first address code and the second address code has a data structure of 1 byte, the first address code is set to the first byte in the load instruction, and the second address code is the second byte in the load instruction. Is set to bytes. Depending on the contents set in the first address code and the second address code, the type of area to be read when reading instructions and data, and the type of area to be written when writing data Is identified.

  The execution code has a 1-byte data structure, and the type of instruction to be executed is specified by the contents set in the execution code. As instructions to be executed, a transfer instruction, an arithmetic operation instruction, a logical operation instruction, a bit operation instruction, a rotate instruction, a shift instruction, and the like are set. In the case of a transfer instruction, a process of reading data at an address specified by the first address code and the second address code to the CPU core 102, or predetermined data at an address specified by the first address code and the second address code Is transferred. In the case of an arithmetic operation instruction, processing for adding or subtracting predetermined data to data is executed. In the case of a logical operation instruction, a process for performing a predetermined logical operation on data is executed. In the case of a bit manipulation instruction, a process for switching a predetermined bit of data between “0” and “1” is executed. In the case of a rotate instruction, processing for shifting the bits included in the data so as to circulate in a predetermined direction is executed. In the case of a shift instruction, a process for shifting in a predetermined direction is performed without circulating the bits included in the data.

  Next, the IO space 105 and the memory space 106, which are virtual spaces accessed by the CPU core 102, will be described. FIG. 12 is a block diagram for explaining the IO space 105 and the memory space 106.

  The IO space 105 is a virtual space that is accessed by the CPU core 102 when an in instruction or an out instruction is executed in the CPU core 102. The situation where the CPU core 102 is accessing the IO space 105 is actually a chip select from the corresponding chip select terminal of the CPU 101 to the corresponding input latch circuit 103 in order to input data from the input port 62a. This is a situation in which a signal is output, or a situation in which a chip select signal is output from the corresponding chip select terminal of the CPU 101 to the corresponding output latch circuit 104 in order to output data to the output port 62b.

  In the in instruction and the out instruction that will access the IO space 105, the address code is 1 byte as described above. Therefore, the number of addresses that can be designated as the IO space 105 in the CPU core 102 is 256 corresponding to 1 byte. Correspondingly, when accessing the IO space 105, only the eight address terminals A0 to A7, which are a part of the 16 address terminals A0 to A15 of the CPU core 102, are used. Addressing is performed. That is, when accessing the IO space 105, the same number of address terminals A0 to A7 as the number of bits of the address code set in the in instruction and the out instruction are used. As a result, the contents of the address code set in the IN instruction and OUT instruction can be used as data to be set in the address terminals A0 to A7 as they are. The address data set in the first byte in the in instruction and the out instruction is the eight address terminals A0 that continue from the 0th address terminal A0 to the lower order among the address terminals A0 to A15 of the CPU core 102. It corresponds to ~ A7.

  The memory space 106 is a virtual space accessed by the CPU core 102 when the CPU core 102 reads an instruction from the area of the ROM 63 having an address corresponding to the value of the program counter and when the CPU core 102 executes a load instruction. It is space. The situation in which the CPU core 102 is accessing the memory space 106 is actually the corresponding chip select terminals CS0 to CS4 of the CPU 101 for reading instructions or data from the ROM 63 or reading data from the RAM 64. Corresponds to a situation in which a chip select signal is output to the corresponding input latch circuit 103, and the corresponding output latch circuit from the corresponding chip select terminals CS5 to CS12 of the CPU 101 in order to write data to the RAM 64. The situation where the chip select signal is output to 104 corresponds to this situation.

  In the load instruction that accesses the memory space 106, the address code is a total of 2 bytes of the first address code and the second address code, as already described. Therefore, the number of addresses that can be designated as the memory space 106 in the CPU core 102 is 65536 corresponding to 2 bytes. Correspondingly, when accessing the memory space 106, addressing is performed using all of the 16 address terminals A0 to A15 of the CPU core 102. That is, when accessing the memory space 106, the same number of address terminals A0 to A15 as the total number of bits of the first address code and the second address code set in the load instruction are used. Accordingly, the contents of the first address code and the second address code set in the load instruction can be used as data to be set in the address terminals A0 to A15 as they are.

  The first address data set in the first byte in the load instruction includes eight address terminals A0 to A0 that continue from the 0th address terminal A0 to the lower side among the address terminals A0 to A15 of the CPU core 102. It corresponds to A7. In addition, the second address data set in the second byte in the load instruction includes eight address terminals that continue from the eighth address terminal A8 to the lower order among the address terminals A0 to A15 of the CPU core 102. It corresponds to A8 to A15.

  Here, as already described, in the in instruction and the out instruction, address data is set in the first byte, and data corresponding to the address terminals A0 to A7 is set in the address data as an address code. . That is, in any of the in instruction, the out instruction, and the load instruction, data corresponding to the address terminals A0 to A7 is set in the first byte. As a result, the data set in the first byte can be set in the address terminals A0 to A7 regardless of whether the instruction is an in instruction, an out instruction, or a load instruction. It becomes possible to simplify the processing configuration by making it possible to share the processing configuration.

  Next, the contents that the CPU core 102 can execute the load instruction when inputting data from the input port 62a and when outputting data to the output port 62b will be described.

  As described above, the in instruction and the out instruction have a 2-byte configuration of an address code and an IO identification code, and an address for specifying the type of the latch circuits 103 and 104 to be operated is set in the address code. In the IO identification code, data indicating which of the IN command and the OUT command is set is set. In the case of this configuration, the execution code cannot be set in the in instruction and the out instruction like the load instruction. Further, since the total number of bits of the 2-byte instruction is smaller than that of the 3-byte instruction, the number of usable 2-byte instructions is naturally limited.

  On the other hand, the load instruction can be executed in the CPU core 102 also when data is input from the input port 62a and when data is output to the output port 62b. This makes it possible to use the execution code even when inputting / outputting these data. For example, when data is input from the input port 62a, a load instruction is executed to read data in a state after changing the arrangement of a plurality of bits, or data set in a plurality of bits Thus, it is possible to read data in a state after each is inverted. Further, for example, when data is output to the output port 62b, by executing a load instruction, the data output to the output port 62b is held as it is on the CPU core 102 side, and the data is stored in a predetermined order. It is possible to output the state data after changing the arrangement to the output port 62b.

  However, in the load instruction, as described above, the first address code is set in the first byte and the second address code is set in the second byte, and the CPU core 102 executes the load instruction. Whether the access is to the ROM 63 or the RAM 64, and the access to the input port 62a or the output port 62b, addressing is performed by using all of the 16 address terminals A0 to A15. The memory space 106 is being accessed. When accessing the ROM 63 or the RAM 64 and accessing the input port 62a or the output port 62b, if the handling of the load instruction in the CPU core 102 is made different, the data for identifying the access target is the address code. This is because the load instruction cannot be set as a 3-byte instruction in this case. Further, with the above configuration, when accessing the input port 62a or the output port 62b in the CPU core 102, executing an in instruction or an out instruction (that is, accessing the IO space 105) and executing a load instruction. Different addressing is performed depending on the case (that is, when accessing the memory space 106).

  As described above, when a load instruction is executed in the CPU core 102, it is necessary to set different addresses for accessing the ROM 63 or RAM 64 and for accessing the input port 62a or the output port 62b. Therefore, as shown in the explanatory diagram of the memory space 106 in FIG. 13, the memory space 106 includes not only the ROM space 106a corresponding to the ROM 63 and the RAM space 106b corresponding to the RAM 64, but also the input corresponding to the input port 62a. An output port space 106d corresponding to the port space 106c and the output port 62b exists. The addresses set in the ROM space 106a, RAM space 106b, input port space 106c, and output port space 106d are different from each other.

  The number of areas that need to be addressed is the ROM 63, the RAM 64 is the next, the output latch circuit 104 corresponding to the output port 62b is the next, and the input latch circuit 103 corresponding to the input port 62a is the smallest. . Therefore, the type of address set in the ROM space 106a is the largest, the type of address set in the RAM space 106b is the second most, and the type of address set in the output port space 106d is the next. The number of addresses set in the input port space 106c is the smallest.

  Next, regardless of whether the CPU core 102 executes an in instruction or an out instruction and a load instruction, data is input from the input port 62a or output to the output port 62b. The structure for performing will be described. FIG. 14 is a block diagram showing an electrical configuration for outputting a chip select signal from the chip select terminal CS0 corresponding to the input latch circuit 103 for inputting data from the input port 62a. An electrical configuration for outputting a chip select signal from another chip select terminal corresponding to the input latch circuit 103 that inputs data from the input port 62a, and an output that outputs data to the output port 62b. The electrical configuration for outputting a chip select signal from the chip select terminal corresponding to the latch circuit 104 is the same as the electrical configuration shown in FIG.

  Both the RD terminal and the WR terminal of the CPU core 102 are electrically connected to the operation selection circuit 111 built in the CPU 101. Specifically, the operation selection circuit 111 is provided with an input terminal corresponding to the RD terminal, and a signal path is formed so as to electrically connect the RD terminal and the input terminal. The operation selection circuit 111 is provided with an input terminal corresponding to the WR terminal, and a signal path is formed so as to electrically connect the WR terminal and the input terminal.

  The operation selection circuit 111 selects either the RD signal output from the RD terminal or the WR signal output from the WR terminal as the output trigger of the operation selection signal from the operation selection terminal 111a. Circuit. The operation selection circuit 111 receives an initialization signal when the supply of operating power from the initialization circuit 112 built in the CPU 101 to the CPU 101 is started. The initialization signal is input to the operation selection circuit 111. Thus, as a signal that triggers the output of the operation selection signal, a signal on the side determined in the design stage of the pachinko machine 10 is selected from the RD signal and the WR signal. Specifically, the operation selection circuit 111 is provided with a switch circuit 111b. When an initialization signal is input from the initialization circuit 112, the RD terminal and the operation selection terminal 111a are electrically connected, and WR Of the states in which the terminal and the operation selection terminal 111a are electrically connected, the state determined at the design stage of the pachinko machine 10 is assumed. Since the RD signal is a LOW level signal, when the switch circuit 111b is in a state of conducting the RD terminal and the operation selection terminal 111a, when the RD signal is not output (that is, the HI level signal is output from the RD terminal). HI level signal is output as the non-operation selection signal from the operation selection terminal 111a of the operation selection circuit 111, and the operation selection terminal 111a of the operation selection circuit 111 operates when the RD signal is output. A LOW level signal is output as the selection signal. Similarly, since the WR signal is a LOW level signal, when the switch circuit 111b is in a state where the WR terminal and the operation selection terminal 111a are in a conductive state, when the WR signal is not output (that is, the HI level signal is output from the WR terminal). When the HI level signal is output from the operation selection terminal 111a of the operation selection circuit 111 as a non-operation selection signal, and when the WR signal is output, the operation selection terminal 111a of the operation selection circuit 111 is output. Outputs a LOW level signal as an operation selection signal.

  Since FIG. 14 shows a chip select terminal CS0 for outputting a chip select signal to the input latch circuit 103, the operation selection circuit 111 is brought into conduction between the RD terminal and the operation selection terminal 111a. Thus, when the RD signal is output from the RD terminal of the CPU core 102, the operation selection circuit 111 outputs the operation selection signal from the operation selection terminal 111a.

  In the case of the operation selection circuit 111 corresponding to the chip select terminals CS5 to CS12 for outputting the chip select signal to the output latch circuit 104, the initialization signal is input from the initialization circuit 112, so that the WR terminal When the WR signal is output from the WR terminal of the CPU core 102, the operation selection signal is output from the operation selection terminal 111a of the operation selection circuit 111. Although the details will be described later, the output of the operation selection signal from the operation selection circuit 111 is a necessary condition for the output of the chip select signal from the chip select terminal CS0.

  Both the IREQ terminal and the MREQ terminal of the CPU core 102 are electrically connected to a target selection circuit 113 built in the CPU 101. Specifically, the target selection circuit 113 is provided with an input terminal corresponding to the IREQ terminal, and a signal path is formed so as to electrically connect the IREQ terminal and the input terminal. The target selection circuit 113 is provided with an input terminal corresponding to the MREQ terminal, and a signal path is formed so as to electrically connect the MREQ terminal and the input terminal.

  The target selection circuit 113 is provided with a target selection logic circuit 113a. Each of the signal output from the IREQ terminal and the signal output from the MREQ terminal is input to the NOR circuit in the target selection logic circuit 113a through each NOT circuit in the target selection logic circuit 113a. Since the IREQ signal is a LOW level signal and the MREQ signal is a LOW level signal, a LOW level signal is output from the target selection logic circuit 113a in a situation where either the IREQ signal or the MREQ signal is output. The In a situation where the LOW level signal is output from the target selection logic circuit 113a, the LOW level signal is output as the target selection signal from the target selection terminal 113b of the target selection circuit 113. That is, the target selection signal is output from the target selection circuit 113 regardless of whether the IREQ signal is output from the IREQ terminal or the MREQ signal is output from the MREQ terminal. As a result, when the CPU core 102 accesses the input port 62a or the output port 62b, not only when the in instruction or the out instruction is executed, but also when the load instruction is executed, in any case Even so, the target selection signal can be output from the target selection circuit 113. Although details will be described later, the output of the target selection signal from the target selection circuit 113 is a necessary condition for the output of the chip select signal from the chip select terminal CS0. The target selection circuit 113 outputs a HI level signal as a non-target selection signal in a situation where no IREQ signal is output and no MREQ signal is output.

  Of the address terminals A0 to A15 of the CPU core 102, eight address terminals A0 to A7 continuous from the 0th address terminal A0 to the lower order are electrically connected to the IO address decoder 114. Specifically, the IO address decoder 114 is provided with eight input terminals in a one-to-one correspondence with the eight address terminals A0 to A7, and the corresponding address terminals A0 to A7, input terminals, Are electrically connected to each other to form a signal path. All 16 address terminals A0 to A15 are electrically connected to the memory address decoder 115. Specifically, the memory address decoder 115 is provided with 16 input terminals in a one-to-one correspondence with the 16 address terminals A0 to A15, and the corresponding address terminals A0 to A15, input terminals, Are electrically connected to each other to form a signal path. A signal path from the address terminals A0 to A7 to each input terminal of the IO address decoder 114 is an intermediate position of a signal path that electrically connects the address terminals A0 to A7 and each input terminal of the memory address decoder 115. It is provided to be branched from.

  The IO address decoder 114 has an electric circuit configured to output a LOW level signal as an IO address signal from the IO address output terminal 114a when 1-byte address data corresponding to the chip select terminal CS0 is output from the CPU core 102. Is formed. The CPU core 102 also outputs address data from the address terminals A0 to A7 when outputting a chip select signal from the chip select terminals CS1 to CS12 different from the chip select terminal CS0. The IO address decoder 114 provided in correspondence does not output an IO address signal from the IO address output terminal 114a even if address data different from address data corresponding to a circuit provided in the IO address decoder 114 is input. That is, the HI level signal is output as a non-IO address signal from the IO address output terminal 114a.

  The memory address decoder 115 has an electric circuit configured to output a LOW level signal as a memory address signal from the memory address output terminal 115a when 2-byte address data corresponding to the chip select terminal CS0 is output from the CPU core 102. Is formed. The CPU core 102 also outputs address data from the address terminals A0 to A15 when outputting a chip select signal from the chip select terminals CS1 to CS12 different from the chip select terminal CS0. The memory address decoder 115 provided in correspondence does not output a memory address signal from the memory address output terminal 115a even if address data different from the address data corresponding to the circuit provided therein is input. That is, the HI level signal is output as a non-memory address signal from the memory address output terminal 115a.

  Although details will be described later, the output of the corresponding address signal from the IO address decoder 114 or the memory address decoder 115 is a necessary condition for the output of the chip select signal from the chip select terminal CS0.

  Here, the first of the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 114 and the 2-byte address data that triggers the output of the memory address signal from the memory address decoder 115. The 1-byte address data set in the byte is the same data. For example, while the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 114 is set to “A5” in hexadecimal, the output of the memory address signal from the memory address decoder 115 The address data of the first byte is set to “A5” in hexadecimal and the address data of the second byte is set to “00” in hexadecimal.

  In the electric circuit for outputting a chip select signal to the input latch circuit 103 that inputs data from the input port 62a and the output latch circuit 104 that outputs data to the output port 62b, as described above, IREQ The target selection signal is output from the target selection circuit 113 regardless of whether the signal or the MREQ signal is output. Then, when the 1-byte address data output from the upper address terminals A0 to A7 is address data corresponding to the output of the address signal from the IO address decoder 114, the lower address terminals A8 to A15. The IO address signal is output from the IO address decoder 114 regardless of which one-byte address data is output from the IO. In this case, the 2-byte address data in which the address data of the higher-order address terminals A0 to A7 corresponds to the IO address decoder 114 is changed to a chip select different from the chip select terminal corresponding to the IO address decoder 114. It cannot be used as address data corresponding to the IO address decoder and the memory address decoder in the electric circuit of the terminal. Under such circumstances, 1-byte address data set as the first byte of 2-byte address data for outputting a memory address signal from the memory address decoder 115 is transferred from the IO address decoder 114 to the IO address. By matching with the 1-byte address data for outputting the address signal, it is possible to suppress the number of types of address data that cannot be used as an electric circuit for other chip select terminals.

  The IO address output terminal 114 a of the IO address decoder 114 and the memory address output terminal 115 a of the memory address decoder 115 are both electrically connected to the address circuit 116 built in the CPU 101. Specifically, the address circuit 116 is provided with an input terminal corresponding to the IO address output terminal 114a, and a signal path is formed so as to electrically connect the IO address output terminal 114a and the input terminal. Is formed. The address circuit 116 is provided with an input terminal corresponding to the memory address output terminal 115a, and a signal path is formed so as to electrically connect the memory address output terminal 115a and the input terminal. Yes.

  The address circuit 116 is provided with an address logic circuit 116a. Each of the signal output from the IO address output terminal 114a and the signal output from the memory address output terminal 115a is input to the NOR circuit in the address logic circuit 116a through each NOT circuit in the address logic circuit 116a. ing. Since the IO address signal is the LOW level signal and the memory address signal is the LOW level signal, the LOW level signal is output from the address logic circuit 116a in a situation where at least one address signal is output. When the LOW level signal is output from the address logic circuit 116a, the LOW level signal is output from the address output terminal 116b of the address circuit 116 as a composite address signal. That is, the synthesized address signal is output from the address circuit 116 regardless of whether the IO address signal is output from the IO address output terminal 114a or the memory address signal is output from the memory address output terminal 115a. . As will be described in detail later, the output of the composite address signal from the address circuit 116 is a necessary condition for the output of the chip select signal from the chip select terminal CS0. Note that the address circuit 116 outputs a HI level signal as a non-synthetic address signal in a situation where no IO address signal is output and no memory address signal is output.

  The address output terminal 116 b of the address circuit 116, the operation selection terminal 111 a of the operation selection circuit 111, and the target selection terminal 113 b of the target selection circuit 113 are all electrically connected to the synthesis circuit 117 built in the CPU 101. . Specifically, the synthesis circuit 117 is provided with an input terminal corresponding to the address output terminal 116b, and a signal path is formed so as to electrically connect the address output terminal 116b and the input terminal. Yes. Further, the combining circuit 117 is provided with an input terminal corresponding to the operation selection terminal 111a, and a signal path is formed so as to electrically connect the operation selection terminal 111a and the input terminal. Further, the combining circuit 117 is provided with an input terminal corresponding to the target selection terminal 113b, and a signal path is formed so as to electrically connect the target selection terminal 113b and the input terminal.

  The synthesis circuit 117 is provided with a synthesis logic circuit 117a. Each of the signal output from the address output terminal 116b, the signal output from the operation selection terminal 111a, and the signal output from the target selection terminal 113b passes through each NOT circuit in the synthesis logic circuit 117a, and the NAND in the synthesis logic circuit 117a. It is input to the circuit. Since all of the composite address signal, the operation selection signal, and the target selection signal are LOW level signals, the composite circuit 117 outputs a LOW level in the situation where all of the composite address signal, the operation selection signal, and the target selection signal are output. A signal is output. In a situation where the LOW level signal is output from the synthesizing logic circuit 117a, the LOW level signal is output as the chip select signal from the chip select terminal CS0. That is, when the synthesized address signal is output from the address circuit 116, the operation selection signal is output from the operation selection circuit 111, and the target selection signal is output from the target selection circuit 113, the chip select terminal CS0 outputs the chip select. A signal is output. By outputting the chip select signal from the chip select terminal CS0, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is supplied to the data bus DB.

  Note that the synthesis circuit 117 outputs the HI level signal as a non-chip select signal in a situation where any one of the synthesis address signal, the operation selection signal, and the target selection signal is not output. In this case, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is not supplied to the data bus DB.

  Next, how the chip select signal is output from the chip select terminal CS0 will be described with reference to the time chart of FIG. FIG. 15A shows a period in which 1-byte address data is output from the CPU core 102, and FIG. 15B shows a period in which 2-byte address data is output from the CPU core 102. ) Indicates a period during which the composite address signal is output from the address circuit 116, FIG. 15D illustrates a period during which the operation selection signal is output from the operation selection circuit 111, and FIG. FIG. 15F shows a period during which the MREQ signal is output from the CPU core 102, and FIG. 15G shows a period during which the target selection signal is output from the target selection circuit 113. FIG. 15H shows a period during which the chip select signal is output from the chip select terminal CS0.

  First, a case where a chip select signal is output from the chip select terminal CS0 when the in-command is executed in the CPU core 102 will be described.

  At the timing t1, the CPU core 102 starts outputting 1-byte address data as shown in FIG. 15A, and the CPU core 102 starts outputting the IREQ signal as shown in FIG. 15E. Is done. Note that the output of the RD signal from the CPU core 102 is started at the timing t1. The address data output at the timing t1 is address data corresponding to the IO address decoder 114.

  When the output of 1-byte address data is started at the timing t1, the output of the IO address signal from the IO address decoder 114 is started. When the output of the IO address signal is started, the output of the composite address signal from the address circuit 116 is started at the timing t2, as shown in FIG.

  Further, when the output of the RD signal is started at the timing t1, the operation selection signal output from the operation selection circuit 111 is started at the timing t2, as shown in FIG. Further, when the output of the IREQ signal is started at the timing of t1, the output of the target selection signal from the target selection circuit 113 is started at the timing of t2, as shown in FIG.

  Output of the composite address signal, the operation selection signal, and the target selection signal is all started at the timing t2, so that the chip selection signal is output from the chip selection terminal CS0 as shown in FIG. 15 (h) at the timing t3. Is started. As a result, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is supplied to the data bus DB.

  Thereafter, at the timing t4, the output of 1-byte address data from the CPU core 102 is stopped as shown in FIG. 15A, and the IREQ signal from the CPU core 102 is shown in FIG. 15E. Output is stopped. Note that the output of the RD signal from the CPU core 102 is also stopped at the timing t4. Thereby, at the timing of t5, the output of the composite address signal is stopped as shown in FIG. 15C, the output of the operation selection signal is stopped as shown in FIG. 15D, and the output of FIG. As shown, the output of the target selection signal is stopped. By stopping the output of these signals, the output of the chip select signal from the chip select terminal CS0 is stopped at the timing of t6 as shown in FIG. 15 (h). When the output of the chip select signal is stopped, the supply of the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 to the data bus DB is stopped.

  The above operation flow is the same when the out instruction is executed in the CPU core 102 when data is output to the output port 62b by using the output latch circuit 104.

  Next, a case where a chip select signal is output from the chip select terminal CS0 when a load instruction is executed in the CPU core 102 will be described.

  At the timing t7, output of 2-byte address data from the CPU core 102 is started as shown in FIG. 15B, and output of the MREQ signal from the CPU core 102 is started as shown in FIG. 15F. Is done. Note that the output of the RD signal from the CPU core 102 is started at the timing t7. The address data output at the timing t7 is address data corresponding to the memory address decoder 115.

  When the output of 2-byte address data is started at the timing t7, the output of the memory address signal from the memory address decoder 115 is started. Then, when the output of the memory address signal is started, the output of the synthesized address signal from the address circuit 116 is started as shown in FIG. 15C at the timing of t8.

  Further, when the output of the RD signal is started at the timing of t7, the output of the operation selection signal from the operation selection circuit 111 is started as shown in FIG. 15D at the timing of t8. Further, when the output of the MREQ signal is started at the timing of t7, the output of the target selection signal from the target selection circuit 113 is started as shown in FIG.

  Output of the composite address signal, the operation selection signal, and the target selection signal is started at the timing of t8, so that the output of the chip selection signal from the chip selection terminal CS0 is performed at the timing of t9 as shown in FIG. Is started. As a result, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is supplied to the data bus DB.

  Thereafter, at the timing of t10, the output of 2-byte address data from the CPU core 102 is stopped as shown in FIG. 15B, and the MREQ signal from the CPU core 102 is shown in FIG. 15F. Output is stopped. Note that the output of the RD signal from the CPU core 102 is also stopped at the timing t10. Thereby, at the timing of t11, the output of the composite address signal is stopped as shown in FIG. 15C, the output of the operation selection signal is stopped as shown in FIG. 15D, and the output of FIG. As shown, the output of the target selection signal is stopped. Then, by stopping the output of these signals, the output of the chip select signal from the chip select terminal CS0 is stopped at the timing t12 as shown in FIG. 15 (h). When the output of the chip select signal is stopped, the supply of the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 to the data bus DB is stopped.

  As described above, the target selection circuit 113 is provided with a negative logic OR circuit using the signal output from the IREQ terminal of the CPU core 102 and the signal output from the MREQ terminal of the CPU core 102 as input signals. As a result, the target selection signal is output from the target selection circuit 113 regardless of whether the CPU core 102 outputs the IREQ signal or the MREQ signal. In this case, when data is input from the input port 62a using the input latch circuit 103 corresponding to the chip select terminal CS0, either the in instruction or the load instruction is executed in the CPU core 102. In other words, it is possible to output the target selection signal from the target selection circuit 113 without switching the state of the target selection circuit 113, regardless of whether the CPU core 102 outputs the IREQ signal or the MREQ signal. It becomes. Thus, it is possible to output the chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

  The electrical circuit corresponding to the chip select terminal CS0 is provided with an IO address decoder 114 corresponding to 1-byte address data and a memory address decoder 115 corresponding to 2-byte address data. When 1-byte address data is output from 102, an IO address signal is output from the IO address decoder 114, and when 2-byte address data is output from the CPU core 102, the memory address decoder 115 outputs a memory. An address signal is output. When at least one of the IO address signal and the memory address signal is output, the synthesized address signal is output from the address circuit 116. In this case, when data is input from the input port 62a using the input latch circuit 103 corresponding to the chip select terminal CS0, either the in instruction or the load instruction is executed in the CPU core 102. In other words, the address circuit 116 without switching the state of the circuit for outputting the address signal, regardless of whether 1-byte address data or 2-byte address data is output from the CPU core 102. It is possible to output a composite address signal from. Thus, it is possible to output the chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

  Next, the contents of the instruction execution process that is repeatedly executed in a short cycle by the CPU core 102 will be described with reference to the flowchart of FIG. 16 is executed by the CPU core 102, as a result, the main process (FIG. 6) and the timer interrupt process (FIG. 7) already described in the MPU 62 of the main controller 60 are executed. .

  First, an instruction is read from the area of the ROM 63 corresponding to the address specified in the current value of the program counter (step S301). If the read instruction is a 2-byte instruction (step S302: YES), it is determined whether an IO identification code is set for the instruction (step S303). If the IO identification code is not set (step S303: NO), it means that the current instruction is neither an in instruction nor an out instruction, and therefore processing corresponding to the current instruction in other processing of step S304. Execute.

  If an IO identification code is set for the current instruction (step S303: YES), this means that the current instruction is an in-command or an out-command, and the process proceeds to step S305. In step S305, the address code set in the first byte of the instruction read this time is set for the upper eight address terminals A0 to A7, thereby setting the output of 1-byte address data. . As a result, 1-byte address data is output from the address terminals A0 to A7. In this case, the output states of the remaining eight address terminals A8 to A15 are maintained at the previous output states. In step S306, output of the IREQ signal from the IREQ terminal of the CPU core 102 is started.

  Thereafter, when the IO identification code in the current instruction corresponds to data input from the input port 62a (step S307: YES), output of the RD signal is started from the RD terminal of the CPU core 102 (step S308). On the other hand, when the IO identification code in the current instruction corresponds to the output of data from the output port 62b (step S307: NO), the output of the WR signal is started from the WR terminal of the CPU core 102 (step S309). Thereafter, 1-byte output data is read from the area of the ROM 63 corresponding to the address specified in the next value of the program counter referred to in step S301, and the output data is set to the data bus DB (step S310). ).

  If the current instruction is not a 2-byte instruction (step S302: NO), it is determined whether the current instruction is a 3-byte instruction (step S311). If it is not a 3-byte instruction, it means that the current instruction is a 1-byte instruction or an instruction of 4 bytes or more, and therefore processing corresponding to the current instruction is executed in other processing of step S304. If it is a 3-byte instruction (step S311: YES), a 3-byte instruction process is executed (step S312).

  FIG. 17 is a flowchart showing the 3-byte instruction processing.

  If the current 3-byte instruction is an input instruction for the input port 62a (step S401: YES), the first address code set in the first byte of the instruction read this time is used as the upper eight address terminals A0. To A7, and by setting the second address code set in the second byte of the instruction read this time to the lower eight address terminals A8 to A15, two bytes Set the address data output. As a result, 2-byte address data is output from the address terminals A0 to A15.

  Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S403), and the output of the RD signal is started from the RD terminal of the CPU core 102 (step S404). Thereafter, if the current input instruction includes a logical operation instruction (step S405: YES), the logical operation processing specified in the current instruction is executed on the data input this time from the input port 62a. (Step S406). For example, when it is designated as an instruction to perform an AND process on data stored in the register of the MPU 62 and data input this time from the input port 62a, the AND process is executed.

  If the current 3-byte instruction is an output instruction for the output port 62b (step S407: YES), output setting of 2-byte address data is performed as in step S402 (step S408). As a result, 2-byte address data is output from the address terminals A0 to A15.

  Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S409), and the output of the WR signal is started from the WR terminal of the CPU core 102 (step S410). Thereafter, if the current output command includes a shift command (step S411: YES), a process of shifting the bit of the data to be output this time to the output port 62b in a predetermined direction is executed (step S412). ). Thereafter, the data to be output this time is set for the data bus DB (step S413).

  When the current 3-byte instruction is a read instruction (step S414: YES), output setting of 2-byte address data is performed in the same manner as in step S402 (step S415). As a result, 2-byte address data is output from the address terminals A0 to A15. Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S416), and the output of the RD signal is started from the RD terminal of the CPU core 102 (step S417). As a result, data is read from the area corresponding to the current address data in the ROM 63 or RAM 64.

  If the current 3-byte instruction is a write instruction (step S418: YES), output setting of 2-byte address data is performed as in step S402 (step S419). As a result, 2-byte address data is output from the address terminals A0 to A15. Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S420), and the output of the WR signal is started from the WR terminal of the CPU core 102 (step S421). Thereafter, the data to be output this time is set for the data bus DB (step S422).

  If the current 3-byte instruction is not a write instruction (step S418: NO), other processing is executed (step S423). In other processing, for example, a calculation operation instruction or a bit operation instruction is executed.

  According to the embodiment described in detail above, the following excellent effects are obtained.

  The CPU core 102 outputs an MREQ signal from the MREQ terminal when executing a load instruction, and outputs an IREQ signal from the IREQ terminal when executing an in instruction or an out instruction. As a result, it is possible to prevent data reading, data writing, and data input / output from being performed in a situation where none of the load instruction, the in instruction, and the out instruction is executed. It is possible to distinguish the operation target between the case where is executed and the case where the in instruction or the out instruction is executed. In this case, the combining circuit 117 for outputting the chip select signal to the input latch circuit 103 corresponding to the input port 62a outputs either the MREQ signal or the IREQ signal from the CPU core 102. A chip select signal is output. The same applies to the configuration for outputting a chip select signal to the output latch circuit 104 corresponding to the output port 62b. Thereby, not only when the in instruction or the out instruction is executed, but also when the load instruction is executed, the data can be received from the input port 62a or set to the output port 62b. It becomes possible. Therefore, it is possible to widen the range of types of instructions executed when receiving data from the input port 62a or setting data to the output port 62b.

  In a configuration in which a chip select signal is output from the synthesis circuit 117 on the condition that the target selection signal is output from the target selection circuit 113, the target selection circuit 113 outputs an IREQ signal or an MREQ signal. Since the configuration is such that the target selection signal is output, the above-described excellent effects can be achieved while diverting the configuration other than the target selection circuit 113 as it is.

  The target selection circuit 113 is provided with a negative logic OR circuit that uses the signal output from the IREQ terminal of the CPU core 102 and the signal output from the MREQ terminal of the CPU core 102 as input signals. The target selection signal is output from the target selection circuit 113 regardless of whether the IREQ signal or the MREQ signal is output from the core 102. In this case, when data is input from the input port 62a using the input latch circuit 103 corresponding to the chip select terminal CS0, either the in instruction or the load instruction is executed in the CPU core 102. In other words, it is possible to output the target selection signal from the target selection circuit 113 without switching the state of the target selection circuit 113, regardless of whether the CPU core 102 outputs the IREQ signal or the MREQ signal. It becomes. Thus, it is possible to output the chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

  When executing an in instruction or an out instruction, 1-byte address data is output from the CPU core 102, and when executing a load instruction, 2-byte address data is output from the CPU core 102. Thereby, it becomes possible to output the address data in a manner corresponding to each of the case where the in instruction or the out instruction is executed and the case where the load instruction is executed. Further, even when the in instruction or the out instruction is executed as described above, 1 byte of address data is output, and when the load instruction is executed, 2 bytes of address data is output. The chip select signal is output from the synthesis circuit 117 regardless of whether the address data is output or the 2-byte address data is output. Thereby, not only when the in instruction or the out instruction is executed, but also when the load instruction is executed, the data can be received from the input port 62a or set to the output port 62b. It becomes possible.

  The electric circuit corresponding to the chip select terminal CS0 is provided with an IO address decoder 114 corresponding to 1-byte address data and a memory address decoder 115 corresponding to 2-byte address data. When 1-byte address data is output, an IO address signal is output from the IO address decoder 114, and when 2-byte address data is output from the CPU core 102, a memory address signal is output from the memory address decoder 115. Is output. When at least one of the IO address signal and the memory address signal is output, the synthesized address signal is output from the address circuit 116. In this case, when data is input from the input port 62a using the input latch circuit 103 corresponding to the chip select terminal CS0, either the in instruction or the load instruction is executed in the CPU core 102. In other words, the address circuit 116 without switching the state of the circuit for outputting the address signal, regardless of whether 1-byte address data or 2-byte address data is output from the CPU core 102. It is possible to output a composite address signal from. Thus, it is possible to output the chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

<Second Embodiment>
In this embodiment, even if the CPU core 102 does not execute processing for separately storing output data, it is possible to process data that has already been output and output the processed data. The configuration is different from the first embodiment. The different configuration will be described below. The description of the same configuration as that of the first embodiment is basically omitted.

  FIG. 18 is an explanatory diagram for explaining the electrical configuration of the CPU 101 in the present embodiment.

  The CPU 101 includes chip select terminals CS0 to CS12 as in the first embodiment. However, in this embodiment, the chip select terminal CS0, the chip select terminal CS2, the chip select terminal CS4, and the chip select terminal CS6 are for outputting a chip select signal to the output latch circuits 121a to 121d. The other chip select terminals CS1, CS3, CS5, CS7 to CS12 are for outputting a chip select signal to the input latch circuits 122a to 122i.

  A signal path is formed between the chip select terminals CS0, CS2, CS4, and CS6 corresponding to the output latch circuits 121a to 121d and the corresponding output latch circuits 121a to 121d, and the input latch circuits 122a to 122i. Signal paths are formed between the corresponding chip select terminals CS1, CS3, CS5, CS7 to CS12 and the corresponding input latch circuits 122a to 122i. Each of the output latch circuits 121a to 121d has a signal path formed between the data terminals D10 to D17 of the CPU 101 and the data bus DB electrically connected to the data terminals D10 to D17. Data supplied to DB can be latched in the output latch circuits 121a to 121d. Each of the input latch circuits 122a to 122i has a signal path with the data bus DB, and temporarily stores and holds the data supplied from the corresponding data output source. It is possible to supply the stored data to the data bus DB as needed.

  Of the chip select terminals CS0, CS2, CS4 and CS6 corresponding to the output latch circuits 121a to 121d, a plurality (specifically, three) of chip select terminals CS0, CS2 and CS4 are connected to the output port 62b. The other chip select terminals CS6 are connected to the output latch circuit 121d for outputting data to the RAM 64, and the chip select signal is output to the output latch circuits 121a to 121c. This is for outputting a select signal. In this case, input latch circuits 122a to 122c are provided in a one-to-one correspondence with the output latch circuits 121a to 121c for outputting data to the output port 62b, and these output latch circuits 121a to 121c are provided. The data output from 121c to the output port 62b is latched in the input latch circuits 122a to 122c corresponding to the output latch circuits 121a to 121c. More specifically, the data paths L1 to L3 that electrically connect the output latch circuits 121a to 121c and the output port 62b each branch in the middle, and the branch paths L4 to L6 correspond to the input latch circuits. It is electrically connected to 122a to 122c. The data latched by the input latch circuits 122a to 122c is output as chip select signals from chip select terminals CS1, CS3, and CS5 provided in one-to-one correspondence with the input latch circuits 122a to 122c. As a result, the data is supplied to the data bus DB and input to the data terminals D10 to D17 of the CPU 101. As a result, when data is output to the output port 62b, the CPU core 102 reads and processes the output target data without executing processing for separately storing the data to be output in the register or RAM 64 of the CPU core 102. The processed data can be output to the output port 62b.

  Next, a configuration for processing data that has been output to the output port 62b in the CPU core 102 and outputting the processed data to the output port 62b will be described in detail. FIG. 19 is a block diagram showing an output circuit 131 for outputting a chip select signal to the output latch circuit 121a in the CPU 101 and an input circuit 141 for outputting a chip select signal to the input latch circuit 122a in the CPU 101. It is. FIG. 19 shows an electrical configuration for outputting a chip select signal to other combinations of output latch circuits 121b and 121c and input latch circuits 122b and 122c for circulating output data to the output port 62b. It is the same as the electrical configuration shown.

  Similarly to the electrical configuration shown in FIG. 14 in the first embodiment, the output circuit 131 is electrically connected to the operation selection circuit 132 electrically connected to the RD terminal and the WR terminal, and electrically connected to the IREQ terminal and the MREQ terminal. When the out instruction is executed in the CPU core 102, the IO address decoder 134 to which 1-byte address data is input when the out instruction is executed, and the load instruction is executed in the CPU core 102 A memory address decoder 135 to which 2-byte address data is input, an IO address decoder 134, an address circuit 136 electrically connected to the memory address decoder 135, an address circuit 136, an operation selection circuit 132, and A synthesis circuit 137 electrically connected to the object selection circuit 133; That. Specific configurations of the operation selection circuit 132, the object selection circuit 133, the IO address decoder 134, the memory address decoder 135, the address circuit 136, and the synthesis circuit 137 are the same as those in the first embodiment.

  The switch circuit 132a provided in the operation selection circuit 132 receives an initialization signal when the supply of operation power to the CPU 101 is started, so that a signal that triggers the output of the operation selection signal is output from the RD terminal. Of the RD signal and the WR signal from the WR terminal, the WR signal is set. Therefore, when the WR signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 132.

  The target selection circuit 133 outputs a target selection signal regardless of whether an IREQ signal or an MREQ signal is output from the CPU core 102. The IO address decoder 134 outputs an IO address signal when 1-byte address data corresponding to the IO address decoder 134 is output from the CPU core 102. The memory address decoder 135 outputs a memory address signal when 2-byte address data corresponding to the memory address decoder 135 is output from the CPU core 102. The address circuit 136 outputs a composite address signal when either the IO address signal or the memory address signal is output. The synthesis circuit 137 outputs a chip select signal from the chip select terminal CS0 to the output latch circuit 121a when all of the synthesized address signal, the operation selection signal, and the target selection signal are output. As a result, the data set in the data terminals D0 to D7 of the CPU core 102 is latched in the output latch circuit 121a and latched for each area of the output port 62b corresponding to the output latch circuit 121a. Data is output. The output data is latched by the input latch circuit 122a through the data path L1 and the branch path L4.

  Similarly to the electrical configuration shown in FIG. 14 in the first embodiment, the input circuit 141 is electrically connected to the RD terminal and the WR terminal, the IREQ terminal and the MREQ terminal. When the out instruction is executed in the CPU core 102, the IO address decoder 144 to which 1-byte address data is input when the out instruction is executed, and when the load instruction is executed in the CPU core 102 A memory address decoder 145 to which 2-byte address data is input; an address circuit 146 electrically connected to the IO address decoder 144 and the memory address decoder 145; an address circuit 146; an operation selection circuit 142; A synthesis circuit 147 electrically connected to the target selection circuit 143; That. The specific configurations of the operation selection circuit 142, target selection circuit 143, IO address decoder 144, memory address decoder 145, address circuit 146, and synthesis circuit 147 are the same as those in the first embodiment.

  In FIG. 19, the CPU core 102 is shown as having two each of the address terminals A0 to A15, the RD terminal, the WR terminal, the IREQ terminal, and the MREQ terminal. Only one of each of these terminals is provided, and the signal from each terminal is supplied to each of the output circuit 131 and the input circuit 141 by branching a signal path extending from each terminal. Yes.

  The switch circuit 142a provided in the operation selection circuit 142 receives an initialization signal when the supply of operation power to the CPU 101 is started, so that a signal that triggers the output of the operation selection signal is output from the RD terminal. The RD signal and the WR signal from the WR terminal are set to be the RD signal. Therefore, when the RD signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 142.

  The target selection circuit 143 outputs a target selection signal regardless of whether an IREQ signal or an MREQ signal is output from the CPU core 102. The IO address decoder 144 outputs an IO address signal when 1-byte address data corresponding to the IO address decoder 144 is output from the CPU core 102. The memory address decoder 145 outputs a memory address signal when 2-byte address data corresponding to the memory address decoder 145 is output from the CPU core 102. The address circuit 146 outputs a composite address signal when either the IO address signal or the memory address signal is output. The synthesizing circuit 147 outputs a chip select signal from the chip select terminal CS1 to the input latch circuit 122a when all of the synthesized address signal, the operation selection signal, and the target selection signal are output. As a result, the data latched in the input latch circuit 122a is supplied to the data bus DB, and the supplied data is acquired by the CPU core 102. The acquired data is data that was output last time to the corresponding area of the output port 62b using the output latch circuit 121a.

  Here, the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 144 of the input circuit 141 triggers the output of the IO address signal from the IO address decoder 134 of the output circuit 131. It is the same as 1-byte address data. The 2-byte address data that triggers the output of the memory address signal from the memory address decoder 145 of the input circuit 141 triggers the output of the memory address signal from the memory address decoder 135 of the output circuit 131 2. It is the same as the byte address data. Thus, the address data for outputting the chip select signal from the output circuit 131 to the output latch circuit 121a is the same as the address data for outputting the chip select signal from the input circuit 141 to the input latch circuit 122a. It becomes possible to make it data. Therefore, the CPU core 102 can process the data already output to the output port 62b and output the processed data to the output port 62b by designating one address data.

  Even if the configuration is such that the output of the chip select signal to the output latch circuit 121a and the output of the chip select signal to the input latch circuit 122a by the designation of one address data, the chip to the output latch circuit 121a. The output of the select signal is performed when the WR signal is output from the CPU core 102, and the output of the chip select signal to the input latch circuit 122a is performed when the RD signal is output from the CPU core 102. Therefore, the data output timing using the output latch circuit 121a can be different from the data input timing using the input latch circuit 122a.

  Next, a case where the processing performed by processing the data already output to the output port 62b in the CPU core 102 and outputting the processed data to the output port 62b is used for display control in the special figure display unit 37a. Will be described.

  FIG. 20A is a front view of the special figure display section 37a. The special figure display unit 37 a is provided with eight light emitting units 151 to 158. Each of the light emitting units 151 to 158 has an individual light source composed of LEDs, and by turning on and off these individual light sources, only one arbitrary light emitting unit 151 to 158 can be turned on. In any combination, the light emitting units 151 to 158 can be turned on. Since each of the individual light sources emits light of the same color, the same color is displayed in each of the light emitting units 151 to 158, but is not limited thereto. It is good also as a structure by which a different color is displayed in each light emission part 151-158. Of the light emitting units 151 to 158, the seven first to seventh light emitting units 151 to 158 are all linear display segments, and the first to seventh light emitting units 151 to 151 are so-called 7-segment displays. 158 are arranged. The remaining eighth light emitting unit 158 is a circular light emitting unit, and is provided at a position adjacent to the first to seventh light emitting units 151 to 158.

  FIG. 20B is an explanatory diagram for explaining an output area 159 in which data defining the contents of data output to the first to eighth light emitting units 151 to 158 is set in the output port 62b.

  The output area 159 has a 1-byte data structure, and each bit corresponds to the first to eighth light emitting units 151 to 158 on a one-to-one basis. Specifically, the output area 159 includes a first bit 159 a corresponding to the first light emitting unit 151, a second bit 159 b corresponding to the second light emitting unit 152, and a third bit 159 c corresponding to the third light emitting unit 153. The fourth bit 159d corresponding to the fourth light emitting unit 154, the fifth bit 159e corresponding to the fifth light emitting unit 155, the sixth bit 159f corresponding to the sixth light emitting unit 156, and the seventh light emitting unit 157. A corresponding seventh bit 159g and an eighth bit 159h corresponding to the eighth light emitting unit 158 are provided. The main control board 61 is provided with a drive circuit for outputting a drive signal to the first to eighth light emitting units 151 to 158 based on the data set in the output area 159. In the drive circuit, the light emitting units 151 to 158 corresponding to the bits 159a to 159h in which data “1” corresponding to the light emission corresponding data among the first to eighth bits 159a to 159h is set to the light emitting state, and the light is turned off. The light emission control for the first to eighth light emitting units 151 to 158 is executed so that the light emitting units 151 to 158 corresponding to the bits 159a to 159h in which the data “0” corresponding to the corresponding data is set are turned off. .

  FIG. 21 is an explanatory diagram for explaining the relationship between the contents set in the output area 159 and the light emission modes of the first to eighth light emitting units 151 to 158. 21 (a1) to 21 (a8) are explanatory diagrams for explaining the contents of data set in the output area 159, and FIGS. 21 (b1) to 21 (b8) are first to eighth. It is explanatory drawing for demonstrating the light emission aspect of the light emission parts 151-158.

  When “1” is set only in the first bit 159a of the output area 159 as shown in FIG. 21 (a1), the first to eighth light emitting units 151 to 158 are shown in FIG. 21 (b1). Among these, only the 1st light emission part 151 will be in a lighting state, and the remainder will be in a light extinction state. From this state, as shown in FIGS. 21A2 to 21A8, the bits 159a to 159h in which “1” is set are changed from the first bit 159a → the second bit 159b → the third bit 159c → the fourth bit. By shifting in the order of bit 159d → fifth bit 159e → sixth bit 159f → seventh bit 159g → eighth bit 159h, the light emitting state is obtained as shown in FIGS. The light emitting units 151 to 158 are the first light emitting unit 151 → the second light emitting unit 152 → the third light emitting unit 153 → the fourth light emitting unit 154 → the fifth light emitting unit 155 → the sixth light emitting unit 156 → the seventh light emitting unit 157 → the eighth. It changes in the order of the light emitting unit 158. Thereby, the display content of the special figure display part 37a can be changed only by changing the bit for setting “1” in the output area 159.

  Next, the control process of the special figure display unit executed by the MPU 62 of the main controller 60 will be described with reference to the flowchart of FIG. The control process of the special figure display unit is executed in the display control process (step S215) in the timer interrupt process (FIG. 7).

  When the fluctuation display of the special figure display unit 37a is not in progress and the fluctuation start condition of the special figure display unit 37a is satisfied (step S501: NO, step S502: YES), driving for fluctuation start which is a 3-byte instruction The instruction is read from the ROM 63 (step S503). Then, the first address code set in the first byte of the read instruction is set to the upper eight address terminals A0 to A7 in the CPU core 102, and the second address of the read instruction is set. By setting the second address code set in this byte to the lower eight address terminals A8 to A15 in the CPU core 102, output setting of 2-byte address data is performed (step S504). As a result, 2-byte common address data is output from the address terminals A0 to A15.

  Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S505), and the output of the WR signal is started from the WR terminal of the CPU core 102 (step S506). Thereafter, the drive data at the start of fluctuation is read from the area of the ROM 63 corresponding to the next value with respect to the value of the program counter corresponding to the instruction read in step S503, and the data to be output this time is sent to the data bus DB. (Step S507). As the drive data at the start of fluctuation, “1” is set only in the first bit 159a of the first to eighth bits 159a to 159h of the output area 159, and “0” is set in the remaining bits 159a to 159h. It is drive data for doing so. By executing the processing of step S507, the drive data at the start of the fluctuation is latched in the output latch circuit 121a, and the data corresponding to the drive data at the start of the fluctuation is the first to eighth bits 159a of the output area 159. ~ 159h. Thereby, the variation display of a picture is started in the special figure display part 37a. The data output from the output latch circuit 121a to the output area 159 is latched by the input latch circuit 122a.

  When the variation display of the special figure display section 37a is being performed (step S501: YES), it is not the end timing of the current variation display (step S508: NO), and it is the display content update timing (step S509). : YES) A drive instruction for update, which is a 3-byte instruction, is read from the ROM 63 (step S510). Then, the first address code set in the first byte of the read instruction is set to the upper eight address terminals A0 to A7 in the CPU core 102, and the second address of the read instruction is set. By setting the second address code set in this byte to the lower eight address terminals A8 to A15 in the CPU core 102, output setting of 2-byte address data is performed (step S511). As a result, 2-byte common address data is output from the address terminals A0 to A15.

  Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S512), and the output of the RD signal is started from the RD terminal of the CPU core 102 (step S513). As a result, the drive data latched by the input latch circuit 122 a is provided to the data bus DB, and the drive data is read out to the CPU core 102. This drive data is the drive data currently set in the output area 159.

  Thereafter, the drive data rotation process is executed in accordance with the instruction read in step S510 (step S514). Specifically, the rotation process is executed so that each bit of the drive data acquired from the input latch circuit 122a circulates in a predetermined direction. As a result, as shown in FIGS. 21A1 to 21A8, the bits in which “1” is set in the drive data are shifted so as to circulate in a predetermined direction.

  Thereafter, in accordance with the instruction read in step S510, the common address data output is set in the same manner as in step S511 (step S515). Then, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S516), the output of the WR signal is started from the WR terminal of the CPU core 102 (step S517), and the rotation process is executed in step S514. The drive data after this is set for the data bus DB as the data to be output this time (step S518). As a result, the current drive data is latched in the output latch circuit 121a, and the data corresponding to the drive data is set in the first to eighth bits 159a to 159h of the output area 159. Thereby, the display content in the special figure display part 37a is changed. The data output from the output latch circuit 121a to the output port 62b is latched by the input latch circuit 122a.

  The processing contents of steps S510 to S518 are executed every time the display contents are updated before the end of the variable display. In this case, the update driving command data read out is always the same command. As a result, it is possible to execute the display control of the special figure display unit 37a while suppressing the number of types of instructions stored in advance in the ROM 63.

  If it is the end timing of the variable display (step S508: YES), the variable display end process is executed (step S519). As a result, the drive data corresponding to the determination result of the current game round and the allocation determination result are set in the output area 159, and the special display is displayed so that the display contents corresponding to the determination result and the allocation determination result are displayed. The display of the unit 37a is controlled.

  According to the present embodiment described in detail above, the following excellent effects are obtained in addition to the effects in the first embodiment.

  Input latch circuits 122a to 122c are provided in one-to-one correspondence with the output latch circuits 121a to 121c for outputting data to the output port 62b. The data output to 62b is latched in the input latch circuits 122a to 122c corresponding to the output latch circuits 121a to 121c of the output source. The data latched by the input latch circuits 122a to 122c is output as chip select signals from chip select terminals CS1, CS3, and CS5 provided in one-to-one correspondence with the input latch circuits 122a to 122c. As a result, the data is supplied to the data bus DB and input to the data terminals D10 to D17 of the CPU 101. As a result, when data is output to the output port 62b, the CPU core 102 reads and processes the output target data without executing processing for separately storing the data to be output in the register or RAM 64 of the CPU core 102. The processed data can be output to the output port 62b.

  The input latch circuits 122a to 122c supply the acquired output data to the data bus DB. As a result, output data can be supplied to the CPU core 102 using the configuration of the existing transmission path.

  By outputting a chip select signal from the chip select terminals CS1, CS3, CS5, the data latched in the input latch circuits 122a-122c is supplied to the data bus DB and input to the data terminals D10-D17 of the CPU 101. With the configuration, it is possible to acquire data from the input latch circuits 122a to 122c at a preferable timing in the control of the CPU 101.

  The data paths L1 to L3 that electrically connect the output latch circuits 121a to 121c and the output port 62b respectively branch in the middle, and the branch paths L4 to L6 correspond to the corresponding input latch circuits 122a to 122c. Electrically connected. This makes it possible to reacquire output data in the CPU core 102 without incorporating the input latch circuits 122a to 122c in the CPU 101.

  The 1-byte address data that triggers the output of the IO address signal from the IO address decoder 144 of the input circuit 141 is the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 134 of the output circuit 131. It is the same as the address data. The 2-byte address data that triggers the output of the memory address signal from the memory address decoder 145 of the input circuit 141 triggers the output of the memory address signal from the memory address decoder 135 of the output circuit 131 2. It is the same as the byte address data. Thus, the address data for outputting the chip select signal from the output circuit 131 to the output latch circuit 121a is the same as the address data for outputting the chip select signal from the input circuit 141 to the input latch circuit 122a. It becomes possible to make it data. Therefore, the CPU core 102 can process the data already output to the output port 62b and output the processed data to the output port 62b by designating one address data.

  Even if the chip select signal is output to the output latch circuit 121a and the chip select signal is output to the input latch circuit 122a by designating one address data, the chip select signal to the output latch circuit 121a. Is output when the WR signal is output from the CPU core 102, and the output of the chip select signal to the input latch circuit 122a is performed when the RD signal is output from the CPU core 102. Therefore, the data output timing using the output latch circuit 121a can be different from the data input timing using the input latch circuit 122a.

<Third Embodiment>
In the present embodiment, the output latch circuit 162 and the input latch circuit 163 that are used when the CPU core 102 processes data that has already been output to the output port 62b and outputs the processed data to the output port 62b. The second embodiment is different from the second embodiment in that it is not provided outside the CPU 101 but is built in the CPU 101. The different configuration will be described below. The description of the same configuration as that of the second embodiment is basically omitted.

  FIG. 23 is a block diagram showing an electrical configuration of the CPU 101.

  The CPU 101 includes an output circuit 171 for outputting a chip select signal to each of an external output latch circuit 161 provided outside the CPU 101 and an internal output latch circuit 162 provided inside the CPU 101; Only an internal input latch circuit 163 provided in the CPU 101 is provided with an input circuit 181 for outputting a chip select signal.

  Similarly to the electrical configuration shown in FIG. 14 in the first embodiment, the output circuit 171 is electrically connected to the operation selection circuit 172 electrically connected to the RD terminal and the WR terminal, and to the IREQ terminal and the MREQ terminal. The target selection circuit 173 connected to the I / O, the IO address decoder 174 to which 1-byte address data is input when an out instruction is executed in the CPU core 102, and the load instruction is executed in the CPU core 102 A memory address decoder 175 to which 2-byte address data is input, an IO address decoder 174, an address circuit 176 electrically connected to the memory address decoder 175, an address circuit 176, an operation selection circuit 172, and A synthesis circuit 177 electrically connected to the target selection circuit 173; That. Specific configurations of the operation selection circuit 172, target selection circuit 173, IO address decoder 174, memory address decoder 175, address circuit 176, and synthesis circuit 177 are the same as those in the first embodiment.

  The switch circuit 172a provided in the operation selection circuit 172 receives an initialization signal when the supply of operation power to the CPU 101 is started, so that a signal that triggers the output of the operation selection signal is output from the RD terminal. Of the RD signal and the WR signal from the WR terminal, the WR signal is set. Therefore, when the WR signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 172.

  The target selection circuit 173 outputs a target selection signal even when either the IREQ signal or the MREQ signal is output from the CPU core 102. The IO address decoder 174 outputs an IO address signal when 1-byte address data corresponding to the IO address decoder 174 is output from the CPU core 102. The memory address decoder 175 outputs a memory address signal when 2-byte address data corresponding to the memory address decoder 175 is output from the CPU core 102. The address circuit 176 outputs a composite address signal when either the IO address signal or the memory address signal is output. The synthesis circuit 177 outputs a chip select signal from the chip select terminal CS0 to the external output latch circuit 161 when all of the synthesized address signal, the operation selection signal, and the target selection signal are output. As a result, the data set in the data terminals D0 to D7 of the CPU core 102 is latched in the external output latch circuit 161, and is latched for each area of the output port 62b corresponding to the external output latch circuit 161. Data is output.

  The signal path L7 that electrically connects the output terminal of the synthesizing logic circuit 177a provided in the synthesizing circuit 177 and the chip select terminal CS0 is branched in the middle, and the branch path L8 is an internal output. The latch circuit 162 is electrically connected. Accordingly, when a chip select signal is output from the chip select terminal CS0 to the external output latch circuit 161, the chip select signal is also output to the internal output latch circuit 162. When the chip select signal is input to the internal output latch circuit 162, the same data as the data set in the data terminals D0 to D7 of the CPU core 102, that is, the data latched in the external output latch circuit 161 is obtained. Latch data.

  The internal output latch circuit 162 is electrically connected to the internal input latch circuit 163 through the data path L9. Therefore, the data latched in the internal output latch circuit 162 is supplied to the internal input latch circuit 163 through the data path L9.

  Similarly to the electrical configuration shown in FIG. 14 in the first embodiment, the input circuit 181 is electrically connected to the operation selection circuit 182 electrically connected to the RD terminal and the WR terminal, and to the IREQ terminal and the MREQ terminal. When the out instruction is executed in the CPU core 102, the IO address decoder 184 to which 1-byte address data is input when the out instruction is executed, and when the load instruction is executed in the CPU core 102 A memory address decoder 185 to which 2-byte address data is input; an address circuit 186 electrically connected to the IO address decoder 184 and the memory address decoder 185; an address circuit 186; an operation selection circuit 182; A synthesis circuit 187 electrically connected to the object selection circuit 183; That. Specific configurations of the operation selection circuit 182, the object selection circuit 183, the IO address decoder 184, the memory address decoder 185, the address circuit 186, and the synthesis circuit 187 are the same as those in the first embodiment.

  In FIG. 23, the CPU core 102 is shown as having two each of the address terminals A0 to A15, the RD terminal, the WR terminal, the IREQ terminal, and the MREQ terminal. Only one of each of these terminals is provided, and the signal from each terminal is supplied to each of the output circuit 171 and the input circuit 181 by branching the signal path extending from each terminal. Yes.

  The switch circuit 182a provided in the operation selection circuit 182 receives an initialization signal when the supply of operation power to the CPU 101 is started, so that a signal that triggers the output of the operation selection signal is output from the RD terminal. The RD signal and the WR signal from the WR terminal are set to be the RD signal. Therefore, the operation selection signal is output from the operation selection circuit 182 when the RD signal is output from the CPU core 102.

  The target selection circuit 183 outputs a target selection signal regardless of whether an IREQ signal or an MREQ signal is output from the CPU core 102. The IO address decoder 184 outputs an IO address signal when 1-byte address data corresponding to the IO address decoder 184 is output from the CPU core 102. The memory address decoder 185 outputs a memory address signal when 2-byte address data corresponding to the memory address decoder 185 is output from the CPU core 102. The address circuit 186 outputs a composite address signal when either the IO address signal or the memory address signal is output. When all of the synthesized address signal, the operation selection signal, and the target selection signal are output, the synthesis circuit 187 is configured to electrically connect the output terminal 187a of the synthesis circuit 187 and the internal input latch circuit 163 to each other. A chip select signal is output to the internal input latch circuit 163 through the signal path L10 provided therein. As a result, the data latched by the internal input latch circuit 163 is supplied to the data bus DB, and the supplied data is acquired by the CPU core 102. The acquired data is data that was previously output to the corresponding area of the output port 62b using the external output latch circuit 161.

  Here, the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 184 of the input circuit 181 triggers the output of the IO address signal from the IO address decoder 174 of the output circuit 171. It is the same as 1-byte address data. The 2-byte address data that triggers the output of the memory address signal from the memory address decoder 185 of the input circuit 181 is a trigger that outputs the memory address signal from the memory address decoder 175 of the output circuit 171 2. It is the same as the byte address data. As a result, the address data for outputting the chip select signal from the output circuit 171 to the external output latch circuit 161 and the internal output latch circuit 162 and the chip select signal from the input circuit 181 to the internal input latch circuit 163 are sent. It is possible to make the address data for output the same data. Therefore, the CPU core 102 can process the data already output to the output port 62b and output the processed data to the output port 62b by designating one address data.

  Even if the configuration is such that the output of the chip select signal to each of the output latch circuits 161 and 162 and the output of the chip select signal to the internal input latch circuit 163 by the designation of one address data, The chip select signal is output to the circuits 161 and 162 when the WR signal is output from the CPU core 102, and the chip select signal is output from the CPU core 102 to the internal input latch circuit 163. To be done. Therefore, the data output timing using the output latch circuits 161 and 162 can be different from the data input timing using the internal input latch circuit 163.

  According to the present embodiment described above in detail, the following excellent effects can be obtained in addition to the effects of the second embodiment.

  An internal input latch circuit 163 for supplying output data to the CPU core 102 again is built in the CPU 101. Thus, it is not necessary to provide the CPU 101 with a terminal for outputting a chip select signal for supplying data from the internal input latch circuit 163 to the data bus DB. Therefore, output data can be supplied to the CPU core 102 again while suppressing an increase in the number of terminals of the CPU 101.

<Common configuration in each embodiment>
A configuration for accessing the ROM 63 or the RAM 64 in each embodiment will be described. FIG. 24 is a block diagram showing an electrical configuration for outputting a chip select signal to a corresponding input latch circuit when data is read from the RAM 64. Note that, when an instruction or data is read from the ROM 63, the electrical configuration for outputting a chip select signal to the corresponding input latch circuit is the same as the electrical configuration shown in FIG. Further, when writing data to the RAM 64, the electrical configuration for outputting the chip select signal to the corresponding output latch circuit is that the signal that triggers the output of the operation selection signal from the operation selection circuit 191 is the RD signal. In other respects, the WR signal is the same as the electrical configuration shown in FIG.

  A circuit for outputting a chip select signal that triggers reading of data from the RAM 64 includes an operation selection circuit 191 electrically connected to the RD terminal and the WR terminal, and a target electrically connected to the IREQ terminal and the MREQ terminal. A selection circuit 192, an initialization circuit 193 for outputting an initialization signal to the operation selection circuit 191 and the object selection circuit 192, and 2-byte address data are input when a load instruction is executed in the CPU core 102. A memory address decoder 194, an operation selection circuit 191, a target selection circuit 192, and a synthesis circuit 195 electrically connected to the memory address decoder 194.

  The switch circuit 191 a provided in the operation selection circuit 191 receives an initialization signal when the supply of operation power to the CPU 101 is started, so that a signal that triggers the output of the operation selection signal is output from the RD terminal. The RD signal and the WR signal from the WR terminal are set to be the RD signal. Therefore, when the RD signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 191.

  The switch circuit 192a provided in the target selection circuit 192 receives an initialization signal when the supply of operating power to the CPU 101 is started, so that a signal that triggers the output of the target selection signal is output from the IREQ terminal. Of the IREQ signal and the MREQ signal from the MREQ terminal, the MREQ signal is set. Therefore, when the MREQ signal is output from the CPU core 102, the target selection signal is output from the target selection circuit 192.

  The memory address decoder 194 is a memory when the CPU core 102 outputs 2-byte address data corresponding to the memory address decoder 194, in other words, 2-byte address data corresponding to data read from the RAM 64. Output address signal. The synthesis circuit 195 outputs a chip select signal from the chip select terminal CS20 to the input latch circuit when all of the memory address signal, the operation selection signal, and the target selection signal are output. As a result, the data written in the area corresponding to the current address designation in the RAM 64 is supplied to the data bus DB, and the data is supplied to the CPU core 102 through the data terminals D0 to D7.

<Other embodiments>
In addition, it is not limited to the description content of embodiment mentioned above, A various deformation | transformation improvement is possible within the range which does not deviate from the meaning of this invention. For example, you may change as follows. Incidentally, the following configuration of another embodiment may be applied individually or in combination to the configuration of the above embodiment.

  (1) In the first embodiment, the IO address decoder 114 and the memory address decoder 115 are individually provided in the circuit corresponding to one chip select terminal CS0. Similarly to the address decoder 115, one address decoder provided with input terminals corresponding to the address terminals A0 to A15 on a one-to-one basis may be provided. In this case, when a predetermined 1-byte address data is output from the upper eight address terminals A0 to A7, the address decoder is output from the lower eight address terminals A8 to A15. The address signal (corresponding to the combined address signal in the first embodiment) is output to the combining circuit 117 regardless of the contents of the address data. Even with this configuration, the output of the RD signal from the CPU core 102, the output of either the IREQ signal or the MREQ signal from the CPU core 102, and the output of predetermined 2-byte address data from the CPU core 102 are performed. In this case, a chip select signal can be output from the chip select terminal CS0. Further, in the case of this configuration, it is possible to simplify the configuration compared to the first embodiment in that only one address decoder is provided. This configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, and may be applied to the second embodiment or the third embodiment.

  (2) In the configuration of (1) above, when accessing the IO space 105, predetermined one byte of address data is output from the upper eight address terminals A0 to A7 and the lower eight The control content of the CPU core 102 is set so that all “0” or all “1” data is output from the address terminals A8 to A15, and when accessing the memory space 106, it is set in the load instruction. The address data of 2 bytes may be output from the address terminals A0 to A15. In this case, even if predetermined one byte address data is output from the upper eight address terminals A0 to A7, one byte output from the lower eight address terminals A8 to A15. When the address data is specific data, the chip select signal is not output from the chip select terminal CS0. As a result, even if the high-order 1-byte address data is predetermined data, if the low-order 1-byte address data is specific data, a chip from a chip select terminal different from the chip select terminal CS0 is used. It can be used as an address that triggers the output of the select signal. This configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, and may be applied to the second embodiment or the third embodiment.

  (3) In the first embodiment, the IO address decoder 114 and the memory address decoder 115 are individually provided in the circuit corresponding to one chip select terminal CS0. Similarly to the address decoder 114, a configuration may be adopted in which one address decoder provided with input terminals corresponding to the address terminals A0 to A7 on a one-to-one basis is provided. In this case, when a predetermined 1-byte address data is inputted from the upper eight address terminals A0 to A7, the address decoder sends an address signal (the first implementation described above) to the synthesis circuit 117. (Corresponding to the combined address signal in the embodiment). Even with this configuration, the output of the RD signal from the CPU core 102, the output of either the IREQ signal or the MREQ signal from the CPU core 102, and the output of predetermined 2-byte address data from the CPU core 102 are performed. In this case, a chip select signal can be output from the chip select terminal CS0. Further, in the case of this configuration, it is possible to simplify the configuration compared to the first embodiment in that only one address decoder is provided. This configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, and may be applied to the second embodiment or the third embodiment.

  (4) In the first embodiment, when the target selection circuit 113 is not provided and the synthesized address signal is output from the address circuit 116 and the operation selection signal is output from the operation selection circuit 111, the synthesis is performed. The circuit 117 may be configured to output a chip select signal. In this case, the chip select signal can be output even when both the IREQ signal and the MREQ signal are not output from the CPU core 102. However, in order to output the chip select signal, the CPU core 102 can output the chip select signal. Either the RD signal or the WR signal must be output and the predetermined address data must be output. This configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, and may be applied to the second embodiment or the third embodiment.

  (5) In each of the embodiments described above, the chip select signal is output to the input latch circuit that inputs data from the input port 62a, and the output latch circuit that outputs data to the output port 62b. All of the circuits for outputting signals are not limited to the configuration for outputting the chip select signal regardless of whether the IREQ signal or the MREQ signal is output from the CPU core 102. Some of them may output a chip select signal when the CPU core 102 outputs an IREQ signal, but may not output a chip select signal when an MREQ signal is output. In this case, the target selection circuit of the part of the circuits is configured to output the target selection signal only when the IREQ signal is output. The part of the circuit includes an IO address decoder, but does not include a memory address decoder and an address circuit. In the configuration, the synthesis circuit mounted on a part of the circuits receives the IO address signal from the IO address decoder, the operation selection signal from the operation selection circuit, and the target selection signal from the target selection circuit. In this case, a chip select signal is output.

  (6) The internal output latch circuit 162 may not be provided in the third embodiment. In this case, the data transmission path from the external output latch circuit 161 to the output port 62b is branched and the branch path is electrically connected to the internal input latch circuit 163, so that the output from the external output latch circuit 161 is performed. Data set in the port 62b can be latched in the internal input latch circuit 163.

  (7) In the third embodiment, the internal input latch circuit 163 may be omitted, and the function of the internal input latch circuit 163 may be assigned to the RAM 64 or the CPU 101 instead. In this case, the configuration can be simplified as compared with the third embodiment in that it is not necessary to provide the internal input latch circuit 163.

  (8) Instead of the configuration in which the input port 62a of the MPU 62 is provided with more connection terminals than one byte, a configuration in which one byte of connection terminals is provided may be adopted. In this configuration, a plurality of input latch circuits are provided on the main control board 61, and a number of chip select terminals corresponding to the input latch circuits are provided on the MPU 62, which are to be output as chip select signals. Data may be input to the input port 62a from the input latch circuit, and the data input to the input port 62a may be supplied to the CPU 101.

  Further, instead of the configuration in which the output port 62b of the MPU 62 is provided with more connection terminals than one byte, a configuration in which one byte of connection terminals is provided may be adopted. In this configuration, a plurality of output latch circuits are provided on the main control board 61, and the number of chip select terminals corresponding to the output latch circuits on a one-to-one basis is provided on the MPU 62, and the chip select signal is to be output. Data may be output from the output port 62b to the output latch circuit.

  (9) Display control based on a command transmitted from the main control device 60 instead of a configuration in which the display control device 90 is controlled by the sound emission control device 80 based on a command transmitted from the main control device 60 The device 90 may be configured to control the sound emission control device 80. Further, instead of the configuration in which the sound emission control device 80 and the display control device 90 are separately provided, both the control devices may be provided as one control device, and one of the two control devices has a function. May be integrated into the main control device 60, and both functions of these two control devices may be integrated into the main control device 60. The configuration of the command transmitted from the main control device 60 to the sound emission control device 80 and the configuration of the command transmitted from the sound emission control device 80 to the display control device 90 are also arbitrary.

  (10) Other types of pachinko machines different from the above embodiments, for example, a pachinko machine in which an electric accessory is released a predetermined number of times when a game ball enters a specific area of a special device, or a game ball in a specific area of a special device The present invention can also be applied to a pachinko machine that generates a right if a player enters, a pachinko machine equipped with other objects, an arrangement ball machine, a sparrow ball, and other gaming machines.

  Also, a non-ball-type gaming machine, for example, a plurality of reels with a plurality of types of symbols attached in the circumferential direction, starts rotation of the reel by inserting a medal and operating a start lever, and a stop switch is operated. If a specific symbol or a combination of specific symbols is established on the active line visible from the display window after the reel has stopped after a predetermined time has passed, a privilege such as paying out medals is given to the player The present invention can also be applied to a slot machine.

  In addition, the gaming machine main body that is supported by the outer frame so as to be openable and closable is provided with a storage unit and a capture device, and the start lever is operated after a predetermined number of game balls stored in the storage unit are captured by the capture device. Thus, the present invention can also be applied to a gaming machine that starts the rotation of the reel and performs a game similar to a slot machine using a game ball as a game medium.

<Invention Group Extracted from Each Embodiment>
Hereinafter, the characteristics of the invention group extracted from each of the above-described embodiments will be described while showing effects and the like as necessary. In the following, for easy understanding, the corresponding configuration in each of the above embodiments is appropriately shown in parentheses, but is not limited to the specific configuration shown in parentheses.

<Feature A group>
Feature A1. Storage means (ROM 63) for storing instructions in advance;
Control execution means (CPU core 102) for executing the instruction read from the storage means;
In a gaming machine equipped with
The control execution means includes
First signal output means (MREQ terminal) for outputting a first instruction corresponding signal (MREQ signal) when executing the first instruction;
Second signal output means (IREQ terminal) for outputting a second command corresponding signal (IREQ signal) when executing a second command having a different amount of information from the first command;
With
The gaming machine is
At least in the case where the first command corresponding signal is output and the case where the second command corresponding signal is output, the specific output means (the first output signal) for outputting the specific signal (chip select signal) In the embodiment, the synthesis circuit 117, in the second embodiment, the synthesis circuit 137, in the third embodiment, the synthesis circuit 177),
When the specific signal is output, the operation means (in the first embodiment, the input latch circuit 103 or the output latch circuit 104, the first latch circuit 104) is in a specific operation state of at least one of information input and output. In the second embodiment, the output latch circuit 121a, and in the third embodiment, the external output latch circuit 161),
A gaming machine characterized by comprising:

  According to the feature A1, the first command output signal is output from the first signal output unit when the first command is executed, and the second command output signal is output from the second signal output unit when the second command is executed. Therefore, it is possible to prevent the predetermined operation from being executed in a situation where neither the first instruction nor the second instruction is executed, and the case where the first instruction is executed and the case where the first instruction is executed. It is possible to distinguish the operation target from the case where two instructions are executed.

  In this case, the specific signal output for setting the operating means to a specific operating state is output when either the first command corresponding signal or the second command corresponding signal is output from the control execution means. The As a result, the operating means can be brought into a specific operating state regardless of whether the first instruction or the second instruction is executed. Therefore, it is possible to widen the range of instruction types when the operation means is set to a specific operation state.

  The “first signal output unit” includes “first signal output unit” or “first signal output terminal”, and the “second signal output unit” includes “second signal output unit” or “second signal output unit”. Signal output terminal ”.

Feature A2. Predetermined output means for outputting a predetermined signal when the first instruction corresponding signal or the second instruction corresponding signal is output (the object selecting circuit 113 in the first embodiment, the object selecting circuit 133 in the second embodiment) In the third embodiment, an object selection circuit 173) is provided.
The gaming machine according to Feature A1, wherein the specific output means outputs the specific signal when the predetermined signal is output.

  According to the feature A2, in the configuration in which the specific signal is output from the specific output means on the condition that the predetermined signal is output from the predetermined output means, the predetermined output means is the first command corresponding signal or the second command Since the configuration is such that the predetermined signal is output when the corresponding signal is output, the above-described excellent effects can be achieved while diverting the configuration other than the predetermined output means as it is.

  Feature A3. The predetermined output means has input means electrically connected to the first signal output means and input means electrically connected to the second signal output means, and the first command corresponding signal and the second The gaming machine according to Feature A2, further comprising a logic circuit (target selection logic circuit 113a) that outputs the predetermined signal when any of the instruction corresponding signals is input.

  According to the feature A3, when the first command corresponding signal or the second command corresponding signal is output, the predetermined output means naturally outputs the predetermined signal, and therefore, the first command corresponding signal is output. There is no need to switch the state of the predetermined output means between when the second command corresponding signal is output. Therefore, it is possible to achieve the excellent effects as described above while simplifying the configuration of the predetermined output means.

  Feature A4. The gaming machine according to any one of features A1 to A3, wherein the first instruction is a load instruction, and the second instruction is either an in instruction or an out instruction.

  According to the feature A4, when the operation means is controlled to be in a specific operation state of at least one of information input and output, the load instruction is executed in addition to either the in instruction or the out instruction. Is possible.

Feature A5. The control execution means includes
Designation information output means (address terminals A0 to A15) for outputting designation information for designating an operation target;
When the operation unit is set to the specific operation state by executing the first instruction, first designation information is output from the designation information output unit, and the operation unit is executed by executing the second instruction. Designation information output means for outputting second designation information from the designation information output means in the case of a specific operating state (function for executing the processing of steps S305, S402, S408, S415 and S419 in the CPU core 102) )When,
With
The specific output means outputs the specific signal regardless of whether the first designation information is output or the second designation information is output. A1 to A4 The gaming machine according to any one of the above.

  According to the feature A5, in the configuration in which both the first instruction and the second instruction can be executed when the operation means is set to a specific operation state, the first designation information is output when the first instruction is executed. When the second instruction is executed, second designation information is output. Thereby, it is possible to output the designation information in a manner corresponding to each of the case where the first instruction is executed and the case where the second instruction is executed. In addition, when the first instruction is executed, the first designation information is output, and when the second instruction is executed, the first designation information is output even if the second designation information is output. Since the specific signal is output from the specific output means regardless of whether the second designation information is being output or the second designation information is being output, regardless of whether the first instruction or the second instruction is executed, The operating means can be brought into a specific operating state.

  The “designated information output means” includes “designated information output unit” or “designated information output terminal”.

  Feature A6. The gaming machine according to Feature A5, wherein the first designation information and the second designation information are different in information amount.

  According to the feature A6, when the first instruction is executed, the designation information is output with the amount of information corresponding to the first instruction, and when the second instruction is executed, the information corresponding to the second instruction is output. The specified information is output in quantity. In this case, the configuration of the feature A5 is provided, and the specific signal is output from the specific output means regardless of whether the first specification information is output or the second specification information is output. In any situation where either the first instruction or the second instruction is executed, the operating means can be brought into a specific operating state.

Feature A7. A designation corresponding means for outputting a designation corresponding signal when the first designation information or the second designation information is output (in the first embodiment, an IO address decoder 114, a memory address decoder 115, and an address circuit 116). In the second embodiment, an IO address decoder 134, a memory address decoder 135, and an address circuit 136, and in the third embodiment, an IO address decoder 174, a memory address decoder 175, and an address circuit 176) are provided.
The gaming machine according to A5 or A6, wherein the specific output means outputs the specific signal when the designation corresponding signal is output.

  According to the feature A7, the designation corresponding means outputs the designation corresponding signal when the first designation information or the second designation information is output, and at least one of the fact that the designation corresponding signal is output from the designation corresponding means. Since the specific signal is output from the specific output unit as a condition, it is not necessary to execute an operation corresponding to each of the first designation information and the second designation information in the specific output unit. Thereby, it is possible to achieve the excellent effects as described above while simplifying the configuration of the specific output means.

Feature A8. The designation corresponding means is
Means for outputting a first corresponding signal when the first designation information is output (memory address decoder 115 in the first embodiment, memory address decoder 135 in the second embodiment, third embodiment Then, the memory address decoder 175),
Means for outputting a second corresponding signal when the second designation information is output (IO address decoder 114 in the first embodiment, IO address decoder 134 in the second embodiment, third embodiment Then, the IO address decoder 174),
Means for outputting the specified corresponding signal when the first corresponding signal or the second corresponding signal is output (the address circuit 116 in the first embodiment, the address circuit 136 in the second embodiment, the second In the third embodiment, an address circuit 176),
The gaming machine according to Feature A7, comprising:

  According to the feature A8, a means for outputting a first corresponding signal in response to the first designation information being output, and a second correspondence signal corresponding to the second designation information being output in response thereto Are separately provided, it is possible to output signals corresponding to the first designation information and the second designation information with a relatively simple configuration. Further, since the designated corresponding signal is output when the first corresponding signal or the second corresponding signal is output, the types of signals output to the specific output unit can be suppressed.

  Note that one or more configurations of the features A1 to A8, the features B1 to B6, and the features C1 to C6 may be applied to the configurations of the features A1 to A8. Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

<Feature B group>
Feature B1. Control execution means (CPU core 102) for setting predetermined information to the output means (output port 62b);
Operation executing means for executing an operation corresponding to the predetermined information set in the output means (a special electric drive unit 32b, a general electric drive unit 34b, a special figure display unit 37a, a special figure hold display unit 37b, A figure display unit 38a, a general map hold display unit 38b, etc.),
Supply means for acquiring the predetermined information set in the output means from a transmission path through which the predetermined information is transmitted, and supplying the acquired predetermined information to the control execution means (in the second embodiment, an input latch) Circuits 122a to 122c, in the third embodiment, an internal output latch circuit 162 and an internal input latch circuit 163);
A gaming machine characterized by comprising:

  According to the characteristic B1, the predetermined information set in the output unit is supplied to the control execution unit via the transmission path. This makes it possible to read and use the predetermined information again in the control execution unit without separately storing the predetermined information set in the output unit or reading it again.

  Feature B2. The game according to Feature B1, wherein the supply means supplies the predetermined information to the control execution means when an input acquisition signal is input to the supply means based on the control of the control execution means. Machine.

  According to the feature B2, it is possible to supply the predetermined information from the supply unit to the control execution unit at a preferable timing in the control execution unit.

Feature B3. A first transmission path (data bus DB) that enables transmission of information to the control execution means and transmission of information from the control execution means;
Output setting means for setting the predetermined information acquired from the first transmission path in the output means (output latch circuits 121a to 121c in the second embodiment, external output latch circuit 161 in the third embodiment) When,
With
The supply means is electrically connected to a target path which is one of the first transmission path and the second transmission path (data paths L1 to L3) of information from the output setting means to the output means. The gaming machine according to B1 or B2, wherein the predetermined information acquired from the target route is supplied to the first transmission route so as to be supplied to the control execution unit.

  According to the characteristic B3, it is possible to supply the predetermined information to the control execution unit using a transmission path for setting the predetermined information in the output unit.

Feature B4. The output setting means sets the predetermined information acquired from the first transmission path to the output means when an output acquisition signal is input,
The supply means supplies the predetermined information to the first transmission path to supply the predetermined information to the control execution means when an input acquisition signal is input,
When predetermined designation information (address data) is output from the control execution means, first output corresponding means (the synthesis circuit 137 in the second embodiment) that outputs the output acquisition signal to the output setting means. In the third embodiment, the synthesis circuit 177),
Second output corresponding means for outputting the input acquisition signal to the supply means when the predetermined designation information is output from the control execution means (the synthesis circuit 147 in the second embodiment, the third embodiment) Then, the synthesis circuit 187),
A gaming machine according to Feature B3, characterized by comprising:

  According to the feature B4, the output setting unit sets predetermined information to the output unit when the output acquisition signal is input, and the supply unit sets the predetermined information when the input acquisition signal is input. Since it is supplied to the control execution means, it is possible to make the setting timing of the predetermined information to the output means and the supply timing of the predetermined information to the control execution means preferable. In this case, predetermined designation information output from the control execution means for causing the output setting means to output the output acquisition signal, and predetermined output from the control execution means for causing the supply means to output the input acquisition signal. The specified information is the same. This makes it possible to supply the control execution means with the predetermined information using the predetermined designation information used for setting the predetermined information in the output means.

Feature B5. The control execution means includes
First corresponding means (WR terminal) for outputting a first signal when the predetermined information is set by the output setting means;
Second response means (RD terminal) for outputting a second signal when the supply means supplies the predetermined information;
With
The first output corresponding means outputs the output acquisition signal to the output setting means when the first signal is output;
The gaming machine according to Feature B4, wherein the second output corresponding means outputs the input acquisition signal to the supply means when the second signal is output.

  According to the feature B5, the output acquisition signal is output when the first signal is output from the control execution unit, while the input acquisition signal is output when the second signal is output from the control execution unit. Is done. Thus, the predetermined designation information output from the control execution means for causing the output setting means to output the output acquisition signal, and the predetermined designation output from the control execution means for causing the supply means to output the input acquisition signal. Even when the information is the same, the timing at which the predetermined information is set by the output setting means can be different from the timing at which the predetermined information is supplied by the supplying means.

  The “first corresponding means” includes “first corresponding part” or “first corresponding terminal”, and the “second corresponding means” includes “second corresponding part” or “second corresponding terminal”. It is done.

Feature B6. The control execution means includes
Generating means for generating different information by executing predetermined processing on the predetermined information supplied by the supplying means (function for executing the process of step S514 in the CPU core 102);
Means for causing the different information generated by the generating means to be set for the output means (function for executing the processing of step S518 in the CPU core 102);
A gaming machine according to any one of features B1 to B5, characterized by comprising:

  According to the feature B6, the control execution unit can generate different information by processing the predetermined information already set in the output unit, and set the different information in the output unit.

  Note that one or more of the features A1 to A8, the features B1 to B6, and the features C1 to C6 may be applied to the features B1 to B6. Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

<Feature C group>
Feature C1. Control means (CPU 101) for inputting and outputting information using a predetermined transmission path (data bus DB);
When the selection signal (chip select signal) is output from the selection signal means (chip select terminal CS0) provided in the control means, the predetermined information acquired from the predetermined transmission path is output means (output port 62b). Output setting means (external output latch circuit 161) for setting to
Operation executing means for executing an operation corresponding to the predetermined information set in the output means (a special electric drive unit 32b, a general electric drive unit 34b, a special figure display unit 37a, a special figure hold display unit 37b, A figure display unit 38a, a general map hold display unit 38b, etc.),
In a gaming machine equipped with
The control means includes
Control execution means (CPU core 102) having information output means for enabling output of the predetermined information to the output means;
Supply means (internal output latch circuit 162 and internal input latch circuit 163) for acquiring the predetermined information output from the information output means and supplying the acquired predetermined information to the control execution means;
A gaming machine characterized by comprising:

  According to the feature C1, the predetermined information set in the output unit is supplied to the control execution unit. This makes it possible to read and use the predetermined information again in the control execution unit without separately storing the predetermined information set in the output unit or reading it again. Further, since the supply means is built in the control means, it is not necessary to prepare means for operating the supply means in the control means. Therefore, it is possible to read and use the predetermined information again in the control execution unit while suppressing an increase in the number of terminals of the control unit.

  The “selection signal means” includes “selection unit” or “selection terminal”.

  Feature C2. The game according to claim C1, wherein the supply means supplies the predetermined information to the control execution means when an input acquisition signal is input to the supply means based on the control of the control execution means. Machine.

  According to the feature C2, it is possible to supply predetermined information to the control execution unit from the supply unit at a preferable timing in the control execution unit.

Feature C3. The predetermined transmission path enables transmission of information to the control execution unit and transmission of information from the control execution unit,
The gaming machine according to claim C1 or C2, wherein the supply means supplies the predetermined information acquired from the predetermined transmission path to the predetermined transmission path so as to be supplied to the control execution means.

  According to the feature C3, it is possible to supply the predetermined information to the control execution unit using a predetermined transmission path for setting the predetermined information in the output unit.

Feature C4. The output setting means sets the predetermined information acquired from the predetermined transmission path to the output means when an output acquisition signal is input,
The supply means supplies the predetermined information to the predetermined transmission path to supply the predetermined information to the control execution means when an input acquisition signal is input,
First output corresponding means (combining circuit 177) for outputting the output acquisition signal to the output setting means when predetermined designation information (address data) is output from the control execution means;
Second output corresponding means (combining circuit 187) for outputting the input acquisition signal to the supply means when the predetermined designation information is outputted from the control execution means;
The gaming machine according to Feature C3, comprising:

  According to the feature C4, the output setting unit sets predetermined information to the output unit when the output acquisition signal is input, and the supply unit controls the execution unit when the input acquisition signal is input. Therefore, it is possible to make the setting timing of the predetermined information to the output means and the supply timing of the predetermined information to the control execution means preferable. In this case, predetermined designation information output from the control execution means for causing the output setting means to output the output acquisition signal, and predetermined output from the control execution means for causing the supply means to output the input acquisition signal. The specified information is the same. This makes it possible to supply the control execution means with the predetermined information using the predetermined designation information used for setting the predetermined information in the output means.

Feature C5. The control execution means includes
First corresponding means (WR terminal) for outputting a first signal when the predetermined information is set by the output setting means;
Second response means (RD terminal) for outputting a second signal when the supply means supplies the predetermined information;
With
The first output corresponding means outputs the output acquisition signal to the output setting means when the first signal is output;
The game machine according to C4, wherein the second output corresponding means outputs the input acquisition signal to the supply means when the second signal is output.

  According to the feature C5, the output acquisition signal is output when the first signal is output from the control execution unit, while the input acquisition signal is output when the second signal is output from the control execution unit. Is done. Thus, the predetermined designation information output from the control execution means for causing the output setting means to output the output acquisition signal, and the predetermined designation output from the control execution means for causing the supply means to output the input acquisition signal. Even when the information is the same, the timing at which the predetermined information is set by the output setting means can be different from the timing at which the predetermined information is supplied by the supplying means.

  The “first corresponding means” includes “first corresponding part” or “first corresponding terminal”, and the “second corresponding means” includes “second corresponding part” or “second corresponding terminal”. It is done.

Feature C6. The control execution means includes
Generating means for generating different information by executing predetermined processing on the predetermined information supplied by the supplying means (function for executing the process of step S514 in the CPU core 102);
Means for causing the different information generated by the generating means to be set for the output means (function for executing the processing of step S518 in the CPU core 102);
The gaming machine according to any one of features C1 to C5, comprising:

  According to the feature C6, the control execution unit can generate different information by processing the predetermined information already set in the output unit, and set the different information in the output unit.

  Note that one or more configurations of the features A1 to A8, the features B1 to B6, and the features C1 to C6 may be applied to the configurations of the features C1 to C6. Thereby, it becomes possible to produce a synergistic effect by the combined configuration.

  According to the invention relating to the feature A group, the feature B group, and the feature C group, it is possible to solve the following problems.

  As a kind of gaming machine, a pachinko gaming machine, a slot machine, and the like are known. These gaming machines include a control element such as a CPU, a read-only storage element such as a ROM, and a read / write storage element such as a RAM. The control element executes processing in accordance with a program read from the read-only storage element while writing information to the read / write storage element and reading information from the storage element. When this process is executed, information is input from the sensor or the like to the control element, and information is output from the control element to the electric actuator or the light emitting element. It is also known that a control element, a read-only memory element, a read / write memory element, and the like are integrated into one chip.

  Here, in the gaming machine such as the above-described example, a configuration capable of suitably performing control is required, and there is still room for improvement in this respect.

  The basic configuration of the gaming machine to which the above features can be applied or applied to each feature is shown below.

  Pachinko gaming machine: operation means operated by a player, game ball launching means for launching a game ball based on the operation of the operation means, a ball path for guiding the launched game ball to a predetermined game area, and a game A gaming machine that includes each gaming component arranged in an area, and gives a bonus to a player when a gaming ball passes through a predetermined passing portion of each gaming component.

  Revolving type gaming machine such as a slot machine: equipped with a picture display device for variably displaying a plurality of pictures, variably starting display of the plurality of pictures due to the operation of the start operation means, and due to the operation of the stop operation means In addition, the game machine is configured such that the variable display of the plurality of patterns is stopped when a predetermined time elapses and a privilege is given to the player according to the pattern after the stop.

  DESCRIPTION OF SYMBOLS 10 ... Pachinko machine, 32b ... Drive part for special electricity, 34b ... Drive part for ordinary electricity, 37a ... Special figure display part, 37b ... Special figure hold display part, 38a ... General figure display part, 38b ... General figure hold display , 62b ... output port, 63 ... ROM, 102 ... CPU core, 103 ... input latch circuit, 104 ... output latch circuit, 113 ... target selection circuit, 113a ... target selection logic circuit, 114 ... IO address decoder 115, memory address decoder, 116, address circuit, 117, synthesis circuit, 121a, output latch circuit, 122a to 122c, input latch circuit, 133, target selection circuit, 134, IO address decoder, 135,. Memory address decoder, 136... Address circuit, 137... Synthesis circuit, 147... Synthesis circuit, 161. DESCRIPTION OF SYMBOLS 2 ... Internal output latch circuit, 163 ... Internal input latch circuit, 173 ... Object selection circuit, 174 ... IO address decoder, 175 ... Memory address decoder, 176 ... Address circuit, 177 ... Synthesis circuit, 187 ... Synthesis Circuits A0 to A15... Address terminals, CS0... Chip select terminals, DB... Data bus, L1 to L3.

Claims (8)

Storage means for storing instructions in advance;
Control execution means for executing the instructions read from the storage means;
In a gaming machine equipped with
The control execution means includes
First signal output means for outputting a first instruction corresponding signal when executing the first instruction;
A second signal output means for outputting a second command corresponding signal when executing a second command having a different amount of information from the first command;
With
The gaming machine is
A specific output means for outputting a specific signal at least in the case where the first command corresponding signal is output and in the case where the second command corresponding signal is output;
When the specific signal is output, an operation means that is in a specific operation state that is at least one of information input and output; and
A gaming machine characterized by comprising: A predetermined output means for outputting a predetermined signal when the first instruction corresponding signal or the second instruction corresponding signal is output;
The gaming machine according to claim 1, wherein the specific output means outputs the specific signal when the predetermined signal is output.   The predetermined output means has input means electrically connected to the first signal output means and input means electrically connected to the second signal output means, and the first command corresponding signal and the second The gaming machine according to claim 2, further comprising a logic circuit that outputs the predetermined signal when any one of the instruction corresponding signals is input.   4. The gaming machine according to claim 1, wherein the first instruction is a load instruction, and the second instruction is either an in instruction or an out instruction. 5. The control execution means includes
A designation information output means for outputting designation information for designating an operation target;
When the operation unit is set to the specific operation state by executing the first instruction, first designation information is output from the designation information output unit, and the operation unit is executed by executing the second instruction. Designation information output means for outputting the second designation information from the designation information output means in the case of a specific operation state;
With
2. The specific output unit outputs the specific signal regardless of whether the first designation information is output or the second designation information is output. 4. The gaming machine according to any one of four.   The gaming machine according to claim 5, wherein the first designation information and the second designation information are different in information amount. A designation corresponding means for outputting a designation correspondence signal when the first designation information or the second designation information is output;
The gaming machine according to claim 5 or 6, wherein the specific output means outputs the specific signal when the designation corresponding signal is output. The designation corresponding means is
Means for outputting a first corresponding signal when the first designation information is output;
Means for outputting a second corresponding signal when the second designation information is output;
Means for outputting the designated corresponding signal when the first corresponding signal or the second corresponding signal is output;
The gaming machine according to claim 7, comprising:

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