JP6445286B2 - Phase detector, phase adjustment circuit, receiver and transmitter - Google Patents

Description

  The present invention relates to a phase detector, a phase adjustment circuit, a receiver, and a transmitter suitable for detecting the phase of a high-frequency signal.

  Currently, a radar system using a high frequency RF (Radio Frequency) signal is used for detecting the radar of an automobile or the altitude of an aircraft. In a radar system using a high-frequency RF signal, information related to the phase of the received RF signal is very important. In the present specification, information relating to the phase of the RF signal is also referred to as “phase information”. An example of utilizing RF phase information is, for example, a radar system using FMCW (Frequency Modulated Continuous Wave) modulation.

  FIG. 10 is a schematic diagram for explaining a radar system using FMCW modulation. The radar system illustrated in FIG. 10 includes a receiver 91 including a plurality of antennas 911. In the radar system shown in FIG. 10, a plurality of antennas 911 are arranged in one direction, and a transmitted RF signal is received by a receiver 91. When the RF signals are transmitted from positions separated by a sufficient distance, the phases of the RF signals received by the adjacent antennas 911 have a phase difference θ with respect to each other. The phase difference θ is determined by the distance d between the adjacent antennas 911 and the incident angle φ of the RF signal with respect to the antenna 911.

  FIG. 11 is a functional block diagram for explaining the inside of the receiver 91 shown in FIG. The receiver 91 includes one local signal generation source 101 and a plurality of mixer circuits 102. The local signal generated by the local signal generation source 101 is distributed to each mixer circuit 102. Each mixer circuit 102 amplifies the distributed local signal as necessary.

When the phase of the local signal supplied to each mixer circuit 102 is exactly the same, the IF (Intermediate Frequency) signal output from each mixer circuit 102 has the same phase difference as the phase difference θ of the received RF signal. θ. This is represented by the following equation (1).

In addition, in Formula (1), each symbol shows the following parameters.
ω ₁ : Angular frequency of the received RF signal ω ₂ : Angular frequency of the local signal generated by the local signal generation source θ: Phase information of the received RF signal (the phase of the received RF signal and reception by the adjacent antenna 911 Difference from the phase of the measured RF signal (phase difference))
In Expression (1), it is assumed that the right side shows only the component down-converted by frequency conversion, and other frequency components are removed by an LPF (Low-pass filter) or the like (not shown).

When there is a phase error θ _err between the local signals input to each mixer circuit 102, the relationship between the error θ _err and the IF signal shown in Equation (1) is expressed by Equation (2) below.

According to equation (2), it can be seen that the phase error of the local signal appears directly as the error of the IF signal. In such a radar system, the relative phase accuracy between the local signals input to each mixer circuit 102 is directly linked to the detection accuracy of the detected object.
The phase error of the local signal can be corrected together with the error caused by the antenna 911 and the wiring. In such a case, after creating the radar system, the operator measures the error θ _err of the phase difference θ between the RF signals received by the antennas 911 in the receiver 91. Then, the operator corrects the value of the phase difference θ by subtracting the error θ _err obtained by the measurement when calculating the incident angle φ.

However, the local signal supplied to each mixer circuit 102 has different phase temperature characteristics and phase power supply voltage characteristics due to mismatch between the amplifier circuits. For this reason, in order to perform phase detection with higher accuracy, the error θ _err must be measured in advance under a plurality of temperature conditions and a plurality of power supply voltage conditions. There was a drawback that it took time.

As a correction of the phase difference θ that does not require the error θ _err to be measured in advance, there is a method using a phase adjustment circuit. A phase adjustment circuit that corrects the phase difference θ is described in Patent Document 1, for example. The phase adjustment circuit receives a reference signal such as a clock signal, outputs an output signal, and detects a phase difference or a delay difference between the reference signal and the output signal by a phase detector. Further, the phase adjustment circuit uses the detected phase difference or delay difference to match the phase of the output signal with the phase of the reference signal.

  FIG. 12 is a diagram showing an example in which the phase adjustment circuit 110 is applied to the receiver 91 shown in FIG. The phase adjustment circuit 110 inputs a reference signal and a local signal. At this time, each phase adjustment circuit 110 outputs an output signal having the same phase. That is, in the receiver shown in FIG. 12, the phase of the local signal input to all of the plurality of mixer circuits 102 matches the phase of a single reference signal, and the local signals input to all the mixer circuits 102 are Correction can be made to the same phase. Therefore, for phase correction using the phase adjustment circuit 110, it is not necessary to measure phase errors under a plurality of temperature conditions and power supply voltage conditions in advance.

  FIG. 13 is a diagram illustrating a known phase adjustment circuit 110. The phase adjustment circuit 110 is configured as a delay locked loop circuit. The phase adjustment circuit 110 is a circuit that receives a reference signal and a local signal, adjusts the phase of the local signal, and outputs an output signal. The phase adjustment circuit 110 illustrated in FIG. 13 includes a phase shifter 111, a phase detector 113, and a charge pump 115. The phase shifter 111 receives a local signal and changes (shifts) the phase of the local signal. The local signal whose phase has changed is output from the phase adjustment circuit 110 as an output signal. The phase detector 113 detects the phase of the reference signal and the phase of the output signal, and outputs the phase difference between them to the charge pump 115. The charge pump 115 generates a voltage signal corresponding to the phase difference between the reference signal and the output signal, and outputs the voltage signal to the phase shifter 111. The phase shifter 111 determines the phase shift amount of the local signal according to the voltage signal, and changes the phase.

Special table 9-512966

However, in order to realize the phase adjustment circuit 110 described above, a phase detector is required as shown in FIG. Currently, examples of a phase detector that detects the phase of a signal include a frequency phase comparator, an Ex-OR circuit, and a mixer circuit.
FIG. 14 is a diagram illustrating the configuration of the phase detector 113 shown in FIG. The phase detector 113 includes two D flip-flops 131, a D flip-flop 132, an AND circuit 133, and a mixer circuit 135. A reference signal is input to the clock signal input terminal of the D flip-flop 131. Further, the output signal of the phase adjustment circuit shown in FIG. 13 is input to the clock signal input terminal of the D flip-flop 132.

A data signal is input to the D terminals of the D flip-flops 131 and 132.
The phase detector 113 inputs the reference signal and the output signal of the phase adjustment circuit, and inputs the value of the data signal latched based on the input reference signal and the output signal to the AND circuit 133. The AND circuit 133 outputs a reset signal to the D flip-flops 131 and 132 when the latched signals are both “1”, that is, when the phases of the reference signal and the output signal coincide with each other. 131 and 132 are reset. If the phase of the reference signal and the phase of the output signal do not match, the reference signal and the output signal are added by the adder 135 and output to the charge pump 115 shown in FIG.

In such a frequency phase comparator or Ex-OR circuit applied as the phase detector 113, when the frequency of the output signal is a high-frequency signal exceeding several GHz, the characteristics variation of the transistors used and the parasitic capacitance It is known that the phase detection accuracy decreases due to the influence.
Also, as shown in FIGS. 12 and 13, when frequency conversion is performed using a mixer circuit, a DC component corresponding to the phase difference between the reference signal and the local signal appears in the output signal of the receiver. At this time, in the actual circuit, there is a problem that a DC signal generated by a phenomenon called self-mixing peculiar to a high frequency signal is mixed into the output signal and the detection accuracy is deteriorated.

As described above, in order to accurately detect the phase of the RF high-frequency signal, it is necessary to match the phase of the local signal of the receiver with high accuracy.
The present invention has been made in view of the above points, and is a phase detector capable of detecting the phase of a high-frequency signal with high accuracy, a phase adjustment circuit using such a phase detector, and reception. An object is to provide a transmitter and a transmitter.

The above problem can be solved by the following means. That is, according to one aspect of the phase detector of the present invention, the first signal and the first control signal are input, the first control signal switches the polarity of the first signal, and the first signal is output as the second signal. The switch, the second signal, and the third signal are input, the adder that adds the second signal and the third signal and outputs the fourth signal, the fourth signal is input, and the fourth signal is input. A distortion circuit that outputs a nonlinear fifth signal including even-order and odd-order distortions , a fifth signal, and a second control signal synchronized with the first control signal are input to the second control signal. comprising a second switch for outputting the switched positive and negative polarity of the fifth signal as the sixth signal, and a circuit for removing a modulated signal included in the modulated signal or the sixth signal included in the fifth signal, the by, the 1 signal, that (the N 2 or more even number) N of the angular frequency of the third signal having a multiple of the angular frequency.

In the phase detector according to one aspect of the present invention, in the above aspect, the second switch may output a signal corresponding to the difference between the phase of the first signal and the phase of the third signal as the sixth signal. it can.
In the phase detector of one embodiment of the present invention, the frequency of the first signal can be N times (N is an integer of 2 or more) of the third signal.
The phase detector according to one aspect of the present invention can include at least one of a low-pass filter, a smoothing circuit, an averaging circuit, and an integrating circuit in the subsequent stage of the second switch in the above aspect.

In the phase detector of one embodiment of the present invention, a distributor can be provided between the first switch and the adder in the above embodiment.
In the phase detector according to one aspect of the present invention, in the above aspect, the distributor inputs the second signal from the first switch, outputs the seventh signal to the adder, and is relative to the seventh signal. It is possible to output the eighth signal in which a simple phase relationship is maintained.
In the phase detector of one embodiment of the present invention, in the above embodiment, a distributor can be provided before the first switch.

In the phase detector according to one aspect of the present invention, in the above aspect, the distributor inputs the first signal, outputs the ninth signal to the first switch, and has a relative phase relationship with the ninth signal. The tenth signal in which is maintained can be output.
The phase detector of one embodiment of the present invention can include a directional coupler in place of the adder in the above embodiment.
In the phase detector of one embodiment of the present invention, in the above embodiment, the directional coupler receives the second signal and the third signal, and the relative phase relationship with the fourth signal and the fourth signal is maintained. The eleventh signal can be output.

A phase adjustment circuit according to an aspect of the present invention includes a phase detector according to any one of the above aspects, an input signal, and a first signal by changing a phase of the input signal according to a sixth signal. And a phase shifter for generating.
The phase adjustment circuit of one embodiment of the present invention receives a zeroth signal, changes a phase of the zeroth signal and outputs the first signal, a first signal, and a first control signal. The first switch that switches the polarity of the first signal in accordance with the first control signal and outputs the second signal as the second signal, the second signal is input, and the second signal is converted into the first distribution signal and the second distribution signal. A first distributor for distributing and outputting, a first distribution signal and a third signal, an adder for adding the first distribution signal and the third signal and outputting as a fourth signal; A distortion circuit for inputting a signal and outputting a nonlinear fifth signal including even-order and odd-order distortions with respect to the fourth signal; a second control signal synchronized with the fifth signal and the first control signal; enter the door, a second switching outputs the second control signal by switching the positive and negative polarities of the fifth signal as a sixth signal And vessels, type a sixth signal, removes a control circuit for outputting a control signal for controlling the phase of the 0 signal in the phase shifter, the modulation signal included in the modulated signal or the sixth signal included in the fifth signal comprising a circuit, a first signal, (the N 2 or more even number) N of the angular frequency of the third signal may Rukoto to have a multiple of the angular frequency.

In the phase adjustment circuit of one embodiment of the present invention, in the above embodiment, the control circuit can include a charge pump circuit.
In the phase adjustment circuit of one embodiment of the present invention, in the above embodiment, the control circuit can include an AD converter, a processor, and a DA converter.
In the phase adjustment circuit of one embodiment of the present invention, the third signal can be a predetermined reference signal in the above embodiment.

In the phase adjustment circuit of one embodiment of the present invention, the 0th signal can be an input signal input to the phase adjustment circuit in the above embodiment.
In the phase adjustment circuit of one embodiment of the present invention, in the above embodiment, the input signal is input, the second distributor that distributes the input signal to the third distribution signal and the third signal, and the third distribution signal is input. And a frequency N multiplier that outputs a signal having a frequency N times (N is an integer equal to or greater than 2) the frequency of the third distribution signal to the phase shifter.

The phase adjustment circuit according to one aspect of the present invention, in the above aspect, includes a second distributor that inputs an input signal, distributes the input signal to a zeroth signal and a third signal that are input to the phase shifter, and a phase shifter. A frequency N multiplier that outputs a signal having a frequency N times (N is an even number equal to or greater than 2) as the first signal.
The phase adjustment circuit of one embodiment of the present invention can include a buffer provided between the phase shifter and the first switch in the above embodiment.
A receiver of one embodiment of the present invention includes the phase adjustment circuit of the above embodiment.
A transmitter according to one embodiment of the present invention includes the phase adjustment circuit according to the above embodiment.

  According to the above aspect, it is possible to provide a phase detector capable of detecting the phase of a high-frequency signal with high accuracy, a phase adjustment circuit using such a phase detector, a receiver, and a transmitter. .

It is a figure for demonstrating the phase detector of 1st Embodiment of this invention. It is a figure for demonstrating the phase detector of 2nd Embodiment of this invention. It is a figure for demonstrating the phase detector of 3rd Embodiment of this invention. It is a figure for demonstrating the phase adjustment circuit of 4th Embodiment of this invention. It is a figure for demonstrating the phase adjustment circuit of 5th Embodiment of this invention. It is a figure for demonstrating the phase adjustment circuit of 6th Embodiment of this invention. It is a figure for demonstrating the phase adjustment circuit of 7th Embodiment of this invention. It is a figure for demonstrating the receiver of 8th Embodiment of this invention. It is a figure for demonstrating the transmitter of 9th Embodiment of this invention. It is a schematic diagram for demonstrating the radar system using a well-known FMCW modulation. It is a functional block diagram for demonstrating the inside of the receiver shown in FIG. It is the figure which showed the example which applied the phase adjustment circuit to the receiver shown in FIG. It is a figure for demonstrating a well-known phase adjustment circuit. It is the figure which illustrated the composition of the phase detector.

Hereinafter, the first to sixth embodiments of the present invention will be described. Note that the phase detectors of the first to sixth embodiments are both circuits that receive the signal A and the signal B and detect the phase of the signal A on the basis of the phase of the signal B.
First embodiment [configuration]
FIGS. 1A and 1B are diagrams for explaining the phase detector 1 of the first embodiment. As shown in FIG. 1A, the phase detector 1 includes a polarity control circuit 3 that outputs a first polarity switching signal Sa and a second polarity switching signal Sb to the phase detector 1, and an output from the phase detector 1. It is used together with an LPF (Low-pass filter) 5 for filtering the processed signal.

FIG.1 (b) is a figure which shows the phase detector 1 shown to Fig.1 (a). The phase detector 1 includes a first polarity switch 11, an adder 13, a distortion circuit 15, and a second polarity switch 17.
The first polarity switch 11 receives the first polarity switching signal Sa together with the signal A. Then, the polarity of the signal A is switched between positive and negative by the first polarity switching signal Sa, and the signal after the polarity switching is output to the adder 13 as the signal Sc.

The adder 13 receives the signal Sc and the signal B. The angular frequency of the signal B has a value that is ½ of the angular frequency of the signal A. That is, when the angular frequency of the signal B is ω, the angular frequency of the signal A is expressed as 2ω. The adder 13 adds the signal Sc and the signal B. The signal after the addition is denoted as signal Sd. The signal Sd is output to the distortion circuit 15.
In the first embodiment, the angular frequency of the signal A is not limited to the angular frequency twice that of the signal B, and the angular frequency is N (N is an even number equal to or greater than 2). It only has to have it.
In the above, in the first embodiment, the frequency of the signal A and the signal B is indicated by an angular frequency. However, as a matter of course, when the angular frequency of the signal A has an angular frequency N times the angular frequency of the signal B, the frequency of the signal A is N times the frequency of the signal B.

The distortion circuit 15 is a circuit having nonlinear input / output characteristics. For this reason, the signal Sd input to the distortion circuit 15 is converted to a signal Se that is not represented by a linear function related to the signal Sd, that is, a signal Se that is nonlinear with respect to the signal Sd, and is output to the second polarity switch 17. In addition, the distortion circuit 15 of 1st Embodiment points out general circuits, such as an amplifier, a buffer, a diode, for example.
The second polarity switch 17 receives the polarity switching signal Sb together with the signal Se. Then, the polarity of the signal Se is switched by the second polarity switching signal Sb, and the signal after the polarity switching is output to the LPF 5 as a signal Sf. The LPF 5 smoothes the signal Sf, removes frequency components other than direct current (DC), and outputs it as a DC signal. At this time, the DC signal is a DC signal corresponding to the phase difference between the signal A and the signal B.

In the example shown in FIG. 1A, the LPF 5 is arranged at the subsequent stage of the phase detector 1, but the first embodiment is not limited to such a configuration. For example, the first embodiment may have a configuration in which the LPF 5 is provided before the second polarity switch 17 of the phase detector 1 shown in FIG. In addition, the configuration for smoothing the signal Sf is not limited to the LPF, and a smoothing circuit, an averaging circuit, an integrator, and the like that smooth the signal by digital calculation and remove frequency components other than DC are used. Also good.
Further, in the first embodiment, the phase detector 1 shown in FIG. 1B may also include the LPF 5 shown in FIG.

[principle]
Next, the principle that the phase detector 1 of the first embodiment can accurately detect the phase information of the detected signal will be described. In this description, first, the operation of the phase detector 1 when the first polarity switching signal Sa and the second polarity switching signal Sb are not input (when the first polarity switching device and the second polarity switching device are not provided) will be described.

信号Ａのθは、信号Ａと信号Ｂの位相の差に相当する。また、信号Ａの「Ａ」は信号Ａの最大振幅であり、信号Ｂの「Ｂ」は信号Ｂの最大振幅である。ωは信号Ａ、信号Ｂの角周波数であり、ｔは時間を示している。この場合、歪回路１５に入力される信号Ｓｄの値Ｐは、以下の式（３）によって表される。

Here, it is assumed that the signal A and the signal B are expressed as follows.

Θ of the signal A corresponds to a phase difference between the signal A and the signal B. Further, “A” of signal A is the maximum amplitude of signal A, and “B” of signal B is the maximum amplitude of signal B. ω is the angular frequency of signals A and B, and t indicates time. In this case, the value P of the signal Sd input to the distortion circuit 15 is expressed by the following equation (3).

The distortion circuit here refers to a circuit in which a harmonic component is generated. When the input / output characteristics of the distortion circuit 15 of the first embodiment are expressed by an expression having a third-order nonlinearity, it is expressed as the following expression (4).

When the term having the frequency component is removed from the output of the distortion circuit 15 by the LPF 5 illustrated in FIG. 1 or the averaging process, and only the DC component is left, the DC signal is expressed by the following equation (5). . According to Equation (5), it is clear that the DC signal depends on the phase difference θ between the signal A and the signal B. Further, a ₃ in equation (5) and a ₁ and a ₂ described later are constants determined by the design of the distortion circuit 15.

In the above formulas (4) and (5), the third-order distortion is exemplified as the input / output characteristics of the distortion circuit 15. However, the above relationship is an odd-order distortion circuit whose input / output characteristics are higher than the third order. The same applies to.
By the way, the nonlinearity of the input / output characteristics of the distortion circuit 15 may not only be the third-order or odd-order, but also the second-order nonlinearity as shown in Expression (6).

When the input / output characteristic of the distortion circuit 15 has second-order nonlinearity, the DC component through which the signal Se output from the distortion circuit 15 passes through the LPF 5 is expressed as the following Expression (7).

According to the equation (7), it can be seen that a DC component other than the DC component having phase information is generated by the secondary distortion. DC components other than the DC component having phase information are represented by the second and third terms on the right side of Equation (7). Although the second-order distortion is exemplified here, the same applies to the case of higher-order even-order distortion. The value of a ₂ in equation (7) is sufficiently smaller than the value of a _{3 due to} the use of a differential circuit or the like. Also, by increasing the value of A in equation (7), the value of the third term in equation (7) can be made sufficiently smaller than the first term.
However, the second term in Equation (7) includes A ^2, and the contribution of the value of A is larger than that of the first term. For this reason, increasing the value of A also increases the second term. In an actual circuit, if the value of A is increased in order to detect the component of the first term, an error occurs in the phase information to be detected by the unnecessary DC component shown in the second term.

In order to eliminate the above points, in the first embodiment, the first polarity switch 11 and the second polarity switch 17 shown in FIG. A signal obtained by switching the polarity of the signal A by the first polarity switching signal Sa is expressed by the following equation (8).

When the signal A is inverted as shown in the equation (8), the value P of the signal Sd that is added to the signal B in the adder 13 and output is as shown in the following equation (9).

When the value P of the signal Sd shown in Expression (9) is input to the distortion circuit 15 having the input / output characteristics of Expression (6), the output f (P) is expressed by the following Expression (10).

In f (P) shown in Expression (10), the polarity of the DC signal of only the first term of f (P) shown in Expression (7) is inverted. When this DC signal is input to the second polarity switch 17 and the polarity is inverted by the control of the second polarity switching signal Sb synchronized with the first polarity switching signal Sa, the output g (P) is expressed by the equation (11). ).

  When the equation (11) is compared with the signal f (P) shown in the equation (7) output from the phase detector without the first polarity switch 11 and the second polarity switch 17, the equation (11) The polarity of the first term of Eq. (7) is equal to the polarity of the first term of Eq. (7), and the polarities of the second and third terms of Eq. It has been reversed. Using this point, the first embodiment switches the polarities of the first polarity switching signal Sa and the second polarity switching signal Sa at an appropriate period T. By doing in this way, the phase detector of 1st Embodiment is represented by the following formula | equation (12), DC signal according to the relative phase difference (theta) of the signal A and the signal B, and Formula (13). The signal is divided into a modulated signal that switches between positive and negative in the time period T expressed.

式１３中のｈ（ｔ）は周期的矩形関数であり、以下の式（１４）によって表される。

H (t) in Expression 13 is a periodic rectangular function, and is expressed by Expression (14) below.

The component shown by Formula (12) is a signal which changes periodically. For this reason, the component shown by Formula (12) is separable from DC signal by LPF5, an averaging process, etc. For this reason, the first embodiment separates the DC signal corresponding to the relative phase difference θ between the signal A and the signal B expressed by Expression (12), and obtains only the signal expressed by Expression (12). it can. Such a 1st embodiment can detect phase information on a detected signal correctly.
Such a phase detector according to the first embodiment has an even-order even when there is a second-order or higher-order even order in the nonlinearity of the input / output characteristics of the distortion circuit 15 in a high-frequency signal such as an RF signal. The phase of the two signals A and B can be compared very accurately without being affected by the effect.

-2nd Embodiment Next, the phase detector of 2nd Embodiment of this invention is demonstrated.
FIGS. 2A and 2B are diagrams for explaining a phase detector according to the second embodiment. In FIG. 2, the same components as those shown in FIGS. 1A and 1B are denoted by the same reference numerals, and the description thereof is partially omitted.
The phase detector 21 according to the second embodiment shown in FIG. 2A is provided with a distributor 23 between the first polarity switch 11 and the adder 13 shown in FIG. . The distributor 23 distributes the signal input from the first polarity switch 11 into the signal Sh and the signal Sg. The distributor 23 can match the phases of the signal Sh and the signal Sg with high accuracy. The signal Sh is input to the adder 13. The signal Sg can be used as a local signal input to, for example, a mixer circuit of a receiver.

  The phase detector 21 is provided with a distributor 23 in the subsequent stage of the first polarity switch 11 so that the phase of the signal Sg that is actually input to the mixer circuit or the like and the phase of the signal Sh that is input to the adder 13. The relative relationship can be matched with high accuracy. For this reason, the phase detector 21 of the second embodiment can substantially detect the phase difference between the signal Sg (local signal) and the signal B.

  The relative phase relationship described above refers to the relationship between the phase of one signal and the phase of the other signal based on the phase of this signal in two signals. For example, the phase difference between two signals indicates the relative relationship between one signal and the other signal. In the present specification, hereinafter, such “relative phase” is also simply referred to as “phase”. Alternatively, “relative phase difference” is also simply referred to as “phase difference”.

Further, the phase detector of the second embodiment is not limited to the phase detector 21 shown in FIG. In the second embodiment, for example, like the phase detector 22 shown in FIG. 2B, the distributor 23 may be provided in the front stage of the first polarity switch 11. At this time, the distributor 23 receives the signal A, outputs the signal Sk to the first polarity switch 11, and outputs the signal Sl having a phase relationship with the signal Sk. At this time, the signal S1 of the phase detector 22 is also a local signal input to the mixer circuit, like the signal Sg.
According to the phase detector 21 and the phase detector 22 of the second embodiment described, the phase between the local signal actually input to the mixer circuit of the receiver and the desired reference signal (signal B shown in FIG. 2) is calculated. Since the comparison is possible, the phase of the local signal and the phase of the reference signal can be matched with high accuracy.

-3rd Embodiment Next, the phase detector of 3rd Embodiment of this invention is demonstrated.
FIG. 3 is a diagram for explaining the phase detector 31 of the third embodiment. Of the configurations shown in FIG. 3, the configurations shown in FIGS. 1 (a), (b), and FIG. 2 are given the same reference numerals as those in FIGS. 1 (a), (b), and FIG. Some explanations will be omitted.

  The phase detector 31 according to the third embodiment is provided with a directional coupler 33 instead of the adder 13 between the first polarity switch 11 and the distortion circuit 15 shown in FIG. is there. The directional coupler 33 receives the signal Sc from the first polarity switch 11 and also receives the signal B and outputs a signal Sg and a signal Sd. At this time, the directional coupler 33 can match the phase of the signal Sg actually input to the mixer circuit and the phase of the signal Sd output to the distortion circuit 15 with high accuracy.

  The directional coupler 33 is a 4-port circuit. In FIG. 3, among the four ports, p1 is connected to the port connected to the first polarity switch 11, p2 is connected to the port from which the signal Sg is output, p3 is connected to the port to which the signal B is input, and the distortion circuit 15 is connected. P4 is attached to the port. At this time, the signal Sc input from the port p1 is divided into a signal that passes through the port p2 (Through) and a signal that is output after being coupled with the port p4. The ratio between the intensity of the signal passing through the port p2 and the intensity of the signal coupled to the port p4 can be arbitrarily selected depending on the design of the directional coupler 33.

  Further, the port p3 and the port p1 are insulated from each other (Isolate relationship), and any signal input from the port p1 is ideally not output to the port p3. The signal B input to the port p3 is distributed to the port p2 and the port p4. With such a configuration, a signal Sd obtained by adding the signal input to the port p1 and the signal input to the port p3 is output from the port p4.

In such a third embodiment, the distributor 23 and the adder 13 of the second embodiment can be replaced with one directional coupler 33. Therefore, the third embodiment can realize the phase detector 31 having a simple configuration with a small number of parts while having the same function as the phase detector 21 of the second embodiment.
In the phase detector 31 of the third embodiment, a signal Sm obtained by adding the signals of the port p1 and the port p3 from the port p2 is output. However, in the third embodiment, since the frequency of the signal B input to the port p3 is ½ of the frequency of the signal Sc input to the port p1, the directional coupler 33 is designed to change from the port p3 to the port p2. The intensity of the output signal can be made sufficiently small.
According to the phase detector 31 of the third embodiment as described above, the functions of the distributor 23 and the adder 13 of the second embodiment described above can be realized more easily.

-4th Embodiment Next, the phase adjustment circuit of 4th Embodiment of this invention is demonstrated.
FIG. 4 is a diagram for explaining the phase adjustment circuit 41 of the fourth embodiment using the phase detector 21. 4, the configurations shown in FIGS. 1A, 1 </ b> B, 2, and 3 are the same as those shown in FIGS. 1A, 1 </ b> B, 2, and 3. A reference numeral is attached, and a part of the description is omitted.
A phase adjustment circuit 41 shown in FIG. 4 includes a phase detector 21 according to the second embodiment, a phase shifter 42 provided in the previous stage of the phase detector 21, and a charge pump 44 provided in the subsequent stage of the phase detector 21. And have. The output of the charge pump 44 is output to the phase shifter 42 and also to the integration filter 45.

The phase adjustment circuit 41 receives an input signal and adjusts the phase of the input signal by the phase shifter 42 to generate a signal Sj.
The signal Sj is input to the phase detector 21, and an output signal is output from the distributor 23 of the phase detector 21. The distributor 23 outputs a signal Sh. The signal Sh is input to the adder 13 in the phase detector 21, added to the reference signal, and output as the signal Sd to the distortion circuit 15 having nonlinear input / output characteristics. The distortion circuit 15 converts the signal Sd into a signal Se and outputs it. The signal Se is output as a signal Sf after the polarity is switched by the second polarity switching signal Sb by the second polarity switching signal Sb.

The signal Sf is output to the charge pump 44 and becomes a DC signal. The DC signal is integrated by the integration filter 45. The output of the integration filter 45 is input to the phase shifter 42 as the phase adjustment control signal Sk. In the phase adjustment circuit 41 of the fourth embodiment, the charge pump 44 and the integration filter 45 perform the function of the LPF 5 shown in FIG. In the fourth embodiment, an LPF can be added as necessary. In the fourth embodiment, the DC signal output from the phase detector 21 is 0, that is, the phase difference between the reference signal component and the DC signal component of the signal Sd input to the distortion circuit 15 is 0. Feedback is provided via the phase shifter 42. As a result, the fourth embodiment can realize the phase adjustment circuit 41 that outputs an output signal having a phase that matches the phase of the reference signal.
According to the phase adjustment circuit 41 of the fourth embodiment, it is possible to obtain an output signal whose phase matches with the reference signal with high accuracy.

Fifth Embodiment FIG. 5 is a diagram for explaining a phase adjustment circuit 51 according to a fifth embodiment. Of the configurations shown in FIG. 5, the configurations shown in FIGS. 1A, 1 </ b> B, 2, and 4 are the same as those in FIGS. 1A, 1 </ b> B, 2, and 4. A reference numeral is attached, and a part of the description is omitted.
The phase adjustment circuit 51 according to the fifth embodiment includes an ADC (analog / digital converter) 53, a processor 55, and a DAC (digital / analog conversion) instead of the charge pump 44 and the integration filter 45 of the phase adjustment circuit 41 shown in FIG. The delay lock loop is realized by providing 57).

The phase adjustment circuit 51 sequentially converts the signal Sh, which is a DC signal having phase information of the phase detector 21, through the adder 13, the distortion circuit 15, and the second polarity switch 17, and then converts the signal Sh into the ADC 53 as the signal Sf. Entered. The ADC 53 converts the signal Sf into a digital signal. The digital signal is input to the processor 55, processed as necessary to become a digital signal S1, and then converted into an analog signal Sm by the DAC 57. The analog signal Sm is input to the phase shifter 42 as a phase variation control signal.
Note that the phase adjustment circuit 51 may be provided with an LPF in the previous stage of the first polarity switch 11 or the subsequent stage of the ADC 53 as necessary. In the fifth embodiment, smoothing processing by the processor 55 may be performed instead of the LPF.

  Furthermore, the fifth embodiment is not limited to such a configuration. For example, in the phase adjustment circuit 51 shown in FIG. 5, the second polarity switch 17 is provided in the previous stage of the ADC 53, but the second polarity switch 17 may be in the subsequent stage of the ADC 53. In the fifth embodiment, the ADC 53 may be omitted, and the processor 55 may perform analog / digital conversion by calculation. In the phase adjustment circuit 51, the analog signal Sm output from the DAC 57 is used as the phase control signal of the phase shifter 42. However, when the phase shifter 42 is controlled by a digital signal, the digital signal S1 output from the processor 55 may be used as the phase control signal of the phase shifter 42.

Sixth Embodiment FIGS. 6A and 6B are diagrams for explaining a phase adjustment circuit according to a sixth embodiment. Of the configurations shown in FIGS. 6A and 6B, the configurations shown in FIGS. 1A and 1B, FIGS. 2, 4, and 5 are the same as those shown in FIGS. ), FIG. 4, FIG. 5 and FIG.
The phase adjustment circuit 61 shown in FIG. 6A is configured by providing a distributor 63 and a frequency doubler 65 in the preceding stage of the phase shifter 42 of the phase adjustment circuit 41 shown in FIG. The phase adjustment circuit 61 inputs the input signal to the distributor 63 and distributes it to the reference signal and the signal Sn.

  The reference signal is input to the adder 13 of the phase detector 21. On the other hand, the signal Sn is input to the frequency doubler 65 to become a signal So having a double frequency, and further input to the phase shifter 42. The signal So is frequency-adjusted by the phase shifter 42 to become a signal Sj, amplified by the amplifier 66, and then input to the first polarity switch 11 of the phase detector 21. Note that the sixth embodiment is not limited to the phase adjustment circuit 61 shown in FIG. For example, the frequency doubler 65 illustrated in FIG. 6A may be disposed in front of the phase shifter 42.

  FIG. 6B shows a phase adjustment circuit 62 in which a frequency doubler 65 is arranged in front of the phase shifter 42. The phase adjustment circuit 62 may be configured by exchanging the positions of the phase shifter 42 and the frequency doubler 65. According to such a configuration, the distributor 63 receives the input signal and distributes it to the reference signal and the signal Sn. The signal Sn is input to the phase shifter 42. The frequency doubler 65 provided at the subsequent stage of the phase shifter 42 receives a signal having a frequency N times the frequency of the signal output from the phase shifter 42 (N is an even number of 2 or more) via the amplifier 66 as a signal Sj. To the phase detector 21.

Seventh Embodiment FIG. 7 is a diagram for explaining a phase adjustment circuit 71 according to a seventh embodiment. Of the configurations shown in FIG. 7, the configurations shown in FIGS. 1A, 1 </ b> B, 2, 4, 5, and 6 are shown in FIGS. 1A, 1 </ b> B, and 2. 4, 5, and 6 are denoted by the same reference numerals, and the description thereof is partially omitted.
The phase adjustment circuit 71 shown in FIG. 7 is configured by providing a distributor 63 and a frequency doubler 65 in the previous stage of the phase shifter 42 of the phase adjustment circuit 51 shown in FIG. The phase adjustment circuit 71 inputs the input signal to the distributor 63 and distributes it to the reference signal and the signal Sn. The reference signal is input to the adder 13 of the phase detector 21. On the other hand, the signal Sn is input to the frequency doubler 65 to become a signal So having a double frequency, and further input to the phase shifter 42. The signal So is frequency-adjusted by the phase shifter 42 to become a signal Sj, amplified by the amplifier 66, and then input to the first polarity switch 11 of the phase detector 21.
The phase adjustment circuits of the fourth to seventh embodiments described above can adjust the phase of the input signal to match the phase of the reference signal.

-8th Embodiment Next, 8th Embodiment which concerns on the receiver of this invention is described.
FIG. 8 is a diagram for explaining a receiver 81 according to the eighth embodiment. The receiver 81 uses the phase adjustment circuit 61 of the sixth embodiment. Note that the eighth embodiment is not limited to the configuration using the phase adjustment circuit 61, and any of the phase adjustment circuits 61 and 51 and the phase adjustment circuit 71 may be used.

The receiver 81 includes a plurality of antennas 83 that receive RF signals, and a plurality of mixer circuits 85 that input a plurality of branched input signals and amplify them together with the received RF signals. Further, the receiver 81 includes the phase adjustment circuit 61 of the sixth embodiment. The phase adjustment circuit 61 receives an input signal, adjusts the phase, and outputs a local signal that is a DC signal. At this time, even if there is a phase error θ _err between the local signals, the phase adjustment circuit 61 removes the error θ _err and matches the phases of the branched local signals.

In FIG. 8, the input signal is a signal having half the frequency of the local signal input to the mixer circuit 85. In the receiver 81, an input signal is input to each phase adjustment circuit 61, and is input as a local signal to each mixer circuit 85 via the phase adjustment circuit 61. Each phase adjustment circuit 61 can easily match the phases of the input signals.
Further, the phase adjustment circuit shown in FIGS. 6 and 7 can make the phase of the local signal coincide with the input signal by the phase detector 21 even when there is a mismatch in the frequency doubler 65, the amplifier 66, or the like. . Therefore, the receiver 81 shown in FIG. 8 can match the phases of the local signals input to all the mixer circuits 85. For this reason, 8th Embodiment can provide the receiver 81 which can acquire phase information with high precision.
In the eighth embodiment, the example in which the phase adjustment circuit according to the fourth to seventh embodiments is applied to the receiver 81 has been described. However, the embodiment of the present invention is not limited to such an eighth embodiment, and can be applied to all configurations in which the phases of a plurality of high-frequency signals are to be matched, such as a plurality of transmitters.

Ninth Embodiment Next, a ninth embodiment according to the transmitter of the invention will be described.
FIG. 9 is a diagram for explaining a transmitter 91 according to the ninth embodiment. The transmitter 91 uses the phase adjustment circuit 61 of the sixth embodiment. Note that the ninth embodiment is not limited to the configuration using the phase adjustment circuit 61, and any of the phase adjustment circuits 61 and 51 and the phase adjustment circuit 71 may be used.

The transmitter 91 includes a plurality of antennas 83 that transmit RF signals, and a plurality of mixer circuits 85 that input a plurality of branched input signals and amplify them together with baseband signals from the inside. Furthermore, the transmitter 91 includes the phase adjustment circuit 61 of the sixth embodiment. The phase adjustment circuit 61 receives an input signal, adjusts the phase, and outputs a local signal. At this time, even if there is a phase error θ _err between the local signals, the phase adjustment circuit 61 removes the error θ _err and matches the phases of the branched local signals.

In FIG. 9, the input signal is a signal having half the frequency of the local signal input to the mixer circuit 85. In the transmitter 91, an input signal is input to each phase adjustment circuit 61 and is input as a local signal to each mixer circuit 85 via the phase adjustment circuit 61. Each phase adjustment circuit 61 can easily match the phases of the input signals.
Further, the phase adjustment circuit shown in FIGS. 6 and 7 can make the phase of the local signal coincide with the input signal by the phase detector 21 even when there is a mismatch in the frequency doubler 65, the amplifier 66, or the like. . Therefore, the transmitter 91 shown in FIG. 9 can match the phases of local signals input to all the mixer circuits 85. For this reason, 9th Embodiment can provide the transmitter 91 which can supply phase information with high precision.
In the ninth embodiment, the example in which the phase adjustment circuit according to the fourth to seventh embodiments is applied to the transmitter 91 has been described. However, the embodiment of the present invention is not limited to the ninth embodiment, and can be applied to all configurations in which the phases of a plurality of high-frequency signals are to be matched, for example.

  The present invention can be applied to any configuration as long as the circuit matches the phases of a plurality of high-frequency signals.

1, 2, 22, 22, 31 Phase detector 3 Polarity control circuit 5 LPF
DESCRIPTION OF SYMBOLS 11 1st polarity switch 13 Adder 15 Distortion circuit 17 2nd polarity switch 23 Divider 33 Directional coupler 41, 51, 61, 62, 71 Phase adjustment circuit 42 Phase shifter 44 Charge pump 45 Integration filter 53 ADC
55 Processor 57 DAC
63 Distributor 65 Frequency doubler 66 Amplifier 81, 91 Receiver 85, 95 Mixer circuit

Claims (21)

A first switch that inputs a first signal and a first control signal, switches the polarity of the first signal according to the first control signal, and outputs it as a second signal;
An adder that inputs the second signal and the third signal, adds the second signal and the third signal, and outputs the result as a fourth signal;
A distortion circuit that receives the fourth signal and outputs a nonlinear fifth signal including even-order and odd-order distortions with respect to the fourth signal;
Wherein the fifth signal, the first type control signal and a second control signal synchronized, the second switching output as a sixth signal by switching the positive and negative polarities of said fifth signal by said second control signal And
A circuit for removing the modulation signal included in the fifth signal or the modulation signal included in the sixth signal;
Equipped with a,
Wherein the first signal includes a phase detector that the (in N 2 or more even number) N of the angular frequency of the third signal having a multiple of the angular frequency.   The phase detector according to claim 1, wherein the second switch outputs a signal corresponding to a difference between a phase of the first signal and a phase of the third signal as the sixth signal.   3. The phase detector according to claim 1, wherein the frequency of the first signal is a frequency N times that of the third signal (N is an integer of 2 or more).   The phase detector according to any one of claims 1 to 3, further comprising at least one of a low-pass filter, a smoothing circuit, an averaging circuit, and an integrating circuit at a subsequent stage of the second switch.   The phase detector according to any one of claims 1 to 4, wherein a distributor is provided between the first switch and the adder.   The distributor inputs the second signal from the first switch, outputs a seventh signal to the adder, and outputs an eighth signal having a relative phase relationship with the seventh signal. The phase detector according to claim 5.   The phase detector according to any one of claims 1 to 4, wherein a distributor is provided in front of the first switch.   The distributor receives the first signal, outputs a ninth signal to the first switch, and outputs a tenth signal having a relative phase relationship with the ninth signal. The phase detector according to 1.   5. The phase detector according to claim 1, further comprising a directional coupler instead of the adder.   10. The directional coupler according to claim 9, wherein the directional coupler receives the second signal and the third signal and outputs an eleventh signal having a relative phase relationship with the fourth signal and the fourth signal. Phase detector. The phase detector according to any one of claims 5 to 10,
A phase adjustment circuit comprising: a phase shifter that receives the 0th signal and generates the first signal by changing the phase of the 0th signal according to the sixth signal. A phase shifter for inputting a zeroth signal, changing the phase of the zeroth signal and outputting the first signal as a first signal;
A first switch that inputs the first signal and the first control signal, switches the polarity of the first signal according to the first control signal, and outputs the first signal as a second signal;
A first distributor that inputs the second signal, distributes the second signal into a first distribution signal and a second distribution signal, and outputs the second distribution signal;
An adder that inputs the first distribution signal and the third signal, adds the first distribution signal and the third signal, and outputs the result as a fourth signal;
A distortion circuit that receives the fourth signal and outputs a nonlinear fifth signal including even-order and odd-order distortions with respect to the fourth signal;
Wherein the fifth signal, the first type control signal and a second control signal synchronized, the second switching output as a sixth signal by switching the positive and negative polarities of said fifth signal by said second control signal And
A control circuit for inputting the sixth signal and outputting a control signal for controlling the phase of the zeroth signal to the phase shifter;
A circuit for removing the modulation signal included in the fifth signal or the modulation signal included in the sixth signal;
Equipped with a,
Said first signal, said N of the angular frequency of the third signal (N is an even number of at least two) phase adjustment circuit that have a multiple of the angular frequency.   The phase adjustment circuit according to claim 12, wherein the control circuit includes a charge pump circuit.   The phase adjustment circuit according to claim 12, wherein the control circuit includes an AD converter, a processor, and a DA converter.   The phase adjustment circuit according to claim 12, wherein the third signal is a predetermined reference signal.   The phase adjustment circuit according to claim 12, wherein the zeroth signal is an input signal input to the phase adjustment circuit. A second distributor for inputting an input signal, distributing the third distribution signal to the third signal, and outputting the third distribution signal;
A frequency N multiplier that inputs the third distribution signal and outputs a signal having a frequency N times the frequency of the third distribution signal (N is an even number equal to or greater than 2) to the phase shifter as the zeroth signal;
The phase adjustment circuit according to claim 12, further comprising: A second distributor that inputs an input signal and distributes and outputs the zeroth signal and the third signal that are input to the phase shifter; and N times the frequency of the output of the phase shifter (N is 2 or more) A frequency N multiplier that outputs a signal having a frequency of (even number) as the first signal;
The phase adjustment circuit according to claim 12, further comprising:   The phase adjustment circuit according to claim 12, further comprising a buffer provided between the phase shifter and the first switch.   A receiver comprising the phase adjustment circuit according to any one of claims 11 to 18.   A transmitter comprising the phase adjustment circuit according to any one of claims 11 to 18.

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