JP6447231B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device using a nitride semiconductor such as gallium nitride (hereinafter referred to as GaN) or aluminum gallium nitride (hereinafter referred to as AlGaN), and a method for manufacturing the same.

Conventionally, a normally-off type MOS device has been proposed as a lateral switching device having a heterojunction structure in GaN. In this MOS device, an AlGaN layer is disposed on an undoped GaN (hereinafter referred to as u-GaN) layer that is not doped with impurities, and a gate insulating film or a gate is formed in a recess portion that reaches the u-GaN layer from the surface of the AlGaN layer. It is set as the structure provided with the electrode. The recess is formed by placing a resist on the surface of the AlGaN layer and then etching using this as a mask. However, the nitride semiconductor is scientifically stable and cannot be etched by wet etching. It is formed by etching. For example, the recess etching is performed by dry etching using a Cl ₂ gas (BCl ₃ , Cl ₂ , SiCl _4, etc.).

  However, when the recess etching is performed, physical damage is caused at the bottom of the recess, and the threshold voltage (Vt) of the MOS device is negatively shifted. Due to this, it becomes impossible to create a device with the threshold voltage as designed, and there arises a problem that the variation in threshold voltage is increased due to the in-plane variation of damage caused by dry etching.

  In order to deal with such a problem, a technique for removing damage by performing heat treatment after recess etching or performing epitaxial growth again after forming a recess portion as disclosed in Patent Document 1 has been proposed. . Thereby, it is possible to suppress a minus shift of the threshold voltage.

JP 2014-011462 A

  However, even if the heat treatment is performed after the recess etching, the damage cannot be completely removed. Even if the epitaxial growth is performed again, the damage is inherited because the epitaxial growth is performed on the damaged base. For this reason, suppression of the minus shift of the threshold voltage is insufficient. In a wide band gap semiconductor such as GaN, a technique for eliminating countless defects and trap levels formed in the band gap and a technique for returning to an epitaxial layer without damage before etching have not been established yet.

  In view of the above points, an object of the present invention is to provide a structure capable of suppressing a negative shift of a threshold voltage in a semiconductor device using a nitride semiconductor having a normally-off MOS device, and a manufacturing method thereof. And

In order to achieve the above object, in the first or second aspect of the present invention, the first nitride semiconductor layer (3, 30, 31) constituting the electron transit layer and the first nitride semiconductor layer are formed on the first nitride semiconductor layer. are stacked, the band gap energy than the first nitride semiconductor layer constitute a large electron supply portion, the recessed portion with a surface of the first nitride semiconductor layer by being arranged plurality spaced (5) The second nitride semiconductor layer (4, 4a, 4b) constituting the gate electrode, the gate insulating film (6) formed in the recess portion, and the gate electrode (7) formed on the gate insulating film And a source electrode (8) and a drain electrode (9) disposed on both sides of the gate structure portion on the second nitride semiconductor layer, the first nitride The first at the interface between the semiconductor layer and the second nitride semiconductor layer A channel is formed in the surface portion of the first nitride semiconductor layer at the bottom of the recess portion when a two-dimensional electron gas carrier is induced on the nitride semiconductor layer side and a voltage is applied to the gate electrode. Thus, in the lateral switching device in which a current flows between the source electrode and the drain electrode, the second nitride semiconductor layer is formed by the selective epitaxial growth portions formed on both sides of the recess portion while being not formed in the recess portion. The portion of the first nitride semiconductor layer where the second nitride semiconductor layer is stacked and the portion located at the bottom of the recess portion are coplanar, and the first nitride semiconductor layer An AlN layer (20) is formed between the physical semiconductor layer and the second nitride semiconductor layer, and the AlN layer is not formed in the recessed portion, and both sides of the recessed portion are formed. Ri formed selective epitaxial growth unit der, the first nitride semiconductor layer, a first undoped layer in which no impurity is doped (3) and, p-type layer stacked on the first undoped layer (30 ) .

  As described above, the second nitride semiconductor layer on the first nitride semiconductor layer is formed by selective epitaxial growth, and the recess is formed without using dry etching. For this reason, damage due to dry etching can be prevented from being formed on the surface of the first nitride semiconductor layer at the bottom of the recess where the gate structure is formed, and a negative shift of the threshold voltage (Vt) occurs. Can be suppressed.

Specifically, as in the invention described in claim 3 , after the mask (10) is arranged at the position where the recess portion is to be formed on the first nitride semiconductor layer, the first nitride semiconductor is covered with the mask. A step of selectively epitaxially growing the second nitride semiconductor layer on both sides of the recess portion while covering the surface of the layer; a step of forming a gate electrode in the recess portion through a gate insulating film after removing the mask; And selectively epitaxially growing the AlN layer (20) on both sides of the recess portion in a state where the surface of the first nitride semiconductor layer is covered with a mask before the step of selectively epitaxially growing the second nitride semiconductor layer. The manufacturing method containing can be applied.

  With such a manufacturing method, the semiconductor device according to the invention described in claim 1 can be manufactured.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

1 is a cross-sectional view of a semiconductor device having a 2DEG region according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 1. It is sectional drawing of the semiconductor device which has 2DEG area | region concerning 2nd Embodiment of this invention. 6 is a chart showing sheet resistance, sheet carrier concentration, and electron mobility in each of a sample A provided with an AlN layer 20 and a sample B not provided. It is the figure which showed the change of the electron concentration [cm ^<-3 >] in the depth direction (thickness direction) in each of the sample A provided with the AlN layer 20, and the sample B which is not provided. It is sectional drawing of the semiconductor device which has 2DEG area | region concerning 3rd Embodiment of this invention. It is sectional drawing of the semiconductor device which has 2DEG area | region concerning 4th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A semiconductor device according to the present embodiment will be described with reference to FIG. As shown in FIG. 1, the semiconductor device according to the present embodiment has a 2DEG region as a normally-off MOS device.

  The 2DEG region of the present embodiment is formed using a structure in which the u-GaN layer 3 is stacked on the surface of the substrate 1 with the buffer layer 2 interposed therebetween as a compound semiconductor substrate. On the surface of the u-GaN layer 3, the AlGaN layer 4 is formed at two positions apart from each other, and the u-GaN layer 3 and the AlGaN layer 4 constitute a heterojunction structure. In the 2DEG region, these u-GaN layer 3 and AlGaN layer 4 are used as channel forming layers, and two-dimensional electron gas (2DEG) carriers are induced on the u-GaN layer 3 side of the AlGaN / GaN interface by the piezoelectric effect and the spontaneous polarization effect. It works by being.

  The substrate 1 is made of a semi-insulating material such as Si (111), SiC or sapphire, or a semiconductor material, and a buffer layer serving as a base film for forming the u-GaN layer 3 with good crystallinity thereon. 2 is formed. The buffer layer 2 is composed of, for example, an AlGaN-GaN superlattice layer. If the u-GaN layer 3 can be formed on the substrate 1 with good crystallinity, the buffer layer 2 may be omitted. Here, the crystallinity means defects or dislocations in the u-GaN layer 3 and has an influence on electrical and optical characteristics.

  A u-GaN layer 3 and an AlGaN layer 4 are formed on the buffer layer 2 by, for example, heteroepitaxial growth.

  The u-GaN layer 3 constitutes an electron transit layer formed of a first nitride semiconductor material that is a wide bandgap semiconductor, and corresponds to the first nitride semiconductor layer. In this embodiment, the u-GaN layer 3 is an undoped GaN layer that is not doped with impurities. The term “undoped” as used herein does not mean that there is no impurity at all, but means that the concentration is not such that the impurity is intentionally doped for carrier generation. For example, even when impurity atoms present in the atmosphere when forming the u-GaN layer 3 enter, it can be said to be undoped.

  The AlGaN layer 4 constitutes an electron supply portion formed of a second nitride semiconductor material having a band gap energy larger than that of the first nitride semiconductor material, and corresponds to a second nitride semiconductor layer. Is. In the case of this embodiment, the AlGaN layer 4 is configured to have a first AlGaN layer 4a and a second AlGaN layer 4b. The first AlGaN layer 4a and the second AlGaN layer 4b are arranged with a predetermined distance therebetween, and a recess portion (concave portion) 5 is formed between them. As will be described later, the AlGaN layer 4 is formed by selective epitaxial growth, and a recess portion 5 is formed between the first AlGaN layer 4a and the second AlGaN layer 4b, but is not formed by recess etching. For this reason, no damage is formed on the surface of the u-GaN layer 3 located between the first AlGaN layer 4a and the second AlGaN layer 4b. And the part in which the 1st AlGaN layer 4a and the 2nd AlGaN layer 4b were laminated | stacked among the surfaces of the u-GaN layer 3 and the part located between these (bottom part of the recess part 5) are made into the same plane. .

  A gate structure 7 is configured by embedding a gate electrode 7 with a gate insulating film 6 interposed between the first AlGaN layer 4 a and the second AlGaN layer 4 b as a recess 5. Specifically, a gate insulating film 6 having a predetermined film thickness is formed on the inner wall surface of the recess portion 5, and a gate electrode 7 is further formed on the gate insulating film 6 to constitute a gate structure portion. Has been.

The gate insulating film 6 is composed of a silicon oxide film (SiO ₂ ), an aluminum oxide film (Al ₂ O ₃ ) or the like, and the gate electrode 7 is a poly-semiconductor doped with a metal such as aluminum or platinum or an impurity. Etc. The gate insulating film 6 and the gate electrode 7 are formed in the recess portion 5 to constitute a MOS structure.

  A source electrode 8 is formed on the surface of the first AlGaN layer 4a disposed on one side of the gate structure, and a drain electrode 9 is formed on the surface of the second AlGaN layer 4b disposed on the other side. The source electrode 8 is in ohmic contact with the first AlGaN layer 4a, and the drain electrode 9 is in ohmic contact with the second AlGaN layer 4b. With this configuration, the 2DEG area according to the present embodiment is configured.

  Although not shown, a gate wiring layer, a source wiring layer, and a drain wiring layer made of Al or the like are formed on the surfaces of the gate electrode 7, the source electrode 8, and the drain electrode 9, respectively. These are electrically separated through an interlayer insulating film, and an arbitrary voltage can be applied to each electrode. Although a cross section of one cell of MOS is shown here, a plurality of MOSs are actually arranged. That is, a plurality of AlGaN layers 4 are arranged as a set, and a plurality of recesses 5 are arranged so as to form a recess portion 5 between them, and each recess portion 5 includes a gate insulating film 6 and a gate electrode. 7 is provided.

  The dimensions of each part of the MOS device configured as described above are arbitrary. For example, the distance between the source and gate and the gate and drain may be determined in view of the on-resistance and breakdown voltage of the target device.

  In such a configuration, the ohmic regions 3a and 3b are disposed below the source electrode 8 and the drain electrode 9 in the surface portion of the u-GaN layer 3, and the access region 3c and the drain electrode 9 are disposed below the AlGaN layer 4a on the source electrode 8 side. 2DEG carriers are generated using the drift region 3d below the side AlGaN layer 4b. Then, the switching operation is performed by forming the channel region 3e based on the application of the gate voltage to the gate electrode 8. That is, by applying a gate voltage to the gate electrode 8, the density of the electron layer (channel) generated at the interface between the GaN layer 3 and the gate insulating film 7 below the gate electrode 8 is controlled, and between the source and drain By applying a voltage to, current is passed between the source and drain.

  Further, since no damage due to dry etching is formed on the surface of the u-GaN layer 3 at the bottom of the recess 4 where the gate structure is formed, it is possible to suppress a negative shift of the threshold voltage (Vt). it can. In addition, it is possible to create a device with the threshold voltage as designed, and it is possible to prevent an increase in variation in threshold voltage due to in-plane variation in damage due to dry etching. As a result, a MOS device having stable characteristics can be obtained.

  Next, a MOS device manufacturing method according to the present embodiment will be described with reference to FIG.

[Step shown in FIG. 2 (a)]
A compound semiconductor substrate having a structure in which a buffer layer 2 and a u-GaN layer 3 are laminated on the surface of a substrate 1 such as Si (111), SiC, and sapphire is prepared. For example, after forming the buffer layer 2 on the surface of the substrate 1, the u-GaN layer 3 is epitaxially grown thereon.

[Step shown in FIG. 2 (b)]
After a silicon oxide film (SiO ₂ ) 10 is formed on the surface of the u-GaN layer 3 as a mask material used during selective epitaxial growth, patterning is performed to leave the silicon oxide film 10 only at the position where the recess portion 4 is to be formed. Then, using an epitaxial growth apparatus, the AlGaN layer 4 is selectively epitaxially grown on the surface of the u-GaN layer 3 with the silicon oxide film 10 masking the formation position of the recess 4. As a result, the AlGaN layer 4 is selectively grown on the surface of the u-GaN layer 3 not covered with the silicon oxide film 10. For example, epitaxial growth is performed by setting the epitaxial growth temperature to 800 to 1200 ° C. and introducing an NH raw material such as trimethyl gallium or triethyl gallium or an Al raw material such as trimethyl aluminum or triethyl aluminum in an NH ₃ atmosphere.

  Although the silicon oxide film 10 is used here as a mask, other materials may be used as long as they are mask materials that do not react with the atmospheric gas during selective epitaxial growth.

[Step shown in FIG. 2 (c)]
The silicon oxide film 10 used when the AlGaN layer 4 is selectively epitaxially grown is removed. Thereby, the recess part 4 is comprised. At this time, the u-GaN layer 3 exposed at the bottom of the recess 4 is a good one in which damage due to dry etching is not introduced because the recess 4 is not formed by dry etching. .

[Step shown in FIG. 2 (d)]
A step of forming the gate insulating film 6 is performed. For example, the gate insulating film 6 is formed by forming an aluminum oxide film or the like by atomic layer deposition (ALD) or sputtering. Then, a metal material such as polysilicon doped with impurities or Al is sequentially formed on the surface of the gate insulating film 6 including the inside of the recess-shaped portion 3a, and then patterned using a mask (not shown). Thereby, the gate electrode 7 is formed. At this time, if the gate electrode 7 is formed of polysilicon doped with impurities by CVD (chemical vapor deposition) or the like, the gate electrode 7 can be formed at a low temperature without undergoing activation annealing. Thereby, the gate insulating film 6 and the gate electrode 7 are formed.

  The subsequent steps are the same as in the prior art, but the semiconductor device having the MOS device shown in FIG. 1 is obtained through an interlayer insulating film forming step, a contact hole forming step, a source electrode 8 and a drain electrode 9 forming step, and the like. Complete.

  As described above, in this embodiment, the AlGaN layer 4 on the GaN layer 3 is formed by selective epitaxial growth, and the recess 4 is formed without using dry etching. For this reason, it is possible to prevent damage caused by dry etching on the surface of the u-GaN layer 3 at the bottom of the recess 4 where the gate structure is formed, and to suppress a negative shift of the threshold voltage (Vt). it can. In addition, it is possible to create a device with the threshold voltage as designed, and it is possible to prevent an increase in variation in threshold voltage due to in-plane variation in damage due to dry etching. As a result, a MOS device having stable characteristics can be obtained.

(Second Embodiment)
A second embodiment of the present invention will be described. The present embodiment is intended to obtain a better heterointerface with respect to the first embodiment, and the other aspects are the same as those of the first embodiment. Therefore, only differences from the first embodiment will be described. To do.

  As shown in FIG. 3, in this embodiment, an AlN layer 20 is provided between the u-GaN layer 3 and the AlGaN layer 4. The AlN layer 20 is set to have a thickness equal to or larger than the thickness formed without voids on the surface of the u-GaN layer 3 and to a thickness equal to or less than the thickness at which the crystallinity of the AlN layer 20 deteriorates. For example, by setting the thickness of the AlN layer 20 to 1 to 2 nm, the AlN layer 20 having no voids and good crystallinity can be obtained.

  Thus, by providing the AlN layer 20, it is possible to obtain a heterointerface in which the electron concentration can be changed sharply as compared with the case where the AlGaN layer 4 is directly formed on the u-GaN layer 3. . Therefore, the electron mobility of 2DEG is improved and 2DEG characteristics can be improved.

Specifically, the sample A provided with the AlN layer 20 and the sample B not provided are prepared, and for each of the samples A and B, the sheet resistance [Ω / □] at the surface layer part of the u-GaN layer 3, the sheet carrier The concentration [cm ⁻² ] and the electron mobility [cm ² / V · s] were examined. For each sample A and B, a Schottky electrode having a diameter of 3 mm was formed on the AlGaN layer 4 and the change in the electron concentration [cm ⁻³ ] in the depth direction (thickness direction) was examined at a measurement frequency of 370 Hz. It was. The results are shown in FIG. 4 and FIG.

As shown in FIG. 4, the sample A with the AlN layer 20 has low sheet resistance and sheet carrier concentration, and the sample B without the AlN layer 20 has high sheet resistance and sheet carrier concentration. It was. In Sample A, the electron mobility was as high as 1200 [cm ² / V · s], and in Sample B, it was as low as 90 [cm ² / V · s].

  Further, as shown in FIG. 5, the sample A having the AlN layer 20 has an electron concentration between the u-GaN layer 3 and the AlGaN layer 4 subjected to selective epitaxial growth as compared with the sample B not having the AlN layer 20. It changed abruptly.

  From these results, by providing the AlN layer 20, it is possible to obtain a heterointerface in which the electron concentration can be sharply changed at the interface between the u-GaN layer 3 and the AlGaN layer 4, and the electron mobility can be increased. Thus, it can be seen that good 2DEG characteristics can be obtained.

The manufacturing method of the semiconductor device having such a structure is basically the same as that of the first embodiment, but it is necessary to perform the step of forming the AlN layer 20 before forming the AlGaN layer 4 at the time of selective epitaxial growth. . The AlN layer 20 and the AlGaN layer 4 can be formed in the same epitaxial growth apparatus. For example, when the AlN layer 20 is grown, the Al source is introduced into the NH ₃ atmosphere while the Ga source is not introduced, and then the Ga source is introduced when the AlGaN layer 4 is grown. Layer 4 can be formed continuously.

  In addition, about the thickness of the AlN layer 20, the thickness which can be made into the AlN layer 20 without a void | hole is 1 nm or more, and the thickness which can make the crystallinity of the AlN layer 20 favorable here was given 2 nm or less. However, each numerical value exemplifies a numerical value that can surely obtain each effect, and each effect can be obtained even if the thickness of the AlN layer 20 is 1 nm or less or 2 nm or more.

(Third embodiment)
A third embodiment of the present invention will be described. In this embodiment, the negative shift of the threshold voltage can be further suppressed with respect to the first and second embodiments, and the others are the same as those in the first and second embodiments. Only the differences from the first and second embodiments will be described. In addition, although the case where the structure of this embodiment is applied with respect to the structure of 1st Embodiment is demonstrated here, it is applicable also to the structure of 2nd Embodiment.

As shown in FIG. 6, in the present embodiment, the first nitride semiconductor is formed by the u-GaN layer 3 and the p-GaN layer 30 by forming the p-GaN layer 30 on the entire surface of the u-GaN layer 3. A layer is formed, and an AlGaN layer 4 is formed thereon. The p-GaN layer 30 is a p-type nitride semiconductor having a hole concentration of 1 × 10 ¹⁸ cm ⁻³ or more, for example, and has a thickness of 5 to 500 nm, for example.

In a nitride semiconductor such as the u-GaN layer 3, it is known that Si serving as a donor during selective epitaxial growth adheres to the surface layer portion of the u-GaN layer 3 in an amount of about 1 × 10 ¹² cm ⁻² . Due to the adhesion of Si, the threshold voltage may be negatively shifted by, for example, −2 V or more. In order to offset this, by forming the p-GaN layer 30, it is possible to suppress the surface layer portion of the u-GaN layer 3 from becoming n-type due to the adhesion of Si, and to further shift the threshold voltage further. Is possible. According to the Sim results, it was possible to further shift the threshold voltage by about 2V.

  As described above, by forming the p-GaN layer 30 on the u-GaN layer 3 and then forming the AlGaN layer 4, it is possible to further prevent a minus shift of the threshold voltage.

The manufacturing method of the semiconductor device having such a structure is basically the same as that of the first embodiment, but the step of forming the p-GaN layer 30 after the formation of the u-GaN layer 3 and before the selective epitaxial growth is performed. There is a need to do. The u-GaN layer 3 and the p-GaN layer 3 can be formed in the same epitaxial growth apparatus. For example, when the u-GaN layer 3 is grown, a Ga material is introduced into the NH ₃ atmosphere while an Al material is not introduced, and then a material containing an acceptor such as magnesium (Mg) is used when the p-GaN layer 30 is grown. Introduce. For example, bis (cyclopentadienyl) magnesium (CP ₂ Mg) can be used as a raw material containing an acceptor. In this way, the u-GaN layer 3 and the p-GaN layer 30 can be formed continuously.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In the present embodiment, the configuration between the p-GaN layer 30 and the AlGaN layer 4 is changed with respect to the third embodiment, and the others are the same as those in the third embodiment. Only different parts will be described.

  As shown in FIG. 7, in this embodiment, a u-GaN layer 31 is further formed between the p-GaN layer 30 and the AlGaN layer 4, and the u-GaN layer 3, the p-GaN layer 30, and u The first nitride semiconductor layer is constituted by the GaN layer 31. Like the u-GaN layer 3, the u-GaN layer 31 is composed of an undoped GaN layer that is not doped with impurities. Although the thickness of the u-GaN layer 31 is arbitrary, the thickness is, for example, 5 to 200 nm. Of the first nitride semiconductor layers, two u-GaN layers 31 are spaced apart from each other with the recess 5 interposed therebetween, but the surface of the p-GaN layer 30 serving as the base is the entire surface, that is, the recess 5. The portion located on the bottom surface of the substrate and the portion where the AlGaN layer 4 is laminated are in the same plane.

  In the case of the structure of the third embodiment, 2DEG carriers are formed in the p-GaN layer 30. In this case, since impurities in the acceptor material (such as Mg) affect the electron mobility and the electron concentration is offset with holes, the 2DEG characteristics can be degraded. Accordingly, by providing the u-GaN layer 31 as in the present embodiment, 2DEG gallia is formed in the u-GaN layer 31, and the influence of the acceptor material on the electron mobility can be suppressed. .

  In the structure of the present embodiment, Si as a donor can adhere to the u-GaN layer 31, but the influence is offset by the acceptor material contained in the p-GaN layer 30 disposed in the lower layer, and the threshold value It becomes possible to prevent a negative shift of the voltage. In the figure, there is a step between the channel region formed in the surface layer portion of the p-GaN layer 30 and the 2DEG carrier formed in the surface layer portion of the u-GaN layer 31, but in actuality the u-GaN Since the thickness of the layer 31 is very thin, the layers 31 are connected almost without a step.

The manufacturing method of the semiconductor device having such a structure is basically the same as that of the third embodiment, but the selective epitaxial growth of the u-GaN layer 31 needs to be performed before the selective epitaxial growth of the AlGaN layer 4. The u-GaN layer 31 and the AlGaN layer 4 can be formed in the same epitaxial growth apparatus. For example, when the u-GaN layer 31 is grown, the Ga material is introduced into the NH ₃ atmosphere while the Al material is not introduced, and then the Al material is introduced when the AlGaN layer 4 is grown. In this way, the u-GaN layer 31 and the AlGaN layer 4 can be formed continuously.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in each of the above embodiments, the u-GaN layer 3 and the p-GaN layer 30 are taken as an example of the first nitride semiconductor layer, and the AlGaN layer 40 is taken as an example of the second nitride semiconductor layer. However, this is merely an example, and for the first and second nitride semiconductor layers, the second nitride semiconductor layer has a larger band gap energy than the first nitride semiconductor layer. What is necessary is just to be comprised with the material. For example, a combination of any two of GaN, AlGaN, AlInN, InGaN or the like, or the same material with different mixed crystal ratios is used as the constituent material of the first and second nitride semiconductor layers. be able to.

DESCRIPTION OF SYMBOLS 1 Substrate 3, 31 u-GaN layer 4 AlGaN layer 5 Recessed part 6 Gate insulating film 7 Gate electrode 8 Source electrode 9 Drain electrode 20 AlN layer 30 p-GaN layer

Claims (4)

A first nitride semiconductor layer (3, 30, 31) constituting an electron transit layer;
The first nitride semiconductor layer is stacked on the first nitride semiconductor layer, has a band gap energy larger than that of the first nitride semiconductor layer, constitutes an electron supply unit, and a plurality of the first nitride semiconductor layers are arranged apart from each other. A second nitride semiconductor layer (4, 4a, 4b) constituting a recess (5) together with the surface of the nitride semiconductor layer;
A gate structure comprising a gate insulating film (6) formed in the recess and a gate electrode (7) formed on the gate insulating film;
A source electrode (8) and a drain electrode (9) disposed on both sides of the gate structure portion on the second nitride semiconductor layer;
A two-dimensional electron gas carrier is induced on the first nitride semiconductor layer side at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer, and a voltage is applied to the gate electrode. A lateral switching device that causes a current to flow between the source electrode and the drain electrode by forming a channel in the surface portion of the first nitride semiconductor layer at the bottom of the recess portion when being formed,
The second nitride semiconductor layer is a selective epitaxial growth portion formed on both sides of the recess portion while being not formed in the recess portion.
Of the first nitride semiconductor layer, the portion where the second nitride semiconductor layer is laminated and the portion located at the bottom of the recess are coplanar,
An AlN layer (20) is formed between the first nitride semiconductor layer and the second nitride semiconductor layer, and the AlN layer is not formed in the recess portion, selective epitaxial growth portion der formed on both sides of the recess is,
The first nitride semiconductor layer has a first undoped layer (3) that is not doped with impurities, and a p-type layer (30) stacked on the first undoped layer. A featured semiconductor device. The first nitride semiconductor layer is a second undoped layer that is not doped with an impurity formed of a constituent material of the first undoped layer between the p-type layer and the second nitride semiconductor layer. (31) has a, the second undoped layer, while preventing being formed in the recessed portion, Ri selective epitaxial growth portion der formed on both sides of the recess,
The portion of the first nitride semiconductor layer where the second nitride semiconductor layer is stacked and the portion located at the bottom of the recess are coplanar. 2. The semiconductor device according to claim 1 , wherein the semiconductor device is a surface of the p-type layer of one nitride semiconductor layer . A first nitride semiconductor layer (3, 30, 31) constituting an electron transit layer;
The first nitride semiconductor layer is stacked on the first nitride semiconductor layer, has a band gap energy larger than that of the first nitride semiconductor layer, constitutes an electron supply unit, and a plurality of the first nitride semiconductor layers are arranged apart from each other. A second nitride semiconductor layer (4, 4a, 4b) constituting a recess (5) together with the surface of the nitride semiconductor layer;
A gate structure comprising a gate insulating film (6) formed in the recess and a gate electrode (7) formed on the gate insulating film;
A source electrode (8) and a drain electrode (9) disposed on both sides of the gate structure portion on the second nitride semiconductor layer;
A two-dimensional electron gas carrier is induced on the first nitride semiconductor layer side at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer, and a voltage is applied to the gate electrode. A lateral switching device that causes a current to flow between the source electrode and the drain electrode by forming a channel in the surface portion of the first nitride semiconductor layer at the bottom of the recess portion when A method for manufacturing a semiconductor device, comprising:
After disposing a mask (10) at a position where the recess portion is to be formed on the first nitride semiconductor layer, the mask covers the surface of the first nitride semiconductor layer with the mask. Selectively epitaxially growing the second nitride semiconductor layer on both sides;
After removing the mask, forming the gate electrode through the gate insulating film in the recess portion,
Prior to the step of selectively epitaxially growing the second nitride semiconductor layer, an AlN layer (20) is selectively epitaxially grown on both sides of the recess portion with the mask covering the surface of the first nitride semiconductor layer. the process only contains,
A step of forming a first undoped layer (3) that is not doped with impurities as the first nitride semiconductor layer; and a step of stacking a p-type layer (30) on the first undoped layer; Have
The method of manufacturing a semiconductor device , wherein in the step of selectively epitaxially growing the second nitride semiconductor layer, the second nitride semiconductor layer is selectively epitaxially grown above the p-type layer . Before the step of selectively epitaxially growing the second nitride semiconductor layer, as a part of the first nitride semiconductor layer , the surface of the p-type layer of the first nitride semiconductor layer with the mask The method further comprises a step of selectively epitaxially growing a second undoped layer (31) that is not doped with an impurity formed of a constituent material of the first undoped layer on both sides of the recess portion in a state of covering the recess. Item 4. A method for manufacturing a semiconductor device according to Item 3 .

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