JP6447320B2 - Performance monitoring device - Google Patents

Description

  The present invention relates to a performance monitor apparatus used for performance analysis of programs.

  The performance monitoring device is used for storing information on events generated by hardware during execution of a program by a processor and analyzing the performance of the program. For example, Patent Document 1 discloses a performance monitor device that can extract a preset characteristic event from a group of events that occur in accordance with a series of processes performed when a processor executes an instruction. .

JP 2008-186080 A

  According to the configuration disclosed in Patent Document 1, it is possible to extract a feature event by a combination of a plurality of events, but it is not possible to specify in what time series the combination of a plurality of events has occurred. For example, if all the time series information about an event that has occurred is logged, by analyzing the information, it is possible to specify the period in which a plurality of specific events occurred in a specific time series.

  However, in that case, the time-series feature extraction pattern becomes complicated as the number of events increases, making it difficult to process with hardware. On the other hand, in the processing by software, the operation of the performance monitor device increases the load on the system, so that the performance of the program being analyzed may be affected and the evaluation may be inaccurate.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a performance monitoring apparatus that can extract time-series information about an event that has occurred with small-scale hardware.

  According to the performance monitor device of claim 1, the event context recording unit has a context of two event pairs (event pairs) that occur as a result of execution of the program by the processor. To be recorded. In the context characteristic register, the occurrence order of a plurality of events for which a time series is specified is set by the user. The comparison determination unit compares whether or not the combination of the contexts recorded in the event context recording unit matches the generation order set in the context feature register, and sets the time series identification flag 15 if they match. To do. Then, the counter counts the number of times the time series identification flag 15 is set.

  With this configuration, by referring to the value of the counter, it is possible to specify how many times a plurality of events set by the user in the context characteristic register have occurred in the order of occurrence set during the monitoring period. The event context recording unit records the context at the time of occurrence of two event pairs, so the order of occurrence of a plurality of events can be specified by their combination. Therefore, it is possible to extract time-series information about the event that has occurred with relatively small hardware.

The figure which is one Embodiment and shows mainly the structure of the context characteristic determination part in a performance monitor apparatus The figure explaining an example of operation | movement of an event register and an event context recording part Diagram showing the contents of each event Functional block diagram showing the configuration of the performance monitoring device Functional block diagram showing the configuration of the signal processing device Flow chart showing operation of performance monitor device

  Hereinafter, an embodiment will be described. As shown in FIG. 5, in the signal processing apparatus (processor system) of this embodiment, a plurality of stages 1 (1), 1 (2), 1 (3),... Are connected to each other via an internal bus 2. ing. Each stage 1 includes, for example, two processor cores 3 (A) and 3 (B), a shared memory 4, an arbitration device 5, and a performance monitor device 6. The arbitration device 5 mediates access to the internal bus 2 and the shared memory 4 by the processor cores 3 (A) and 3 (B), and information related to the arbitration is input to the performance monitor device 6.

  The performance monitor device 6 is a device for evaluating the performance of the control program executed by the processor core 3. The performance monitor device 6 of each stage 1 is connected to the host processor 8 via the external bus 7. As shown in FIG. 4, for example, an 8-bit event signal is input to the performance monitor device 6 from the internal bus 2 and the arbitration device 5. When each event signal changes from inactive: “0” to active: “1”, the corresponding first to eighth bits of the event register 11 (event context recording unit) are set to “1”.

  According to the set / reset state of each bit in the event register 11, the event context recording unit 12 records the context between the event signal generated for the time being and the event signal generated in the past. In the context characteristic register 13, among the events E <b> 1 to E <b> 8, the generation order (context relation), that is, time series information, is set for the event for which the user specifies the time series. For example, “0” is set for events that do not specify the occurrence order, and occurrence orders 1 to 7 are set for events that specify the occurrence order. In this case, the context characteristic register 13 is a (3 bits) × 8 register. This setting is performed by the user via the host processor 8.

  The context characteristic determination unit 14 (comparison determination unit) compares the setting state in the context characteristic register 13 with the recording state in the event context recording unit 12, and sets the time-series identification flag 15 when the two match. . The time series identification flag 15 is input to the counter 16. The counter 16 is, for example, a 32-bit counter that starts and stops a count operation in response to a start signal and a stop signal input via the start / stop signal selection register 17. The counter 16 counts the number of times that the time series identification flag 15 is set within the monitoring period. For example, a 4-bit monitor start signal and a monitor stop signal are input to the start / stop signal selection register 17, and one of the 4 bits is selected as a trigger according to the setting by the user, and each start / stop signal is selected. A start signal and a stop signal input to the selection register 17 are used.

  In addition, the recording state (56 bits as will be described later) in the event context recording unit 12 and the counter value of the counter 16 are output to the outside of the performance monitor device 6 as serial data (corresponding to a recording state output unit), for example. The user can monitor in real time via the external bus 7 and the host processor 8.

  As shown in FIG. 2, the event context recording unit 12 includes a register selection unit 21 and an event context recording register 22. The event context record register 22 is provided for an event pair (En, Em) which is an arbitrary combination of eight events (n <m), and the initial value is “0”. Then, the flag “1” is set by the register selection unit 21 in accordance with the context at the time when each event occurs. Since each event pair (En, Em) is provided with a pre-occurrence register 22 (En> Em) and a post-occurrence register 22 (En <Em), the register becomes a total of 56 bits.

  For example, for the event pair (E1, E2), there are a pre-occurrence register 22 (E1> E2) and a post-occurrence register 22 (E1 <E2). If event E1 occurs before event E2, it occurs before The flag “1” is set in the register 22 (E1> E2), and when the event E1 occurs after the event E2, the flag “1” is set in the post-generation register 22 (E1 <E2). As shown in FIG. 2, if the flag “1” is set in both registers 22 (E1> E2) and 22 (E1 <E2), the event E1 occurs both before and after the event E2. It shows that.

  As an example of each event illustrated in FIG. 3, events E <b> 1 to E <b> 4 relate to the case where the processor 3 performs read / write access to the shared memory 4 and the occurrence of a stall for those accesses. Events E5 and E6 relate to the case where the processor 3 makes a write access to the internal bus 2 and the occurrence of a stall for the access. Events E7 and E8 relate to the occurrence of a stall when the processor 3 transfers data to the left or right stage 1 of the internal bus 2 in FIG.

For example, as shown in FIG. 2, when events occur in a time series of E1, E3, E2, E1, E7,..., The values of the registers change as follows.
Event Event register Event context record register E1 E1 “1”
E3 E3 “1” (E1 <E3) “1”
E2 E2 “1” (E1 <E2) “1”
(E2> E3) “1”
E1 E1 “1” (E1> E2) “1”
(E1> E3) “1”
E7 E7 “1” (E1 <E7) “1”
(E2 <E7) “1”
(E3 <E7) “1”

  As shown in FIG. 1, the contextual feature determination unit 14 includes a multiplexer 23 and a comparison logic 24 (comparator) that exist as many as the number of event pairs, an event pair selection unit 25, and an AND gate 26. Each multiplexer 23 (En, Em) receives the register values of the subsequent occurrence register (En <Em) and the previous occurrence register (En> Em) of the corresponding event pair, the former being the “1” side and the latter Is the “0” side. The comparison logic 24 (En <Em) compares the magnitude relation of the order of the event pairs in which the generation order is set in the context characteristic register 13, and the comparison result is “1, 0” and the corresponding multiplexer 23 ( En, Em) as a selection signal.

  The output signal of each multiplexer 23 (En, Em) is input to the AND gate 26 via the event pair selection unit 25. The context characteristic register 13 gives a 28-bit selection signal to the event pair selection unit 25. In the context characteristic register 13, it is not necessary to select the corresponding multiplexer 23 for an event pair for which the generation order is not set, that is, an event pair in which at least one is “0”. Therefore, the event pair selection unit 25 directly sets the output of the corresponding multiplexer 23 to “1” and inputs it to the AND gate 26.

In the example shown in FIG. 1, the user enters the generation order E3 <E1 <E7 in the context feature register 13.
Is set. In this case, only three event pairs (E1, E3), (E1, E7), (E3, E7) are valid, and the other 25 event pairs are invalid. At this time, for example, “0” is given to the event pair selection unit 25 from the context characteristic register 13 for the valid three event pairs, and the selection result of the corresponding multiplexer 23 is validated. For other event pairs, “1” is given, and the event pair selection unit 25 inputs “1” directly to the AND gate 26 as described above, regardless of the selection result of the corresponding multiplexer 23.

In addition, when the occurrence order set by the user in the context characteristic register 13 is divided for each event pair,
E1 (2) <E3 (1)? → 0
E3 (1) <E7 (3)? → 1
E1 (2) <E7 (3)? → 1
It becomes. In accordance with the comparison result, the multiplexer 23 (E1, E3) selects the value “1” of the pre-occurrence register 22 (E1> E3), which is the input on the “0” side. Further, the multiplexer 23 (E3, E7) selects the value “1” of the post-generation register 22 (E1 <E7), which is the input on the “1” side. Similarly, the value “1” of the post-generation register 22 (E3 <E7), which is the input on the “1” side, is also selected for the multiplexer 23 (E1, E7).

Therefore, when the context recording state in the event context recording unit 12 matches the order of occurrence set in the context characteristic register 13 by the user, the AND gate 26 outputs “1”, and the time series identification flag 15 is set. Set. Here, as in the present embodiment, the amount of hardware resources necessary for the context characteristic determination unit 14 to set the occurrence order 1 to 7 with the number of events 8 is as follows.
Event context recording unit 12 56 bits, context feature register 13 3 × 8 = 24 bits, multiplexer 23 (2: 1) 28, comparison logic 24 28, event pair selection unit 25 (28 bits) 1 AND gate 26 (28 inputs) 1 piece

  Next, the operation of this embodiment will be described. As shown in FIG. 6, the user first sets the context characteristic register 13 and the start / stop signal selection register 17 of the performance monitor device 6 (S1, S2). Then, when the event register 11 and the event context recording unit 12 are initialized (S3), the processor core 3 starts executing the control program (S4). Along with this, the event context recording unit 12 starts extracting feature events (recording the context of event pairs for which the order of occurrence has been set) (S5).

  When the monitor start signal selected and set by the user is generated, monitoring of the program by the performance monitor device 6 is started (S6), and the counter 16 counts the number of times the time series identification flag 15 is set (S7). Thereafter, when a monitor stop signal selected and set by the user is generated, monitoring by the performance monitor device 6 is stopped (S8). Then, the monitor result is output to the outside (S9). If the execution of the program is not finished (S10: NO), the process returns to step S5, and if the execution of the program is finished (YES), the process is finished.

  As described above, according to the present embodiment, in the performance monitor device 6, the event context recording unit 12 has two event pairs that have occurred as a result of execution of the program by the processor 3. The context is recorded, and the occurrence order of a plurality of events is set in the context characteristic register 13 by the user. The context characteristic determination unit 14 compares whether or not the combination of the contexts recorded in the event context recording unit 12 matches the order of occurrence set in the context characteristic register 13, and if they match, time series The specific flag 15 is set. Then, the counter 16 counts the number of times that the time series identification flag 15 is set.

  With this configuration, by referring to the value of the counter 16, it is possible to specify how many times a plurality of events set by the user in the context characteristic register 13 have occurred in the order set during the monitoring period. it can. Since the event context recording unit 12 records the context of two event pairs at the time when they occurred, the order of occurrence of a plurality of events can be specified by their combination. Therefore, it is possible to extract time-series information about the event that has occurred with relatively small hardware.

  In addition, the event context recording unit 12 includes a pre-occurrence register 22 (En> Em) in which a flag is set when one of the event pairs occurs before the other, and a case where one of the event pairs occurs after the other. Since the post-occurrence register 22 (En <Em) is separately provided, the order of occurrence of each event can be specified by the set state of the flag in these registers.

  In addition, the event context recording unit 12 has a pre-occurrence register 22 (En> Em) and a post-occurrence register 22 (En depending on the state of each flag in the event register 11 in which a flag is set when each event occurs. A register selection unit 21 that sets a flag in <Em) is provided. As a result, the front-rear relationship of the timing at which each event occurs can be appropriately recorded in the pre-occurrence register 22 (En> Em) and the post-occurrence register 22 (En <Em).

  Further, the event context recording unit 12 selects and outputs one of the register values in the pre-occurrence register 22 (En> Em) and the post-occurrence register 22 (En <Em) corresponding to each event pair. A comparison logic 24 for switching the input selection of the multiplexer corresponding to each event pair by comparing the multiplexer 23 with the context for each event pair according to the generation order set in the context characteristic register 13, and the context setting register According to the type of event set to 13, the event pair selection unit 25 that selects the output of the multiplexer 23 and the logical product of the output values of the multiplexer 23 selected through the event pair selection unit 25 are calculated. And an AND gate 26 for setting the time series identification flag 15. Therefore, the time series identification flag 15 can be set with a simple logic configuration.

  In addition, since the recording status of the context in the event context recording unit 12 can be output to the outside, the user can monitor the context of the timing at which each event occurred in real time during the execution of the program by the processor 3. it can.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The setting of the number of bits in each unit is an example, and may be appropriately changed according to individual design.
The number of processor cores 3 mounted on each stage 1 may be one or three or more. Further, the present invention may be applied to a system configured with only a single stage.
The number of events is not limited to 8, and may be “7” or less or “9” or more.
A configuration for outputting the recording state of the context in the event context recording unit 12 and the count value of the counter 16 to the outside may be provided as necessary.

  In the drawing, 6 is a performance monitor device, 11 is an event register, 12 is an event context recording unit, 13 is a context feature register, 14 is a context feature determination unit (comparison determination unit), 15 is a time series identification flag, 16 Represents a counter, and 22 represents an event context record register.

Claims (5)

An event context recording unit (12) for recording the context of two event pairs (hereinafter referred to as event pairs) that occur as a result of execution of a program by the processor;
A context feature register (13) in which the user sets the order of occurrence of a plurality of events;
It is compared whether or not the combination of the contexts recorded in the event context recording unit matches the order of occurrence set in the context characteristic register, and if they match, the time series identification flag (15) is set. A comparison determination unit (14);
And a counter (16) for counting the number of times the time-series specific flag is set. The event context recording unit includes a pre-occurrence register (22 (En> Em)) in which a flag is set when one of the event pairs occurs before the other,
Performance monitoring apparatus according to claim 1, wherein the one of the event pair is a after generating register (22 (En <Em)) flag is set individually when occurring after the other . The event context recording unit includes an event context recording register (22) composed of the pre-occurrence register and the post-occurrence register;
A register selection unit (21) that sets a flag in the event context recording register according to the state of each flag in the event register (11) in which a flag is set when each event occurs. 3. The performance monitor device according to claim 2, wherein The comparison / determination unit includes a plurality of multiplexers (23) that select and output one of the register values in the pre-occurrence register and the post-occurrence register corresponding to each event pair;
A comparator (24) that compares the context for each event pair according to the order of occurrence set in the context characteristic register and switches the input selection of the multiplexer corresponding to each event pair;
An event pair selection unit (25) for selecting outputs of the plurality of multiplexers in accordance with the type of event set in the context characteristic register;
The AND gate (26) according to claim 3, further comprising: an AND gate (26) for setting the time series identification flag by calculating a logical product of the output values of the multiplexers selected via the event pair selection unit. Performance monitor device.
  5. The performance monitoring apparatus according to claim 1, further comprising a recording state output unit that outputs the recording state of the context in the event context recording unit to the outside. 6.

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