JP6447441B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device that forms a first pattern portion and a second pattern portion partitioned through a trench by performing trench etching on a semiconductor substrate, and relates to a semiconductor dynamic quantity sensor such as an acceleration sensor. Etc. are used.

  Conventionally, as a method for manufacturing a general semiconductor device of this type, trench etching is performed to form a trench in the thickness direction of the semiconductor substrate, and the first pattern portion and the second pattern in which the sidewalls face each other through the trench. A method of forming both pattern portions of the pattern portion has been proposed.

  Here, in the trench etching, a protective film is formed on the surface of the semiconductor substrate, and a portion of the semiconductor substrate without the protective film is etched and removed.

  In the trench, the aspect ratio is the ratio of depth to width. Here, in this method, when the aspect ratio is increased to make the trench narrower and deeper, the side walls of both pattern portions are excessively etched, and the side walls become rough.

In the second half of the trench etching, the supply of gas such as C ₄ F ₈ that forms a protective film for protecting the sidewall and gas such as SF ₆ that performs isotropic etching becomes imbalanced, and the sidewall is protected. It is caused by the etching progressing without being done.

Therefore, in Patent Document 1, the trench aspect ratio is improved by performing trench etching using a special gas obtained by adding a gas containing hydrogen in a predetermined range to a mixed gas composed of SF ₆ and O ₂ or the like. It is trying to correspond to. However, using such a special gas is not preferable because it leads to an increase in labor and cost.

JP 2007-103876 A

  On the other hand, according to the study by the present inventor, the temperature difference caused by the heat generated by the etching reaction between the first pattern portion and the second pattern portion during trench etching can be cited as a cause of the side wall roughness.

  When such a temperature difference between the two pattern portions is generated during the trench etching, the protective film becomes thin or the protective film does not adhere to the side wall of the high-temperature pattern portion. Therefore, a difference occurs in the thickness of the protective film attached to the side wall between the two pattern portions.

  When dry etching is performed on a side wall to which the protective film is not sufficiently adhered, the side wall becomes rough or a desired side wall shape cannot be obtained. Note that such a problem of side wall roughness due to a temperature difference is unavoidable even when a special gas as described in Patent Document 1 is used.

  The present invention has been made in view of the above problem, and manufacture of a semiconductor device capable of appropriately suppressing the roughness of the side wall between the first pattern portion and the second pattern portion partitioned by trench etching. It aims to provide a method.

  In order to achieve the above object, according to the first aspect of the present invention, trench etching for forming a trench (20) in the thickness direction of the semiconductor substrate (10) is performed, and the side walls (31, 41) of each other through the trench. Is a method of manufacturing a semiconductor device for forming both the first pattern portion (30) and the second pattern portion (40) facing each other, and further has the following characteristics.

That is, in the trench etching, a protective film (100) is formed on the surface of the semiconductor substrate, and the semiconductor substrate is removed by etching. The first pattern portion and the second pattern portion are removed during the trench etching. as both pattern portions is structured to be the same temperature, have rows trench etching, at least one of the first pattern portion and second pattern portion, escape heat dissipating heat from the at least one pattern portion section As a structure having (60), the trench etching is performed so that both pattern portions have the same temperature during the trench etching .

  According to this, since the trench etching is performed in a state where the first pattern portion and the second pattern portion are at the same temperature during the trench etching, the protective film is evenly attached to the sidewalls of both pattern portions. Etching proceeds in the state. Therefore, according to the manufacturing method of the present invention, it is possible to appropriately suppress the roughness of the side walls between the two pattern portions.

  In addition, the code | symbol in the bracket | parenthesis of each means described in the claim and this column is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

It is a schematic plan view which shows the state immediately after completion | finish of trench etching of the semiconductor device concerning 1st Embodiment of this invention. It is a schematic sectional drawing in alignment with the dashed-dotted line II-II in FIG. It is process drawing which shows in cross section the trench etching in the manufacturing method of the semiconductor device concerning 1st Embodiment. FIG. 4 is a cross-sectional process diagram illustrating trench etching subsequent to FIG. 3. FIG. 5 is a process diagram showing a cross-sectional view of trench etching following FIG. 4. FIG. 6 is a cross-sectional process diagram illustrating trench etching subsequent to FIG. 5. FIG. 7 is a process diagram showing a cross-sectional view of trench etching following FIG. 6. FIG. 8 is a process diagram showing a cross-sectional view of trench etching following FIG. 7. FIG. 9 is a cross-sectional process diagram illustrating trench etching subsequent to FIG. 8. FIG. 10 is a cross-sectional process diagram illustrating trench etching subsequent to FIG. 9. It is a schematic plan view showing a semiconductor device as a comparative example of the first embodiment. It is a schematic plan view which shows the state immediately after completion | finish of trench etching of the semiconductor device concerning 2nd Embodiment of this invention. It is a schematic sectional drawing in alignment with the dashed-dotted line XIII-XIII in FIG. It is a schematic sectional drawing which shows the semiconductor device concerning other embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, parts that are the same or equivalent to each other are given the same reference numerals in the drawings for the sake of simplicity.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. This semiconductor device is applied to a semiconductor dynamic quantity sensor such as an acceleration sensor mounted on a vehicle such as an automobile.

  Here, FIGS. 1 and 2 show the structure of the semiconductor device in a state immediately after the end of trench etching. The semiconductor substrate 10 is composed of an SOI (silicon-on-insulator) substrate in which a supporting silicon layer 11 and a surface silicon layer 12 are bonded together via an oxide film 13 made of a silicon oxide film.

  The trench etching forms a trench 20 that reaches the oxide film 13 from the upper surface of the surface silicon layer 12. Thus, by the trench 20 formed in the thickness direction of the semiconductor substrate 10, the surface silicon layer 12 is partitioned into a first pattern portion 30, a second pattern portion 40, and a frame portion 50 surrounding these pattern portions. Has been.

  The side wall 31 of the first pattern unit 30, the side wall 41 of the second pattern unit 40, and the side wall 51 of the frame unit 50 are opposed to each other through the trench 20. Here, the 1st pattern part 30 and the 2nd pattern part 40 are electrically insulated by the oxide film 13 and the trench 20, and are comprised as an electrode electrically mutually independent, for example.

  Although the shape of the first pattern portion 30 and the second pattern portion 40 is not limited, here, as shown in FIGS. 1 and 2, the first pattern portion 30 and the second pattern portion. 40 has a planar comb shape. Such a shape is, for example, the shape of the movable electrode and the fixed electrode in a typical acceleration sensor.

  In this case, one of the pattern portions 30 and 40 is a movable electrode, and the other is a fixed electrode. Then, the acceleration is detected by displacement of the distance between these electrodes, that is, the distance between the side walls 31 and 41 of the pattern portions 30 and 40 with the application of acceleration.

  Although not shown, when both the pattern portions 30 and 40 are such a movable electrode and a fixed electrode, the oxide film 13 located immediately below both the pattern portions 30 and 40 is the same as a normal acceleration sensor. A part of is removed.

  Part of the oxide film 13 is removed by performing sacrificial layer etching of the oxide film 13 from the state immediately after the trench etching shown in FIG. As a result, a part of the movable electrode of both the pattern portions 30 and 40 floats from the support silicon layer 11 and can be displaced, and a semiconductor device as an acceleration sensor is formed.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. According to this manufacturing method, the semiconductor device up to the state immediately after completion of the trench etching shown in FIGS. 1 and 2 is formed. First, trench etching will be described. This trench etching is basically the same as a typical one, in which a protective film 100 is formed on the surface of the semiconductor substrate 10 and the semiconductor substrate 10 is etched away.

  Although it does not limit, the trench etching of this embodiment repeats the following 1st-3rd processes sequentially. In the first step, the protective film 100 is formed on the entire surface of the semiconductor substrate 10. Here, the surface of the semiconductor substrate 10 is a surface located on the side where the trench 20 is formed, and corresponds to the surface of the surface silicon layer 12 in this embodiment.

  In the subsequent second step, the protective film 100 in the trench formation portion 20a where the trench 20 is formed in the surface of the semiconductor substrate 10 is removed. In the subsequent third step, the semiconductor substrate 10 is removed by isotropic etching at the trench forming portion 20a.

  The trench etching in which the first step, the second step, and the third step are sequentially performed will be described more specifically with reference to FIGS.

  First, as shown in FIG. 3, a mask 200 is formed on the surface of the surface silicon layer 12 where the trench 20 is formed in the semiconductor substrate 10 in a portion other than the trench formation portion 20 a.

Next, as shown in FIG. 4, a first step is performed to form a protective film 100 over the entire surface of the semiconductor substrate 10. Thereby, the protective film 100 is formed on the surface of the mask 200 and the trench formation portion 20a. In this first step, for example, a protective film 100 made of a polymer such as fluorocarbon is formed using a gas such as C ₄ F ₈ .

Next, as shown in FIG. 5, a second step is performed to remove the protective film 100 in the trench formation portion 20a. In this second step, for example, a gas such as SF ₆ is used, and thereby the protective film 100 in the trench forming portion 20a between the masks 200 is removed.

Next, as shown in FIG. 6, a third step is performed, and the surface silicon layer 12 of the semiconductor substrate 10 is removed by isotropic etching in the trench formation portion 20a from which the protective film 100 has been removed. Thereby, a part of the trench 20 is formed in the trench formation portion 20a. In the third step, a gas such as SF ₆ is used as in the second step.

  Subsequently, as shown in FIG. 7, the first process is performed again to form the protective film 100 on the entire surface of the semiconductor substrate 10. As a result, the protective film 100 is formed on the surface of the mask 200 and the side walls and bottom of the trench 20 being formed.

Next, as shown in FIG. 8, a second process using a gas such as SF ₆ is performed as described above to remove the protective film 100 located at the bottom of the trench 20 being formed in the trench forming portion 20a. To do.

Subsequently, as shown in FIG. 9, a third step using a gas such as SF ₆ is performed as described above, and the semiconductor substrate 10 is isotropically etched in the trench formation portion 20a from which the protective film 100 has been removed. And remove. As a result, the trench 20 in a state of being further dug is formed in the trench formation portion 20a.

  As shown in FIGS. 4 to 9, the first step, the second step, and the third step are sequentially repeated to finally reach the oxide film 13 as shown in FIG. 10. A trench 20 in a state is completed. After the state shown in FIG. 10, the mask 200 and the protective film 100 are removed by ashing or the like. As a result, the semiconductor device in the state shown in FIGS. 1 and 2 is completed.

  Here, in the manufacturing method of this embodiment, in the trench etching process, the first pattern portion 30 and the second pattern portion 40 have a structure in which both the pattern portions 30 and 40 are at the same temperature during the trench etching. Then, trench etching is performed. Here, during the trench etching is equivalent to a period from the time when the trench etching is started in the first process to the time when the trench 20 reaches the oxide film 13 in the third process.

  Specifically, the structure in which both pattern portions 30 and 40 have the same temperature during trench etching refers to the area of the entire outer surface of the first pattern portion 30 and the area of the entire outer surface of the second pattern portion 40. Is the same structure.

  Here, the outer surface of the first pattern portion 30 corresponds to the upper surface 32 and the side wall 31 of the first pattern portion 30, and the outer surface of the second pattern portion 40 refers to the second pattern portion 40. This corresponds to the upper surface 42 and the side wall 41 in FIG.

  1 and 2 and later-described FIG. 11, the portions that become the side walls 31 and 41 and the upper surfaces 32 and 42 that are the outer surfaces of the pattern portions 30 and 40 are indicated by thick lines for convenience of identification. Here, the upper surfaces 32 and 42 correspond to the upper surface of the surface silicon layer 12.

  The outer surfaces of both the pattern portions 30 and 40 are heat radiating surfaces to the outside air in both the pattern portions 30 and 40. According to the trench etching of the present embodiment, the heat radiation area during the trench etching is substantially the same between the first pattern portion 30 and the second pattern portion 40.

  Therefore, according to the present embodiment, the trench etching is performed in a state where both the pattern portions 30 and 40 are at the same temperature during the trench etching. Then, the etching proceeds with the protective film 100 uniformly attached to the side walls 31 and 41 of both the pattern portions 30 and 40. As a result, according to the present embodiment, it is possible to appropriately suppress the roughness of the side walls 31 and 40 between the pattern portions 30 and 40.

  Here, in the comparative example shown in FIG. 11, the area of the outer surface of the second pattern portion 40, that is, the side wall 41 and the entire upper surface 42, is the outer surface of the first pattern portion 30, that is, the side wall 31 and the entire upper surface 32. It is considered to be significantly larger than the area. In such a case, during the trench etching, the first pattern portion 30 becomes hotter than the second pattern portion 40, and the protective film 100 is formed on the side wall of the first pattern portion 30 as described above. Adhesion will be insufficient.

  In addition, the fact that the area of the entire outer surface is the same between the pattern portions 30 and 40 does not mean only the completely same, and as long as the effect of the present embodiment of suppressing the roughness of the side wall is achieved, It does not have to be exactly the same. Furthermore, the fact that the pattern portions 30 and 40 are at the same temperature does not mean that they are completely identical, and may not be exactly the same as long as the effect of the present embodiment is achieved. .

(Second Embodiment)
A semiconductor device manufacturing method according to the second embodiment of the present invention will be described with reference to FIGS. 12 and 13 focusing on differences from the first embodiment. In the present embodiment, the structure in which both pattern portions 30 and 40 are at the same temperature during trench etching is different from the first embodiment.

  As shown in FIG. 12 and FIG. 13, in this embodiment, as the structure, the second pattern portion 40 out of both the pattern portions 30 and 40 has a heat release portion 60 that releases heat from the second pattern portion 40. The structure which has is adopted. In this embodiment, the trench etching is performed so as to obtain this structure during the trench etching.

  In the present embodiment, when compared with a structure without the heat escape portion 60, the heat escape portion is closer to the second pattern portion 40, which is narrower overall than the first pattern portion 30 and tends to be high in temperature. 60 is provided. Although not limited, in the illustrated example, the heat release portion 60 protrudes from a portion of the side wall of the second pattern portion 40 that does not face the side wall of the first pattern portion 30. .

  Thereby, during the trench etching, the heat of the second pattern portion 40 is radiated from the heat release portion 60 to the etching atmosphere or the oxide film 13. According to the present embodiment, the temperature of the second pattern unit 40 can be brought close to the temperature of the first pattern unit 30 by the heat release unit 60 during the trench etching. Easy to achieve the same temperature.

(Other embodiments)
In FIGS. 12 and 13, the heat release portion 60 is provided in the second pattern portion 40 that tends to be high in temperature. However, the shapes of the pattern portions 30 and 40 are not limited to those shown in FIGS. When the temperature on the first pattern portion 30 side tends to be higher, the heat release portion 60 may be provided on the first pattern portion 30 side.

  In any case, it is sufficient that the effect of reducing the temperature difference between the pattern portions 30 and 40 during trench etching to be the same temperature by the heat release portion 60 is achieved. The pattern portions 30 and 40 may be provided with heat escape portions.

  In other words, if the above-described effect of the same temperature is exhibited, trench etching is performed so that the first pattern portion 30 and / or the second pattern portion 40 have a heat release portion 60 in one or both of them. Can be done.

  Moreover, in the said embodiment, as shown in FIG. 1, FIG. 2, both the pattern parts 30 and 40 were applied as a movable electrode or a fixed electrode. However, the present invention is not limited to this. For example, both the pattern portions 30 and 40 may be configured as electrodes for external connection by wire bonding or the like.

  In this case, the oxide film 13 is shown in FIG. 2 without performing the sacrificial layer etching of the oxide film 13 so that a part of both the pattern portions 30 and 40 is floated from the supporting silicon layer. The structure may be allowed to exist in the state.

  Further, in order to realize a configuration in which a part of both the pattern portions 30 and 40 described above is lifted from the support silicon layer 11, for example, a semiconductor substrate 10 as shown in FIG. 14 may be used. In this case, the cavity 11a is provided in advance in the portion of the supporting silicon layer 11 located immediately below the floating portion in both the pattern portions 30 and 40.

  Such a semiconductor substrate 10 is formed by bonding the supporting silicon layer 11 in which the cavity 11 a is formed and the surface silicon layer 12 through the oxide film 13. According to this, even if the sacrificial layer etching of the oxide film 13 after the trench etching as described above is not performed, the floating portion is formed with the completion of the trench etching of the surface silicon layer 12. That is, the structure shown in FIG. 14 can be applied to the above embodiments.

  In addition, the first pattern portion 30 and the second pattern portion 40 are not limited to those that are electrically independent, and may be electrically conductive at portions other than the trench 20. .

In addition, the trench etching may include the first step, the second step, and the third step described above, and these may be repeated in this order, and the gas used may be the above-described C ₄ F _8. Needless to say, the gas is not limited to the gas such as SF ₆ or the like.

  Needless to say, the semiconductor substrate 10 is not limited to the above-described SOI substrate, and is not limited to such a multilayer substrate, and may be a single-layer substrate, for example. In addition, the same effect can be expected not only in a method of forming a protective film by switching gases but also in an etching method in which an etching gas and a raw material gas for the protective film are simultaneously flowed.

  Further, the present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope described in the claims. The above embodiments are not irrelevant to each other, and can be combined as appropriate unless the combination is clearly impossible, and the above embodiments are not limited to the illustrated examples. Absent.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 20 Trench 30 1st pattern part 31 Side wall of 1st pattern part 40 2nd pattern part 41 Side wall of 2nd pattern part 100 Protective film

Claims (2)

Trench etching is performed to form a trench (20) in the thickness direction of the semiconductor substrate (10), and the first pattern portion (30) and the second pattern portion where the side walls (31, 41) face each other through the trench. A method of manufacturing a semiconductor device for forming both pattern portions of a pattern portion (40),
In the trench etching, a protective film (100) is formed on the surface of the semiconductor substrate, and the semiconductor substrate is etched and removed.
The first pattern portion and the second pattern portion, so that the two pattern portions in the trench etch is a structure comprising the same temperature, have lines the trench etching,
By performing the trench etching so that at least one of the first pattern portion and the second pattern portion has a heat release portion (60) for releasing heat from the at least one pattern portion. A method of manufacturing a semiconductor device in which both the pattern portions have the same temperature during the trench etching .   The trench so that the entire area of the outer surface (31, 32) of the first pattern portion and the area of the entire outer surface (41, 42) of the second pattern portion are the same. The method for manufacturing a semiconductor device according to claim 1, wherein etching is performed.

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