JP6448743B2 - Semiconductor device - Google Patents

Description

One embodiment of the disclosed invention relates to a method for manufacturing a semiconductor device.

In recent years, in the field of computer system technology, when processing is necessary, such as when the supply of power within the device is stopped when processing is not being performed and an input operation is performed on the device, power is instantaneously generated. A power control technique for reducing power consumption during standby has been developed by resuming the supply of power (see Patent Document 1).

In particular, CPU (Central Processing Unit)
In addition, research has been conducted on computing technology for realizing ultra-low power consumption by actively utilizing nonvolatile elements.

Japanese Patent Laid-Open No. 2007-11652

As the above-described nonvolatile element, a transistor including an oxide semiconductor layer as an active layer (hereinafter, “
When a semiconductor device is manufactured using an “oxide semiconductor transistor”, a semiconductor device capable of holding data for a long time can be obtained. Details will be described below.

Note that in this specification, a region in contact with the source electrode in the oxide semiconductor layer is referred to as a source region, and a region in contact with the drain electrode in the oxide semiconductor layer is referred to as a drain region. A region between the source region and the drain region in the oxide semiconductor layer and overlapping with the gate electrode is referred to as a channel formation region.

In this specification, an active layer refers to a semiconductor layer including a channel formation region, a source region, and a drain region.

In this specification, the length of the channel formation region (hereinafter referred to as “channel length”) refers to the length of the channel formation region in the direction in which carriers flow. The width of the channel formation region (hereinafter referred to as “channel width”) refers to the length in the direction perpendicular to the direction in which carriers flow in the channel formation region.

An oxide semiconductor transistor has an off-state leakage current (hereinafter referred to as “off-state current”).
Very low. Note that the off-state current refers to the drain current I when the transistor is off, for example, when the potential difference from the gate potential Vg with respect to the source potential is equal to or lower than the threshold voltage.
Let d.

Note that in this specification, the threshold voltage is defined as the value of the gate potential when the slope of the square root of the drain current Id with respect to the gate potential Vg becomes maximum in the saturation region.

An oxide semiconductor transistor with extremely low off-state current can hold a charge of a node electrically connected to one of a source and a drain for a long time. Such a semiconductor device including an oxide semiconductor transistor with extremely small off-state current is a semiconductor device that can hold data for a long time. In other words, a semiconductor device including an oxide semiconductor transistor with extremely low off-state current can be said to be a nonvolatile semiconductor device.

By stacking such oxide semiconductor transistors in a three-dimensional hierarchy, the area of a semiconductor device using the oxide semiconductor transistor can be reduced.

However, oxygen vacancies serve as donors in the oxide semiconductor layer, and electrons serving as carriers are generated in the oxide semiconductor layer. If there are many oxygen vacancies in the oxide semiconductor layer including the channel formation region of the oxide semiconductor transistor, electrons are generated in the channel formation region, and the threshold voltage of the oxide semiconductor transistor is shifted in the negative direction. It becomes.

Therefore, oxygen is preferably added to the oxide semiconductor layer in order to reduce oxygen vacancies in the oxide semiconductor layer and stabilize the electrical characteristics of the oxide semiconductor transistor. By adding oxygen to the oxide semiconductor layer, the threshold voltage of the oxide semiconductor transistor can be shifted in the positive direction.

As a method for adding oxygen to the oxide semiconductor layer, oxygen in an amount exceeding at least the stoichiometric composition ratio exists in the layer (in the bulk) in either or both of the upper and lower sides of the oxide semiconductor layer. An example is a method in which an insulating layer, for example, a silicon oxide layer is formed and oxygen is supplied from the silicon oxide layer to the oxide semiconductor layer by heat treatment.

In the method of supplying oxygen from the silicon oxide layer to the oxide semiconductor layer by heat treatment, the amount of oxygen supplied from the silicon oxide layer to the oxide semiconductor layer increases as the heat treatment time increases. As the amount of oxygen supplied to the oxide semiconductor layer increases, the density of oxygen vacancies in the oxide semiconductor layer can be reduced. As a result, the amount of shift in the positive direction of the threshold voltage of the oxide semiconductor transistor increases. Become.

However, when oxide semiconductor transistors are three-dimensionally layered and stacked, the heat treatment time of the oxide semiconductor transistor formed in the lower layer (the oxide semiconductor transistor formed earlier) is the oxidation time formed in the lower layer. It is the sum of the heat treatment time performed when forming the physical semiconductor transistor and the heat treatment time performed when forming the oxide semiconductor transistor formed in the upper layer (the oxide semiconductor transistor formed later). Therefore, the heat treatment time of the oxide semiconductor transistor formed in the lower layer is longer than the heat treatment time of the oxide semiconductor transistor formed in the upper layer.

If the heat treatment times for the lower and upper oxide semiconductor transistors are different, the amount of oxygen added to the oxide semiconductor layer may be different. If the amount of oxygen added to the oxide semiconductor layer is different, the threshold voltage shift amount of the oxide semiconductor transistor is different, and there is a risk that an oxide semiconductor transistor having different characteristics in the lower and upper layers may be manufactured. Arise.

When a semiconductor device is manufactured using oxide semiconductor transistors having different characteristics in the lower layer and the upper layer, the reliability of the semiconductor device may be reduced.

In view of the above, an object of one embodiment of the disclosed invention is to obtain an oxide semiconductor transistor with uniform electric characteristics in a semiconductor device in which oxide semiconductor transistors are three-dimensionally layered and stacked. .

In one embodiment of the disclosed invention, when the heat treatment time is the same, a transistor having a lower threshold voltage is formed in a lower layer (first) and a transistor having a higher threshold voltage is Form in the hierarchy (later).

When the heat treatment time is the same, a transistor having a lower threshold voltage is formed in the lower layer (first), and a transistor having a higher threshold voltage is formed in the upper layer (later). The heat treatment time of the transistors formed in the hierarchy is longer than the heat treatment time of the transistors formed in the upper hierarchy.

By performing a longer heat treatment on the oxide semiconductor transistor formed in the lower layer, a threshold voltage similar to that of the oxide semiconductor transistor formed in the upper layer and having a short heat treatment time can be obtained. By making the electrical characteristics such as the threshold voltage uniform, a highly reliable semiconductor device can be obtained.

For example, when the heat treatment time is the same, a transistor having a short channel length as a transistor having a lower threshold voltage, and a transistor having a long channel length can be given as a transistor having a higher threshold voltage. A transistor with a short channel length is formed in the lower layer to increase the heat treatment time, and a transistor with a long channel length is formed in the upper layer to shorten the heat treatment time, thereby making the threshold voltage of which transistor the same. It is possible.

Further, by forming a transistor that requires more heat treatment in the lower layer, it is possible to increase the heat treatment time of a transistor that requires more heat treatment without changing the overall heat treatment time. When the heat treatment time is long, the arrangement of atoms is further stabilized, so that there is an advantage that electrical characteristics of the transistor are improved.

As described above, an oxide semiconductor transistor has extremely low off-state current, so that power consumption of a multi-layer semiconductor device can be reduced.

In one embodiment of the disclosed invention, a first oxide semiconductor layer is formed over a first base insulating film in which oxygen in an amount exceeding at least the stoichiometric composition ratio exists in the layer, and the first oxide semiconductor layer is formed. By performing the first heat treatment on the oxide semiconductor layer, oxygen is supplied from the first base insulating film to the first oxide semiconductor layer, and the first heat treatment is performed on the first oxide semiconductor layer. A first conductive film is formed in contact with the oxide semiconductor layer, a part of the first conductive film is removed, a first source electrode and a first drain electrode are formed, and the first oxide A first gate insulating film is formed to cover the semiconductor layer, the first source electrode, and the first drain electrode, and over the first oxide semiconductor layer and the first gate insulating film, Forming a first gate electrode to form a first transistor;
An interlayer insulating film is formed to cover the first gate insulating film and the first gate electrode, and an amount of oxygen exceeding at least the stoichiometric composition ratio exists in the layer on the interlayer insulating film. A second base insulating film is formed, a second oxide semiconductor layer is formed over the second base insulating film, and a second oxide semiconductor layer is formed on the first oxide semiconductor layer and the second oxide semiconductor layer. By performing the heat treatment of 2,
Oxygen is supplied from the first base insulating film to the first oxide semiconductor layer and from the second base insulating film to the second oxide semiconductor layer, and the second heat treatment is performed. A second conductive film is formed in contact with the second oxide semiconductor layer, a part of the second conductive film is removed, a second source electrode and a second drain electrode are formed; A second gate insulating film is formed to cover the second oxide semiconductor layer, the second source electrode, and the second drain electrode, and the second oxide semiconductor layer and the second gate are formed. The present invention relates to a method for manufacturing a semiconductor device, in which a second transistor is formed by forming a second gate electrode over an insulating film.

In one embodiment of the disclosed invention, the first base insulating film and the second base insulating film are
Each includes silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, or gallium oxide.

In one embodiment of the disclosed invention, the channel formation region of the first transistor is shorter than the channel formation region of the second transistor.

In one embodiment of the disclosed invention, the threshold voltage of the first transistor and the threshold voltage of the second transistor are the same.

According to one embodiment of the disclosed invention, an oxide semiconductor transistor with uniform electrical characteristics can be obtained in a semiconductor device in which oxide semiconductor transistors are three-dimensionally layered and stacked.

2A and 2B are a cross-sectional view and a plan view of a semiconductor device. 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device. 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device. 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device. 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device. FIG. 6 is a plan view and a circuit diagram of a semiconductor device. The figure which shows Vg-Id characteristic. The circuit diagram explaining CPU. The figure explaining PLD. The figure which shows the example of an electric equipment. The figure which shows the example of an electric equipment. The figure which shows the example of an electric equipment.

Hereinafter, embodiments of the invention disclosed in this specification will be described with reference to the drawings. However, the invention disclosed in this specification can be implemented in many different modes, and various changes can be made in form and details without departing from the spirit and scope of the invention disclosed in this specification. It will be readily understood by those skilled in the art. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the drawings described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted. In addition, the same hatch pattern is used when referring to the same thing, and there is a case where no reference numeral is given.

Note that in the invention disclosed in this specification, a semiconductor device refers to all elements and devices that function by utilizing a semiconductor, an electric device including an electronic circuit, a display device, a light-emitting device, a memory device, and the like, and the electric device The category is electrical equipment equipped with the device.

Note that the position, size, range, and the like of each component illustrated in the drawings and the like may not represent the actual position, size, range, or the like for easy understanding of the description. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like.

It should be noted that ordinal numbers such as “first”, “second”, “third”, etc. in this specification and the like are added to avoid confusion between components and are not limited numerically. To do.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring”
The reverse is also true. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

In addition, the functions of “source” and “drain” may be switched when transistors having different polarities are employed, or when the direction of current changes during circuit operation. For this reason,
In this specification, the terms “source” and “drain” can be used interchangeably.

Note that in this specification and the like, “electrically connected” includes a case of being connected via “something having an electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets.
For example, “things that have some electrical action” include electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

In this specification and the like, the term “substantially equal” regarding thickness is not only in the case of being completely equal,
It is used for the purpose including the case where it is substantially equal. For example, “substantially equal” means that the influence on the characteristics of the semiconductor device is negligible (the influence on the characteristics is 5% or less) compared to the case where it is completely equal, or is slightly unintentionally. (When the polishing amount is less than about 5 nm) and the like.

In the present specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between the constituent elements is “directly above” or “directly below”. For example, the expression “a gate electrode over a gate insulating film” does not exclude an element including another component between the gate insulating film and the gate electrode.

[Embodiment 1]
FIG. 1A illustrates a cross section of a semiconductor device having a multi-layer structure in which oxide semiconductor transistors having different channel lengths are stacked. FIG. 1B is a plan view of the semiconductor device.
FIG. 2A is a cross-sectional view taken along line X1-X2 in FIG. First transistor 10 shown in FIG.
The 0 and second transistors 110 are top gate structures and are examples of an oxide semiconductor transistor including an oxide semiconductor layer as an active layer.

As shown in FIG. 1, a substrate 10 having an insulating surface provided with a first base insulating film 102 is provided.
An oxide semiconductor transistor (first transistor 100) provided in a lower layer (first formed), and an upper layer provided on the first transistor 100 with the second interlayer insulating film 108 interposed therebetween. An oxide semiconductor transistor (second transistor 110) provided in a hierarchy (formed later) is stacked.

In this embodiment mode, a transistor having a lower threshold voltage (first transistor 1
00), a transistor having a short channel length is used. In this embodiment, a transistor having a long channel length is used as the transistor having the higher threshold voltage (second transistor 110). By forming the first transistor 100 with a short channel length in the lower layer and taking a long heat treatment time, and forming the second transistor 110 with a long channel length in the upper layer and taking a short heat treatment time, It is possible to make the threshold voltage the same.

A transistor having a lower threshold voltage when the heat treatment time is the same;
As another example of a transistor having a higher threshold voltage, a transistor with a high oxygen vacancy density in an oxide semiconductor layer and a transistor with a low oxygen vacancy density in an oxide semiconductor layer can be given. As described above, when the heat treatment time is the same, examples of a transistor with different threshold voltages include a transistor with a different channel length and a transistor with a different oxygen deficiency density. Transistors having different threshold voltages may be formed by changing the configuration.

A first transistor 100 illustrated in FIG. 1 includes a first oxide semiconductor layer 103 and a first oxide semiconductor layer 10 over a substrate 101 having an insulating surface provided with a first base insulating film 102.
3, an electrode 104 a that is one of the first source electrode and the first drain electrode and an electrode 104 b that is the other of the first source electrode and the first drain electrode. In addition, the first transistor 100 illustrated in FIG. 1 includes a first oxide semiconductor layer 103 and an electrode 10.
4a and a first gate insulating film 105 covering the electrode 104b. Further, the first transistor 100 illustrated in FIG. 1 includes a first gate electrode 106 provided over the first oxide semiconductor layer 103 with the first gate insulating film 105 interposed therebetween. A first interlayer insulating film 107 and a second interlayer insulating film 108 are provided so as to cover the first gate insulating film 105 and the first gate electrode 106. In addition, the first interlayer insulating film 107 and the second interlayer insulating film 108
, A second base insulating film 112, a second gate insulating film 115, and a third interlayer insulating film 11 described later.
7 and the first gate electrode 106 through the opening provided in the fourth interlayer insulating film 118.
The electrode 109 is electrically connected to the fourth interlayer insulating film 118. Further, the first interlayer insulating film 107, the second interlayer insulating film 108, and a second base insulating film 112 described later.
The electrode 149 that is electrically connected to the electrode 104b through the opening provided in the second gate insulating film 115, the third interlayer insulating film 117, and the fourth interlayer insulating film 118 has a fourth shape. On the interlayer insulating film. Note that an electrode electrically connected to the electrode 104a is an electrode 10a.
9 and the electrode 149 may be provided on the fourth interlayer insulating film.

A second transistor 110 is provided over the first interlayer insulating film 107 and the second interlayer insulating film 108. A second transistor 110 illustrated in FIG. 1 includes a second oxide semiconductor layer 113 and a second source electrode or a second drain in contact with the second oxide semiconductor layer 113 over a second base insulating film 112. The electrode 114a, which is one of the electrodes, and the second source electrode or second
Electrode 114b which is the other of the drain electrodes. In addition, the second transistor 110 illustrated in FIG. 1 includes the second oxide semiconductor layer 113, the electrode 114a, and the second gate insulating film 115 that covers the electrode 114b. The second transistor 1 shown in FIG.
10 includes a second gate electrode 116 provided over the second oxide semiconductor layer 113 with the second gate insulating film 115 interposed therebetween. A third interlayer insulating film 117 and a fourth interlayer insulating film 118 are provided so as to cover the second gate insulating film 115 and the second gate electrode 116. The second gate insulating film 115, the third interlayer insulating film 117, and the fourth interlayer insulating film 1
An electrode 159 that is electrically connected to the electrode 114 a is provided on the fourth interlayer insulating film 118 through the opening provided in 18. Note that the second gate electrode 116 and the electrode 11 are provided.
Similarly to the electrode 159, an electrode electrically connected to 4b may be provided over the fourth interlayer insulating film 118.

A wiring layer (not shown) may be further provided on the fourth interlayer insulating film 118.

Note that the first base insulating film 102 described in this embodiment mode is an example in which the first base insulating film 102a and the first upper base insulating film 102b are stacked. In addition, an example is shown in which the second base insulating film 112 is formed by stacking a second lower base insulating film 112a and a second upper base insulating film 112b.

In addition, the first gate insulating film 105 described in this embodiment is a first lower gate insulating film 105a.
In addition, an example in which the first upper gate insulating film 105b is stacked is shown. The second gate insulating film 115 includes the second lower gate insulating film 115a and the second upper gate insulating film 1.
An example in which a stack of 15b is formed is shown.

A first upper base insulating film 102b in contact with a lower portion of the first oxide semiconductor layer 103; and a second
The second upper base insulating film 112b in contact with the lower portion of the oxide semiconductor layer 113 is an insulating layer in which oxygen in the layer (in the bulk) has an amount of oxygen exceeding at least the stoichiometric composition ratio. Oxygen can be supplied to each of the oxide semiconductor layer 103 and the second oxide semiconductor layer 113, so that oxygen defects in the oxide semiconductor layer can be filled.

For example, in the case where silicon oxide is used for the first upper layer base insulating film 102b and the second upper layer base insulating film 112b, SiO _{2 + α} (where α> 0) is set. By using the first upper base insulating film 102b and the second upper base insulating film 112b, oxygen is supplied to each of the first oxide semiconductor layer 103 and the second oxide semiconductor layer 113. And the characteristics of the oxide semiconductor layer can be improved.

Note that not only the first upper base insulating film 102b and the second upper base insulating film 112b, but also the first lower gate insulating film 105a in contact with the upper part of the first oxide semiconductor layer 103, and the second
Each of the second lower gate insulating films 115a in contact with the top of the oxide semiconductor layer 113 is
When the insulating layer includes oxygen in an amount exceeding the stoichiometric composition ratio in the layer (in the bulk), oxygen is supplied to each of the first oxide semiconductor layer 103 and the second oxide semiconductor layer 113. And the characteristics of the oxide semiconductor layer can be improved.

First lower base insulating film 102a, first upper gate insulating film 105b, first interlayer insulating film 1
07 is preferably an insulating layer having a barrier property against impurities such as hydrogen, moisture, hydride, or hydroxide, and oxygen. By applying a material having a barrier property to the insulating layer, impurities from the outside are prevented from being mixed, and the first oxide semiconductor layer 103, the first upper base insulating film 102b, and the first lower gate insulating film are used. Desorption of oxygen from 105a can be prevented.

The second lower base insulating film 112a, the second upper gate insulating film 115b, and the third interlayer insulating film 117 have a barrier property against impurities such as hydrogen, moisture, hydride, or hydroxide, and oxygen. The insulating layer is preferably included. By applying a material having a barrier property to the insulating layer, entry of impurities from the outside is prevented, and the second oxide semiconductor layer 113 and the second oxide semiconductor layer 113 are formed.
Desorption of oxygen from the upper base insulating film 112b and the second lower gate insulating film 115a can be prevented.

As the substrate 101, a quartz substrate, a glass substrate, or the like is used. In this embodiment, a glass substrate is used as the substrate 101.

Of the first base insulating film 102, the first lower base insulating film 102a is an insulating layer having a barrier property against impurities such as hydrogen, moisture, hydride, or hydroxide and oxygen as described above. Preferably there is. Such an insulating layer can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, gallium oxide, or a mixed material thereof. In particular, aluminum oxide is preferable because it has a high barrier property against impurities such as hydrogen, moisture, hydride, or hydroxide, and oxygen.

Note that in this specification, oxynitridation refers to a composition having a higher oxygen content than nitrogen, and nitridation oxidation refers to a composition having a higher nitrogen content than oxygen. Shall. Here, the content of oxygen and nitrogen is determined by Rutherford backscattering method (RBS: R
username Backscattering Spectrometry (HFS) or Hydrogen Forward Scattering
It shall be measured using Spectrometry.

Of the first base insulating film 102, the first upper base insulating film 102b is an insulating layer in which oxygen in the layer (in the bulk) has an amount of oxygen exceeding the stoichiometric composition ratio as described above. Preferably there is. As the first upper-layer base insulating film 102b, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, gallium oxide, or the like can be formed by a plasma CVD method, a sputtering method, or the like. It can be formed using a mixed material. The first upper base insulating film 102b
Even if the material of the first lower base insulating film 102a is the same, the first upper base insulating film 102b has at least oxygen in an amount exceeding the stoichiometric composition ratio in the layer (in the bulk). It is preferable to do. In order to form such a first upper-layer base insulating film 102b, for example, oxygen may be added to the insulating layer after the insulating layer is formed. In this embodiment, a 300-nm-thick silicon oxide film is used as the first base insulating film 102.

As the oxide semiconductor used for the first oxide semiconductor layer 103, at least indium (I
n) or zinc (Zn) is preferably included. In particular, In and Zn are preferably included.
In addition, it is preferable to include gallium (Ga) in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Aluminum (Al) as a stabilizer
It is preferable to have. Moreover, it is preferable to have a zirconium (Zr) as a stabilizer.

In addition, as other stabilizers, lanthanoids such as lanthanum (La), cerium (
Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium ( Tm), ytterbium (Yb), or lutetium (Lu) may be used alone or in combination.

For example, as the first oxide semiconductor layer 103, indium oxide, tin oxide, zinc oxide, an In—Zn-based oxide, an Sn—Zn-based oxide, or an Al—Zn-based oxide that is an oxide of a binary metal Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide, In-Ga-Zn-based oxide which is an oxide of a ternary metal (also referred to as IGZO) ), In
-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-
Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-L
a-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd
-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-
Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Z
n-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn
-Based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Z that is an oxide of a quaternary metal
n-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In
-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Z
An n-based oxide can be used.

Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. In and G
Metal elements other than a and Zn may be contained.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0) may be used as the oxide semiconductor. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. As an oxide semiconductor, In ₂ SnO ₅ (ZnO) _n (n> 0)
A material represented by may be used.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Ga: Z
n = 2: 2: 1 (= 2/5: 2/5: 1/5), or In: Ga: Zn = 3: 1: 2
An In—Ga—Zn-based oxide having an atomic ratio of (= 1/2: 1/6: 1/3) or an oxide in the vicinity of the composition thereof can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3:
1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1/2) or In: Sn: Zn = 2: 1: 5 (= 1 / 4: 1/8: 5/8) atomic ratio In-Sn
A Zn-based oxide or an oxide in the vicinity of the composition may be used.

In addition to a single crystal oxide semiconductor, a polycrystalline (also referred to as polycrystal) oxide semiconductor, or an amorphous oxide semiconductor, an oxide semiconductor disclosed in this embodiment includes a CAAC-OS (C
Axis Aligned Crystalline-Oxide Semiconductor
ctor).

The CAAC-OS is not completely single crystal nor completely amorphous. CAAC-OS
An oxide semiconductor having a crystal-amorphous mixed phase structure in which an amorphous phase has a crystal part. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. In addition, transmission electron microscope (TEM: Transmission Electron Microsco)
In the observation image by pe), the boundary between the amorphous part and the crystal part included in the CAAC-OS is not clear. Further, a grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS by TEM. Therefore, in CAAC-OS, reduction in electron mobility due to grain boundaries is suppressed.

The crystal part included in the CAAC-OS has a c-axis aligned in a direction perpendicular to the formation surface or surface of the CAAC-OS and a triangular or hexagonal atomic arrangement when viewed from the direction perpendicular to the ab plane. , When viewed from the direction perpendicular to the c-axis, metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, a simple term “perpendicular” includes a range from 85 ° to 95 °.

Note that in the CAAC-OS, the distribution of crystal parts may not be uniform. For example, CAAC
In the -OS formation process, in the case where crystal growth is performed from the surface side of the oxide semiconductor layer, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor layer may increase in the vicinity of the surface. CAAC
When an impurity is added to -OS, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

Since the c-axis of the crystal part included in the CAAC-OS is aligned in a direction perpendicular to the formation surface or surface of the CAAC-OS, the shape of the CAAC-OS (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface)
Depending on the situation, they may face different directions. The c-axis direction of the crystal part is CAAC
-A direction perpendicular to the surface or surface where the OS is formed. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

A transistor using a CAAC-OS can reduce variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

Note that part of oxygen included in the first oxide semiconductor layer 103 may be replaced with nitrogen.

Further, in an oxide semiconductor having a crystal part such as a CAAC-OS, defects in a bulk can be further reduced, and mobility higher than that of an oxide semiconductor in an amorphous state can be obtained by increasing surface flatness. . In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on the flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.
. It may be formed on the surface of 3 nm or less, more preferably 0.1 nm or less.

Ra is a three-dimensional extension of the centerline average roughness defined in JIS B0601 so that it can be applied to a surface. “A value obtained by averaging the absolute values of deviations from a reference surface to a specified surface” Can be expressed. Ra is an atomic force microscope (AFM).
Evaluation can be made at Microscope).

In this embodiment, the first oxide semiconductor layer 103 has an In—Ga—Z thickness of 10 nm.
An n-based oxide (also referred to as IGZO) film is used.

As described above, in this specification, a region in contact with the source electrode in the oxide semiconductor layer is referred to as a source region, and a region in contact with the drain electrode in the oxide semiconductor layer is referred to as a drain region. A region between the source region and the drain region in the oxide semiconductor layer and overlapping with the gate electrode is referred to as a channel formation region. Therefore, in FIG. 1, the region where the first oxide semiconductor layer 103 and the electrodes 104 a and 104 b which are the first source electrode and the first drain electrode are in contact with each other are the first source region and the first drain region. It becomes. In FIG. 1, a region overlapping with the first gate electrode 106 in a region between the first source region and the first drain region is a first channel formation region.

As a material of the electrode 104a and the electrode 104b which are the first source electrode and the first drain electrode, for example, aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta)
, Titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), a metal film containing an element selected from scandium (Sc), or a metal nitride film containing the above elements as a component (nitriding) A titanium film, a molybdenum nitride film, a tungsten nitride film, or the like can be used. Moreover, high or low such as titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta) or the like on one or both of the lower side or upper side of a low resistance metal film such as aluminum (Al), copper (Cu), etc. A structure in which a melting point metal film or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is stacked may be employed. It is preferable to stack a refractory metal film or a metal nitride film thereof on one or both of the lower resistance metal film and the lower resistance metal film, because the metal migration (diffusion) of the low resistance metal film can be inhibited. . That is, each of the electrode 104a and the electrode 104b is a stack of a first conductive layer, a metal film that is a second conductive layer, and a third conductive layer, and a low-resistance conductive layer is used as the second conductive layer. . A material capable of inhibiting the movement of the metal of the second conductive layer is used for at least one of the first conductive layer and the third conductive layer. Further, when the third conductive layer on the second conductive layer covers the end portion of the second conductive layer,
This is preferable because the movement of the metal from the end of the conductive layer can be suppressed.

For example, as the electrode 104a and the electrode 104b, tungsten (W), copper (Cu)
A layer of tantalum nitride is used, and low resistance copper (Cu) may be sandwiched between tungsten (W) and tantalum nitride that inhibit the movement of copper.

Further, each of the electrode 104a and the electrode 104b may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ) and tin oxide (SnO
₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ , abbreviated as ITO), indium zinc oxide (In ₂ O ₃ —ZnO) or silicon oxide on these metal oxides What was included can be used.

In this embodiment, a 30-nm-thick tungsten film is used as the electrodes 104a and 104b.

The first gate insulating film 105 includes an insulating layer in which oxygen in an amount exceeding at least the stoichiometric composition ratio exists in the layer (in the bulk) from the side closer to the first oxide semiconductor layer 103, and hydrogen And an insulating layer having a barrier property against impurities such as moisture, hydride, or hydroxide, and oxygen. In other words, the first lower gate insulating film 105a is an insulating layer in which oxygen in the layer (in the bulk) has an amount of oxygen exceeding the stoichiometric composition ratio, and the first upper gate insulating film 105b is formed of hydrogen. It is an insulating layer having a barrier property against impurities such as moisture, hydride, or hydroxide, and oxygen. By forming the first gate insulating film 105 as a stack of such insulating layers, oxygen is supplied to the first oxide semiconductor layer 103 and the first oxide semiconductor layer 103 is supplied.
The desorption of oxygen from can be suppressed.

As the material of the first lower gate insulating film 105a, the same material as that of the first upper base insulating film 102b can be used. Further, as the material of the first upper gate insulating film 105b, the same material as that of the first lower base insulating film 102a can be used.

In this embodiment, a silicon nitride oxide film with a thickness of 20 nm is used as the first gate insulating film 105.

As a material of the first gate electrode 106, molybdenum, titanium, tantalum, tungsten,
A metal material such as aluminum, copper, chromium, neodymium, or scandium, a metal nitride material including the above-described element as a component, or an alloy material including the above-described element as a component can be used. Alternatively, as the first gate electrode 106, a semiconductor layer typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. The first gate electrode 106 may have a single-layer structure or a stacked structure.

The material of the first gate electrode 106 is indium oxide tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide. , Indium zinc oxide,
A conductive material such as indium tin oxide to which silicon oxide is added can also be used. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

Further, as a material of the first gate electrode 106, a metal oxide containing nitrogen, specifically, an In—Ga—Zn-based metal oxide containing nitrogen, an In—Sn-based metal oxide containing nitrogen, Use of an In—Ga-based metal oxide containing nitrogen, an In—Zn-based metal oxide containing nitrogen, a tin oxide containing nitrogen, an indium oxide containing nitrogen, or a metal nitride film (InN, SnN, etc.) Can do. These materials have a work function of 5 eV (electron volts) or more, and the first gate electrode 1
When used as 06, the threshold voltage of the electrical characteristics of the first transistor 100 can be shifted in the positive direction.

In this embodiment, a stacked layer of a tantalum nitride film with a thickness of 30 nm and a tungsten film with a thickness of 135 nm is used as the first gate electrode 106.

The first interlayer insulating film 107 is preferably formed using a material having a barrier property against impurities such as hydrogen, moisture, hydride, or hydroxide, and oxygen. The first interlayer insulating film 107 can be formed using the same material as that of the first upper base insulating film 102b and the first lower gate insulating film 105a.

The second interlayer insulating film 108 is formed with a thickness capable of flattening unevenness caused by the layers formed on the substrate 101 so far. In this embodiment, silicon oxynitride is formed to a thickness of 460 nm as the second interlayer insulating film 108.

After the second interlayer insulating film 108 is formed, oxygen is supplied to the second interlayer insulating film 108 so that the second interlayer insulating film 108 is in an oxygen-excess state. This is preferable because oxygen can be supplied to the oxide semiconductor layer 103.

In this embodiment, aluminum oxide with a thickness of 70 nm is used as the first interlayer insulating film 107. As the second interlayer insulating film 108, a silicon nitride oxide film with a thickness of 460 nm is used.

On the second interlayer insulating film 108, a second lower base insulating film 112a and a second upper base insulating film 112b are provided. The second lower base insulating film 112a and the second upper base insulating film 112b are respectively the first lower base insulating film 102a and the first upper base insulating film 102.
What is necessary is just to provide like b.

Note that in this embodiment mode, the second base insulating film 112 (the second lower base insulating film 112a and the second upper base insulating film) is formed over the first interlayer insulating film 107 and the second interlayer insulating film 108. 112
Although the structure which provides b) was demonstrated, it is not limited to this. The first interlayer insulating film 107 and the second interlayer insulating film 108 form the second base insulating film 112 (second lower base insulating film 112a).
In the case of fulfilling the function of the second upper base insulating film 112b), the second base insulating film 112 is not necessarily provided.

In this embodiment, a 330 nm-thick silicon oxide film is used as the second base insulating film 112.

The second oxide semiconductor layer 113 may be provided similarly to the first oxide semiconductor layer 103. In this embodiment, the second oxide semiconductor layer 113 has an In—Ga—Zn thickness of 10 nm.
A system oxide (also referred to as IGZO) film is used.

As described above, in this specification, a region in contact with the source electrode in the oxide semiconductor layer is referred to as a source region, and a region in contact with the drain electrode in the oxide semiconductor layer is referred to as a drain region. A region between the source region and the drain region in the oxide semiconductor layer and overlapping with the gate electrode is referred to as a channel formation region. Therefore, in FIG. 1, the region where the second oxide semiconductor layer 113 and the electrodes 114 a and 114 b which are the second source electrode and the second drain electrode are in contact with each other are the second source region and the second drain region. It becomes. In FIG. 1, a region overlapping with the second gate electrode 116 in a region between the second source region and the second drain region is a second channel formation region.

The channel length L1 of the first transistor 100 is shorter than the channel length L2 of the second transistor 110. Although details will be described later, the heat treatment time performed on the first transistor 100 is longer than the heat treatment time performed on the second transistor 110. Accordingly, the amount of oxygen supplied to the first oxide semiconductor layer 103 of the first transistor 100 is larger than that of the second oxide semiconductor layer 113 of the second transistor 110. Therefore, the shift amount of the threshold voltage of the first transistor 100 in the positive direction is larger than that of the second transistor 110. In this manner, by setting the heat treatment time of the first transistor 100 with a short channel length to be longer than the heat treatment time of a transistor with a long channel length, the threshold voltages of the first transistor 100 and the second transistor 110 can be set. The same can be done. Therefore, the electrical characteristics of the first transistor 100 and the second transistor 110 can be made uniform.

The second gate insulating film 115 includes an insulating layer in which oxygen in an amount exceeding at least the stoichiometric composition ratio exists in the layer (in the bulk) from the side closer to the second oxide semiconductor layer 113, and hydrogen And an insulating layer having a barrier property against impurities such as moisture, hydride, or hydroxide, and oxygen. In other words, the second lower gate insulating film 115a is an insulating layer in which oxygen in an amount exceeding at least the stoichiometric composition ratio exists in the layer (in the bulk), and the second upper gate insulating film 115b is formed of hydrogen. It is an insulating layer having a barrier property against impurities such as moisture, hydride, or hydroxide, and oxygen. By forming the second gate insulating film 115 as a stack of such insulating layers, oxygen is supplied to the second oxide semiconductor layer 113 and the second oxide semiconductor layer 113 is used.
The desorption of oxygen from can be suppressed.

As the material of the second lower gate insulating film 115a, the same material as that of the first lower gate insulating film 105a can be used. As the material of the second upper gate insulating film 115b, the first
A material similar to that of the upper gate insulating film 105b can be used.

In this embodiment, a 20-nm-thick silicon nitride oxide film is used as the second gate insulating film 115.

As a material of the second gate electrode 116, a material similar to that of the first gate electrode 106 can be used. In this embodiment, a stacked layer of a tantalum nitride film with a thickness of 30 nm and a tungsten film with a thickness of 135 nm is used as the second gate electrode 116.

The third interlayer insulating film 117 and the fourth interlayer insulating film 118 are respectively composed of the first interlayer insulating film 1
07 and the second interlayer insulating film 108 can be used. In this embodiment, as the third interlayer insulating film 117, an aluminum oxide film with a thickness of 70 nm, and
As the fourth interlayer insulating film 118, a silicon nitride oxide film with a thickness of 460 nm is used.

Note that in the first transistor 100 and the second transistor 110 of this embodiment,
Although the source electrode and the drain electrode are provided in contact with the oxide semiconductor layer over the oxide semiconductor layer functioning as the active layer, this embodiment is not limited thereto. The source electrode and the drain electrode may be provided below the oxide semiconductor layer and in contact with the oxide semiconductor layer.

According to this embodiment, an oxide semiconductor transistor with uniform electrical characteristics can be obtained in a semiconductor device in which oxide semiconductor transistors are three-dimensionally layered and stacked.

[Embodiment 2]
In this embodiment, a method for manufacturing the semiconductor device described in Embodiment 1 will be described.

First, a first lower base insulating film 102a and a first upper base insulating film 102 are formed on a substrate 101.
A first base insulating film 102 having b is formed (see FIG. 2A).

First base insulating film 102 (first lower base insulating film 102a and first upper base insulating film 10)
2b) uses the above-mentioned materials and is formed, for example, by plasma CVD or sputtering. Note that as described above, in the case where a thermal oxide film is used as the first lower base insulating film 102a, for example, a single crystal silicon substrate is used as the substrate 101, and an atmosphere containing oxygen or an atmosphere containing water vapor is used. By performing a heat treatment for several hours at a temperature of from 1 to 1200 ° C., the substrate 10
A thermal oxide film can be formed on the surface of 1.

The temperature at which the first base insulating film 102 is formed is preferably equal to or lower than the temperature that the substrate 101 can withstand. For example, the temperature of the substrate 101 is 25 ° C. or higher and 250 ° C. or lower, preferably 50 ° C.
The first base insulating film 102 is formed while being heated to 150 ° C. or higher. Note that the temperature at which the first base insulating film 102 is formed is preferably constant. For example, the first base insulating film 1
02 is formed by heating the substrate 101 to 100.degree.

Further, after the first base insulating film 102 is formed, heat treatment may be performed under reduced pressure, a nitrogen atmosphere, a rare gas atmosphere, or an ultra-dry air nitrogen atmosphere. By the heat treatment, the concentration of hydrogen, moisture, hydride, hydroxide, or the like contained in the first base insulating film 102 can be reduced. The degree of heat treatment is preferably equal to or lower than a temperature that the substrate 101 can withstand and higher. Specifically, it is preferable that the temperature be higher than the deposition temperature of the first base insulating film 102 and lower than the strain point of the substrate 101.

Note that the hydrogen concentration of the first base insulating film 102 is less than 5 × 10 ¹⁸ atoms / cm ³ , preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms.
/ Cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or less.

In order for oxygen to exist at least in a stoichiometric composition ratio in the first upper base insulating film 102b (in the bulk), oxygen may be supplied to the first upper base insulating film 102b. Good.

By supplying oxygen, a bond between an element constituting the first upper base insulating film 102b and hydrogen, or a bond between the element and a hydroxyl group is cut, and these hydrogen or hydroxyl group reacts with oxygen. When heat treatment is performed after supply of oxygen in order to generate water, impurities such as hydrogen or a hydroxyl group are easily released as water. Therefore, the first upper base insulating film 102b
Heat treatment may be performed after supplying oxygen. Thereafter, a further first upper base insulating film 1
Oxygen may be supplied to 02b so that the first upper base insulating film 102b is in an oxygen-excess state.
Further, the supply of oxygen to the first upper base insulating film 102b and the heat treatment may be alternately performed a plurality of times. Further, heat treatment and oxygen supply may be performed at the same time.

Next, the first oxide semiconductor layer 123 is formed over the first base insulating film 102 by a sputtering method (see FIG. 2B).

In the formation step of the first oxide semiconductor layer 123, hydrogen is added to the first oxide semiconductor layer 123.
Alternatively, in order to prevent water from being contained as much as possible, as a pretreatment for forming the first oxide semiconductor layer 123, a substrate over which the first base insulating film 102 is formed is preliminarily formed in a preheating chamber of a sputtering apparatus. It is preferable to heat and desorb impurities such as hydrogen and moisture adsorbed on the substrate 101 and the first base insulating film 102 and exhaust them. Note that a cryopump is preferable as an exhaustion unit provided in the preheating chamber.

Planarization treatment may be performed on a region where the first oxide semiconductor layer 123 is formed in contact with the first base insulating film 102. Although it does not specifically limit as planarization processing, Polishing processing (for example, chemical mechanical polishing method), dry etching processing, and plasma processing can be used.

As the plasma treatment, for example, reverse sputtering in which an argon gas is introduced to generate plasma can be performed. Reverse sputtering is RF on the substrate side in an argon atmosphere.
In this method, a voltage is applied using a power source to form plasma in the vicinity of the substrate to modify the surface.
Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. When reverse sputtering is performed, powdery substances (also referred to as particles or dust) attached to the surface of the first base insulating film 102 can be removed.

As the planarization treatment, the polishing treatment, the dry etching treatment, and the plasma treatment may be performed a plurality of times or in combination. In the case of performing the combination, the order of steps is not particularly limited, and may be set as appropriate in accordance with the uneven state of the surface of the first base insulating film 102.

For example, the planarization treatment is performed on the surface of the silicon oxide layer used as the first base insulating film 102 by a chemical mechanical polishing (CMP).
(Polishing conditions: polyurethane-based polishing cloth, silica-based slurry, slurry temperature room temperature, polishing pressure 0.001 MPa, polishing rotation speed (table / spindle) 60 rpm / 56)
rpm, polishing time 0.5 minutes), and the average surface roughness (Ra) on the surface of the silicon oxide layer may be about 0.15 nm.

Note that as a sputtering gas for forming the first oxide semiconductor layer 123, a rare gas (typically argon) atmosphere, an oxygen atmosphere, a mixed gas of a rare gas and oxygen is used as appropriate. As the sputtering gas, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed.

Note that the first oxide semiconductor layer 123 has a condition that contains a large amount of oxygen (for example, oxygen 1
The film is formed by sputtering under a 00% atmosphere, etc., and contains a large amount of oxygen or is supersaturated with oxygen (preferably with respect to the stoichiometric composition ratio of the oxide semiconductor in the crystalline state. It is preferable that a region with an excessive content of is included.

For example, when the first oxide semiconductor layer 123 is formed by a sputtering method, the sputtering gas is preferably used under a condition where the proportion of oxygen in the sputtering gas is large, and the sputtering gas is preferably used as 100% oxygen gas.

The first oxide semiconductor layer 123 is preferably a highly purified layer that hardly contains impurities such as copper, aluminum, and chlorine. In the manufacturing process of the transistor, it is preferable to select as appropriate a process in which these impurities are not mixed or attached to the surface of the oxide semiconductor layer. Specifically, the copper concentration of the first oxide semiconductor layer 123 is 1 × 10 ¹⁸ atoms.
s / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³ or less. The aluminum concentration of the first oxide semiconductor layer 123 is 1 × 10 ¹⁸ atoms / cm ³ or less. The chlorine concentration of the first oxide semiconductor layer 123 is 2 × 10 ¹⁸ atoms / cm ³ or less.

The concentration of alkali metal such as sodium (Na), lithium (Li), potassium (K), or the like in the first oxide semiconductor layer 123 is 5 × 10 ¹⁶ cm ⁻³ or less, preferably 1 ×
10 ¹⁶ cm ⁻³ or less, more preferably 1 × 10 ¹⁵ cm ⁻³ or less, and Li is 5 × 10 ^1.
5 cm ⁻³ or less, preferably 1 × 10 ¹⁵ cm ⁻³ or less, and K is 5 × 10 ¹⁵ cm ⁻³ or less, preferably 1 × 10 ¹⁵ cm ⁻³ or less.

In this embodiment, as the first oxide semiconductor layer 123, an In—Ga—Zn-based oxide (IGZO) with a thickness of 35 nm is formed by a sputtering method using a sputtering apparatus having an AC power supply device. As a target for manufacturing by a sputtering method, a metal oxide target having a composition ratio of In: Ga: Zn = 3: 1: 2 [atomic ratio] is used.

The relative density (filling rate) of the metal oxide target is 90% to 100%, preferably 95% to 99.9%. By using a metal oxide target with a high relative density, the formed first oxide semiconductor layer 123 can be a dense film.

As a sputtering gas used for forming the first oxide semiconductor layer 123, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed is preferably used.

First, a substrate is held in a film formation chamber held in a reduced pressure state. Then, a sputtering gas from which hydrogen and moisture are removed is introduced while moisture remaining in the deposition chamber is removed, and the first oxide is formed over the first base insulating film 102 provided over the substrate 101 using the target. A semiconductor layer 123 is formed. In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, the exhaust means may be a turbo molecular pump provided with a cold trap. In the deposition chamber evacuated using a cryopump, for example, a compound containing hydrogen atoms (more preferably a compound containing carbon atoms) such as hydrogen atoms and water (H ₂ O) is exhausted. The concentration of impurities contained in the first oxide semiconductor layer 123 formed in the chamber can be reduced.

Alternatively, the first base insulating film 102 and the first oxide semiconductor layer 123 may be continuously formed without being released to the atmosphere. When the first base insulating film 102 and the first oxide semiconductor layer 123 are continuously formed without being exposed to the air, impurities such as hydrogen and moisture adhere to the surface of the first base insulating film 102. Can be prevented.

After the formation of the first oxide semiconductor layer 123, heat treatment for supplying oxygen from the first base insulating film 102 (particularly, the first upper base insulating film 102b) to the first oxide semiconductor layer 123 is performed.
In the heat treatment, the heating temperature is 150 ° C. or higher and 450 ° C. or lower, and the heat treatment time is defined as heat treatment time T1. The heat treatment time T1 is 1 hour or more and 15 hours or less.

If the heat treatment for supplying oxygen is performed after the formation of the first oxide semiconductor layer 123, the island-shaped first
The oxide semiconductor layer 103 may be formed before or after the formation.

The heat treatment can be performed in an air atmosphere or a reduced pressure atmosphere. For example, the substrate 101 on which the first base insulating film 102 and the first oxide semiconductor layer 123 are formed is introduced into an electric furnace which is one of heat treatment apparatuses, and the atmosphere of the first oxide semiconductor layer 123 is Heat treatment is performed at 200 ° C. for 1 hour.

Next, the first oxide semiconductor layer 123 is processed into an island shape, and the island-shaped first oxide semiconductor layer 1 is processed.
03 is formed. Next, a first conductive film 124 is formed to cover the island-shaped first oxide semiconductor layer 103 and the first base insulating film 102 (see FIG. 2C).

As the first conductive film 124, a film of the material of the electrodes 104a and 104b, which are the first source electrode and the first drain electrode, is formed by a sputtering method or the like. In this embodiment, a 30-nm-thick tungsten film is formed as the first conductive film 124 by a sputtering method.

Next, part of the first conductive film 124 is removed, so that the first source electrode and the first drain electrode 104a and the electrode 104b are formed (see FIG. 2D). More specifically, a resist mask is formed over the first conductive film 124, and part of the first conductive film 124 is selectively etched using the resist mask. After selectively etching part of the first conductive film 124, the resist mask is removed, so that the electrodes 104a and 104b which are the first source electrode and the first drain electrode are formed. The distance between the electrode 104a and the electrode 104b formed by selectively etching a part of the first conductive film 124 is expressed as follows.
Distance D1. That is, the electrode 10 which is the first source electrode and the first drain electrode.
4a and the electrode 104b are formed with a first distance D1 apart.

Next, a first gate insulating film 105 is formed so as to cover the first oxide semiconductor layer 103, the first source electrode, and the electrode 104a and the electrode 104b, which are the first drain electrode (FIG. 2 (
F)).

Note that in order to improve the coverage of the first gate insulating film 105, the first oxide semiconductor layer 1
The above planarization treatment may also be performed on the 03 surface. In particular, when a thin insulating layer is used as the first gate insulating film 105, the surface of the first oxide semiconductor layer 103 is preferably flat.

The thickness of the first gate insulating film 105 is greater than or equal to 1 nm and less than or equal to 20 nm.
An MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like can be used as appropriate. The first gate insulating film 105 may be formed using a so-called CP sputtering apparatus that forms a film with a plurality of substrate surfaces set substantially perpendicular to the surface of the sputtering target. .

Note that as the first gate insulating film 105, a silicon oxide film or silicon oxynitride is used as C
When formed by the VD method, the glow discharge plasma is generated from 3 MHz to 30 MHz, typically 13.56 MHz, 27.12 MHz HF band high frequency power, or VHF band high frequency power from 30 MHz to about 300 MHz, Typically, it is preferably performed by applying 60 MHz. Moreover, it can also carry out by applying the microwave high frequency electric power of 1 GHz or more. Note that pulse oscillation in which high-frequency power is applied in a pulsed manner or continuous oscillation in which high-frequency power is continuously applied can be employed. In a silicon oxide film or silicon oxynitride formed using a microwave of 1 GHz or higher, fixed charge in the film of the first gate insulating film 105 and the interface with the first oxide semiconductor layer 103 has normal plasma. Less than a silicon oxide film or silicon oxynitride formed by CVD. Therefore, reliability of electrical characteristics such as a threshold voltage of the transistor can be increased.

In addition, the first gate insulating film 105 may be a single layer or a stacked layer, but the first oxide semiconductor layer 1
In order from the side closer to 03, the insulating layer (first lower gate insulating film 105a) in which oxygen in the layer (in the bulk) has an amount of oxygen exceeding the stoichiometric composition ratio, and hydrogen, moisture, hydride Or an insulating layer having a barrier property against oxygen and impurities such as hydroxide (first upper gate insulating film 105b), oxygen is supplied to the first oxide semiconductor layer 103, and
This is preferable because release of oxygen from the first oxide semiconductor layer 103 can be suppressed.
In this embodiment, the first lower gate insulating film 105 a is used as the first gate insulating film 105.
And a stack of the first upper gate insulating film 105b.

In addition, before the first gate insulating film 105 is formed, the surface of the first oxide semiconductor layer 103 is subjected to plasma treatment using oxygen, dinitrogen monoxide, a rare gas (typically argon), or the like. It is preferable to remove impurities such as moisture and organic matter adhering to the surface.

Next, a second conductive film 126 for forming the first gate electrode 106 is formed over the first gate insulating film 105 (see FIG. 2F). In this embodiment, a tantalum nitride film with a thickness of 20 nm and a tungsten film with a thickness of 135 nm are stacked as the second conductive film 126.

Next, part of the second conductive film 126 is selectively etched by a photolithography step, so that the first gate electrode 106 having the first gate width G1 is formed (see FIG. 3A).

Note that unless otherwise specified, the photolithography process in this specification includes a resist mask forming process, a conductive layer or insulating layer etching process, and a resist mask peeling process. .

A resist mask for forming the first gate electrode 106 by selectively etching part of the second conductive film 126 may be formed by a printing method or an inkjet method. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used.

Further, the etching for forming the first gate electrode 106 may be a dry etching method or a wet etching method, or both may be used. In order to form a fine pattern, it is preferable to use a dry etching method capable of anisotropic etching.

In the case where the second conductive film 126 is etched by a dry etching method, a gas containing a halogen element can be used as an etching gas. As an example of a gas containing a halogen element, a chlorine-based gas such as chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ), or the like is used. Fluorine gas such as carbon fluoride (CF ₄ ), sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ) or trifluoromethane (CHF ₃ ), hydrogen bromide (HBr) or oxygen Can be used. Further, an inert gas may be added to the etching gas used. Further, as a dry etching method, a parallel plate type RIE (Reactive Ion Etching) method, an ICP (
An Inductively Coupled Plasma) etching method can be used. Etching conditions (such as the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the substrate-side electrode temperature, etc.) are adjusted as appropriate so that the desired processed shape can be etched.

Next, a first interlayer insulating film 107 and a second interlayer insulating film 108 are formed so as to cover the first gate insulating film 105 and the first gate electrode 106 (see FIG. 3B). As described above, the first transistor 100 is manufactured.

In the first transistor 100 illustrated in FIG. 3B, the first distance D <b> 1 that is the distance between the first source electrode and the first drain electrode 104 a and the electrode 104 b is the first gate electrode 106. Shorter than the gate width G1. Therefore, in the first transistor 100, the length L1 of the first channel formation region (channel length L1) is the distance between the first source electrode and the first drain electrode 104a and the electrode 104b. Is equal to the distance D1.

The first interlayer insulating film 107 includes a first upper gate insulating film 105b, a first lower base insulating film 1
It can be formed by the same material and method as 02a. The first interlayer insulating film 107 is preferably formed using a material having a barrier property against impurities such as hydrogen, moisture, hydride, or hydroxide, such as aluminum oxide, or oxygen. In the present embodiment, the first interlayer insulating film 1
As 07, an aluminum oxide film with a thickness of 70 nm is formed by a sputtering method. Furthermore, the aluminum oxide has a high density (density 3.2 g / cm ³ or more, preferably 3.6 g).
/ Cm ³ or more), stable electrical characteristics can be imparted to the first transistor 100. The film density is determined by Rutherford Backscattering Method (RBS).
Backscattering Spectrometry) and X-ray reflectivity measurement method (X
It can be measured by RR: X-Ray Reflection.

In addition, the second interlayer insulating film 108 is formed with a thickness that can flatten the unevenness caused by the layers formed on the substrate 101 so far. In this embodiment, C is used as the second interlayer insulating film 108.
A silicon oxynitride film is formed to a thickness of 460 nm by the VD method.

After the second interlayer insulating film 108 is formed, oxygen is supplied to the second interlayer insulating film 108 so that the second interlayer insulating film 108 is in an oxygen-excess state. This is preferable because oxygen can be supplied to the oxide semiconductor layer 103.

After forming the first interlayer insulating film 107 and the second interlayer insulating film 108, the first base insulating film 102
The second base insulating film 112 (second lower base insulating film 11 is formed using the same material and the same process as
2a and a second upper base insulating film 112b) are formed. However, as described above, the first interlayer insulating film 107 and the second interlayer insulating film 108 form the second base insulating film 112 (the second lower base insulating film 112a and the second upper base insulating film 112b). If it functions as the second
The base insulating film 112 may not be formed.

When the second base insulating film 112 is not formed on the second base insulating film 112 or when the second base insulating film 112 is not formed,
A second oxide semiconductor layer 133 is formed over the interlayer insulating film 108 (see FIG. 3B).
The second oxide semiconductor layer 133 may be formed using a material and a process similar to those of the first oxide semiconductor layer 123.

After the formation of the second oxide semiconductor layer 133, heat treatment for supplying oxygen from the second base insulating film 112 (particularly, the second upper base insulating film 112b) to the second oxide semiconductor layer 133 is performed.
In the heat treatment, the heat treatment temperature is 150 ° C. or higher and 450 ° C. or lower, and the heat treatment time is the heat treatment time T2.
And The heat treatment time T2 is 1 hour or more and 15 hours or less.

The heat treatment time of the first oxide semiconductor layer 123 or the island-shaped first oxide semiconductor layer 103 is the sum of the heat treatment time T1 and the heat treatment time T2. On the other hand, the heat treatment time of the second oxide semiconductor layer 133 or the island-shaped second oxide semiconductor layer 113 formed in a later step is the heat treatment time T2.
It is. That is, the first oxide semiconductor layer 123 or the island-shaped first oxide semiconductor layer 103
The heat treatment time is longer than that of the second oxide semiconductor layer 133 or the island-shaped second oxide semiconductor layer 113. When the heat treatment time is long, an insulating layer (in the case of the first oxide semiconductor layer 123, the first upper base insulating film 102b) in which oxygen in the layer (in the bulk) has an amount of oxygen exceeding the stoichiometric composition ratio is present. In the case of the second oxide semiconductor layer 133, the second upper base insulating film 112b)
The amount of oxygen supplied from the air increases. Therefore, the amount of oxygen supplied to the first oxide semiconductor layer 123 or the island-shaped first oxide semiconductor layer 103 is the amount of oxygen supplied to the second oxide semiconductor layer 133 or the island-shaped second oxide semiconductor layer. The amount of oxygen supplied to 113 is large. When the amount of oxygen supplied to the oxide semiconductor layer functioning as the active layer of the transistor is large, the shift amount of the threshold voltage of the transistor in the positive direction increases. As a result, the shift amount of the threshold voltage of the first transistor 100 in the positive direction is larger than that of the second transistor 110.

The heat treatment for supplying oxygen may be performed before or after the formation of the island-shaped second oxide semiconductor layer 113 as long as it is after the formation of the second oxide semiconductor layer 133. .

The heat treatment can be performed in an air atmosphere or a reduced pressure atmosphere. For example, the substrate 10 in which a stacked structure up to the second oxide semiconductor layer 133 is formed in an electric furnace which is one of heat treatment apparatuses.
1 is introduced, and the second oxide semiconductor layer 133 is subjected to heat treatment at 200 ° C. in an air atmosphere for 5 hours.

Next, the second oxide semiconductor layer 133 is processed into an island shape, and the island-shaped second oxide semiconductor layer 1 is processed.
13 is formed. Next, a third conductive film 134 is formed in contact with the island-shaped second oxide semiconductor layer 113 (see FIG. 3D). The third conductive film 134 may be formed using the same material and the same process as the first conductive film 124.

Next, part of the third conductive film 134 is removed, so that the electrode 114a and the electrode 114b which are the second source electrode and the second drain electrode are formed (see FIG. 4A). Third
Part of the conductive film 134 is removed to form the second source electrode and the second drain electrode 1
About the method of forming 14a and the electrode 114b, what is necessary is just to form similarly to the electrode 104a and the electrode 104b which are the 1st source electrode and the 1st drain electrode. Third conductive film 13
A distance between the electrode 114a and the electrode 114b formed by selectively etching a part of 4 is a second distance D2. That is, the electrode 114a and the electrode 114b which are the second source electrode and the second drain electrode are formed apart from each other by the second distance D2.

Next, a second gate insulating film 115 is formed so as to cover the second oxide semiconductor layer 113, the electrodes 114a and 114b which are the second source electrode and the second drain electrode (FIG. 4 (
B)). The second gate insulating film 115 may be formed using the same material and the same process as the first gate insulating film 105.

Next, a fourth conductive film 136 for forming the second gate electrode 116 is formed over the second gate insulating film 115 (see FIG. 4C). The fourth conductive film 136 is the second conductive film 12.
6 may be formed by using the same material and the same process as 6.

Next, part of the fourth conductive film 136 is selectively etched by a photolithography process, so that the second gate electrode 116 having the second gate width G2 is formed (see FIG. 5A). A method for selectively etching part of the fourth conductive film 136 to form the second gate electrode 116 may be formed by a method similar to that for the first gate electrode 106.

Next, a third interlayer insulating film 117 and a fourth interlayer insulating film 118 are formed so as to cover the second gate insulating film 115 and the second gate electrode 116 (see FIG. 5B). The third interlayer insulating film 117 and the fourth interlayer insulating film 118 are composed of the first interlayer insulating film 107 and the second interlayer insulating film 1.
What is necessary is just to form like 08. As described above, the second transistor 110 is manufactured.

In the second transistor 110 illustrated in FIG. 5B, the second distance D2, which is the distance between the electrode 114a and the electrode 114b which are the second source electrode and the second drain electrode, is the second gate electrode 116. Shorter than the gate width G2. Therefore, in the second transistor 110, the length L2 of the second channel formation region (channel length L2) is the same as that of the second source electrode and the second source electrode.
This is equivalent to the second distance D2 which is the distance between the electrode 114a and the electrode 114b which are the drain electrodes of the first electrode.

As described above, the heat treatment time performed on the first transistor 100 is the second transistor 1.
10 is longer than the heat treatment time performed. Accordingly, the amount of oxygen supplied to the first oxide semiconductor layer 103 of the first transistor 100 is larger than that of the second oxide semiconductor layer 113 of the second transistor 110. Therefore, the shift amount of the threshold voltage of the first transistor 100 in the positive direction is larger than that of the second transistor 110. On the other hand, the channel length L 1 of the first transistor 100 is shorter than the channel length L 2 of the second transistor 110. As the channel length of the transistor becomes shorter, the threshold voltage of the transistor shifts in the negative direction.

In this embodiment, the channel length L1 of the first transistor 100 with a long heat treatment time is formed to be shorter than the channel length L2 of the second transistor 110 with a short heat treatment time. Accordingly, the threshold voltages of the first transistor 100 and the second transistor 110 can be made similar. Therefore, the electrical characteristics of the first transistor 100 and the second transistor 110 can be made uniform.

After forming the fourth interlayer insulating film 118, the first interlayer insulating film 107, the second interlayer insulating film 108,
A second base insulating film 112, a second gate insulating film 115, a third interlayer insulating film 117, and
A part of each of the fourth interlayer insulating films 118 is removed to form an opening reaching the first gate electrode 106 (not shown). A conductive film is formed over the fourth interlayer insulating film 118, and a part of the conductive film is removed by etching or the like, whereby the first gate is formed over the fourth interlayer insulating film 118 through the opening. An electrode 109 reaching the electrode 106 can be formed (see FIG. 1). Note that a wiring layer electrically connected to another electrode may be provided over the fourth interlayer insulating film 118 if necessary.

Note that in the method for manufacturing the first transistor 100 and the second transistor 110 in this embodiment, after the oxide semiconductor layer functioning as an active layer is formed, a source electrode and a drain electrode are formed in contact with the oxide semiconductor layer. The present embodiment is not limited to this. After the source electrode and the drain electrode are formed, the oxide semiconductor layer may be formed in contact with the source electrode and the drain electrode.

In the case where a multilevel semiconductor device having three or more layers is manufactured by further increasing the hierarchy, a base insulating film is further formed after the fourth interlayer insulating film 118 is formed, and the multilevel semiconductor device is formed by the same procedure. What is necessary is just to produce.

According to this embodiment, an oxide semiconductor transistor with uniform electrical characteristics can be obtained in a semiconductor device in which oxide semiconductor transistors are three-dimensionally layered and stacked.

[Embodiment 3]
In this embodiment, a semiconductor device having a structure different from that of the semiconductor device described in Embodiments 1 and 2 is described.

The oxide semiconductor transistors described in Embodiments 1 and 2 may have at least a gate electrode that exists only on one side of the oxide semiconductor layer with a gate insulating film interposed therebetween.
The oxide semiconductor transistor of this embodiment may include a pair of gate electrodes that are present with an oxide semiconductor layer interposed therebetween. In the case where an oxide semiconductor transistor includes a pair of gate electrodes that are sandwiched between oxide semiconductor layers, a signal line is connected to one gate electrode and the other gate electrode (also referred to as a back gate) May be in a floating state that is electrically insulated, or may be in a state in which a potential is applied from another. In the latter case, the same potential may be applied to the pair of electrodes, or a fixed potential such as a ground potential may be applied only to the back gate. By controlling the potential applied to the back gate, the threshold voltage of the oxide semiconductor transistor can be controlled. By controlling the threshold voltage of the oxide semiconductor transistor, the oxide semiconductor transistor can be easily kept normally off.

FIG. 6 shows a cross section of a semiconductor device having a structure different from that in FIG. In the semiconductor device illustrated in FIG. 6, the first transistor 120 is different from the first transistor 100 illustrated in FIG. 1 on the side opposite to the first gate electrode 106 (the substrate 101) with the first oxide semiconductor layer 103 interposed therebetween. The other side gate electrode (first back gate 121) is provided. By providing the first back gate 121, the threshold voltage of the first transistor 100 can be controlled more easily. In the case where the first back gate 121 is provided, the first base insulating film 102 is provided.
The (first lower base insulating film 102a and first upper base insulating film 102b) also function as a gate insulating film.

In the semiconductor device illustrated in FIG. 6, the second transistor 130 includes the second transistor illustrated in FIG.
The second gate electrode 116 is sandwiched between the second oxide semiconductor layer 113 and the transistor 110 of FIG.
Another gate electrode (second back gate 131) on the opposite side (second interlayer insulating film 108 side)
Is provided. By providing the second back gate 131, it becomes easier to control the threshold voltage of the second transistor 130. The second back gate 13
When 1 is provided, the second base insulating film 112 (the second lower base insulating film 112a and the second upper base insulating film 112b) also functions as a gate insulating film.

According to this embodiment, an oxide semiconductor transistor with uniform electrical characteristics can be obtained in a semiconductor device in which oxide semiconductor transistors are three-dimensionally layered and stacked.

[Embodiment 4]
In this embodiment, a semiconductor device having a structure different from those in Embodiments 1 to 3 is described.

FIG. 7 shows a cross section of a semiconductor device having a structure different from those in FIGS. In the oxide semiconductor transistor illustrated in FIGS. 1 and 6, since the distance between the source electrode and the drain electrode is shorter than the gate width of the gate electrode, the length of the channel formation region (channel length) is between the source electrode and the drain electrode. Is equal to the channel length. On the other hand, in the oxide semiconductor transistor illustrated in FIG.
Since the gate width of the gate electrode is shorter than the distance between the source electrode and the drain electrode, the gate width of the gate electrode becomes equal to the channel length.

As described above, in this specification, the region between the source region in contact with the source electrode in the oxide semiconductor layer and the drain region in contact with the drain electrode in the oxide semiconductor layer is used. A region overlapping with the gate electrode is referred to as a channel formation region. In this embodiment, the length of the channel formation region (channel length) is the shorter of the distance between the source electrode and the drain electrode and the gate width of the gate electrode.

In the semiconductor device illustrated in FIG. 7A, the first transistor 125 includes a first gate electrode whose gate width is shorter than the distance between the first source electrode and the first drain electrode 104a and the electrode 104b. 146. In the first transistor 125, the channel length L <b> 3 of the channel formation region is equal to the gate width of the first gate electrode 146.

In the semiconductor device illustrated in FIG. 7A, the second transistor 135 includes a second gate whose gate width is shorter than the distance between the electrode 114a and the electrode 114b which are the second source electrode and the second drain electrode. An electrode 156 is provided. In the second transistor 135, the channel length L4 of the channel formation region is equal to the gate width of the second gate electrode 156.

Similar to the first transistor 100 and the second transistor 110 illustrated in FIGS.
The channel length L3 of the first transistor 125 shown in FIG.
Shorter than the channel length. However, the heat treatment time of the first transistor 125 manufactured first is longer than the heat treatment time of the second transistor 135 manufactured later. Accordingly, the amount of oxygen supplied to the first oxide semiconductor layer 103 of the first transistor 125 is larger than that of the second oxide semiconductor layer 113 of the second transistor 135. for that reason,
The shift amount of the threshold voltage of the first transistor 125 in the positive direction is larger than that of the second transistor 135. Accordingly, the threshold voltages of the first transistor 125 and the second transistor 135 can be made similar. Thus, the first transistor 125
In addition, the electrical characteristics of the second transistor 135 can be made uniform.

A first transistor 127 and a second transistor 137 illustrated in FIG. 7B are examples in which back gates are provided in the first transistor 125 and the second transistor 135 illustrated in FIG. 7A, respectively.

A first transistor 127 illustrated in FIG. 7B includes another gate electrode (first back gate) on the opposite side (substrate 101 side) to the first gate electrode 146 with the first oxide semiconductor layer 103 interposed therebetween. 122). Providing the first back gate 122 makes it easier to control the threshold voltage of the first transistor 127. In the case where the first back gate 122 is provided, the first base insulating film 102 (the first lower base insulating film 102a and the first upper base insulating film 102b) also functions as a gate insulating film.

The second transistor 137 illustrated in FIG. 7B includes another gate electrode (on the second interlayer insulating film 108 side) opposite to the second gate electrode 156 with the second oxide semiconductor layer 113 interposed therebetween. A second back gate 132) is provided. By providing the second back gate 132, the threshold voltage of the second transistor 137 can be controlled more easily. In the case where the second back gate 132 is provided, the second base insulating film 112 (the second lower base insulating film 112a and the second upper base insulating film 112b) also functions as a gate insulating film.

Note that in each of the first oxide semiconductor layer 103 and the second oxide semiconductor layer 113 illustrated in FIGS. 7A and 7B, a region between a channel formation region and a source region, and channel formation A region between the region and the drain region is referred to as an offset region.

Each of the first transistor 125 and the second transistor 135 illustrated in FIG.
In addition, in each of the first transistor 127 and the second transistor 137 illustrated in FIG. 7B, the parasitic capacitance generated between the gate electrode and the source electrode can be reduced by providing the above-described offset region. In addition, parasitic capacitance generated between the gate electrode and the drain electrode can be reduced.

The first oxide semiconductor layer 103 and the second oxide semiconductor layer 113 are impurities that change the conductivity of the oxide semiconductor using the first gate electrode 106 and the second gate electrode 116 as masks, respectively. When an element is added, a low resistance region is formed in a self-aligned manner in an offset region between the source region and the channel formation region and an offset region between the drain region and the channel formation region. When the low-resistance region is formed, the on-resistance of each of the first transistor 125 and the second transistor 135 and each of the first transistor 127 and the second transistor 137 is reduced, and the operation speed is improved. Can be made.

Note that although an example in which the first transistor, the second transistor, and two oxide semiconductor transistors are stacked (integrated) is described in this embodiment, the number of oxide semiconductor transistors is not limited thereto. In the case where a multi-layer semiconductor device is manufactured by stacking three or more oxide semiconductor transistors, the channel length of the oxide semiconductor transistor provided in the upper layer may be increased.

According to this embodiment, an oxide semiconductor transistor with uniform electrical characteristics can be obtained in a semiconductor device in which oxide semiconductor transistors are three-dimensionally layered and stacked.

[Embodiment 5]
In this embodiment, a semiconductor device (storage device) which can hold stored contents even when power is not supplied and has no limit on the number of writing operations will be described.

8 and 9, a transistor including a semiconductor having a forbidden bandwidth different from that of an oxide semiconductor,
In addition, a structure of a semiconductor device in which oxide semiconductor transistors are three-dimensionally layered and stacked is shown. FIG. 8 is a cross-sectional view of the semiconductor device, FIG. 9A is a plan view of the semiconductor device, and FIG.
(B) shows a circuit diagram of the semiconductor device. Here, FIG. 8 is a cross-sectional view taken along AB of FIG.
, And corresponds to a cross section taken along CD. Note that in FIG. 9A, some components of the semiconductor device illustrated in FIG. 8 are not illustrated.

The semiconductor device illustrated in FIG. 8 includes, in order from the bottom, a transistor using a semiconductor having a band gap different from that of an oxide semiconductor (referred to as a third transistor 660), and a first using an oxide semiconductor layer.
The transistor 100, the fourth transistor 670 having the same structure as the third transistor 660, and the second transistor 110 having a longer channel length than the first transistor 100 are stacked (integrated) using an oxide semiconductor layer. It is a semiconductor device.

In FIG. 8, the first transistor 100 and the second transistor 110 illustrated in FIG. 1 are used. Instead of the first transistor 100 and the second transistor 110, the first transistor 120 and the second transistor 110 illustrated in FIG. The second transistor 130, the first transistor 125 and the second transistor 135 illustrated in FIG. 7A, or the first transistor 127 and the second transistor 137 illustrated in FIG. 7B may be used. Not to say.

Here, the semiconductor layer of the third transistor 660 is a layer formed using a semiconductor having a forbidden band width different from that of the oxide semiconductor. An example of such a semiconductor is silicon. A transistor including a semiconductor layer other than an oxide semiconductor layer can easily operate at high speed. On the other hand, a transistor including an oxide semiconductor layer can hold charge for a long time due to its characteristics.

Note that although all the above transistors are described as n-channel transistors, it goes without saying that p-channel transistors can be used. Further, the specific structure of the semiconductor device, such as a material used for the semiconductor device or a structure of the semiconductor device, need not be limited to that shown here.

The third transistor 660 in FIG. 8 sandwiches the channel formation region 616 between the channel formation region 616 provided in the substrate 600 including a semiconductor layer (eg, silicon) having a forbidden band width different from that of the oxide semiconductor layer. An impurity region 620 provided in this manner, a gate insulating film 608 provided over the channel formation region 616, and a gate electrode 610 provided over the gate insulating film 608. Note that in the drawing, the source electrode and the drain electrode may not be explicitly provided, but for convenience, the state may be referred to as a transistor. In this case, in order to describe the connection relation of the transistors, the source and drain electrodes including the source and drain regions may be expressed. That is, in this specification, the term “source electrode” can include a source region.

An element isolation insulating layer 606 is provided over the substrate 600 so as to surround the third transistor 660, and an insulating layer 630 is provided so as to cover the third transistor 660. Note that in the third transistor 660, a sidewall insulating layer (sidewall insulating layer) may be provided on a side surface of the gate electrode 610 so that the impurity region 620 includes regions having different impurity concentrations.
Note that the element isolation insulating layer 606 has a LOCOS (Local Oxidation of
It can be formed using an element isolation technique such as Silicon or STI (Shallow Trench Isolation).

The third transistor 660 using a single crystal semiconductor substrate can operate at high speed. Therefore, information (data) can be obtained by using the transistor as a reading transistor.
Can be read at high speed. Two insulating layers are formed so as to cover the third transistor 660, and as a process before forming the first transistor 100 and the capacitor 664, a CMP process is performed on the two insulating layers to planarize the insulating layer. 630 is formed and at the same time the gate electrode 6
The top surface of 10 is exposed.

As the insulating layer 630, an inorganic insulating material such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon nitride oxide, or aluminum nitride oxide can be typically used. The insulating layer 630 can be formed by a plasma CVD method, a sputtering method, or the like.

Alternatively, an organic material such as polyimide, acrylic resin, or benzocyclobutene resin can be used. In addition to the organic material, a low dielectric constant material (low-k material) or the like can be used. When an organic material is used, the insulating layer 6 is formed by a wet method such as a spin coating method or a printing method.
30 may be formed.

Note that in this embodiment, a silicon oxide film is used as the insulating layer 630.

Planarization treatment is preferably performed on the surface of the insulating layer 630 where the oxide semiconductor layer 644 is formed. In the present embodiment, the surface is sufficiently planarized by polishing processing (for example, CMP processing) (
The average surface roughness of the surface of the insulating layer 630 is preferably 0.15 nm or less.) The oxide semiconductor layer 644 is formed over the insulating layer 630.

The impurity region 620 is formed in the first upper base insulating film 1 through an opening provided in the insulating layer 630, a first lower base insulating film 102a described later, and a first upper base insulating film 102b.
It is electrically connected to an electrode 653 provided on 02b. The electrode 653 is the electrode 104
a and the same material and the same process as the electrode 104b.

The electrode 104 a of the first transistor 100 and the gate electrode 61 of the third transistor 660
0 is electrically connected through an opening provided in the first lower base insulating film 102a and the first upper base insulating film 102b.

In addition, the first lower gate insulating film 105a, the first upper gate insulating film 105b, the first interlayer insulating film 107, and the second interlayer insulating film 108 are overlapped with the electrode 104a of the first transistor 100. A wiring 654 is provided in the region where the electrode 104a, the first lower gate insulating film 105a, the first upper gate insulating film 105b, the first interlayer insulating film 107, and the second interlayer insulating film 108 are provided. The capacitor 664 is formed by the wiring 654. That is, the electrode 104 a of the first transistor 100 functions as one electrode of the capacitor 664, and the wiring 654 functions as the other electrode of the capacitor 664. Capacitance element 6
A configuration without 64 is also possible.

A second transistor 110 using the second oxide semiconductor layer 113 as an active layer is provided over the first transistor 100 and the capacitor 664. The electrode 114b of the second transistor 110 includes a first lower gate insulating film 105a, a first upper gate insulating film 105b,
Through the opening provided in the first interlayer insulating film 107, the second interlayer insulating film 108, the second lower base insulating film 112a, and the second upper base insulating film 112b, the third transistor 6 is provided.
60 is electrically connected to the gate electrode 610 of the fourth transistor 670 having the same structure as the transistor 60. Note that the structure of the fourth transistor 670 is similar to that of the third transistor 660, and thus detailed description thereof is omitted.

In addition, the second lower gate insulating film 115a, the second upper gate insulating film 115b, the third interlayer insulating film 117, and the fourth interlayer insulating film 118 are overlapped with the electrode 114b of the second transistor 110. A wiring 674 is provided in the region to be formed, and the electrode 114b, the second lower gate insulating film 115a, the second upper gate insulating film 115b, the third interlayer insulating film 117, and the fourth interlayer insulating film 118 are provided. The capacitor 684 includes the wiring 674. That is, the electrode 114 b of the second transistor 110 functions as one electrode of the capacitor 684 and the wiring 674 functions as the other electrode of the capacitor 684. Note that a structure in which the capacitor 684 is not provided may be employed.

An insulating layer 652 is provided over the second transistor 110 and the capacitor 684. Further, a wiring may be provided over the insulating layer 652 as necessary.

8 and 9A, the first transistor 100 and the third transistor 660 are used.
In addition, each of the second transistor 110 and the fourth transistor 670 is provided so as to overlap at least partially. For example, the source region or the drain region of the third transistor 660 and the first oxide semiconductor layer 103 of the first transistor 100 are used.
It is preferable that a part of each is overlapped. For example, the first transistor 100 and the capacitor 664 are provided so as to overlap with at least part of the third transistor 660. For example, the wiring 654 of the capacitor 664 is the third transistor 6
60 gate electrodes 610 are provided so as to overlap at least partly. By adopting such a planar layout, the occupation area of the semiconductor device can be reduced,
High integration can be achieved.

With the above structure, a transistor using a forbidden band different from an oxide semiconductor, which has high-speed operation performance, and a transistor using an oxide semiconductor layer with extremely low off-state current are three-dimensional. Thus, it is possible to obtain a semiconductor device (storage device) operating at high speed and capable of reducing power consumption.

Next, an example of a circuit configuration corresponding to FIGS. 8 and 9A is illustrated in FIG.

In FIG. 9B, the first wiring (1st Line) and the source electrode of the third transistor 660 are electrically connected, and the second wiring (2nd Line) and the drain electrode of the third transistor 660 are connected. Are electrically connected. Also, the third wiring (3rd L
ine) and one of the source electrode and the drain electrode of the first transistor 100 are electrically connected, and the fourth wiring (4th Line) and the gate electrode of the first transistor 100 are electrically connected. Has been. The gate electrode of the third transistor 660 and one of the source electrode and the drain electrode of the first transistor 100 are connected to the capacitor 664.
A fifth wiring (5th Line), and a capacitor 664.
The other electrode is electrically connected.

In the semiconductor device illustrated in FIG. 9B, data can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the third transistor 660 can be held.

Data writing and holding will be described. First, the potential of the fourth wiring is set to a potential at which the first transistor 100 is turned on, so that the first transistor 100 is turned on. Accordingly, the potential of the third wiring is supplied to the gate electrode of the third transistor 660 and the capacitor 664. That is, predetermined charge is given to the gate electrode of the third transistor 660 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given.
After that, the potential of the fourth wiring is set to a potential at which the first transistor 100 is turned off.
By turning off the first transistor 100, the charge given to the gate electrode of the third transistor 660 is held (held).

Since the off-state current of the first transistor 100 is extremely small, the charge of the gate electrode of the third transistor 660 is held for a long time.

Next, data reading will be described. When an appropriate potential (readout potential) is applied to the fifth wiring in a state where a predetermined potential (constant potential) is applied to the first wiring, the third transistor 660 is provided.
The second wiring has different potentials depending on the amount of charge held in the gate electrode. In general, when the third transistor 660 is an n-channel transistor, the apparent threshold voltage V _{th_H in the} case where a high-level charge is applied to the gate electrode of the third transistor 660 is equal to the gate of the third transistor 660. This is because the voltage becomes lower than the apparent threshold voltage _{Vth_L} when a low level charge is applied to the electrode. Here, the apparent threshold voltage refers to the potential of the fifth wiring necessary for turning on the third transistor 660. Therefore, the potential of the fifth wiring is _{set to} an intermediate potential V ₀ between V _{th_H} and V _{th_L.}
Thus, the charge applied to the gate electrode of the third transistor 660 can be determined. For example, in the case where a high-level charge is applied in writing, if the potential of the fifth wiring becomes V ₀ (> V _{th_H} ), the third transistor 660 is “ON”.
It becomes. When the low level charge is applied, the potential of the fifth wiring is V ₀ (<V _{t
h_L} ), the third transistor 660 remains in the “off state”. Therefore, the stored data can be read by looking at the potential of the second wiring.

Note that in the case of using memory cells arranged in an array, it is necessary to read only data of desired memory cells. When data is not read out in this way, a potential at which the third transistor 660 is “off” regardless of the state of the gate electrode, that is, V
_A potential smaller than _{th_H} may be _supplied to the fifth wiring. _{Alternatively} , the potential at which the third transistor 660 is turned on regardless of the state of the gate electrode, that is, V _{th_L}
A higher potential may be supplied to the fifth wiring.

In the semiconductor device described in this embodiment, data can be held for an extremely long time by using a transistor with an extremely small off-state current that uses an oxide semiconductor for a channel formation region. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely low, so that power consumption can be sufficiently reduced. Further, data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

Further, in the semiconductor device described in this embodiment, high voltage is not needed for writing information (data), and there is no problem of deterioration of elements. For example, unlike the conventional nonvolatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so that the problem of deterioration of the gate insulating layer does not occur at all. That is, in the semiconductor device according to the disclosed invention, the number of rewritable times that is a problem in the conventional nonvolatile memory is not limited, and the reliability is dramatically improved. Further, since data (data) is written depending on the on state and the off state of the transistor, high-speed operation can be easily realized.

As described above, an oxide semiconductor transistor has a feature that an off-state current is extremely small. Therefore, by turning off the oxide semiconductor transistor, the charge (data) of the node electrically connected to one of the source and the drain of the oxide semiconductor transistor
Can be held for a long time.

As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

[Embodiment 6]
In this embodiment mode, a CPU (Central) including the semiconductor device described in Embodiment Mode 5 is used.
(Processing Unit) will be described below.

FIG. 11A is a block diagram illustrating a specific configuration of a CPU. C shown in FIG.
The PU is mounted on the substrate 1190 with an ALU 1191 (ALU: Arithmetic logic).
unit, arithmetic circuit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus
I / F), rewritable ROM 1199, and ROM interface 1189 (R
OM I / F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 11A is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

The timing controller 1195 includes an ALU 1191 and an ALU controller 119.
2. Generates a signal for controlling the operation timing of the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1.
An internal clock generator for generating LK2 is provided, and an internal clock signal CLK2 is supplied to the various circuits.

In the CPU illustrated in FIG. 11A, the register 1196 is provided with a plurality of memory cells. As each of the plurality of memory cells in the register 1196, the semiconductor device illustrated in FIG. 9B can be used.

In the CPU illustrated in FIG. 11A, the register controller 1197 includes an ALU 1191.
The holding operation in the register 1196 is selected in accordance with the instruction from. That is, in the memory cell included in the register 1196, it is selected whether to hold data by the phase inversion element or to hold data by the capacitor element. When data retention by the phase inverting element is selected, the power supply voltage is supplied to the memory cells in the register 1196.
When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

Regarding the power supply stop, as shown in FIG. 11B or FIG.
This can be performed by providing a switching element between nodes to which the power supply potential VDD or the power supply potential VSS is applied. The circuits in FIGS. 11B and 11C will be described below.

A semiconductor device illustrated in FIG. 11B includes a switching element 1141 and a memory cell group 1143 including a plurality of memory cells 1142. Specifically, for each memory cell 1142, the semiconductor device illustrated in FIG. 9B can be used. Each memory cell 1142 included in the memory cell group 1143 has a high-level power supply potential V through a switching element 1141.
DD is supplied. Further, each memory cell 1142 included in the memory cell group 1143 is supplied with the potential of the signal IN and the low-level power supply potential VSS.

In FIG. 11B, an oxide semiconductor transistor is used as the switching element 1141, and switching of the transistor is controlled by a signal SigA applied to the gate electrode thereof. As the oxide semiconductor transistor, the first transistor 100 illustrated in FIG. 1, the second transistor 110 illustrated in FIG. 1, the first transistor 120 illustrated in FIG. 6,
The second transistor 130 illustrated in FIG. 6, the first transistor 125 illustrated in FIG. 7A, the second transistor 135 illustrated in FIG. 7A, and the first transistor 127 illustrated in FIG. 7B.
Alternatively, the second transistor 137 illustrated in FIG. 7B may be used.

Note that FIG. 11B illustrates a structure in which the switching element 1141 includes only one transistor; however, there is no particular limitation, and a plurality of transistors may be included. In the case where the switching element 1141 includes a plurality of transistors functioning as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be combined in series and parallel. May be connected.

In FIG. 11B, the switching element 1141 controls the supply of the high-level power supply potential VDD to each memory cell 1142 included in the memory cell group 1143, but the switching element 1141 controls the low-level power supply potential VDD. The supply of the power supply potential VSS may be controlled.

FIG. 11C illustrates an example of a semiconductor device in which a low-level power supply potential VSS is supplied to each memory cell 1142 included in the memory cell group 1143 through the switching element 1141. The switching element 1141 can control supply of the low-level power supply potential VSS to each memory cell 1142 included in the memory cell group 1143.

A switching element is provided between the memory cell group and a node to which the power supply potential VDD or the power supply potential VSS is applied to temporarily stop the operation of the CPU and retain data even when the supply of the power supply voltage is stopped. It is possible to reduce power consumption. Specifically, for example, even when a personal computer user stops inputting information to an input device such as a keyboard, the operation of the CPU can be stopped, thereby reducing power consumption. it can.

Here, the CPU has been described as an example, but a DSP (Digital Signal P) is used.
processor, custom LSI, FPGA (Field Programmable)
e Gate Array) and the like.

Incidentally, a magnetic tunnel junction element (MTJ element) is known as a nonvolatile random access memory. The MTJ element is an element that stores information by being in a low resistance state if the spin directions in the films arranged above and below the insulating film are parallel and in a high resistance state if the spin directions are antiparallel. Therefore, the principle is completely different from that of a memory using a wide band gap semiconductor such as an oxide semiconductor described in this embodiment. Table 1 shows a comparison between the MTJ element and the semiconductor device according to the present embodiment.

Since the MTJ element uses a magnetic material, there is a drawback that the magnetism is lost when the temperature is higher than the Curie temperature. Further, since the MTJ element is current driven, it is compatible with a silicon bipolar device, but the bipolar device is not suitable for integration. Although the MTJ element has a small write current, there is a problem that the power consumption increases due to the increase in the capacity of the memory.

In principle, the MTJ element is weak in magnetic field resistance, and when exposed to a strong magnetic field, the direction of spin tends to go wrong.
In addition, it is necessary to control the magnetization fluctuation caused by the nanoscale formation of the magnetic material used in the MTJ element.

Further, the MTJ element is expensive in view of the material cost per bit.

On the other hand, a transistor using a wide band gap semiconductor such as the above-described oxide semiconductor has the same element structure and operating principle as the silicon MOSFET except that the semiconductor forming the channel is a metal oxide. In addition, a transistor including an oxide semiconductor is not affected by a magnetic field and has a characteristic that a soft error cannot occur. Therefore, it can be said that the compatibility with the silicon integrated circuit is very good.

In addition, as shown in Table 1, a memory in which a transistor using a wide bandgap semiconductor such as an oxide semiconductor described above and a transistor using silicon are combined is more heat resistant and 3D (three layers) than a spintronic device. This is advantageous in many respects, such as the above laminated structure), magnetic field resistance, and write power amount. Note that the overhead power in Table 1 means that when multiple processors spin on a lock, these processors compete for the lock and generate excessive traffic on the bus and system interconnect. This is the power consumed for so-called overhead.

In this manner, by using a semiconductor device using an oxide semiconductor, which has many advantages over spintronic devices, power saving of the semiconductor device can be realized.

As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

[Embodiment 7]
In the sixth embodiment, the CPU has been described as an example, but a DSP (Digital Signal) is described.
l Processor), custom LSI, FPGA (Field Program)
The present invention can also be applied to LSIs such as (able Gate Array). In this embodiment, a programmable logic device (PLD) typified by an FPGA using a hierarchical structure of transistors will be described.

The PLD is an integrated circuit whose configuration can be set by a purchaser or designer after manufacture, and the design can be partially reconstructed after shipment. It has a plurality of logic blocks that are programmable logic components and a reconfigurable wiring layer that interconnects them. Accordingly, a complex logic circuit can be configured by combining a plurality of logic blocks, and can be reconfigured.

The logical block is configured using, for example, a lookup table (LUT).
The look-up table performs an arithmetic process on the input signal according to the setting data to generate an output signal. Here, the setting data is stored in a storage circuit provided corresponding to each logical block. That is, the look-up table can perform different arithmetic processing depending on the data stored in the storage circuit. Therefore, the function of the logic block can be specified by storing specific setting data in the storage circuit.

The setting data of the lookup table is called configuration data. A storage circuit provided corresponding to each logical block and storing configuration data is referred to as a configuration memory. Furthermore, storing configuration data in the configuration memory is called configuration. In particular, rewriting (updating) configuration data stored in the configuration memory is called reconfiguration. Changing the PLD to a circuit configuration according to the user's purpose can be realized by creating (programming) desired configuration data and performing configuration.

In general, the PLD is configured in a state where the operation of the semiconductor device having the PLD is stopped (static configuration). On the other hand, in order to make better use of the characteristics of PLD, configuration is performed during operation of the semiconductor device (dynamic configuration).
You can also.

The PLD can fix bugs and change design specifications in the field, shorten the development period and manufacturing period, and can be manufactured at low cost.

As shown in FIG. 12A, a conventional PLD 9800 includes a plurality of logic blocks 9801 arranged in a lattice pattern, and a plurality of wirings 9 provided between the plurality of logic blocks 9801 and extending vertically and horizontally.
804 and a plurality of switches 9805 provided at intersections of the wiring 9804.

The logic block 9801 has a configuration as shown in FIG.
A look-up table (LUT) 9806 constituting the logic of the PLD has an SRAM 9802. The lookup table shown in FIG. 12B is an example of 4 inputs and 1 output, and an arbitrary logic circuit that obtains 1 bit output from 4 bits input can be configured. The flip-flop 9807 forms a sequential circuit, and the selector 9808 switches between sequential circuit operation and combinational circuit operation.

The switch 9805 is formed by a transfer gate (analog switch) or the like, and is turned on or off by the look-up table of the SRAM 9802 in the logic block 9801 to realize an arbitrary connection of the logic block 9801.

In this embodiment, instead of SRAM 9802 used for the lookup table,
The memory device using the oxide semiconductor transistor described in Embodiment 5 is used. Thereby, it is possible to realize a PLD that is three-dimensionally layered and stacked.

In the conventional structure, the logic blocks are two-dimensionally arranged as shown in FIG. For this reason, a region for forming a logic circuit or wiring is limited, and functions that can be formed in a logic block are limited. For this reason, in order to construct a more advanced logic circuit in a logic block, further miniaturization of elements, wirings, and the like is required, leading to an increase in cost.

However, as described above, for example, when an SRAM used for a lookup table is replaced with an oxide semiconductor transistor and the oxide semiconductor transistor is formed in an upper layer, an additional circuit configuration is disposed in the lower layer region accordingly. Is possible.

In addition, by creating an electrical circuit that is difficult to arrange in a plane in combination with the upper layer, the circuit arrangement of each layer is further simplified, and high-density integration can be achieved.

In particular, when the hierarchical structure of the transistor described in one embodiment of the disclosed invention is used for a PLD, a semiconductor having high-speed operation performance and a forbidden band different from an oxide semiconductor as described in Embodiment 5 It is preferable to combine a transistor using an oxide semiconductor and a transistor including an oxide semiconductor with extremely low off-state current. When a transistor including an oxide semiconductor film has a multi-layer structure of two or more layers, a logic block integrated with high density can be formed.

As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

[Embodiment 8]
The semiconductor device described in any of the above embodiments can be applied to a variety of electric appliances (including game machines). As electrical equipment, display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, DVDs (Dig)
image playback device for playing back still images or moving images stored in a recording medium such as ital Versatile Disc), portable CD player, radio, tape recorder, headphone stereo, stereo, cordless telephone cordless handset, transceiver, portable radio, mobile phone , Car phones, portable game machines, calculators, personal digital assistants, electronic notebooks, electronic books, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens and other high-frequency heating devices, electric rice cookers , Air conditioning equipment such as electric washing machines, vacuum cleaners, air conditioners,
Examples include dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerators, DNA storage freezers, smoke detectors, radiation measuring instruments, and dialysis devices. Further examples include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, and power storage systems. In addition, an engine using petroleum, a moving body driven by an electric motor using electric power from a non-aqueous secondary battery, and the like are also included in the category of electric equipment. Examples of the mobile body include an electric vehicle (EV), a hybrid vehicle (HEV) having both an internal combustion engine and an electric motor, and a plug-in hybrid vehicle (PHEV).
, Tracked vehicles that changed these tire wheels into endless tracks, motorbikes including electric assist bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircrafts, rockets, satellites, Examples include space probes, planetary probes, and spacecraft.
Specific examples of these electric devices are shown in FIGS.

FIG. 13A illustrates a table 9000 having a display portion. Table 9000
A display portion 9003 is incorporated in the housing 9001 and an image can be displayed on the display portion 9003. Note that a structure in which the housing 9001 is supported by four legs 9002 is shown. In addition, the housing 9001 has a power cord 9005 for supplying power. The multi-layer semiconductor device described in the above embodiment can be applied to a driver circuit of the display portion 9003 or the like.

The display portion 9003 has a touch input function. By touching a display button 9004 displayed on the display portion 9003 of the table 9000 with a finger or the like, screen operation or information can be input. It is good also as a control apparatus which controls other household appliances by screen operation by enabling communication with household appliances or enabling control. For example, when a semiconductor device having an image sensor function is used, the display portion 9003 can have a touch input function.

Further, the hinge of the housing 9001 can be used to stand the screen of the display portion 9003 perpendicular to the floor, which can be used as a television device. In a small room, if a television apparatus with a large screen is installed, the free space becomes narrow. However, if the display portion is built in the table, the room space can be used effectively.

FIG. 13B shows a portable music player. The main body 3021 has a display portion 3023, a fixing portion 3022 for wearing on the ear, a speaker, operation buttons 3024, and an external memory slot 3.
025 etc. are provided. The multi-level semiconductor device described in the above embodiment includes a main body 302.
1 can be applied to a memory, a CPU, and the like built in 1.

Further, if the portable music player shown in FIG. 13B has an antenna, a microphone function, and a wireless function and is linked to a mobile phone, wireless hands-free conversation is possible while driving a passenger car or the like.

FIG. 13C illustrates a computer, which includes a main body 9201 including a CPU, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, and a pointing device 92.
Including 06. The computer is a CPU of the multi-layer semiconductor device described in the above embodiment.
It is produced by using for etc. Alternatively, the multilevel semiconductor device described in the above embodiment can be applied to a memory or the like included in the main body 9201.

14A and 14B illustrate a tablet terminal that can be folded. FIG. 14 (A)
Is an open state, and the tablet terminal includes a housing 9630, a display portion 9631a, a display portion 9631b, a display mode change switch 9034, a power switch 9035, a power saving mode change switch 9036, a fastener 9033, an operation switch 9038, Have

In portable devices as shown in FIGS. 14A and 14B, SRAM or DRAM is used as a memory for temporary storage of image data or the like. The multilevel semiconductor device described in any of the above embodiments can be applied to the memory.

Part of the display portion 9631a can be a touch panel region 9632a, and data can be input by touching operation keys 9638 displayed. Note that in the display portion 9631a, for example, a structure in which half of the regions have a display-only function and a structure in which the other half has a touch panel function is shown, but the structure is not limited thereto. The entire region of the display portion 9631a may have a touch panel function. For example, a keyboard button is displayed on the entire surface of the display portion 9631a to form a touch panel, and the display portion 9631b is displayed.
Can be used as a display screen.

Further, in the display portion 9631b, as in the display portion 9631a, part of the display portion 9631b can be a touch panel region 9632b. In addition, a keyboard button can be displayed on the display portion 9631b by touching a position where the keyboard display switching button 9639 on the touch panel is displayed with a finger, a stylus, or the like.

Touch input can be performed simultaneously on the touch panel region 9632a and the touch panel region 9632b.

A display mode switching switch 9034 can switch the display direction such as vertical display or horizontal display, and can select switching between monochrome display and color display. The power saving mode change-over switch 9036 can optimize the display luminance in accordance with the amount of external light during use detected by an optical sensor built in the tablet terminal. The tablet-type terminal may include not only an optical sensor but also other detection devices such as a gyroscope, an acceleration sensor, and other sensors that detect inclination.

FIG. 14A shows an example in which the display areas of the display portion 9631b and the display portion 9631a are the same, but there is no particular limitation. One size and the other size may be different, and the display quality is also high. May be different. For example, one display panel may be capable of displaying images with higher definition than the other.

FIG. 14B illustrates a closed state, in which the tablet terminal includes a housing 9630, a solar cell 96
33, a charge / discharge control circuit 9634, a battery 9635, and a DCDC converter 9636. In FIG. 14B, as an example of the charge / discharge control circuit 9634, a battery 9635, D
A structure including the CDC converter 9636 is shown.

Note that since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Accordingly, since the display portion 9631a and the display portion 9631b can be protected, a tablet terminal with excellent durability and high reliability can be provided from the viewpoint of long-term use.

In addition, the tablet terminal shown in FIGS. 14A and 14B has a function for displaying various information (still images, moving images, text images, etc.), a calendar, a date or a time. A function for displaying on the display unit, a touch input function for performing touch input operation or editing of information displayed on the display unit, a function for controlling processing by various software (programs), and the like can be provided.

The solar cell 9633 mounted on the surface of the tablet terminal allows power to be supplied to the touch panel,
It can be supplied to a display unit, a video signal processing unit, or the like. Note that the solar cell 9633 is preferable because it can efficiently charge the battery 9635 on one or two surfaces of the housing 9630. Note that as the battery 9635, when a lithium secondary battery is used, there is an advantage that the size can be reduced.

FIG. 14C illustrates the structure and operation of the charge and discharge control circuit 9634 illustrated in FIG.
) Will be described with reference to a block diagram. FIG. 14C illustrates a solar cell 9633, a battery 963, and the like.
5 shows a DCDC converter 9636, a converter 9637, switches SW1 to SW3, and a display portion 9631. The battery 9635, the DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 are connected to the charge / discharge control circuit 9 shown in FIG.
This corresponds to 634.

First, an example of operation in the case where power is generated by the solar battery 9633 using external light is described.
The DCDC is used so that the power generated by the solar battery becomes a voltage for charging the battery 9635.
The converter 9636 performs step-up or step-down. When power from the solar battery 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on and the converter 963 is turned on.
7, the voltage required for the display portion 9631 is increased or decreased. In addition, the display portion 963
When the display at 1 is not performed, SW1 is turned off, SW2 is turned on, and the battery 9635 is turned on.
The configuration may be such that charging is performed.

Note that the solar cell 9633 is described as an example of the power generation unit, but is not particularly limited, and the battery 9635 is charged by another power generation unit such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). There may be. For example, it is good also as a structure performed combining a non-contact electric power transmission module which transmits / receives electric power by radio | wireless (non-contact), and another charging means.

In FIG. 15A, a display device 8002 is incorporated in a housing 8001 in a television device 8000. An image can be displayed on the display portion 8002 and sound can be output from a speaker portion 8003. The multi-layer semiconductor device described in any of the above embodiments can be applied to a CPU or a memory for performing information communication. FIG. 15A illustrates an example in which the multilevel semiconductor device described in the above embodiment is applied to the CPU 8004.

The display portion 8002 includes a liquid crystal display device, a light emitting device including a light emitting element such as an organic EL element in each pixel, an electrophoretic display device, and a DMD (Digital Micromirror Device).
), A PDP (Plasma Display Panel), or the like can be used.

The television device 8000 may include a receiver, a modem, and the like. The television device 8000 can receive a general television broadcast by a receiver, and is connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional. It is also possible to perform information communication (between the sender and the receiver or between the receivers).

In FIG. 15A, an air conditioner including an indoor unit 8200 and an outdoor unit 8204 is an example of an electrical device using the CPU described in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CPU 8203, and the like. FIG. 15 (A)
, The case where the CPU 8203 is provided in the indoor unit 8200 is illustrated.
The CPU 8203 may be provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. Since the CPU described in any of the above embodiments is a CPU using an oxide semiconductor, it has excellent heat resistance and can realize a highly reliable air conditioner.

In FIG. 15A, an electric refrigerator-freezer 8300 is an example of an electric device including a CPU including an oxide semiconductor. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a CPU 8304, and the like. In FIG. 15A, C
A PU 8304 is provided inside the housing 8301.

FIG. 15B illustrates an example of an electric vehicle which is an example of an electric device. Electric vehicle 970
In 0, a secondary battery 9701 is mounted. The power of the secondary battery 9701 is supplied to the control circuit 97.
The output is adjusted by 02 and supplied to the driving device 9703. The control circuit 9702 is controlled by a processing device 9704 having a ROM, a RAM, a CPU, etc. (not shown). The CPU described in the above embodiment can be used for the CPU of the electric vehicle 9700.

The drive device 9703 is configured by a DC motor or an AC motor alone, or a combination of an electric motor and an internal combustion engine. The processing device 9704 is based on input information such as operation information (acceleration, deceleration, stop, etc.) of the driver of the electric vehicle 9700 and information at the time of travel (information such as uphill and downhill, load information on the drive wheels, etc.). The control signal is output to the control circuit 9702. Control circuit 970
2 controls the output of the driving device 9703 by adjusting the electric energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704. If you have an AC motor,
Although not shown, an inverter that converts direct current into alternating current is also incorporated.

As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

10A and 10B illustrate a gate potential V applied to a gate electrode in an oxide semiconductor transistor with a long channel length and an oxide semiconductor transistor with a short channel length.
The relationship between g and drain current Id (hereinafter referred to as “Vg-Id characteristics”) is shown.

FIG. 10A shows a channel length of 9.9 μm and a channel formation region width (channel width) of 10 μm.
The Vg-Id characteristic of the oxide semiconductor transistor is shown. On the other hand, FIG. 10B illustrates Vg-Id characteristics of an oxide semiconductor transistor having a channel length of 0.25 μm and a channel width of 10 μm.

The oxide semiconductor transistor having a long channel length (9.9 μm) used in FIG.
This is a normally-off transistor that is off when the gate potential Vg is 0V. On the other hand, the oxide semiconductor transistor with a short channel length (0.25 μm) used in FIG.
When the gate potential Vg is 0 V, the transistor is a normally-on transistor that is on. Thus, the threshold voltage decreases as the channel length decreases.

As described above, according to this embodiment, a transistor having a short channel length has a lower threshold voltage,
It was confirmed that a transistor having a long channel length has a higher threshold voltage.

100 First transistor 101 Substrate 102 First base insulating film 102a First lower base insulating film 102b First upper base insulating film 103 First oxide semiconductor layer 104a Electrode 104b Electrode 105 First gate insulating film 105a First lower gate insulating film 105b First upper gate insulating film 106 First gate electrode 107 First interlayer insulating film 108 Second interlayer insulating film 109 Electrode 110 Second transistor 112 Second base insulating film 112a Second lower base insulating film 112b Second upper base insulating film 113 Second oxide semiconductor layer 114a Electrode 114b Electrode 115 Second gate insulating film 115a Second lower gate insulating film 115b Second upper gate insulating film 116 Second gate electrode 117 Third interlayer insulating film 118 Fourth interlayer insulating film 120 First transistor 121 1st back gate 122 1st back gate 123 1st oxide semiconductor layer 124 1st conductive film 125 1st transistor 126 2nd conductive film 127 1st transistor 130 2nd transistor 131 2nd Back gate 132 Second back gate 133 Second oxide semiconductor layer 134 Third conductive film 135 Second transistor 136 Fourth conductive film 137 Second transistor 146 First gate electrode 149 Electrode 156 Second Gate electrode 159 electrode 600 substrate 606 element isolation insulating layer 608 gate insulating film 610 gate electrode 616 channel formation region 620 impurity region 630 insulating layer 652 insulating layer 653 electrode 654 wiring 660 third transistor 664 capacitor 670 fourth transistor 674 Wiring 684 Capacitor element 114 Switching elements 1142 memory cells 1143 memory cell group 1189 ROM interface 1190 substrate 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
3021 Main body 3022 Fixed portion 3023 Display portion 3024 Operation button 3025 External memory slot 8000 Television apparatus 8001 Housing 8002 Display portion 8003 Speaker portion 8004 CPU
8200 Indoor unit 8201 Housing 8202 Air outlet 8203 CPU
8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Housing 8302 Refrigeration room door 8303 Freezing room door 8304 CPU
9000 Table 9001 Case 9002 Leg 9003 Display unit 9004 Display button 9005 Power cord 9033 Fastener 9034 Display mode switch 9035 Power switch 9036 Power saving mode switch 9038 Operation switch 9201 Main body 9202 Case 9203 Display unit 9204 Keyboard 9205 External connection Port 9206 Pointing device 9630 Case 9631 Display unit 9631a Display unit 9631b Display unit 9632a Region 9632b Region 9633 Solar cell 9634 Charge / discharge control circuit 9635 Battery 9636 DCDC converter 9537 Converter 9638 Operation key 9639 Keyboard display switching button 9700 Electric vehicle 9701 Secondary battery 9702 Control circuit 9703 Driving device 9704 Processing device 9 00 PLD
9801 Logic block 9802 SRAM
9804 Wiring 9805 Switch 9806 LUT
9807 Flip-flop 9808 selector

Claims (1)

A first source electrode and a first drain electrode on the first oxide semiconductor layer;
A first gate insulating film on the first source electrode and the first drain electrode;
A first gate electrode on the first gate insulating film;
A first insulating film on the first gate electrode;
A second insulating film on the first insulating film;
A second oxide semiconductor layer on the second insulating film;
A second source electrode and a second drain electrode on the second oxide semiconductor layer;
A second gate insulating film on the second source electrode and on the second drain electrode;
A second gate electrode on the second gate insulating film;
A third insulating film on the second gate electrode;
A fourth insulating film on the third insulating film;
A first electrode, a second electrode, and a third electrode on the fourth insulating film;
The second oxide semiconductor layer does not overlap with the first oxide semiconductor layer,
The first electrode is connected to the first gate electrode through a first opening of the first insulating film, the second insulating film, the third insulating film, and the fourth insulating film. Connected with
The first opening is provided in the first insulating film, the second insulating film, the third insulating film, and the fourth insulating film,
The second electrode is connected to one of the first source electrode and the first drain electrode through a second opening,
The second opening is provided in the first insulating film, the second insulating film, the third insulating film, and the fourth insulating film,
The third electrode is connected to one of the second source electrode and the second drain electrode through a third opening,
The third opening is provided in the third insulating film and the fourth insulating film,
The first electrode, the second electrode, and the third electrode each extend in the channel width direction of the first transistor having the first oxide semiconductor layer,
The first electrode, the second electrode, and the third electrode each extend in the channel width direction of the second transistor having the second oxide semiconductor layer,
A line connecting the second opening and the third opening extends in the channel width direction of the first transistor,
Each of the second opening and the third opening does not overlap with the first oxide semiconductor layer and the second oxide semiconductor layer,
When viewed from above, a line connecting the second opening and the third opening is located between the first oxide semiconductor layer and the second oxide semiconductor layer,
The semiconductor device is characterized in that the channel length of the first transistor is shorter than the channel length of the second transistor.

Images