JP6452592B2 - Parallel resonant circuit and harmonic processing circuit - Google Patents

Description

  The present invention relates to a parallel resonance circuit and a harmonic processing circuit for operating a high-frequency amplifier composed of a field effect transistor (hereinafter abbreviated as FET) and the like with high efficiency.

  In a conventional high-frequency amplifier, there is known a technique for improving the efficiency of an amplifier by controlling a second harmonic using a circuit that resonates with a second harmonic of a fundamental wave to be used (for example, non-patent document). 1).

  FIG. 12 is a circuit configuration diagram showing a second harmonic processing circuit in a conventional high-frequency amplifier. 12 includes an input terminal 1, an external load circuit 2, a parallel resonance circuit 3 including an inductor and a capacitor, a second harmonic load impedance control circuit 4 including an inductor and a capacitor, an FET 5, and an output matching circuit 6. , And an output terminal 7.

  In the circuit of FIG. 12, the second harmonic load impedance control circuit 4 realizes a second harmonic load impedance for operating the FET 5 with high efficiency. In the parallel resonance circuit 3, the second harmonic load impedance due to the load of the external circuit is realized. The impact is minimized.

“A 67% PAE, 100 W GaN Power Amplifier with On-Chip Harmonic Tuning Circuits for C-band Space Applications” 2011 International Microwave Symposium. "High-efficiency operating characteristics of FETs by the double-wave injection method" FY2000 IEICE Spring National Convention, C-6

However, the prior art has the following problems.
Problems with the conventional configuration will be described with reference to FIGS. 13 and 14. FIG. 13 is a diagram illustrating a conventional configuration of a parallel resonant circuit. 13 includes an output terminal 9, an upper electrode 10 of a parallel plate capacitor, a capacitance portion 11 of the parallel plate capacitor, a base electrode 12 of the parallel plate capacitor, an inductor 13 by a transmission line, and an input terminal 14. It is prepared for.

  FIG. 14 is an explanatory diagram in which three current paths are overwritten in the parallel resonant circuit of FIG. Specifically, FIG. 14 shows a current path 16 that flows from the input terminal 14 to the output terminal 9, a current path 17 that circulates in a parallel circuit of an inductor and a capacitor during resonance, and a current that flows from the base electrode of the capacitor to the top electrode. It is the figure which overwrote each path 18.

  In the parallel resonance circuit of an inductor and a capacitor, current circulates in the parallel circuit of the inductor and the capacitor at the time of resonance. Further, unless the circuit is completely lossless, current flows from the input terminal 14 to the output terminal 9 even during resonance. In FIG. 14, the former current path is indicated by a current path 16, and the latter current path is indicated by a current path 17.

  In the conventional configuration, on the input side, the point 15b connecting the inductor and the capacitor is the same as the point 15b connecting the external circuit. Similarly, on the input side, the point 15a connecting the inductor and the capacitor and the point 15a connecting the external circuit are the same.

  Therefore, the current path 16 that flows from the input terminal to the output terminal in the upper electrode 10 and the base electrode 12 of the capacitor and the current path 17 that goes around the inductor and the parallel circuit are in the same direction. As a result, the value of the current flowing between the upper electrode 10 and the lower electrode 12 increases.

  For this reason, the influence of the conductor loss in the upper electrode 10 and the lower electrode 12 of the capacitor is increased. In addition, when the current value to the base electrode 12 is large, the dielectric loss generated between the base electrode 12 and the substrate also increases. In particular, when a substrate having a large dielectric loss is used, the effect is remarkable.

  Since these conductor loss and dielectric loss are large, the parallel resonance circuit cannot realize high impedance at the resonance frequency. For example, when the parallel resonant circuit cannot realize a high impedance at the second harmonic of the fundamental wave to be used, there is a problem that the double harmonic load impedance is affected by the external load and the operation efficiency of the FET is lowered. .

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a parallel resonance circuit and a harmonic processing circuit capable of operating a high-frequency amplifier with high efficiency.

A parallel resonant circuit according to the present invention includes a parallel plate capacitor having an upper electrode and a base electrode, and a transmission line, and is formed by parallel connection of a capacitance component of the parallel plate capacitor and an inductor component of the transmission line. In the parallel resonance circuit, the upper electrode has a first input terminal and a first output terminal as input / output terminals, and the lower electrode has a second input terminal and a second output terminal as input / output terminals. The second input terminal is used as an external input terminal for a signal input from the outside, the first output terminal is used as an external output terminal for a signal output to the outside, and the transmission line is Connected between the second output terminal and the first input terminal, the connection point between the transmission line and the first input terminal is disposed at a position closer to the external input terminal than the external output terminal, Connection with the second output terminal Point is one that is disposed at a position of the external output terminal side of the external input terminals.

A harmonic processing circuit according to the present invention is a harmonic treatment circuit including the parallel resonant circuit of the present invention and a second harmonic load impedance control circuit having an inductor and a capacitor connected in series, the high frequency amplifier The external output terminal of the parallel resonance circuit is connected to the input terminal, and the second harmonic load impedance control circuit has one end grounded and the other end connected to the external output terminal.

  According to the present invention, by applying a parallel resonant circuit in which the impedance at the resonant frequency is increased, the influence on the double wave load impedance with respect to the external load is suppressed, the efficiency reduction is suppressed, and the amplifier has a high efficiency. It has a circuit configuration that can be realized. As a result, it is possible to obtain a parallel resonance circuit and a harmonic processing circuit capable of operating the high-frequency amplifier with high efficiency.

It is a circuit block diagram which shows the parallel resonant circuit in Embodiment 1 of this invention. In the parallel resonance circuit in Embodiment 1 of this invention, it is explanatory drawing which overwritten three current paths. In Embodiment 1 of this invention, it is the result of having calculated the high frequency electric current value which flows into an inductor, a base electrode, and an upper electrode as a function of a phase. FIG. 15 shows the result of calculating the value of the high-frequency current flowing through the inductor, the base electrode, and the top electrode in the prior art shown in FIG. 14 as a function of phase as in FIG. In Embodiment 1 of this invention, it is a figure which shows the comparison of the result of having calculated the impedance of a parallel resonant circuit using the parallel resonant circuit shown in previous FIG. 1, and the conventional parallel resonant circuit. It is a top view which shows the harmonic processing circuit by Embodiment 2 of this invention. It is a figure which shows the result of having calculated the 2nd harmonic impedance external circuit dependence using the harmonic processing circuit in Embodiment 2 of this invention. It is a figure which shows the result of having changed the parallel resonant circuit in Embodiment 2 of this invention into the conventional circuit structure, and having calculated the 2nd harmonic impedance external circuit dependence similarly to previous FIG. It is a top view which shows the harmonic processing circuit by Embodiment 3 of this invention. It is a top view which shows the harmonic processing circuit by Embodiment 4 of this invention. It is a top view which shows the harmonic processing circuit by Embodiment 5 of this invention. It is a circuit block diagram which shows the 2nd harmonic processing circuit in the conventional high frequency amplifier. It is a figure which shows the conventional structure of a parallel resonant circuit. FIG. 14 is an explanatory diagram in which three current paths are overwritten in the parallel resonant circuit of FIG. 13. FIG. 13 is a circuit configuration diagram different from FIG. 12 showing a second harmonic processing circuit in a conventional high-frequency amplifier.

  Hereinafter, preferred embodiments of a parallel resonant circuit and a harmonic processing circuit of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a circuit configuration diagram showing a parallel resonant circuit according to Embodiment 1 of the present invention. The configuration of FIG. 1 is different from the conventional configuration of FIG. 13 in that the connection location of the inductor and the capacitor is changed so that the current path changes.
(1) The location 15a connecting the inductor and the capacitor on the output side is changed to the location of the upper electrode 10 immediately above the location where the base electrode 12 and the input terminal 14 are connected.
(2) The location 15b where the inductor and the capacitor on the input side are connected is changed to the location of the underlying electrode 12 directly below the location where the upper electrode 10 and the output terminal 9 are connected.

  FIG. 2 is an explanatory diagram in which two current paths are overwritten in the parallel resonant circuit in the first embodiment of the present invention. Specifically, FIG. 2 is different from the circuit configuration diagram of FIG. 1 in that a current path 16 flows from the input terminal 14 to the output terminal 9 and a current path 17 that circulates in a parallel circuit of an inductor and a capacitor during resonance. And a current path 18 that flows from the base electrode 12 to the top electrode 10 in the capacitor is overwritten.

  According to the configuration of the first embodiment, the current path 16 that flows from the input terminal 14 to the output terminal 9 flows from the input terminal to the output terminal 9 via the base electrode 12, the capacitor 11, and the top electrode 10.

  With respect to the current path 17 that circulates in the parallel circuit of the inductor and the capacitor at the time of resonance, the current input from the inductor 13 to the base electrode 12 flows from the base electrode 12 to the top electrode 10 at the place where the electric field is strongest.

  In the case of a parallel plate capacitor, the electric field is the strongest near the input terminal 14 to the parallel plate capacitor, and the electric field is the weakest near the output terminal 9. Therefore, the current input from the inductor 13 to the base electrode 12 flows to the upper electrode 10 via the capacitor 11 in the vicinity of the input terminal of the base electrode 12 having the strongest electric field.

  The current flowing through the upper electrode 10 flows toward the inductor 13 or the output terminal 9. At this time, the direction in which the current flows is determined by the magnitude of the impedance viewed from the output terminal 9 side and the impedance viewed from the inductor 13 side from the point where the current flows to the upper electrode 10.

  When the impedance viewed from the output terminal 9 side is lower than the impedance viewed from the inductor 13 side, a current flows toward the output terminal 9. On the other hand, when the impedance viewed from the output terminal 9 side is lower than the impedance viewed from the inductor side, current flows to the inductor 13 side.

  Since the current flowing from the base electrode 12 to the upper electrode 10 in the immediate vicinity of the input terminal 14 having the strongest electric field includes the inductance of the upper electrode 10 when the output terminal 9 side is viewed from the point where the current flows, Impedance increases. Therefore, the above current flows to the inductor 13 side.

  In FIG. 1, the portion 15 a for connecting the upper electrode 10 and the inductor 13 is disposed immediately above the input terminal 14 of the base electrode 12, but this is not necessarily the case. The relationship between the two impedances described above is that the impedance relationship is reversed in the middle between the input terminal 14 and the output terminal 9 of the parallel plate electrode. Therefore, the location 15a connecting the upper electrode 10 and the inductor 13 is the output terminal of the parallel plate. 9 is required to be closer to the input terminal 14 than 9.

  Similarly, in FIG. 1, the portion 15 b for connecting the base electrode 12 and the inductor 13 is disposed immediately below the output terminal 9 of the top electrode, but this is not necessarily required. The direction in which the current flows from the input terminal 14 is determined by the impedance when the upper electrode 10 side is viewed from the input point.

  In the case of FIG. 1, the impedance when the upper electrode is viewed from the input terminal 14 via the capacitor 11 is determined only by the capacitor 11, but the impedance when the upper electrode is viewed via the inductor is the ground electrode 12 and the inductor 13. Since the former has a lower impedance, the current flowing from the input terminal flows to the upper electrode through the capacitor and does not flow toward the inductor 13. Therefore, the current path 16 flowing from the input terminal and the circulating current 17 are in opposite directions.

  Since this current relationship is reversed in the middle between the input terminal 14 and the output terminal 9, the portion 15b connecting the base electrode 12 and the inductor 13 needs to be connected to the output terminal 9 side rather than the input terminal 14 in the parallel plate. .

  In the case of the current path as described above, unlike the prior art, the location 15a connecting the inductor and the capacitor is in the opposite direction to the output terminal 9, so the current path 17 and the current path 16 at the upper electrode are in the opposite direction. Become.

  As described above, according to the configuration of the first embodiment, regarding the current flowing through each of the upper electrode 10 and the lower electrode 12, the current path 16 flowing from the input terminal 14 to the output terminal 9, the inductor and the capacitor at the time of resonance The current path 17 that goes around the parallel circuit is in the opposite direction.

  Therefore, the amount of current flowing through the upper electrode 10 and the lower electrode 12 is reduced as compared with the conventional configuration. When the amount of current decreases, both the conductor loss between the upper electrode 10 and the lower electrode 12 and the dielectric loss between the lower electrode 12 and the substrate decrease. Therefore, the parallel resonant circuit can realize higher impedance at the resonant frequency.

  FIG. 3 shows the result of calculating the value of the high-frequency current flowing through the inductor, the base electrode 12 and the top electrode 10 as a function of phase in the first embodiment of the present invention. The solid line represents the current flowing through the inductor, the dotted line represents the current flowing through the base electrode, and the alternate long and short dash line represents the current flowing through the top electrode.

  FIG. 4 shows the result of calculating the high-frequency current value flowing through the inductor, the base electrode 12 and the top electrode 10 in the prior art shown in FIG.

  Comparing FIG. 3 and FIG. 4, it can be seen that the sign of the current value flowing through the inductor is reversed, and the effective value of the current flowing through the upper electrode and the lower electrode is reduced.

  Next, FIG. 5 shows a comparison of the results of calculating the impedance of the parallel resonant circuit using the parallel resonant circuit shown in FIG. 1 and the conventional parallel resonant circuit in the first embodiment of the present invention. FIG. The calculation result shown in FIG. 5 shows the impedance when the output terminal 9 is grounded and the output side is viewed from the input terminal 14.

  A solid line 19 represents a calculation result in the conventional circuit configuration, and a dotted line 20 represents a calculation result in the circuit configuration of the first embodiment. A mark A on the solid line 19 and a mark B on the dotted line 20 represent resonance frequency points. The impedance at the resonance frequency is 22Ω in the case of the conventional circuit configuration and 45Ω in the case of the circuit configuration of the first embodiment, and the impedance at the resonance frequency is higher in the first embodiment. I understand that it is expensive.

  As described above, according to the first embodiment, the position where the output-side inductor and the capacitor are connected is the position of the upper electrode immediately above the connection position between the base electrode and the input terminal, and the input-side The parallel resonant circuit is configured so that the location where the inductor and the capacitor are connected is the location of the base electrode 12 directly below the location where the upper electrode and the output terminal 9 are connected. As a result, the impedance at the resonance frequency is increased, and the second harmonic impedance control circuit 4 is not affected by the external load. Therefore, a harmonic processing circuit capable of operating the amplifier with high efficiency can be realized.

Embodiment 2. FIG.
In the second embodiment, the parallel resonance circuit described in the first embodiment is applied to a harmonic processing circuit configured by combining a field effect transistor (FET) and a second harmonic load impedance control circuit. Will be described.

  FIG. 6 is a top view showing a harmonic processing circuit according to the second embodiment of the present invention. In FIG. 6, the FET is formed by a source electrode 25, a gate electrode 27, and a drain electrode 28, and a via hole 26 for grounding is formed in the source electrode 25.

  A transmission line composed of transmission lines 29a, 29b, and 29c is connected to the gate electrode 27 of the FET. The transmission line is connected to a second harmonic load impedance control circuit 24 in parallel, and a parallel resonant circuit 23 is connected in series.

  FIG. 12 is a diagram illustrating FIG. 6 with an equivalent circuit.

  In FIG. 12, in order to operate the FET 5 with high efficiency, the amplitude of the second harmonic load reflection coefficient that expects the input circuit from the gate that is the input terminal of the FET 5 is set to 1, and the phase is set to −90 ° to −180 °. Has been reported to be effective.

  Therefore, the inductance and the capacitance value in the second harmonic load impedance control circuit 24 in FIG. 6 are set so that the impedance in the second harmonic load impedance control circuit 24 becomes an optimum impedance for operating the FET with high efficiency. Is done.

  The parallel plate capacitor in the parallel resonance circuit 23 is formed in a rectangle, and the transmission line 29a is connected to the base electrode 22 at one end of the rectangle of the parallel plate capacitor in the parallel resonance circuit 23.

  On the other hand, the transmission line 29c and the upper electrode 21 of the parallel plate capacitor are connected by an air bridge 30 at the end of the side opposite to the rectangular side of the parallel plate capacitor to which the transmission line 29a is connected.

  At this time, the transmission line 29a and the transmission line 29c are connected to the parallel plate capacitor in the same direction, and both are connected to the ends of the opposite sides of the rectangular parallel plate capacitor in the same direction. On the other hand, one end of the transmission line 29 b is perpendicular to the direction in which the transmission line 29 a is connected to the base electrode 22 of the parallel plate capacitor, and is connected to the upper electrode 21 of the parallel plate capacitor at the same vertex of the rectangular parallel plate capacitor. Are connected by an air bridge 30.

  The other end of the transmission line 29b is connected to the base electrode 22 of the parallel plate capacitor in a direction perpendicular to the transmission line 29c at the position of the rectangular vertex where the transmission line 29c is connected to the parallel plate capacitor. .

  The area of the parallel plate capacitor of the parallel resonant circuit 23 and the transmission line 29b are set so as to resonate with a second harmonic of the fundamental wave to be used.

  FIG. 7 is a diagram showing the result of calculating the second harmonic impedance external circuit dependency using the harmonic processing circuit according to the second embodiment of the present invention. Here, for the impedance of the second harmonic load impedance control circuit 24, the reflection coefficient is set to 0.98, and the reflection phase is set to 158 degrees.

  As for the impedance of the external load circuit, the reflection coefficient is fixed at 0.9, the reflection phase is changed at an interval of 15 degrees between 0 and 360 degrees, and the input side from the input terminal of the FET at this time is changed. FIG. 7 shows the result of calculating the expected second harmonic load impedance.

  FIG. 8 is a diagram illustrating a result of calculating the second harmonic impedance external circuit dependency, similar to FIG. 7, by changing the parallel resonant circuit in the second embodiment of the present invention to the conventional circuit configuration. The calculation result is shown as reference numeral 32. By comparing the calculation results of FIG. 7 and FIG. 8, the harmonic processing circuit of the second embodiment has no influence on the impedance of the external load circuit compared to the case where the conventional parallel resonance circuit is used. It can be seen that the wave load impedance is robust.

  As described above, according to the second embodiment, the harmonic resonance circuit is configured by applying the parallel resonance circuit described in the first embodiment, so that the operation efficiency of the FET can be reduced without decreasing. A highly efficient amplifier can be realized.

Embodiment 3 FIG.
FIG. 9 is a top view showing a harmonic processing circuit according to the third embodiment of the present invention. When the configuration of FIG. 9 in the third embodiment and the configuration of FIG. 6 in the second embodiment are compared, the connection positions and connection directions of the transmission lines 29b and 29c are different.

  Specifically, in the second embodiment, the transmission line 29a and the transmission line 29c are connected to the parallel plate capacitor in the same direction, and both are end portions in the same direction on opposite sides of the rectangular parallel plate capacitor. Was connected to.

  On the other hand, in this Embodiment 3, the transmission line 29a and the transmission line 29c are connected to the diagonal vertex of a rectangular parallel plate capacitor. As a result, the third embodiment is characterized in that the connection direction of the transmission line 29c is changed to a direction orthogonal to the connection direction of the transmission line 29a by 90 degrees.

  As described above, according to the third embodiment, the connection direction of the transmission line can be changed after obtaining the same effect as in the second embodiment.

Embodiment 4 FIG.
In the second and third embodiments, the case where the harmonic processing circuit is arranged on the input side of the FET has been described. In contrast, in the fourth embodiment, a case where the harmonic processing circuit is arranged on the output side of the FET will be described.

  FIG. 15 is an equivalent circuit when the second harmonic processing circuit of FIG. 12 is configured on the output side of the FET 5. It has been reported that even if a circuit similar to FIG. 12 is configured on the output side of the FET 5 as shown in FIG. 15, the FET 5 can be operated with high efficiency (for example, see Non-Patent Document 2). ).

  The high frequency amplifier in FIG. 15 is a circuit in which the second harmonic load impedance control circuit 4 and the parallel resonance circuit 3 in FIG. 12 are added to the output side of the FET 5. A second harmonic load impedance control circuit 4 is arranged between the drain terminal which is the output terminal of the FET 5 and the parallel resonance circuit 3. Further, an input matching circuit 8 is arranged between the input terminal 1 and the gate which is the input terminal of the FET 5, and an external load circuit 2 is arranged between the parallel resonance circuit 3 and the output terminal 7.

  FIG. 10 is a top view showing a circuit configuration equivalent to FIG. 15 in the harmonic processing circuit according to the fourth embodiment of the present invention. In the fourth embodiment shown in FIG. 10, the harmonic processing circuit is arranged on the output side of the FET by arranging the second harmonic load impedance control circuit 24 between the parallel resonance circuit 23 and the drain electrode 28 of the FET. It is characterized by having been arranged in.

  In the configuration of FIG. 10, the transmission line 29a and the transmission line 29c are connected to the parallel plate capacitor in the same direction, and both are connected to the ends of the opposite sides of the rectangular parallel plate capacitor in the same direction. ing.

  As described above, according to the fourth embodiment, even when the harmonic processing circuit is arranged on the output side of the FET, the second and third embodiments in which the harmonic processing circuit is arranged on the input side of the FET and Similar effects can be obtained.

Embodiment 5. FIG.
FIG. 11 is a top view showing a harmonic processing circuit according to the fifth embodiment of the present invention. When the configuration of FIG. 11 in the fifth embodiment is compared with the configuration of FIG. 10 in the previous fourth embodiment, the connection positions and connection directions of the transmission lines 29b and 29c are different.

  Specifically, in the fourth embodiment, the transmission line 29a and the transmission line 29c are connected to the parallel plate capacitor in the same direction, and both are end portions in the same direction on opposite sides of the rectangular parallel plate capacitor. Was connected to.

  On the other hand, in this Embodiment 5, the transmission line 29a and the transmission line 29c are connected to the diagonal vertex of a rectangular parallel plate capacitor. As a result, the fifth embodiment is characterized in that the connection direction of the transmission line 29c is changed to a direction orthogonal to the connection direction of the transmission line 29a by 90 degrees.

  As described above, according to the fifth embodiment, the connection direction of the transmission line can be changed after obtaining the same effect as in the fourth embodiment.

  1 input terminal, 2 external load circuit, 3 parallel resonant circuit, 4 double wave load impedance control circuit, 6 output matching circuit, 7 output terminal, 8 input matching circuit, 9 output terminal, 10 upper electrode, 11 capacitance part, 12 ground electrode, 13 inductor, 14 input terminal, 15a, 15b connection point, 16 current path from input terminal to output terminal, 17 current path that circulates in parallel circuit of inductor and capacitor, 18 ground electrode to ground electrode in capacitor Current path flowing in the direction of, 21 upper electrode of the parallel plate capacitor, 22 ground electrode of the parallel plate capacitor, 23 parallel resonant circuit, 24 double wave load impedance control circuit, 25 source electrode, 26 via hole, 27 gate electrode, 28 Drain electrode, 29a, 29b, 29c Transmission line, 30 Air bullet .

Claims (3)

A parallel resonant circuit comprising a parallel plate capacitor having an upper electrode and a base electrode, and a transmission line, and formed by parallel connection of a capacitance component of the parallel plate capacitor and an inductor component of the transmission line,
The upper electrode has a first input terminal and a first output terminal as input / output terminals,
The base electrode has a second input terminal and a second output terminal as input / output terminals,
The second input terminal is used as an external input terminal for a signal input from the outside,
The first output terminal is used as an external output terminal of a signal output to the outside,
The transmission line is connected between the second output terminal and the first input terminal;
The connection point between the transmission line and the first input terminal is disposed at a position closer to the external input terminal than the external output terminal,
A connection point between the transmission line and the second output terminal is a parallel resonance circuit arranged at a position closer to the external output terminal than the external input terminal . A parallel resonant circuit according to claim 1;
A harmonic treatment circuit comprising an inductor connected in series and a second harmonic load impedance control circuit having a capacitor,
The external input terminal of the parallel resonant circuit is connected to the input terminal of the high frequency amplifier,
The harmonic processing circuit, wherein one end of the second harmonic load impedance control circuit is grounded and the other end is connected to the external output terminal. A parallel resonant circuit according to claim 1;
A harmonic treatment circuit comprising an inductor connected in series and a second harmonic load impedance control circuit having a capacitor,
The external input terminal of the parallel resonant circuit is connected to the output terminal of the high frequency amplifier,
One end of the second harmonic load impedance control circuit is grounded , and the other end is connected to the external input terminal.

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