JP6455014B2 - Infrared imaging device and infrared imaging device - Google Patents

Description

  The present invention relates to an infrared imaging device and an infrared imaging device.

  Conventionally, what uses infrared rays as a night vision camera is known. This is because all the objects having temperature emit infrared rays, and the emission of infrared rays in the 10 μm band is the greatest at room temperature.

  Therefore, in order to detect such infrared rays in the 10 μm band with high sensitivity, a photodetector that detects light by capturing a current that flows when absorbing incident infrared rays is used. In particular, a quantum well infrared detector (QWIP) using a transition through a quantum level on the conduction band side in a quantum well structure has attracted attention.

  Such QWIPs are arranged in a two-dimensional matrix, and a signal readout circuit is connected to each pixel element via an In electrode, which is used as an FPA (Focal Plane Array) type infrared imaging device. In QWIP, a pixel is obtained by scanning a change in charge amount in a certain accumulation time or a specified time of integration time in an electric capacity (storage capacity) due to an element current flowing in each pixel element as a voltage change at both ends of the capacity in time series. A method of reading as output is performed.

  Here, with reference to FIG. 14, an FPA type infrared imaging device will be described. FIG. 14 is an equivalent circuit diagram showing one pixel of a conventional FPA type infrared imaging device. The QWIP element 71 is connected to a bias / switching transistor 72, and the other end of the bias / switching transistor 72 is connected to a charge storage capacitor 73.

In such a connection state, a bias voltage V _A that actually applied to the QWIP device 71 is determined by a constant I ₀ determined by the transistor 72 for bias and switching. When V _g is a voltage between the source and gate of the transistor 72, V _th is a threshold gate voltage, and I is a current flowing through the whole,
_{I = (I 0/2)} × (V g -V th) 2
It is represented by If this is transformed,
V _g −V _th = (2I / I ₀ ) ^1/2
It becomes.

Here, when V _IG is an applied gate voltage applied to the gate of the transistor 72,
_{V g} = V _IG -V _A
And substituting the above equation for Vg,
V _g = V _IG -V _A = (2I / I ₀ ) ^1/2 + V _th
It becomes. Organizing this for _VA ,
V _A = V _IG −V _th − (2I / I ₀ ) ^1/2
It becomes.

By the way, when such an FPA-type infrared imaging device is actually created, if a configuration in which V _IG is individually applied to each pixel, the readout circuit becomes complicated, which is not practical. Therefore, as shown in FIG. 15, it is often configured to apply uniformly to all pixels or at least a block of a plurality of pixels.

FIG. 15 is an explanatory diagram of a voltage application method of a conventional FPA type infrared imaging device. The QWIP elements 71 ₁ and 71 ₂ are connected to the transistors 72 ₁ and 72 ₂ and to the common line 74, respectively. The gate of the transistor ₇₂ 1, 72 _2, applied gate voltage _{V IG} via the word line 75 is applied.

JP 2010-192815 A

Matsunami Hiroyuki, “Semiconductor Engineering”, Shoshodo, 1983, p.175

However, in the case of the conventional voltage application method, there is a possibility that problems such as hindering signal processing may occur due to variations in manufacturing of the QWIP element. For example, the QWIP device 71 ₁ shown in FIG. 15 at a relatively high resistance, QWIP element 71 ₂ may, as a low resistance, the pixel output is output with a course difference that reflects the difference. At this time, if the QWIP device ₇₁ 1, 71 is large resistance difference between the _two, whereas in the QWIP device 71 ₁ yet not sufficiently pixel output is obtained, the storage capacitor in the QWIP device ₇₁₂ will be completely discharged all. Alternatively, the difference in output between the QWIP elements 71 ₁ and 71 ₂ exceeds the width (dynamic range) assumed in the signal processing circuit in the subsequent stage, which hinders signal processing.

  Therefore, an object of the present invention is to improve the in-plane uniformity of pixel output without greatly complicating the device configuration in an infrared imaging device and an infrared imaging device.

More of the one aspect disclosed, having a semiconductor substrate, as well as arranged in a two-dimensional lattice shape on a semiconductor substrate, a second electrode for reading an output a first electrode connected to the first common wiring and pixels, said to have the said suppressing control mechanism output difference between pixels by applying the negative feedback with respect to automatically detect and each pixel output difference between pixels, the control mechanism An infrared imaging device is provided, which is a load element connected between the second electrode and a second common wiring connected to a fixed potential other than the ground potential .

From another viewpoint disclosed a semiconductor substrate, as well as arranged in a two-dimensional lattice shape on a semiconductor substrate, a second electrode for reading an output a first electrode connected to the first common wiring possess a plurality of pixels, said a suppressing control mechanism output difference between the respective pixels by the output difference automatically detects give negative feedback with respect to each of the pixels between the pixels having the An infrared imaging device that is a load element connected between the second electrode and a second common wiring connected to a fixed potential other than the ground potential; and a bias and switching corresponding to each pixel. There is provided an infrared imaging device comprising: a signal processing circuit board in which transistors are arranged in a two-dimensional lattice pattern; and a protruding electrode that connects the pixels and the transistors in a 1: 1 ratio.

  According to the disclosed infrared imaging element and infrared imaging device, it is possible to improve in-plane uniformity of pixel output without greatly complicating the device configuration.

It is sectional drawing of the infrared imaging element of embodiment of this invention. 1 is an equivalent circuit diagram of an infrared imaging device according to an embodiment of the present invention. It is IV characteristic view of an infrared detection element. It is explanatory drawing of the simulation result of a pixel output. It is a schematic sectional drawing of the infrared image sensor of Example 1 of this invention. 1 is an equivalent circuit diagram of an infrared imaging device according to Embodiment 1 of the present invention. It is explanatory drawing to the middle of the manufacturing process of the infrared imaging element of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 7 of the manufacturing process of the infrared imaging element of Example 1 of this invention. It is explanatory drawing after FIG. 8 of the manufacturing process of the infrared image pick-up element of Example 1 of this invention. It is a schematic perspective view of the infrared image sensor of Example 1 of the present invention. 1 is a partially cutaway perspective view of an infrared imaging device according to Embodiment 1 of the present invention. It is a schematic sectional drawing of the infrared image sensor of Example 2 of this invention. It is the equivalent circuit schematic of the infrared imaging device of Example 2 of this invention. It is an equivalent circuit diagram which shows one pixel of the conventional FPA type infrared imaging device. It is explanatory drawing of the voltage application method of the conventional FPA type infrared imaging device.

Here, with reference to FIG. 1 thru | or FIG. 4, the infrared imaging device of embodiment of this invention is demonstrated. FIG. 1 is a cross-sectional view of a main part of an infrared imaging device according to an embodiment of the present invention. The infrared imaging element is integrated with the signal processing circuit board to form an infrared imaging device. A first electrode 16 ₁ , 16 ₂ connected to the first common wiring 18 and a second electrode 17 ₁ , 17 ₂ for reading out the output are arranged on the semiconductor substrate 11 in a two-dimensional lattice pattern. A plurality of pixels 14 ₁ and 14 ₂ are provided. Each pixel ₁₄ 1, 14 automatically detects each pixel ₁₄ 1, 14 pixels ₁₄ 1 by providing a negative feedback for _two, 14 suppressing control mechanism output difference between the _two output difference between the _two Provide.

The control mechanism is a load element ₁₃ 1, 13 _2, such as the connected fixed resistance element or a diode between the second electrode ₁₇ 1, 17 ₂ and the second common line 12, load elements ₁₃ 1, Reference numeral 13 ₂ denotes a semiconductor layer provided between the semiconductor substrate 11 and the pixels 14 ₁ and 14 ₂ . Reference numeral 19 denotes an extraction electrode from the second common wiring 12.

The pixels 14 ₁ and 14 _{2 in} this case are typically QWIP provided with a multiple quantum well structure using a transition through a quantum level on the conduction band side in the quantum well structure or QDIP using a quantum dot. Become. However, the structure of the light receiving portion is not limited to QWIP or QDIP using transition via a quantum level on the conduction band side, and the material is not limited to a III-V group compound semiconductor. When such QWIP is used, it is necessary to provide an optical coupling structure 15 such as a diffraction grating on the top.

Such an infrared imaging device and a signal processing circuit board in which transistors for bias and switching corresponding to each of the pixels 14 ₁ and 14 ₂ are arranged in a two-dimensional lattice are 1: 1 by a protruding electrode such as an In bump. It becomes an infrared imaging device by connecting with.

FIG. 2 is an equivalent circuit diagram of the infrared imaging device according to the embodiment of the present invention. The equivalent circuit shown in the voltage application method of the conventional infrared imaging device in FIG. Load elements 13 ₁ and 13 ₂ are connected between the electrodes 17 ₁ and 17 ₂ . Also here, the storage capacitor C connected to the drain side of the transistors 21 ₁ and 21 ₂ is not shown.

In the initial state, the storage capacitor C is fully charged at a certain voltage V _R. When a constant applied gate voltage _VIG is applied to the gate electrodes of the transistors 21 ₁ and 21 ₂ connected to the storage capacitor C through the word line 22 for a certain time τ, the channels of the transistors 21 ₁ and 21 ₂ become conductive. . As a result, to the current I corresponding to the intensity of the infrared light incident on the pixel ₁₄ 1, 14 ₂ flows into the pixel ₁₄ 1, 14 _2.

At this time, if the amount of change in the voltage across the storage capacitor C before and after the time τ (0 → τ = Δt) is _VDC , the charge Q stored in the storage capacitor C and the both ends of the storage capacitor C From the well-known relational expression Q = CV concerning the potential V,
ΔQ = CΔV
And the flowing current I is the time change of the charge,
I = ΔQ / Δt = (CΔV) / τ = C · V _DC / τ
The relationship is established. On the other hand, the source-drain saturation current _ID in the field effect transistor uses a constant I ₀ that does not depend on the bias state of the field effect transistor, where V _g is the source-gate voltage and V _th is the threshold voltage. And
_{I D = (I 0/2} ) × (V g -V th) 2
(For example, refer nonpatent literature 1 etc.).

Normally, since the charging voltage V _R of the storage capacity up to conduct the transistors 21 _1, 21 ₂ of the channel it is designed to be sufficiently large, the source at the time the transistor 21 _1, 21 ₂ channels are turned - drain The voltage _Vg is sufficiently large. Therefore, the transistors 21 ₁ and 21 ₂ operate so as to supply a constant saturation current _ID corresponding to infrared incident light to the pixels 14 ₁ and 14 ₂ .

On the other hand, the potential V _A of the second electrodes 17 ₁ and 17 ₂ connected to the transistors of the infrared detector elements that are the pixels 14 ₁ and 14 ₂ with respect to the first electrodes 16 ₁ and 16 ₂ is the same as in the conventional case. It is represented by the following formula.
_{V g} = V IG -V _A
However, an applied gate voltage applied between the second common wiring 12 and the gate electrodes of the transistors 21 ₁ and 21 ₂ is V _IG .

Here, when substituting into the above-mentioned formula relating to _ID ,
_{I D = (I 0/2} ) × (V g -V th) 2 = (I 0/2) × (V IG -V A -V th) 2
It becomes. Therefore,
_{C · V DC / τ = (} I 0/2) × (V IG -V A -V th) 2
Then, when organizing the formula for _VA ,
V _A = V _IG −V _th − [2C / (I ₀ · τ) × V _DC ] ^1/2
The relationship is derived.

From this equation, the current corresponding to the infrared light incident on a certain pixel 14 ₁ (14 ₂ ), and hence the difference in _VDC between the pixels, is the difference in the voltage _VA applied to that pixel 14 ₁ (14 ₂ ). It is understood that it is reflected as. The pixel ₁₄ 1, 14 the difference between _{V A} of between ₂ detected somehow, be given a negative feedback to the pixel ₁₄ 1 (14 ₂₎ on the basis thereof, the pixel ₁₄ 1, 14 of the output of between ₂ It has been found that the difference can be suppressed.

Therefore, as a result of earnest research, the inventors have come up with the idea that the necessary negative feedback can be provided by the equivalent circuit conceptually shown in FIG. 2 as a simple method for realizing such negative feedback. That is, the second common wiring 12 is provided in the conventional infrared imaging device, and the load element 13 is provided between the second common wiring 12 and the second electrodes 17 ₁ and 17 ₂ of the pixels 14 ₁ and 14 ₂ . _1, 13 can provide a negative feedback required by connecting ₂ to.

Here, for the sake of simplicity, it is assumed that the second common wiring 12 is set to the potential V _A1 . In the pixel 14 _1, a new current component since both ends of the load element 13 ₁ are both located at a potential V _A1 does not occur, the same as the conventional operation. On the other hand, in the pixel 14 _2, before connecting the load element 13 _2, since the bias voltage to the pixel 14 ₂ is _V A2 _{<V A1,} the second common with connecting the load device 13 ₂ to the load device 13 ₂ It tends to flow current toward the wiring 12 to the pixel 14 _2. Incidentally, the load element 13 ₂ is the resistance value if fixed resistance element R, the magnitude of the current tries to flow becomes _{(V A1 -V A2) / R} . Further, by using the diode as a load element 17 _2, which tends to flow a current corresponding to the non-linear characteristics.

On the other hand, the transistor 21 ₂ to the pixel 14 ₂ is connected, since it is possible to compensate for the portion of the current flowing in the pixel 14 ₂ by a current tends to flow toward the pixel 14 _2, the transistor 21 ₂ The flowing current is reduced, so that _VA2 rises. As a result, the pixel 14 _2, a pixel 14 ₂ is operated in _{V A2 '(V A1> V} A2'> V A2) in which the current flowing through each of the transistors 21 ₂ and the load device 13 ₂ are balanced. As a result, the pixel output of the pixel 14 ₂ is smaller than the pixel output of the prior art, it is possible to suppress the variation of the pixel output in the entire FPA as compared with the conventional art.

For example, it is assumed that two infrared detector elements having IV characteristics as shown in FIG. 3 are pixels 14 ₁ and 14 ₂ , respectively. FIG. 4 is a diagram in which the pixel outputs of the pixels 14 ₁ and 14 ₂ are obtained by simulation and expressed as a relative variation with respect to the pixel 14 ₁ . Here, the simulation was performed with the light receiving portion having a size of V _IG = 1.5 V, R = 20 MΩ, and 20 μm × 20 μm. As a result, the effect of the present invention explained qualitatively as described above could be confirmed. Accordingly, by using the load elements 13 _1, 13 ₂ as in the present invention, a self-aligned manner negative feedback occurs speak to each pixel output, as a result, improved in-plane uniformity of the FPA pixel output .

  Next, an infrared imaging device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a schematic cross-sectional view of the infrared imaging device according to the first embodiment of the present invention. The n-type is a second common electrode provided on the semi-insulating GaAs substrate 31 via the i-type GaAs buffer layer 32. A laminated structure of fixed resistance elements and pixels is formed on the GaAs layer 33. The fixed resistance element is formed of an n-type AlGaAs layer 34, and the pixel is formed of an n-type GaAs layer 35 serving as a lower electrode, a multiple quantum well layer 36, and an n-type GaAs layer 37 serving as an upper electrode. Further, the diffraction grating 40 is provided by processing an n-type GaAs layer provided on the pixel via an n-type AlGaAs etching stop layer 38. The first electrode 46 of each pixel is connected by an extraction electrode 49 serving as a first common wiring. In addition, an individual extraction electrode 50 is extracted from the second electrode 47. In addition, an extraction electrode 51 is extracted from the common electrode 48 provided on the n-type GaAs layer 33 serving as the second common electrode, and an In bump 52 for lip chip bonding is provided on each of the extraction electrodes 49 to 51.

FIG. 6 is an equivalent circuit diagram of the infrared imaging device according to the first embodiment of the present invention. In the equivalent circuit shown by the voltage application method of the conventional infrared imaging device in FIG. 15, n-type GaAs serving as a second common wiring is shown. Fixed resistance elements 54 ₁ and 54 ₂ having a resistance value R are connected between the layer 33 and the second electrodes 47 ₁ and 47 ₂ . Also here, the storage capacitor C connected to the drain side of the transistors 63 ₁ and 63 ₂ is not shown.

In the initial state, the storage capacitor C is fully charged at a certain voltage V _R. When a constant applied gate voltage _VIG is applied to the gate electrodes of the transistors 63 ₁ and 63 ₂ to which the storage capacitor C is connected via the word line 64 for a certain time τ, the channels of the transistors 63 ₁ and 63 ₂ become conductive. . As a result, the current I corresponding to the intensity of the infrared light incident on the pixel ₅₃ 1, 53 ₂ flows into the pixel ₅₃ 1, 53 _2.

As described above, it is assumed that the n-type GaAs layer 33 serving as the second common wiring is set to the potential V _A1 . In the pixel 53 ₁ , both ends of the fixed resistance element 54 ₁ are at the potential V _A1 , so no new current component is generated and the operation is the same as in the conventional operation. On the other hand, in the pixel 53 _2, before connecting the fixed resistance element 54 _2, since the bias voltage to the pixel 53 ₂ is _V A2 _{<V A1,} the fixed resistance element 54 ₂ to n-type GaAs layer 33 from the pixel 53 ₂ A current of the magnitude of (V _A1 −V _A2 ) / R tends to flow toward

On the other hand, the transistor 63 ₂ to the pixel 53 ₂ is connected, since it is possible to compensate for the portion of the current flowing in the pixel 53 ₂ by a current tends to flow toward the pixel 53 _2, the transistor 63 ₂ The flowing current is reduced, so that _VA2 rises. As a result, the pixel 53 _2, with _{V A2 '(V A1> V} A2'> V A2) in which the current flowing through each of the transistors 63 ₂ and the fixed resistance element 54 ₂ are balanced pixel 53 ₂ is operated . As a result, the pixel output of the pixel ₅₄₂ is smaller than the pixel output of the prior art, it is possible to suppress the variation of the pixel output in the entire FPA as compared with the conventional art.

  Next, with reference to FIGS. 7 to 9, the manufacturing process of the infrared imaging element according to the first embodiment of the present invention will be described. First, as shown in FIG. 7A, after the i-type GaAs buffer layer 32 is grown on the semi-insulating GaAs substrate 31 by using the molecular beam epitaxy technique, the thickness of the second common wiring is as follows. A 500 nm n-type GaAs layer 33 is grown. Subsequently, an n-type AlGaAs layer 34 having a thickness of 1000 nm to be a fixed resistance element is grown. Subsequently, an n-type GaAs layer 35 having a thickness of 500 nm serving as a lower electrode layer, a multiple quantum well layer 36 serving as a light receiving portion, and an n-type GaAs layer 37 serving as an upper electrode having a thickness of 500 nm are grown. Subsequently, an n-type AlGaAs etching stop layer 38 having a thickness of 5 nm and an n-type GaAs layer 39 having a thickness of 350 nm are sequentially grown. The multiple quantum well layer 36 is formed by growing 50 cycles of an AlGaAs barrier layer having a thickness of 50 nm and a GaAs well layer having a thickness of 5 nm.

  Next, as shown in FIG. 7B, the n-type GaAs layer 39 is etched to form a diffraction grating 40. Since QWIP has no sensitivity to light perpendicularly incident on the multiple quantum well layer 36, incident light is diffracted by the diffraction grating 40 and absorbed by the multiple quantum well layer 36.

  Next, as shown in FIG. 8C, the n-type GaAs layer 39 (n-type AlGaAs etching stop layer 38) to the n-type AlGaAs layer 34 are selectively etched to form a pixel isolation groove 41. At this time, the width of the pixel isolation trench 41 is increased in the contact electrode formation portion for the n-type GaAs layer 33 serving as the second common wiring.

  Next, as shown in FIG. 8D, the n-type GaAs layer 39 (n-type AlGaAs etching stop layer 38) to the multiple quantum well layer 36 are etched to expose the n-type GaAs layer 35 serving as the lower electrode layer.

  Next, as shown in FIG. 9E, after a SiON film 42 is deposited on the entire surface, contact holes 43 to 45 for the n-type GaAs layer 39, the n-type GaAs layer 35, and the n-type GaAs layer 33 are formed.

  Next, as shown in FIG. 9 (f), an Au · Ge / Ni film is deposited to form ohmic electrodes in the contact holes 43 to 45, and the first electrode 46, the second electrode 47 and the common electrode 48 are formed. To do. Next, after depositing an Au film on the entire surface, extraction electrodes 49 to 51 are formed by etching. Finally, by forming the In bumps 52, the basic structure of the infrared imaging element 30 according to the first embodiment of the present invention is completed. The lead electrode 49 serves as a first common wiring, and the lead electrode 51 serves as a lead electrode from the second common wiring.

  FIG. 10 is a schematic perspective view of the infrared imaging element at the stage where the In bump is formed. A stacked body of fixed resistance elements and pixels is arranged in a lattice pattern on the n-type GaAs layer 33 serving as the second common wiring. It becomes a state.

  FIG. 11 is a partially cutaway perspective view of the infrared imaging device according to the first embodiment of the present invention. The infrared imaging device 30 shown in FIG. 10 is hybrid-connected to the Si signal processing circuit device 60 in which the signal readout circuit 61 and the bias / switching transistor are formed by the In bumps 52 by using the flip chip bonding technique, thereby the infrared imaging device. It becomes the main body. Finally, the infrared imaging device of the present invention is completed by completing the necessary optical system and the installation in the cooling dewar container for the main body of the infrared imaging device.

  As described above, in the first embodiment of the present invention, the second common wiring is connected to the second electrode of each pixel via the fixed resistance element. Negative feedback will occur. As a result, the in-plane uniformity of the FPA pixel output can be improved without greatly complicating the overall apparatus configuration.

  Next, an infrared imaging apparatus according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 12 is a schematic cross-sectional view of the infrared imaging device according to the second embodiment of the present invention. The basic structure is the same as that of the first embodiment, but the p-type GaAs layer 55 is used as the second common wiring. A diode using the p-type AlGaAs layer 56 is used as a load element.

  That is, a stacked structure of a diode and a pixel is formed on the semi-insulating GaAs substrate 31 on the i-type GaAs buffer layer 32 and the p-type GaAs layer 55 that serves as the second common electrode. The diode is formed by a pn junction between the p-type AlGaAs layer 56 and the n-type GaAs layer 35.

Figure 13 is an equivalent circuit diagram of the infrared imaging apparatus of the second embodiment of the present invention, the fixed resistance elements 54 _1, 54 ₂ diodes 57 ₁ in the equivalent circuit of the infrared imaging apparatus of the first embodiment shown in FIG. 6, it is replaced with a 57 _2. Also here, the storage capacitor C connected to the drain side of the transistors 63 ₁ and 63 ₂ is not shown. In this case, the diode ₅₇ 1, 57 a current corresponding to negative feedback by the diodes ₅₇ 1, 57 ₂ of the non-linear characteristics because of the use of ₂ tries to flow toward the pixel ₅₃ 1, 53 ₂ as a load element.

  Also in Embodiment 2 of the present invention, negative feedback is generated in a self-aligned manner with respect to each pixel output by utilizing the non-linear characteristics of the diode, so that the FPA pixel output can be reduced without greatly complicating the device configuration. In-plane uniformity can be improved.

  In the description of each of the above embodiments, the first common wiring and the first electrode are electrically connected on the infrared imaging element side. However, the first common wiring is electrically connected to each other. In addition, since it only needs to be connected to the bias circuit, it may be performed on the Si signal processing circuit board side. In the description of the present invention, the QWIP element has been described as an example. However, as often described above, the present invention is not limited to the QWIP element. That is, a semiconductor substrate, a plurality of pixels arranged in a two-dimensional lattice pattern on the semiconductor substrate, and having a first electrode connected to a common wiring and a second electrode for reading out an output, and between the pixels And a control mechanism that suppresses the output difference between the pixels by automatically detecting the output difference and giving negative feedback to the pixels. An infrared imaging device can be formed by arranging in a dimension.

Here, the following supplementary notes are attached to the embodiment of the present invention including Example 1 and Example 2.
(Supplementary Note 1) and the semiconductor substrate, as well as arranged in a two-dimensional lattice shape on a semiconductor substrate, a plurality of pixels having a second electrode for reading an output a first electrode connected to the first common wiring , wherein possess a suppressing control mechanism output difference between pixels by applying the negative feedback with respect to automatically detect and each pixel output difference between pixels, the control mechanism, the first An infrared imaging device, characterized in that it is a load element connected between the two electrodes and a second common wiring connected to a fixed potential other than the ground potential .
(Supplementary note 2 ) The infrared imaging element according to supplementary note 1 , wherein the load element is a fixed resistance element.
(Supplementary note 3 ) The infrared imaging element according to supplementary note 2 , wherein the fixed resistance element is formed of a semiconductor layer provided between the semiconductor substrate and the pixel.
(Supplementary note 4 ) The infrared imaging element according to supplementary note 1 , wherein the load element is a diode.
(Supplementary note 5 ) The infrared imaging element according to supplementary note 4 , wherein the diode element includes a p-type semiconductor layer and an n-type semiconductor layer provided between the semiconductor substrate and the pixel.
(Appendix 6 ) In any one of appendix 1 to appendix 5 , the pixel has a multiple quantum well structure using a transition through a quantum level on the conduction band side in the quantum well structure. The infrared imaging element described.
And (Supplementary Note 7) a semiconductor substrate, as well as arranged in a two-dimensional lattice shape on a semiconductor substrate, a plurality of pixels having a second electrode for reading an output a first electrode connected to the first common wiring , wherein possess a suppressing control mechanism output difference between pixels by applying the negative feedback with respect to automatically detect and each pixel output difference between pixels, the control mechanism, the first An infrared imaging device which is a load element connected between the two electrodes and a second common wiring connected to a fixed potential other than the ground potential, and a bias and switching transistor corresponding to each pixel are two-dimensionally arranged. An infrared imaging apparatus, comprising: a signal processing circuit board arranged in a lattice pattern; and a protruding electrode that connects the pixels and the transistors in a 1: 1 ratio.

11 Semiconductor substrate 12 Second common wiring 13 ₁ , 13 ₂ Load element 14 ₁ , 14 ₂ Pixel 15 Optical coupling structure 16 ₁ , 16 ₂ First electrode 17 ₁ , 17 ₂ Second electrode 18 First common wiring 19 Extraction electrodes 21 ₁ and 21 ₂ Transistor 22 Word line 30 Infrared imaging device 31 Semi-insulating GaAs substrate 32 i-type GaAs buffer layer 33 n-type GaAs layer 34 n-type AlGaAs layer 35 n-type GaAs layer 36 Multiple quantum well layer 37 n -type GaAs layer 38 n-type AlGaAs etching stop layer 39 n-type GaAs layer 40 diffraction grating 41 pixel isolation trench 42 SiON film 43 to 45 contact holes 46 _1, 46 ₂ first electrode 47 _1, 47 ₂ second common electrode 49 to 51 lead electrode 52 of the electrode 48 an in bump ₅₃ 1, 53 ₂ pixel ₅₄ 1, 54 ₂ fixed resistance element 5 p-type GaAs layer 56 p-type AlGaAs layer ₅₇ 1, 57 ₂ diodes 60 Si signal processing circuit board 61 read circuit 62 infrared ₆₃ 1, 63 ₂ transistor 64 word lines 71, 71 _{1, 71} 2 QWIP elements 72, 72 _1, 72 ₂ transistor 73 capacitor 74 common wiring 75 word line

Claims (4)

A semiconductor substrate;
While arranged in a two-dimensional lattice shape on a semiconductor substrate, a plurality of pixels having a second electrode for reading an output a first electrode connected to the first common wiring,
Wherein possess a suppressing control mechanism output difference between the pixels by providing a negative feedback with respect to automatically detect and each pixel output difference between the pixels,
The infrared imaging element , wherein the control mechanism is a load element connected between the second electrode and a second common wiring connected to a fixed potential other than a ground potential . The infrared imaging element according to claim 1 , wherein the load element is a fixed resistance element. The infrared imaging element according to claim 1 , wherein the load element is a diode. A semiconductor substrate;
While arranged in a two-dimensional lattice shape on a semiconductor substrate, a plurality of pixels having a second electrode for reading an output a first electrode connected to the first common wiring,
Wherein possess a suppressing control mechanism output difference between pixels by applying the negative feedback with respect to automatically detect and each pixel output difference between pixels, the control mechanism, the second An infrared imaging element which is a load element connected between the electrode of the second electrode and a second common wiring connected to a fixed potential other than the ground potential ;
A signal processing circuit board in which transistors for bias and switching corresponding to each pixel are arranged in a two-dimensional lattice;
An infrared imaging device, comprising: a projection electrode that connects the pixels and the transistors in a ratio of 1: 1.

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