JP6462926B2 - Storage device and electronic device - Google Patents

Description

  Embodiments described herein relate generally to a storage apparatus and an electronic apparatus.

  A semiconductor device having a semiconductor memory chip is provided.

JP 2013-200595 A

  The semiconductor device preferably has good heat dissipation.

  An object of the present invention is to provide a storage device and an electronic apparatus having good heat dissipation.

  According to the embodiment, the storage device includes a substrate, a semiconductor memory, a controller, a sealing unit, and a plurality of heat dissipation balls. The semiconductor memory is disposed on the first surface of the substrate. The controller is disposed on the first surface of the substrate and controls the semiconductor memory. The sealing portion integrally covers the semiconductor memory and the controller on the first surface of the substrate. The plurality of heat dissipation balls are disposed on a second surface of the substrate facing the first surface. The substrate includes a first region which is a region on the second surface facing the controller on the first surface, and a second region located outside the first region. The arrangement density of the heat dissipation balls in the second region is higher than the arrangement density of the heat dissipation balls in the first region.

1 is a perspective view illustrating an electronic apparatus according to a first embodiment. FIG. 2 is a block diagram illustrating the configuration of a part of the circuit board shown in FIG. 1. FIG. 2 is a block diagram illustrating the configuration of the semiconductor package shown in FIG. 1. FIG. 2 is a cross-sectional view illustrating the semiconductor package shown in FIG. 1. FIG. 9 is a cross-sectional view illustrating a first modification of the semiconductor package shown in FIG. 1. FIG. 9 is a cross-sectional view illustrating a second modification of the semiconductor package shown in FIG. 1. FIG. 2 is a bottom view illustrating the bottom surface of the semiconductor package shown in FIG. 1. The figure which illustrated assignment of the solder ball shown in FIG. The figure which illustrated the contents of the assignment shown in FIG. The top view which illustrated the pad of the circuit board concerning a 1st embodiment. The figure which illustrated assignment of the solder ball of the semiconductor package concerning a 2nd embodiment. The figure which expanded and illustrated the area | region enclosed with F12 line | wire of the semiconductor package shown in FIG. The top view which illustrated the pad of the circuit board concerning a 2nd embodiment. FIG. 14 is a diagram schematically illustrating a part of the signal lines illustrated in FIG. 13. The figure which illustrated typically the 1st modification of the signal line shown in FIG. The figure which illustrated typically the 2nd modification of the signal line shown in FIG. The figure which illustrated assignment of the solder ball of the semiconductor package concerning a 3rd embodiment. The figure which expanded and illustrated the area | region enclosed with F18 line | wire of the semiconductor package shown in FIG. The figure which illustrated typically some signal lines concerning a 3rd embodiment. The figure which illustrated assignment of the solder ball of the semiconductor package concerning a 4th embodiment. The figure which expanded and illustrated the area | region enclosed by the F21 line of the semiconductor package shown in FIG. The figure which illustrated typically some signal lines concerning a 4th embodiment.

  Hereinafter, embodiments will be described with reference to the drawings.

  In the present specification, examples of a plurality of expressions are given to some elements. Note that these examples of expressions are merely examples, and do not deny that the above elements are expressed in other expressions. In addition, elements to which a plurality of expressions are not attached may be expressed in different expressions.

  The drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like may be different from the actual ones. Moreover, the part from which the relationship and ratio of a mutual dimension differ between drawings may be contained.

(First embodiment)
1 to 10 show a semiconductor package 1 according to the first embodiment. The semiconductor package 1 is an example of each of “semiconductor device” and “semiconductor memory device”. A semiconductor package 1 according to this embodiment is a so-called BGA-SSD (Ball Grid Array-Solid State Drive), and a plurality of semiconductor memory chips and a controller are integrally configured as one BGA type package.

  FIG. 1 shows an example of an electronic device 2 on which a semiconductor package 1 is mounted. The electronic device 2 is an example of each of “system”, “device”, and “unit”. The electronic device 2 includes a housing 3 and a circuit board 4 (for example, a main board) accommodated in the housing 3. The semiconductor package 1 is attached to the circuit board 4 and functions as a storage device for the electronic device 2. The circuit board 4 has a host controller 5 (for example, CPU). The host controller 5 includes, for example, a south bridge, and controls the overall operation of the electronic device 2 including the semiconductor package 1.

  FIG. 2 schematically shows a part of the configuration of the circuit board 4. The host controller 5 and the semiconductor package 1 according to the present embodiment have an interface conforming to the PCI Express (hereinafter, PCIe) standard. A plurality of signal lines 6 are provided between the host controller 5 and the semiconductor package 1. The semiconductor package 1 exchanges a high-speed signal conforming to the PCIe standard with the host controller 5 via the signal line 6.

  A power supply circuit 7 is provided on the circuit board 4. The power supply circuit 7 is connected to the host controller 5 and the semiconductor package 1 through power supply lines 8a and 8b. The power supply circuit 7 supplies various power supplies for operating the electronic device 2 to the host controller 5 and the semiconductor package 1.

Next, the configuration of the semiconductor package 1 will be described.
FIG. 3 is a block diagram showing an example of the configuration of the semiconductor package 1. The semiconductor package 1 includes a controller chip 11, a semiconductor memory chip 12, a DRAM chip 13, an oscillator (OSC) 14, an electrically erasable and programmable ROM (EEPROM) 15, and a temperature sensor 16.

  The controller chip 11 (that is, the controller) is a semiconductor chip that controls the operation of the semiconductor memory chip 12. The semiconductor memory chip 12 is, for example, a NAND chip (NAND flash memory). The NAND chip is a non-volatile memory and retains data even when power is not supplied. The DRAM chip 13 is used for storing management information of the semiconductor memory chip 12 and for caching data.

  The oscillator (OSC) 14 supplies an operation signal having a predetermined frequency to the controller chip 11. The EEPROM 15 stores a control program and the like as fixed information. The EEPROM 15 is an example of a nonvolatile memory. The temperature sensor 16 detects the temperature in the semiconductor package 1 and notifies the controller chip 11 of the temperature.

  The controller chip 11 controls the operation of each part of the semiconductor package 1 using the temperature information received from the temperature sensor 16. For example, when the temperature detected by the temperature sensor 16 is equal to or higher than a predetermined temperature, the controller chip 11 reduces the operation speed of the semiconductor package 1 or stops the operation of the semiconductor package 1 at a predetermined time or a predetermined interval. Keep the temperature of 1 below the allowable value.

Next, the structure of the semiconductor package 1 will be described.
FIG. 4 is a cross-sectional view of the semiconductor package 1. The semiconductor package 1 includes a substrate 21 (package substrate), a controller chip 11, a semiconductor memory chip 12, bonding wires 22 and 23, molding materials 24 and 25, a mount film 26, and a plurality of solder balls 27.

  The substrate 21 is a multilayer wiring board, and includes a power supply layer 28 and a ground layer 29. The board | substrate 21 has the 1st surface 21a and the 2nd surface 21b located in the opposite side to this 1st surface 21a. The controller chip 11 is placed on the first surface 21 a of the substrate 21. The controller chip 11 is fixed to the substrate 21 by a mount film 26, for example. Further, the controller chip 11 is electrically connected to the substrate 21 by bonding wires 22.

  A first mold material 24 that seals the controller chip 11 and the bonding wires 22 is provided on the first surface 21 a of the substrate 21. A thick film mount film may be used instead of the first mold material 24. As described above, a mold type semiconductor package (first mold package) for sealing the controller chip 11 is formed.

  As shown in FIG. 4, a plurality of semiconductor memory chips 12 are stacked on the first mold material 24. The plurality of semiconductor memory chips 12 are fixed on the first mold material 24 by the mount film 26. The plurality of semiconductor memory chips 12 are electrically connected to the substrate 21 through bonding wires 23. The semiconductor memory chip 12 is electrically connected to the controller chip 11 via the substrate 21.

  A first mold material 24, a plurality of semiconductor memory chips 12, and a second mold material 25 that seals the bonding wires 23 are provided on the first surface 21 a of the substrate 21. As described above, in the present embodiment, the sealing portion 30 provided on the first surface 21 a of the substrate 21 is formed by the first molding material 24 and the second molding material 25. The sealing unit 30 integrally covers the controller chip 11, the plurality of semiconductor memory chips 12, the oscillator 14, the EEPROM 15, and the temperature sensor 16.

  FIG. 5 shows a first modification of the semiconductor package 1 according to this embodiment. In the first modification, the DRAM chip 13 is placed on the first surface 21 a of the substrate 21. The DRAM chip 13 is covered with a first mold material 24. The DRAM chip 13 may be located outside the first mold material 24 and covered with the second mold material 25.

  FIG. 6 shows a second modification of the semiconductor package 1 according to this embodiment. In the second modification, a plurality of semiconductor memory chips 12 are stacked on the first surface 21 a of the substrate 21. That is, the plurality of semiconductor memory chips 12 are placed beside the controller chip 11 and the DRAM chip 13.

  In the present modification, one molding material 25 integrally covers the controller chip 11, the DRAM chip 13, and the plurality of semiconductor memory chips 12. In this case, the sealing portion 30 provided on the first surface 21 a of the substrate 21 is formed by one molding material 25. Note that the sealing portion 30 of the semiconductor package 1 is not limited to being formed of a molding material, and may be formed of a ceramic material or other materials.

Next, the plurality of solder balls 27 provided on the substrate 21 will be described.
As shown in FIG. 4, a plurality of solder balls 27 for external connection are provided on the second surface 21 b of the substrate 21. In the present embodiment, the solder balls 27 are arranged at a pitch of 0.5 mm, for example.

  FIG. 7 shows the arrangement of the solder balls 27 on the second surface 21 b of the substrate 21. As shown in FIG. 7, the plurality of solder balls 27 are not completely disposed on the entire second surface 21 b of the substrate 21 but are partially disposed.

  FIG. 8 schematically shows the assignment of the solder balls 27. FIG. 8 shows a ball arrangement with reference to the posture placed on the circuit board 4 (that is, the posture when the semiconductor package 1 is viewed from above) for convenience of explanation. FIG. 9 shows the contents of the assignment shown in FIG. FIG. 10 shows the pads 32 of the circuit board 4 to which the solder balls 27 are connected.

  The plurality of solder balls 27 according to the present embodiment include PCIe signal balls PS1 to PS16, other signal balls S, power supply balls P, ground balls G, and thermal balls T (heat radiation balls). The PCIe signal balls PS1 to PS16 are examples of “differential signal balls”.

  In FIG. 8, the signal ball S is indicated by hatching, the power supply ball P is indicated as “Power”, the ground ball G is indicated as “GND”, and the thermal ball T is indicated as “T_pad”. Hereinafter, the arrangement of the solder balls 27 will be described in detail.

  As shown in FIG. 8, the plurality of solder balls 27 are divided and arranged in a first group G1, a second group G2, and a third group G3. The first group G1 is located in the center of the substrate 21. The first group G1 includes a plurality of thermal balls T provided in the central portion of the substrate 21, and a plurality of power supply balls P, ground balls G, and signal balls S arranged so as to surround the plurality of thermal balls T. Have.

  The thermal ball T (heat radiating ball) is electrically connected to the ground layer 29 or the power supply layer 28 (that is, the copper layer) of the substrate 21. For this reason, heat from the controller chip 11 or the like easily moves to the thermal ball T via the ground layer 29 or the power supply layer 28.

  The thermal ball T releases part of the heat of the semiconductor package 1 to the circuit board 4. For example, in this embodiment, the controller chip 11 is located at the center of the substrate 21 and overlaps the thermal ball T of the first group G1. The controller chip 11 generates a larger amount of heat during operation than other components (for example, the semiconductor memory chip 12 or the DRAM chip 13). The thermal ball T in the first group G1 releases a part of the heat transferred from the controller chip 11 to the substrate 21 to the circuit board 4.

The power supply ball P is electrically connected to the power supply layer 28 of the substrate 21 and supplies various power supplies to the semiconductor package 1. The ground ball G is electrically connected to the ground layer 29 of the substrate 21 and has a ground potential.

  As shown in FIG. 8, the second counties G2 are arranged in a frame shape surrounding the first counties G1. There is a gap between the second county G2 and the first county G1. The second group G2 includes PCIe signal balls PS1 to PS16, a signal ball S, a power supply ball P, and a ground ball G.

  Here, the PCIe signal balls PS1 to PS16 will be described in detail. As shown in FIGS. 8 and 9, the first PCIe signal ball PS1 corresponds to the first set of PCIe high-speed differential signals (input, positive). The second PCIe signal ball PS2 corresponds to the first set of PCIe high-speed differential signals (input, negative). The first and second PCIe signal balls PS1 and PS2 form a differential pair through which the first differential signal flows.

  The third PCIe signal ball PS3 corresponds to the first set of PCIe high-speed differential signals (output, negative). The fourth PCIe signal ball PS4 corresponds to the first set of PCIe high-speed differential signals (output, positive). The third and fourth PCIe signal balls PS3 and PS4 form a differential pair through which the second differential signal flows.

  These four PCIe signal balls PS1, PS2, PS3, and PS4 have a first solder ball set BS1 (that is, a first lane) corresponding to a first signal set composed of a pair of high-speed differential input signals and high-speed differential output signals. ).

  Similarly, the fifth PCIe signal ball PS5 corresponds to the second set of PCIe high-speed differential signals (output, negative). The sixth PCIe signal ball PS6 corresponds to the second set of PCIe high-speed differential signals (output, positive). The fifth and sixth PCIe signal balls PS5 and PS6 form a differential pair through which the third differential signal flows.

The seventh PCIe signal ball PS7 corresponds to the second set of PCIe high-speed differential signals (input, positive). The eighth PCIe signal ball PS8 corresponds to the second set of PCIe high-speed differential signals (input, negative). The seventh and eighth PCIe signal balls PS7 and PS8 form a differential pair through which the fourth differential signal flows.

  These four PCIe signal balls PS5, PS6, PS7, and PS8 are the second solder ball set BS2 (that is, the second lane) corresponding to the second signal set composed of a pair of high-speed differential input signals and high-speed differential output signals. ).

  The ninth PCIe signal ball PS9 corresponds to the third set of PCIe high-speed differential signals (input, positive). The tenth PCIe signal ball PS10 corresponds to the third set of PCIe high-speed differential signals (input, negative). The ninth and tenth PCIe signal balls PS9 and PS10 form a differential pair through which the fifth differential signal flows.

  The eleventh PCIe signal ball PS11 corresponds to the third set of PCIe high-speed differential signals (output, positive). The twelfth PCIe signal ball PS12 corresponds to the third set of PCIe high-speed differential signals (output, negative). The eleventh and twelfth PCIe signal balls PS11 and PS12 form a differential pair through which the sixth differential signal flows.

  The four PCIe signal balls PS9, PS10, PS11, and PS12 are provided with a third solder ball set BS3 (that is, a third lane) corresponding to a third signal set including a pair of high-speed differential input signals and high-speed differential output signals. ).

  The thirteenth PCIe signal ball PS13 corresponds to the fourth set of PCIe high-speed differential signals (input, positive). The fourteenth PCIe signal ball PS14 corresponds to the fourth set of PCIe high-speed differential signals (input, negative). The thirteenth and fourteenth PCIe signal balls PS13 and PS14 form a differential pair through which the seventh differential signal flows.

The fifteenth PCIe signal ball PS15 corresponds to the fourth set of PCIe high-speed differential signals (output, positive). The 16th PCIe signal ball PS16 corresponds to the fourth set of PCIe high-speed differential signals (output, negative). The fifteenth and sixteenth PCIe signal balls PS15 and PS16 form a differential pair through which the eighth differential signal flows.

  These four PCIe signal balls PS13, PS14, PS15, and PS16 are the fourth solder ball set BS4 (that is, the fourth lane) corresponding to the fourth signal set composed of a pair of high-speed differential input signals and high-speed differential output signals. ). In other words, the semiconductor package 1 according to the present embodiment has four sets of solder ball sets that constitute a PCIe lane.

  Here, the substrate 21 of the semiconductor package 1 has four sides. The four sides include a first side 41a, a second side 41b, a third side 41c, and a fourth side 41d. In a state where the semiconductor package 1 is attached to the substrate 21, the first side 41 a is closest to the host controller 5 in the substrate 21. The first side 41 a is an end (that is, an edge) facing the host controller 5. The first side 41 a extends substantially parallel to the host controller 5. The second side 41b is located on the opposite side to the first side 41a. The third side 41c and the fourth side 41d extend between the first side 41a and the second side 41b.

  In the present embodiment, the first to fourth solder ball sets BS 1, BS 2, BS 3, BS 4 are collectively arranged near the first side 41 a of the substrate 21. The first to fourth solder ball sets BS 1, BS 2, BS 3, BS 4 are located between the first side 41 a of the substrate 21 and the central portion of the substrate 21. The first to fourth solder ball sets BS1, BS2, BS3, BS4 are arranged substantially parallel to the first side 41a of the substrate 21.

  Accordingly, the first to fourth solder ball sets BS1, BS2, BS3, BS4 are located closer to the host controller 5 than the central portion of the substrate 21. That is, the first to fourth solder ball sets BS1, BS2, BS3, BS4 are located in a region between the center line C passing through the center of the substrate 21 and substantially parallel to the first side 41a and the first side 41a.

  Furthermore, in this embodiment, all the PCIe signal balls PS1 to PS16 are arranged in a line along the first line L1. The first line L <b> 1 is located between the first side 41 a of the substrate 21 and the central part of the substrate 21 and extends substantially parallel to the first side 41 a of the substrate 21.

  As shown in FIG. 10, the plurality of pads 32 of the circuit board 4 are provided corresponding to the arrangement of the plurality of solder balls 27. The plurality of pads 32 of the circuit board 4 include 16 PCIe pads PSP to which PCIe signal balls PS <b> 1 to PS <b> 16 are connected and a PCIe signal flows with the host controller 5.

  The circuit board 4 has 16 signal lines 6 (wiring patterns) that electrically connect the PCIe pad PSP and the host controller 5. The signal line 6 is provided, for example, on the surface layer of the circuit board 4. The signal line 6 extends linearly from the PCIe pad PSP toward the host controller 5. The signal line 6 extends in a direction substantially orthogonal to the first side 41 a of the substrate 21 of the semiconductor package 1. The 16 signal lines 6 have, for example, the same wiring length. That is, the equal length of the signal line 6 is ensured between the host controller 5 and the 16 PCIe signal balls PS1 to PS16.

  Next, the arrangement of the ground balls G will be described. Here, for convenience of explanation, “PCIe signal ball” is simply read as “solder ball”.

  Each solder ball set BS1, BS2, BS3, BS4 has two first solder balls corresponding to differential input signals and two second solder balls corresponding to differential output signals. That is, the PCIe signal balls PS1, PS2, PS7, PS8, PS9, PS10, PS13, and PS14 correspond to the first solder balls. On the other hand, the PCIe signal balls PS3, PS4, PS5, PS6, PS11, PS12, PS15, and PS16 correspond to the second solder balls.

  The ground ball G is provided around the PCIe signal balls PS1 to PS16, and electrically shields some of the PCIe signal balls PS1 to PS16. In the present embodiment, the ground ball G includes the first solder ball and the second solder ball between the solder ball sets BS1, BS2, BS3, BS4 and in each of the solder ball sets BS1, BS2, BS3, BS4. It is provided between.

  That is, the ground ball G is provided between the differential pair. Thereby, the plurality of differential input signals and differential output signals are electrically shielded so as to be independent from each other, and the influence of mutual signal interference and external noise is suppressed.

  Some ground balls G face the PCIe signal balls PS1 to PS16 from the side opposite to the signal line 6. As a result, the above-described eight differential signals are electrically shielded so as to be independent of other signals, and the influence of mutual signal interference and external noise is suppressed.

  As shown in FIG. 8, the third group G3 of the solder balls 27 includes a plurality of thermal balls T. The third county G3 is located further outside the second county G2. The third group G3 is located between the second group G2 and the outer peripheral edge (four sides 41a, 41b, 41c, 41d) of the substrate 21. That is, the plurality of thermal balls T are located closer to the outer peripheral edge of the substrate 21 than the first to fourth solder ball sets BS1 to BS4.

  The thermal ball T has a first to a fourth direction in a direction substantially orthogonal to the first side 41a of the substrate 21 in a region between the first side 41a of the substrate 21 and the first to fourth solder ball sets BS1 to BS4. The solder ball sets BS1 to BS4 are arranged so as to avoid the region. That is, the thermal ball T is arranged so as to avoid the region through which the signal line 6 passes. Thereby, the signal line 6 can extend linearly on the surface layer of the circuit board 4 without being disturbed by the thermal ball T.

  From another point of view, the thermal ball T is arranged in a region aligned in a direction substantially orthogonal to the first side 41a of the substrate 21 with respect to the ground ball G positioned between the PCIe signal balls PS1 to PS16. . The thermal balls T are located between the signal lines 6 and on both sides of the signal lines 6. The thermal ball T is electrically connected to, for example, the ground layer 29 of the substrate 21, and contributes to suppressing mutual interference of signals flowing through the signal line 6 and external noise as an electrical shield.

  As shown in FIGS. 7 and 8, the substrate 21 includes a first region 43a and a second region 43b. The first area 43a is an area that overlaps the controller chip 11 in plan view (that is, a projection area of the controller chip 11). On the other hand, the second region 43b is a region located outside the first region 43a.

  Here, the arrangement density of the thermal balls T in the second region 43b is higher than the arrangement density of the thermal balls T in the first region 43a. The “arrangement density” is obtained by dividing the number of thermal balls T arranged in each region by the area of each region.

  As shown in FIG. 10, the pad 32 of the circuit board 4 includes a thermal pad TP to which the thermal ball T is connected. The thermal pad TP is connected to, for example, a ground layer or a power supply layer (that is, a copper layer) of the circuit board 4. The thermal ball T and the thermal pad TP are not limited to those connected to the ground layer or the power supply layer of the substrate 21 or the circuit board 4. A certain heat radiation effect can be obtained also by the thermal ball T or the thermal pad TP not connected to the copper layer.

Next, the arrangement of the power supply balls P and the ground balls G will be described.
As shown in FIG. 8, the plurality of power supply balls P and the plurality of ground balls G are arranged substantially symmetrically with respect to the center of the substrate 21. The “substantially point object” includes not only the case of complete point symmetry but also the case where a small number (for example, one) of the ground balls G are not arranged point-symmetrically.

  From another point of view, any one of the plurality of power supply balls P and the plurality of ground balls G may be arranged symmetrically with respect to the center of the substrate 21. In the present embodiment, the plurality of power supply balls P are arranged point-symmetrically with respect to the center of the substrate 21.

  As shown in FIG. 10, the pad 32 of the circuit board 4 includes a power pad PP to which the power ball P is connected and a ground pad GP to which the ground ball G is connected.

  The plurality of power supply balls P and the plurality of ground balls G are arranged substantially symmetrically with respect to a point, so that even when the semiconductor package 1 is erroneously rotated 180 degrees with respect to the normal direction and attached to the circuit board 4, the power supply balls Correspondence relationships between P and power supply pads PP, and ground balls G and ground pads GP are maintained.

  According to such a configuration, it is possible to provide the semiconductor package 1 with improved high-speed operability. That is, for example, when there is only one solder ball set corresponding to a high-speed signal, there is a limit to high-speed operation.

  Therefore, the semiconductor package 1 according to this embodiment includes a substrate 21, a sealing unit 30, a controller chip 11, a semiconductor chip (for example, a semiconductor memory chip 12), and a plurality of differential signal balls (for example, a PCIe signal ball PS1). To PS16). At least some of the plurality of differential signal balls are arranged substantially parallel to the first side 41 a of the substrate 21.

  According to such a configuration, by increasing the number of solder ball sets corresponding to high-speed signals, it is possible to double the amount of data that can be transmitted and received, thereby improving high-speed operability.

  Further, when the plurality of differential signal balls are arranged substantially parallel to the first side 41a of the substrate 21, the semiconductor package 1 is arranged with the first side 41a of the substrate 21 facing the host controller 5, It is easy to ensure the equal length of the signal line 6 between the plurality of differential signal balls and the host controller 5. For this reason, the signal quality which the semiconductor package 1 transmits / receives can be improved.

  In another aspect, the plurality of differential signal balls are arranged such that the differential pairs are arranged in a direction substantially orthogonal to the first side 41 a of the substrate 21, and the plurality of differential signal balls are substantially parallel to the first side 41 a of the substrate 21. It is also possible to arrange them in two rows. However, in this case, when the solder balls 27 are arranged at a pitch of 0.5 mm as in this embodiment, the differential signal balls and the signal lines 6 are arranged densely, and some signal lines 6 are provided with sharp bent portions. Need arises. This may affect signal quality and reliability.

  On the other hand, in the present embodiment, a plurality of differential signal balls are arranged in a line substantially parallel to the first side 41 a of the substrate 21. According to such a configuration, the plurality of differential signal balls and the signal line 6 are unlikely to become dense, and it is possible to avoid providing a sharp bent portion in the signal line 6. For this reason, signal quality and reliability can be further improved.

  In the present embodiment, the plurality of ground balls G are provided around the plurality of differential signal balls to electrically shield some of the differential signal balls. Thereby, the mutual interference of the signals of a plurality of differential signal balls and the influence of external noise can be suppressed, and the signal quality can be improved.

  In the present embodiment, the plurality of solder balls 27 include a plurality of thermal balls T electrically connected to the ground layer 29 or the power supply layer 28 of the substrate 21. According to such a configuration, the heat of the semiconductor package 1 can be efficiently released to the circuit board 4. Thereby, the temperature rise of the semiconductor package 1 can be suppressed and the high-speed operation of the semiconductor package 1 can be promoted.

  In the present embodiment, the plurality of thermal balls T are located closer to the outer peripheral edge of the substrate 21 than the plurality of solder ball sets BS1 to BS4. According to such a configuration, the thermal ball T can be disposed by effectively utilizing the peripheral portion of the substrate 21 having a sparse wiring layout. Thereby, the freedom degree of the layout design of the semiconductor package 1 can be improved.

  In the present embodiment, a plurality of thermal balls T are arranged in the direction between the first side 41a of the substrate 21 and the solder ball sets BS1 to BS4 in a direction substantially orthogonal to the first side 41a of the substrate 21. Arranged so as to avoid the area aligned with BS to BS4. Thereby, the signal line 6 can be drawn linearly from the pad PSP of the circuit board 4. That is, it is not necessary to bypass the signal line 6 in order to avoid the thermal ball T. For this reason, signal quality can be further improved.

  Note that it is desirable that the number of the thermal balls T be as small as necessary and sufficient, instead of being fully provided on the entire surface of the substrate 21 from the viewpoint of reducing the cost of the semiconductor package 1. When an upper limit is set for the number of thermal balls T in this way, it is preferable from the viewpoint of heat dissipation to dispose a relatively large number of thermal balls T in the second region 43 b of the substrate 21.

  Here, a plurality of thermal balls T may be concentrated on the first region 43a. At first glance, it seems that better heat dissipation can be obtained if a relatively large number of thermal balls T are arranged in the first region 43a located immediately below the controller chip 11 which is a heat generating component.

  However, according to the test results by the present inventors, it was found that the temperature increase of the semiconductor package 1 can be suppressed to a lower level when a relatively large number of thermal balls T are arranged in the second region 43b. This is presumed to be because if the thermal balls T are separately arranged in the second region 43b in addition to the first region 43a, the overall heat dissipation of the semiconductor package 1 is enhanced. Therefore, in the present embodiment, a relatively large number of thermal balls T are arranged in the second region 43b to further enhance the heat dissipation of the semiconductor package 1.

  In the present embodiment, the plurality of solder balls 27 includes a plurality of power supply balls P electrically connected to the power supply layer 28 of the substrate 21 and a plurality of ground balls G electrically connected to the ground layer 29 of the substrate 21. Including. The plurality of power supply balls P and the plurality of ground balls G are arranged substantially symmetrically with respect to the center of the substrate 21.

  Here, when the plurality of power supply balls P and the plurality of ground balls G are not arranged substantially point-symmetrically, when the semiconductor package 1 is attached to the substrate 21 in a state where the power supply balls P and the plurality of ground balls G are rotated by 180 degrees with respect to the normal direction, There is a possibility that the power supply pad PP of the circuit board 4 and the ground ball G of the semiconductor package 1 are connected and short-circuited.

  On the other hand, when the plurality of power supply balls P and the plurality of ground balls G are arranged substantially point-symmetrically with respect to the center of the substrate 21 as in the present embodiment, they are erroneously rotated 180 degrees with respect to the normal direction. Even when the semiconductor package 1 is attached to the substrate 21 in this state, the correspondence relationship between the plurality of power supply balls P and the plurality of power supply pads PP, and the plurality of ground balls G and the plurality of ground pads GP is maintained. For this reason, there is no possibility of a short circuit, and damage to the entire system and the semiconductor package 1 can be prevented.

(Second Embodiment)
Next, a semiconductor package 1 according to the second embodiment will be described with reference to FIGS. In addition, the structure which has the same or similar function as the structure of 1st Embodiment attaches the same code | symbol, and abbreviate | omits the description. The configuration other than that described below is the same as that of the first embodiment.

  FIG. 11 shows the assignment of the solder balls 27 according to the present embodiment. FIG. 12 is an enlarged view of a portion surrounded by F12 in FIG. As shown in FIGS. 11 and 12, in the present embodiment, the plurality of PCIe signal balls PS1 to PS16 are arranged along the first line L1 and the pair of second lines L2a and L2b. The first line L1 is located between the first side 41a of the substrate 21 and the central portion of the substrate 21 and is substantially parallel to the first side 41a of the substrate 21. The pair of second lines L2a, L2b extends from both ends of the first line L1 in a direction away from the first side 41a of the substrate 21.

  That is, some of the PCIe signal balls PS1, PS2, PS15, and PS16 located on the outermost side among the plurality of PCIe signal balls PS1 to PS16 intersect with the first line L1 (for example, substantially orthogonal) second line. They are arranged in different directions along L2a and L2b. The pair of second lines L2a and L2b is not limited to this name, and may be referred to as a second line L2a and a third line L2b, for example.

  In the present embodiment, the PCIe signal balls PS5 to PS12 of the second and third ball sets BS2 and BS3 are arranged in a line along the first line L1. On the other hand, the PCIe signal balls PS1 to PS4 and PS12 to PS16 of the first and fourth ball sets BS1 and BS4 are located on both sides of the second and third ball sets BS2 and BS3, respectively, and at least a part of each is paired. Are arranged along the second lines L2a and L2b.

Also in the present embodiment, all the PCIe signal balls PS1 to PS16 of the first to fourth solder ball sets BS1, BS2, BS3, BS4 have a center line C passing through the center of the substrate 21 substantially parallel to the first side 41a. It is located in a region between the first side 41a.

  Specifically, the second group G2 arranged in a frame shape includes a first portion 61 (first side), a second portion 62 (second side), a third portion 63 (third side), and a fourth portion. 64 (fourth side). The first portions 61 are arranged along the first line L1. The second portion 62 is arranged in a direction substantially orthogonal to the first portion 61 from the first end of the first portion 61.

  The third portion 63 is arranged in a direction substantially orthogonal to the first portion 61 from the second end portion of the first portion 61 located on the side opposite to the first end portion. The second portion 62 and the third portion 63 are separately located on both sides of the first group G1. The fourth portion 64 is arranged substantially in parallel with the first portion 61. The fourth portion 64 extends between the second portion 62 and the third portion 63. The first portion 61 and the fourth portion 64 are separately located on both sides of the first group G1.

  In the present embodiment, the PCIe signal balls PS5 to PS12 of the second and third ball sets BS2 and BS3 are positioned in the first portion 61 and arranged in a line. Further, the two PCIe signal balls PS3 and PS4 of the first ball set BS1 are arranged in the first portion 61. The two PCIe signal balls PS12 and PS13 of the third ball set BS4 are arranged in the first portion 61.

  On the other hand, the two PCIe signal balls PS <b> 1 and PS <b> 2 of the first ball set BS <b> 1 are arranged at the end portion of the second portion 62 connected to the first portion 61. Similarly, the two PCIe signal balls PS15 and PS16 of the fourth ball set BS4 are arranged at the end of the third portion 63 connected to the first portion 61.

  Accordingly, the plurality of PCIe signal balls PS1 to PS16 includes a plurality of first differential pairs disposed along the first line L1 and a second differential disposed along the pair of second lines L2a and L2b. Including pairs. That is, the PCIe signal balls (PS3, PS4), (PS5, PS6), (PS7, PS8), (PS9, PS10), (PS11, PS12), (PS13, PS14) are respectively the first differential pair. It is an example. On the other hand, the PCIe signal balls (PS1, PS2) and (PS15, PS16) are examples of the second differential pair, respectively.

  Here, each second differential pair includes a first ball A and a second ball B. The second ball B is located farther from the first side 41 a of the substrate 21 than the first ball A. In the present embodiment, the PCIe signal balls PS2 and PS15 are examples of the first ball A. The PCIe signal balls PS1 and PS16 are examples of the second ball B.

  FIG. 13 shows the arrangement of the pads 32 of the circuit board 4 according to this embodiment. As shown in FIG. 13, the signal line 6 includes four signal lines 6 a extending between the PCIe signal balls (PS 1, PS 2) and (PS 15, PS 16) constituting the second differential pair and the host controller 5. , 6b. These four signal lines 6a and 6b extend substantially in parallel with the first side 41a of the substrate 21 from the PCIe pad PSP, have a curved portion, and face the host controller 5 with the first side 41a of the substrate. It extends in a direction substantially orthogonal to.

  Specifically, the signal line 6 includes a first signal line 6 a extending between the first ball A and the host controller 5, and a second signal line 6 b extending between the second ball B and the host controller 5. Including. The first signal line 6 a has a first curved portion 71. For example, the second signal line 6 b has a second curve portion 72 located outside the first curve portion 71 with a radius of curvature larger than that of the first curve portion 71. The 1st and 2nd curve parts 71 and 72 are formed in the circular arc shape of 1/4 circle, for example.

  In the present embodiment, all the solder balls 27 including the plurality of ground balls G and the plurality of thermal balls T are arranged in areas avoiding the first and second signal lines 6 a and 6 b having the curved portions 71 and 72. ing.

  FIG. 14 schematically shows the wiring length of the signal line 6 between the first and second balls A and B constituting the second differential pair and the host controller 5. For convenience of explanation, the first ball A and the second ball B have the same influence on the wiring length and are shown with a close distance.

  As shown in FIG. 14, in this embodiment, when the distance between the first ball A and the second ball B is 2, the difference in wiring length between the first signal line 6a and the second signal line 6b is as follows. , Π / 2 (about 1.5705).

  Next, a first modification of the signal line 6 will be described with reference to FIG. In addition, the structure which has the same or similar function as the said embodiment attaches | subjects the same code | symbol, and abbreviate | omits the description.

  The signal line 6 includes four signal lines 6 a and 6 b extending between the PCIe signal balls (PS 1, PS 2) and (PS 15, PS 16) constituting the second differential pair and the host controller 5. These four signal lines 6a and 6b extend from the PCIe pad PSP substantially parallel to the first side 41a of the substrate 21 and have a portion extending obliquely with respect to the first side 41a of the substrate 21. 5 extends in a direction substantially orthogonal to the first side 41a of the substrate.

  Specifically, the first signal line 6 a includes a first oblique line portion 73 extending obliquely with respect to the first side 41 a of the substrate 21. The second signal line 6 b includes, for example, a second shaded portion 74 that is substantially parallel to the first shaded portion 73 and located outside the first shaded portion 73. The first and second hatched portions 73 and 74 are inclined at an angle of 45 ° with respect to the first side 41a of the substrate 21, for example.

  In the present embodiment, all the solder balls 27 including the plurality of ground balls G and the plurality of thermal balls T are arranged in a region avoiding the first and second signal lines 6a and 6b having the hatched portions 73 and 74. ing.

  FIG. 15 schematically shows the wiring length of the signal line 6 between the first and second balls A and B constituting the second differential pair and the host controller 5 in this modification. For convenience of explanation, the first ball A and the second ball B have the same influence on the wiring length and are shown with a close distance.

  As shown in FIG. 15, in this embodiment, when the distance between the first ball A and the second ball B is 2, the difference in wiring length between the first signal line 6a and the second signal line 6b is as follows. 2√2 (about 2.828).

  Next, a second modification of the signal line 6 will be described with reference to FIG. In addition, the structure which has the same or similar function as the said embodiment attaches | subjects the same code | symbol, and abbreviate | omits the description.

  The signal line 6 includes four signal lines 6 a and 6 b extending between the PCIe signal balls (PS 1, PS 2) and (PS 15, PS 16) constituting the second differential pair and the host controller 5. These four signal lines 6 a and 6 b extend from the PCIe pad PSP substantially in parallel with the first side 41 a of the substrate 21, are bent at substantially right angles, and are directed to the host controller 5 from the first side 41 a of the substrate 21. It extends in a substantially orthogonal direction. All the solder balls 27 including the plurality of ground balls G and the plurality of thermal balls T are arranged in a region avoiding the first and second signal lines 6a and 6b.

  FIG. 16 schematically shows the wiring length of the signal line 6 between the first and second balls A and B constituting the second differential pair and the host controller 5 in this modification. For convenience of explanation, the first ball A and the second ball B have the same influence on the wiring length and are shown with a close distance.

  As shown in FIG. 16, in this embodiment, when the distance between the first ball A and the second ball B is 2, the difference in wiring length between the first signal line 6a and the second signal line 6b is as follows. 4.

  According to the configuration of the second embodiment described above and its modification, the high-speed operability can be improved and the connection reliability of the differential signal ball can be further improved as in the first embodiment. The semiconductor package 1 that can be provided can be provided.

  Generally, the peripheral end portion of the substrate 21 is a region where the connection reliability of the solder ball 27 may be lowered due to, for example, thermal stress when the semiconductor package 1 is mounted. Therefore, if the differential signal ball is disposed near the peripheral end of the substrate 21, the connection reliability of the differential signal ball may be lowered.

  Therefore, in the present embodiment, a plurality of differential signal balls (for example, PCIe signal balls PS1 to PS16) include a first line L1 substantially parallel to the first side 41a of the substrate 21 and the substrate from both ends of the first line L1. 21 are arranged along a pair of second lines L2a and L2b extending in a direction away from the first side 41a.

  According to such a configuration, for example, all the differential signal balls can be arranged away from the peripheral end portion of the substrate 21 as compared with the structure of the first embodiment. For this reason, the connection reliability of the differential signal ball can be improved.

  In the present embodiment, the plurality of differential signal balls includes a plurality of first differential pairs disposed along the first line L1 and a second differential disposed along the pair of second lines L2a and L2b. Including pairs. According to such a configuration, it is easy to ensure the equal length of the signal lines 6a and 6b of the second differential pair. For this reason, the signal quality of the signal which the differential signal ball | bowl arrange | positioned along 2nd line L2a, L3b transmits / receives can be improved.

  In the present embodiment, the first and second signal lines 6 a and 6 b extend from the PCIe pad PSP substantially parallel to the first side 41 a of the substrate 21 and have curved portions 71 and 72 toward the host controller 5. It extends. According to such a configuration, for example, the difference in wiring length between the first and second signal lines 6a and 6b can be reduced as compared with the structure of the second modified example of the present embodiment. Therefore, it is possible to improve the signal quality of signals transmitted and received by the differential pair arranged along the second lines L2a and L2b.

  Similarly, the first and second signal lines 6a and 6b according to the first modification of the present embodiment extend substantially parallel to the first side 41a of the substrate 21 from the PCIe pad PSP, and include the hatched portions 73 and 74. And extending toward the host controller 5. According to such a configuration, for example, the difference in wiring length between the first and second signal lines 6a and 6b can be reduced as compared with the structure of the second modified example. Therefore, it is possible to improve the signal quality of signals transmitted and received by the differential pair arranged along the second lines L2a and L2b.

(Third embodiment)
Next, the semiconductor package 1 according to the third embodiment will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected to the structure which has the same or similar function as the structure of 1st and 2nd embodiment, and the description is abbreviate | omitted. The configuration other than that described below is the same as that of the second embodiment.

  FIG. 17 shows the assignment of the solder balls 27 according to this embodiment. FIG. 18 is an enlarged view of a portion surrounded by F18 in FIG. FIG. 19 shows the arrangement of the pads 32 according to the present embodiment.

  In the present embodiment, the PCIe signal balls (PS1, PS2) and (PS15, PS16) constituting the second differential pair are the same as the first ball A and the first ball A, as in the second embodiment. And the second ball B positioned far from the first side 41 a of the substrate 21.

  In the present embodiment, the first ball A is disposed so as to be shifted to the inner side (center side) of the substrate 21 with respect to the second ball B in a direction substantially parallel to the first side 41a of the substrate 21, for example. Note that “disposed on the inner side (center side) of the substrate with respect to the second ball” means that the first ball A is in the first portion 61 of the second group G2 with respect to the second ball B. This means that they are arranged so as to be shifted toward the center of the. In other words, it means that the first ball A is displaced with respect to the center of the first side 41a of the substrate 21 with respect to the second ball B.

  In other words, when the solder balls 27 are arranged in a two-row frame shape (double frame shape) in the second group G2, the second ball B is positioned in the outer frame, One ball A is located in the inner frame.

  As shown in FIG. 19, the first signal line 6 a has a first straight portion 81 between the first ball A and the first curved portion 71. The first straight portion 81 extends substantially parallel to the first side 41 a of the substrate 21. The second signal line 6 b includes a second straight part 82 between the second ball B and the second curved part 72. The second straight part 82 extends substantially parallel to the first side 41 a of the substrate 21. The first straight part 81 is longer than the second straight part 82.

  As shown in FIG. 19, the distance between the first ball A and the second ball B is set to 2, and the first ball A is displaced from the second ball B by the distance 2 inside the substrate 21. In this case, the difference in wiring length between the first signal line 6a and the second signal line 6b is −2 + π / 2 (about −0.4295).

  According to such a configuration, it is possible to provide the semiconductor package 1 that can improve the high-speed operability, as in the first embodiment. Further, according to the above configuration, as in the second embodiment, since all the differential signal balls can be arranged away from the peripheral end portion of the substrate 21, the connection reliability of the differential signal balls is improved. be able to.

  In the present embodiment, the first ball A is disposed so as to be shifted to the inner side (center side) of the substrate 21 with respect to the second ball B. According to such a configuration, for example, it is easy to ensure the equal length of the first and second signal lines 6a and 6b as compared with the structure of the second embodiment. Thereby, the signal quality of the signal which the differential pair arrange | positioned along 2nd line L2a and L2b transmits / receives can be improved.

(Fourth embodiment)
Next, a semiconductor package 1 according to the fourth embodiment will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected to the structure which has the same or similar function as the structure of 1st thru | or 3rd embodiment, and the description is abbreviate | omitted. The configuration other than that described below is the same as that of the third embodiment.

  FIG. 20 shows the assignment of the solder balls 27 according to this embodiment. FIG. 21 is an enlarged view of a portion surrounded by F21 in FIG. FIG. 21 shows the arrangement of the pads 32 according to the present embodiment.

  In the present embodiment, the plurality of PCIe signal balls PS1 to PS16 are disposed along the plurality of first differential pairs arranged along the first line L1 and the pair of second lines L2a and L2b, respectively. And a plurality of second differential pairs. That is, in this embodiment, a plurality of second differential pairs are arranged along one second line L2a. A plurality of second differential pairs are arranged along the other second line L2b.

  Specifically, two differential pairs (PS1, PS2) and (PS3, PS4) of the first solder ball set BS1 are arranged along one second line L2a. Two differential pairs (PS13, PS14) and (PS15, PS16) of the fourth solder ball set BS4 are arranged along the other second line L2b.

  Here, the differential pair of signal lines 6 arranged along one second line L2a will be described. Note that the differential pair disposed along the other second line L2b also has substantially the same configuration.

  The signal line 6 includes a first signal line 6a and a second signal line 6b corresponding to one differential pair (PS3, PS4), and a third signal line 6c corresponding to the other differential pair (PS1, PS2). And a fourth signal line 6d.

  The first signal line 6 a extends between the first ball A of one differential pair (PS 3, PS 4) and the host controller 5. The second signal line 6b extends between the second ball B of the same differential pair (PS3, PS4) and the host controller 5.

  The third signal line 6c extends between the first ball A of the other differential pair (PS1, PS2) and the host controller 5. The fourth signal line 6d extends between the second ball B of the same differential pair (PS1, PS2) and the host controller 5.

  The first signal line 6 a includes a first curve portion 71. For example, the second signal line 6 b has a second curve portion 72 located outside the first curve portion 71 with a radius of curvature larger than that of the first curve portion 71. The third signal line 6 c has a third curve portion 91 located outside the second curve portion 72. In addition, although the 3rd curve part 91 may have a larger curvature radius than the 2nd curve part 72, it may not be so. For example, the fourth signal line 6 d has a fourth curve portion 92 having a larger radius of curvature than the third curve portion 91 and positioned outside the third curve portion 91.

  According to such a configuration, it is possible to provide the semiconductor package 1 that can improve the high-speed operability, as in the first embodiment.

  In the present embodiment, the plurality of differential signal balls include a plurality of first differential pairs arranged along the first line L1, and a plurality of second differentials arranged along the second lines L2a and L2b. Including pairs. According to such a configuration, for example, all the differential signal balls can be arranged further away from the peripheral end portion of the substrate 21 as compared with the structure of the second embodiment. For this reason, the connection reliability of the differential signal ball can be further improved.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

  For example, the signal line shapes as in the first and second modifications of the second embodiment may be adopted as the third and fourth signal lines 6c and 6d of the semiconductor package 1 according to the third embodiment. Good.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor package, 4 ... Circuit board, 5 ... Host controller, 6 ... Signal line, 11 ... Controller chip, 12 ... Semiconductor memory chip, 21 ... Substrate (package substrate), 21a ... 1st surface, 21b ... 2nd surface 27 ... solder ball, 28 ... power supply layer, 29 ... ground layer, 30 ... sealed portion, BS to BS4 ... solder ball set, PSP1-16 ... PCIe signal ball, P ... power supply ball, G ... ground ball, T ... Thermal ball (heat dissipation ball), A ... first ball, B ... second ball, L1 ... first line, L2a, L2b ... second line, 71,72 ... curve part, 73,74 ... hatched part

Claims (10)

A substrate,
A semiconductor memory disposed on the first surface side of the substrate;
A controller that is disposed on the first surface side of the substrate and controls the semiconductor memory;
A sealing portion that integrally covers the semiconductor memory and the controller on the first surface side of the substrate;
A plurality of heat dissipating balls disposed on a second surface facing the first surface of the substrate;
Comprising
The substrate includes a first region which is a region on the second surface facing the controller on the first surface, and a second region located outside the first region,
The arrangement density of the heat dissipation balls in the second region is higher than the arrangement density of the heat dissipation balls in the first region.
Storage device.   The storage device according to claim 1, wherein the number of the heat radiating balls arranged in the second area is larger than the number of the heat radiating balls arranged in the first area. A plurality of differential signal balls;
The plurality of differential signal balls are disposed on the second surface,
At least some of the plurality of differential signal balls are arranged substantially parallel to one side of the substrate.
The storage apparatus according to claim 1.   The plurality of differential signal balls are along a first line substantially parallel to the one side of the substrate and a pair of second lines extending from both ends of the first line in a direction away from the one side of the substrate. The storage device according to claim 3, arranged in a row.   The plurality of differential signal balls includes a plurality of first differential pairs arranged along the first line and a second differential pair arranged along the second line. Storage device.   The second differential pair includes a first ball and a second ball located farther from the one side of the substrate than the first ball, and the first ball is in relation to the second ball. The storage apparatus according to claim 5, wherein the storage apparatus is disposed so as to be displaced inside the substrate. The plurality of differential signal balls include a plurality of first differential pairs arranged along the first line and a plurality of second differential pairs arranged along one second line. ,
Each of the plurality of second differential pairs includes a first ball and a second ball located farther from the one side of the substrate than the first ball, and the plurality of second differential pairs 5. The storage device according to claim 4, wherein each of the first balls is arranged so as to be displaced inward of the substrate with respect to the second balls. A ground ball provided on the second surface of the substrate;
The plurality of differential signal balls include a plurality of differential pairs;
The storage device according to claim 3, wherein the ground ball is located between the plurality of differential pairs.   The storage apparatus according to claim 3, wherein the plurality of heat dissipation balls and the plurality of signal lines that electrically connect the plurality of differential signal balls and an external host controller are arranged so as not to overlap each other. A storage device;
A host controller connected to the storage device by a plurality of signal lines;
Comprising
The storage device
A substrate,
A semiconductor memory disposed on the first surface side of the substrate;
A controller that is disposed on the first surface side of the substrate and controls the semiconductor memory;
A sealing portion that integrally covers the semiconductor memory and the controller on the first surface side of the substrate;
A plurality of heat dissipating balls disposed on a second surface facing the first surface of the substrate;
Comprising
The substrate includes a first region which is a region on the second surface facing the controller on the first surface, and a second region located outside the first region,
The arrangement density of the heat dissipation balls in the second region is higher than the arrangement density of the heat dissipation balls in the first region.
Electronics.

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