JP6463221B2 - ADC self-test circuit - Google Patents

Description

  The present invention relates to an ADC (Analog-to-Digital Converter) test method.

  In recent years, ADCs that convert analog signals such as sensor detection signals into digital signals have become indispensable as system construction components as various control objects are electronically controlled. As a method for determining whether or not the ADC is operating correctly during system operation, there is a method using a self-test function provided in the ADC. IC chips that require high reliability such as those for automobiles require a self-test function for diagnosing whether the ADC is operating normally during system operation.

  The following Patent Document 1 describes a technique related to a diagnostic circuit for diagnosing an ADC. In this document, a three-state (high level / low level / intermediate level) diagnostic signal is input to an analog signal input terminal of an ADC, and this is converted by an ADC based on a digital output signal. It is determined whether or not there is any abnormality.

Japanese Patent No. 4925171

The successive approximation ADC internally has a DAC (Digital-to-Analog Converter) (hereinafter referred to as a local DAC), and converts the analog input signal into a digital output by comparing the analog input signal with the DAC output signal. To do. It is necessary to provide the number of local DAC output levels according to the resolution of the ADC. When the resolution of the ADC is n bits, the output level of the local DAC needs 2 ⁿ −1 stages. For example, in the case of a 10-bit ADC, the output level of the local DAC needs 1023 stages.

  In the conventional ADC self-test, the output level of the local DAC input to the ADC does not necessarily completely cover the resolution of the ADC. For example, when performing a 10-bit ADC self-test, the test should be performed for all 1023 output levels, but some output levels are sampled from the viewpoint of test load and test time. Usually, only the sampled output level is tested.

  For example, in Patent Document 1, a diagnosis signal in three states (high level / low level / intermediate level) is input to an analog signal input terminal of the ADC, and the ADC is tested based on the digital conversion result. Therefore, in the conventional ADC self-test, it is not necessarily confirmed that there is no abnormality for all output levels.

  The present invention has been made in view of the above problems, and provides an ADC self-test circuit capable of confirming that no abnormality has occurred in all output levels of a local DAC with a simple configuration. For the purpose.

  The ADC self-test circuit according to the present invention inputs a test signal exceeding the dynamic range of the ADC and a reference signal within the dynamic range to the comparator and confirms that the Hi level is output, and the dynamic range. A test signal of less than that and a reference signal within the dynamic range range are input to the comparator to confirm that a low level is output.

  According to the ADC self-test circuit of the present invention, it is possible to diagnose all the output levels of the local DAC with a simple configuration. By performing a self-test before the ADC starts normal operation, ADC malfunction can be prevented in advance.

  Problems, configurations, and effects other than those described above will become apparent from the following description of embodiments.

1 is a circuit block diagram of an ADC 100 according to Embodiment 1. FIG. FIG. 2 is a circuit block diagram showing a configuration example in which a control circuit 14 in FIG. FIG. 3 is a signal level diagram illustrating a self-test operation of the ADC 100 described in FIG. 1 or FIG. 3 is a circuit block diagram illustrating a configuration of an ADC 100 according to Embodiment 2. FIG. FIG. 5 is a circuit block diagram illustrating a configuration of an ADC 100 according to a third embodiment. It is a circuit block diagram of ADC100 provided with the conventional self test circuit.

<Regarding the conventional ADC self-test>
Hereinafter, in order to facilitate understanding of the present invention, the configuration of a conventional ADC self-test circuit will be described first. Thereafter, the configuration of the ADC self-test circuit according to the embodiment of the present invention will be described.

  FIG. 6 is a circuit block diagram of an ADC 100 having a conventional self-test circuit. The ADC 100 includes an analog input terminal 1, a digital output terminal 2, a self test result output terminal 3, a self test signal source 10, a local DAC 11, an input selector switch 12, a comparator 13, a control circuit 14, and a determination circuit 15.

  In normal operation, the analog input terminal 1 receives an analog input signal. The local DAC 11 generates a reference signal that serves as a reference when the comparator 13 performs comparison. The comparator 13 compares the analog input signal with the reference signal. The control circuit 14 controls the signal level of the reference signal generated by the local DAC and converts the output of the comparator 13 into a digital output signal according to the signal level.

  When performing the self-test, the input selector switch 12 connects the self-test signal source 10 and the comparator 13 in accordance with instructions from the self-test control circuit 16. The self test signal source 10 inputs a test signal to the comparator 13 instead of the analog input signal in accordance with an instruction from the control circuit 14. The comparator 13 operates in the same way as during normal operation. The control circuit 14 converts the output of the comparator 13 into a digital output signal. The determination circuit 15 determines whether or not the signal level of the digital output signal corresponds to the reference signal level of the local DAC 11. If the two do not correspond, the ADC 100 outputs a test result indicating that the ADC 100 is operating abnormally.

  In the configuration shown in FIG. 6, the determination circuit 15 performs a self test based on the signal level of the self test signal source 10. That is, when the resolution of the ADC 100 is, for example, 10 bits, the local DAC 11 needs to generate a reference signal level of 1023 patterns in order to test all signal levels. As the resolution of the ADC 100 increases, it may not be practical to exhaustively diagnose all these signal levels.

<Embodiment 1>
FIG. 1 is a circuit block diagram of an ADC 100 according to Embodiment 1 of the present invention. The ADC 100 shown in FIG. 1 has a circuit configuration similar to that described with reference to FIG. 6 except that the determination circuit 15 determines the result of the self test based on the output of the comparator 13. The operation of the determination circuit 15 will be described below.

  When the self test of the ADC 100 is performed, the self test control circuit 16 operates the input selector switch 12 to switch the input of the comparator 13 from the analog input terminal 1 to the self test signal source 10.

  The self test control circuit 16 sets the signal level of the test signal output from the self test signal source 10 to a value exceeding the maximum value of the input dynamic range of the ADC 100. The control circuit 14 sequentially selects all levels from the signal level corresponding to the minimum value of the dynamic range of the ADC 100 to the signal level corresponding to the maximum value as the signal level of the reference signal output from the local DAC 11. The determination circuit 15 confirms that the logic output level of the comparator 13 is Hi regardless of the reference signal level. The determination circuit 15 outputs a test result indicating that the ADC 100 is operating abnormally when the output of the comparator 13 is not Hi at any reference signal level, and the ADC 100 is normal when it is Hi at all reference signal levels. Outputs the test result indicating that it is operating.

  Next, the self test control circuit 16 sets the signal level of the test signal output from the self test signal source 10 to a value less than the minimum value of the input dynamic range of the ADC 100. The control circuit 14 sequentially selects all levels from the signal level corresponding to the maximum value of the dynamic range of the ADC 100 to the signal level corresponding to the minimum value as the signal level of the reference signal output from the local DAC 11. The determination circuit 15 confirms that the logic output level of the comparator 13 is Low regardless of the reference signal level. The determination circuit 15 outputs a test result indicating that the ADC 100 is operating abnormally when the output of the comparator 13 is not Low at any reference signal level, and is normal when the ADC 100 is Low at all reference signal levels. Outputs the test result indicating that it is operating.

  FIG. 2 is a circuit block diagram showing a configuration example in which the control circuit 14 in FIG. The up / down counter 17 counts up when the comparator 13 outputs Hi, and counts down when it outputs Low.

  The local DAC 11 outputs a signal level corresponding to the minimum value of the dynamic range of the ADC 100 when the up / down counter 17 outputs the minimum count value, and becomes the maximum value of the dynamic range of the ADC 100 when the up / down counter 17 outputs the maximum count value. Outputs the corresponding signal level. In the count value between the maximum value and the minimum value, the local DAC 11 increases or decreases the signal level by one step as the count value increases or decreases one by one.

  Since the self-test operation of the ADC 100 is substantially the same as that described with reference to FIG. 1, differences will be mainly described below.

  When the self-test control circuit 16 performs a self-test operation of the ADC 100, the self-test control circuit 16 sets the signal level of the test signal output from the self-test signal source 10 to a value that exceeds the maximum value of the input dynamic range of the ADC 100. At this time, the up / down counter 17 initializes the minimum value.

  When the self-test control circuit 16 starts the self-test operation of the ADC 100, the logic output of the comparator 13 becomes Hi, so the up / down counter 17 continues to count up, and the output level of the local DAC 11 is all one step from the minimum value. While gradually selecting the level, it gradually increases and reaches the maximum value and becomes stable. The determination circuit 15 outputs a test result indicating that the ADC 100 is operating normally if the logic output of the comparator 13 is always Hi during this time, and if the ADC 100 is Low at any time, the ADC 100 operates abnormally. Outputs the test result to the effect.

  The self-test control circuit 16 switches the signal level of the self-test signal source 10 to a value less than the minimum value of the input dynamic range of the ADC 100 after reaching the state where the output level of the local DAC 11 is the maximum value. After that, since the logic output of the comparator 13 becomes Low, the up / down counter 17 continues to count down, and the output level of the local DAC 11 is gradually decreased to the minimum value while selecting all levels one by one from the maximum value. Reach and stabilize. The determination circuit 15 outputs a test result indicating that the ADC 100 is operating normally if the logic output of the comparator 13 is always low during this time, and if the ADC 100 is Hi at any point in time, the ADC 100 operates abnormally. Outputs the test result to the effect.

  FIG. 3 is a signal level diagram illustrating a self-test operation of ADC 100 described in FIG. 1 or FIG. FIG. 3A shows the level of the input signal (the output of the self-test signal source 10 and the output of the local DAC 11) to the comparator 13. FIG. 3B shows the output level of the comparator 13. The vertical axis represents each signal level, and the horizontal axis represents the passage of time.

  When the output level of the self-test signal source 10 is higher than the output level of the local DAC 11, the output logic level of the comparator 13 is Hi. When the output level of the self-test signal source 10 is smaller than the output level of the local DAC 11, the output logic level of the comparator 13 is low.

  In FIG. 3, the control circuit 14 (in the case of FIG. 1) or the up / down counter 17 (in the case of FIG. 2) causes the output level of the local DAC 11 to start from the minimum level, reach the maximum level, and then decrease to the minimum level. Thus, the local DAC 11 is controlled. At the same time, the self-test signal source 10 outputs a test signal that exceeds the dynamic range, and outputs a test signal that is less than the dynamic range after the output of the local DAC 11 reaches the maximum value. This order may be reversed, i.e. starting from a maximum value and reaching a minimum value and then increasing to a maximum value.

<Embodiment 1: Summary>
As described above, the ADC 100 according to the first embodiment compares the test signal outside the dynamic range with the reference signal that is sequentially increased or decreased step by step. If the test signal level exceeds the dynamic range, the comparator 13 It is confirmed that Hi is always output, and if the test signal level is less than the dynamic range, it is confirmed that the comparator 13 always outputs Low. Thereby, all the reference signal levels can be diagnosed by a simple test sequence.

  In the first embodiment, unlike the conventional example described with reference to FIG. 6, the determination circuit 15 monitors only the Hi / Low output of the comparator 13 instead of converting the test signal into a digital value. Therefore, there is an advantage that the configuration of the determination circuit 15 can be simplified.

<Embodiment 2>
In the first embodiment, it has been described that the determination circuit 15 performs a self-test based on the output logic level of the comparator 13 to determine whether the ADC 100 is operating normally. In Embodiment 2 of the present invention, a configuration example in which the self-test is performed based on the time until the count value of the up / down counter 17 reaches the maximum value from the minimum value (or the time until it reaches the minimum value from the maximum value). explain.

  FIG. 4 is a circuit block diagram showing a configuration of the ADC 100 according to the second embodiment. The ADC 100 according to the second embodiment has substantially the same circuit configuration as that described with reference to FIG. 2, but the determination circuit 15 performs a self-test based on the above determination criteria. The count value of the counter 17 is received. Except for the operation of the determination circuit 15 described later, other configurations are the same as those in FIG.

  In the self-test of the ADC 100, the self-test control circuit 16 sets the test signal level above the dynamic range, and the up / down counter 17 initializes the count value to the minimum value. The determination circuit 15 measures the time until the count value of the up / down counter 17 starts from the minimum value and reaches the maximum value. Since the conversion time required by the ADC 100 is determined in advance, this time can be predicted in advance. The determination circuit 15 outputs a test result indicating that the ADC 100 is operating abnormally if the count value does not reach the maximum value at the time predicted in advance, and if it reaches, the test result indicating that the ADC 100 is operating normally. Is output.

  The self-test control circuit 16 switches the signal level of the self-test signal source 10 to a value less than the minimum value of the input dynamic range of the ADC 100 after reaching the state where the output level of the local DAC 11 is the maximum value. The determination circuit 15 measures the time until the count value of the up / down counter 17 starts from the maximum value and reaches the minimum value. Similarly, this time can be predicted in advance. The determination circuit 15 outputs a test result indicating that the ADC 100 is operating abnormally if the count value does not reach the minimum value at the time predicted in advance, and if it reaches, the test result indicating that the ADC 100 is operating normally. Is output.

<Embodiment 2: Summary>
As described above, the ADC 100 according to the first embodiment performs the self test based on whether or not the time until the count value of the up / down counter 17 reaches the maximum value / minimum value is as predicted. Thereby, the same effect as Embodiment 1 can be exhibited.

  In the first embodiment, the determination circuit 15 receives the analog logic output level of the comparator 13, but in the second embodiment, the determination circuit 15 receives the count value from the up / down counter 17. Since the up / down counter 17 can be mounted as a digital circuit, the determination circuit 15 and the up / down counter 17 can be mounted separately from the analog circuit such as the comparator 13. This has the advantage that the mounting work can be shared.

<Embodiment 3>
In the third embodiment of the present invention, a configuration example in which the ADC 100 is a current input type will be described. Any of the methods described in the first and second embodiments can be used as the self-test method of the ADC 100. In the following, differences from the first and second embodiments due to the difference in the type of ADC 100 will be described. In the following description, a configuration in which the configuration example described in the second embodiment is replaced with a current input type ADC will be exemplified.

  FIG. 5 is a circuit block diagram showing a configuration of the ADC 100 according to the third embodiment. The ADC 100 shown in FIG. 5 receives a current signal as an analog input signal. The ADC 100 includes circuit blocks similar to those in FIG. 4, but a specific circuit configuration corresponding to the current input type ADC is illustrated for some circuit blocks.

  The self-test signal source 10 is configured to output a current that is a current mirror of the constant current source Iself, and is set to output a current that is equal to or greater than the maximum value of the input dynamic range of the ADC 100.

The local DAC 11 includes 2 ⁿ −1 current sources that are required when the resolution of the ADC 100 is n bits, and includes constant current sources I1 to Ix and switches. The switch control decoder receives the counter value of the up / down counter 17 and controls each switch so that the local DAC 11 outputs a reference current signal corresponding to the count value.

  The input changeover switch 12 is constituted by SW1 and SW2, and only one of them is turned on. SW 1 connects the analog input terminal 1 and the comparator 13, and SW 2 connects the self-test signal source 10 and the comparator 13.

  The comparator 13 is a current comparison type, and if the input current at the (+) terminal is large, the comparator logic output becomes Hi level, and if the input current at the (+) terminal is small, the comparator logic output becomes Low level.

  In the self-test of the ADC 100, the self-test control circuit 16 first turns off SW1 and turns on SW2. The operations of the self-test control circuit 16, the up / down counter 17, and the determination circuit 15 are the same as in the case where the comparator 13 outputs Hi in the second embodiment.

  The self-test control circuit 16 turns off SW2 after reaching the state where the output level of the local DAC 11 is the maximum value. Since the input current disappears when SW2 is turned off, the logic output of the comparator 13 becomes Low. The operations of the self-test control circuit 16, the up / down counter 17, and the determination circuit 15 are the same as in the case where the comparator 13 outputs Low in the second embodiment.

<Modification of the present invention>
The present invention is not limited to the above-described embodiments, and includes various modifications. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of a certain embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of a certain embodiment. In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. Control lines and signal lines are those that are considered necessary for the explanation, and not all control lines and signal lines are necessarily shown in the product.

  In the above embodiment, the example in which the ADC 100 has the circuit configuration for performing the self test has been described. However, the circuit configuration for performing the operation test of the ADC 100 is separated from the ADC 100 and mounted independently. You can also.

  1: Analog input terminal, 2: Digital output terminal, 3: Self test result output terminal, 10: Self test signal source, 11: Local DAC, 12: Input changeover switch, 13: Comparator, 14: Control circuit, 15: Determination Circuit: 16: Self-test control circuit, 17: Up / down counter, 100: ADC.

Claims (5)

An ADC self-test circuit for testing whether the AD converter is operating normally;
A comparator that outputs a result of comparing an analog signal received as an input by the AD converter with a reference signal;
A reference signal supplier for supplying the reference signal having a signal level within a dynamic range of the AD converter to the comparator;
A test signal supplier for supplying a test signal instead of the analog signal to the comparator when testing whether the AD converter is operating normally;
A determination circuit for determining whether or not the AD converter is operating normally based on a result of the comparator comparing the test signal and the reference signal, and outputting the result;
With
The test signal supplier is
Supplying a Hi level test signal having a signal level exceeding the dynamic range of the AD converter or a Low level test signal having a signal level less than the dynamic range of the AD converter to the comparator;
The determination circuit includes:
When the test signal supplier supplies the Hi level test signal, the comparator outputs a level indicating that the test signal is higher, and the test signal supplier supplies the Low level test signal. Test the AD converter by confirming that the comparator outputs a level indicating that the test signal is lower ,
The reference signal supplier is
When the test signal supplier supplies the Hi level test signal, the signal level of the reference signal is switched from the minimum level to the maximum level within the dynamic range.
The determination circuit includes:
While the reference signal supplier switches the signal level of the reference signal from the minimum level to the maximum level, the comparator outputs a level indicating that the test signal is higher regardless of the signal level of the reference signal Determines that the AD converter is operating normally, and determines that the AD converter is operating abnormally when the comparator outputs a level indicating that the test signal is lower at any signal level. And
Further, the reference signal supplier is
When the test signal supplier supplies the low level test signal, the signal level of the reference signal is switched from the maximum level to the minimum level within the dynamic range.
The determination circuit includes:
While the reference signal supplier switches the signal level of the reference signal from the maximum level to the minimum level, the comparator outputs a level indicating that the test signal is lower regardless of the signal level of the reference signal Determines that the AD converter is operating normally, and determines that the AD converter is operating abnormally if the comparator outputs a level indicating that the test signal is higher at any signal level. An ADC self-test circuit. The ADC self-test circuit includes:
An up / down counter that counts up when the comparator outputs a level indicating that the test signal is higher, and counts down when the comparator outputs a level that indicates that the test signal is lower;
The reference signal supplier is
2. The ADC self-test circuit according to claim 1, wherein the signal level of the reference signal is increased or decreased in accordance with an increase or decrease in a count value by the up / down counter. The reference signal supplier is
When the test signal supplier supplies the Hi level test signal, the signal level of the reference signal is switched from the minimum level to the maximum level within the dynamic range.
The determination circuit includes:
The time from when the count value by the up / down counter reaches the value corresponding to the maximum level of the reference signal from the value corresponding to the minimum level of the reference signal is calculated in advance based on the conversion required time of the AD converter 3. The ADC self-test circuit according to claim 2 , wherein when the time matches, it is determined that the AD converter is operating normally, and when the time does not match, it is determined that the AD converter is operating abnormally. . The reference signal supplier is
When the test signal supplier supplies the low level test signal, the signal level of the reference signal is switched from the maximum level to the minimum level within the dynamic range.
The determination circuit includes:
The time until the count value by the up / down counter reaches the value corresponding to the minimum level of the reference signal from the value corresponding to the maximum level of the reference signal is calculated in advance based on the conversion required time of the AD converter. 3. The ADC self-test circuit according to claim 2 , wherein when the time matches, it is determined that the AD converter is operating normally, and when the time does not match, it is determined that the AD converter is operating abnormally. . The reference signal supplier is
When the test signal supplier supplies the Hi level test signal, the signal level of the reference signal is switched from the minimum level to the maximum level within the dynamic range.
The determination circuit includes:
The time from when the count value by the up / down counter reaches the value corresponding to the maximum level of the reference signal from the value corresponding to the minimum level of the reference signal is calculated in advance based on the conversion required time of the AD converter If it matches the time, it is determined that the AD converter is operating normally, and if it does not match, it is determined that the AD converter is operating abnormally,
Further, the reference signal supplier is
When the test signal supplier supplies the low level test signal, the signal level of the reference signal is switched from the maximum level to the minimum level within the dynamic range.
The determination circuit includes:
The time until the count value by the up / down counter reaches the value corresponding to the minimum level of the reference signal from the value corresponding to the maximum level of the reference signal is calculated in advance based on the conversion required time of the AD converter. 3. The ADC self-test circuit according to claim 2 , wherein when the time matches, it is determined that the AD converter is operating normally, and when the time does not match, it is determined that the AD converter is operating abnormally. .

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