JP6463407B2 - Semiconductor device - Google Patents
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本発明は、半導体装置に関し、特に、同一のＳＯＩ（Ｓｌｌｉｃｏｎ Ｏｎ ＩｎｓｕＩａｔｏｒ）基板上に、Ｘ線検出用のフォトダイオードとトランジスタを混在させたＸ線センサに関する。 The present invention relates to a semiconductor device, and more particularly to an X-ray sensor in which a photodiode and transistor for X-ray detection are mixed on the same SOI (Silicon On Insulator) substrate.
同一の半導体基板に、センサと周辺回路とが絶縁膜を介して形成されている構造の半導体装置が特許文献１、２に開示されている。 Patent Documents 1 and 2 disclose a semiconductor device having a structure in which a sensor and a peripheral circuit are formed on the same semiconductor substrate via an insulating film.
同一の半導体基板に、センサと周辺回路とが形成されている構造の半導体装置の中で、Ｘ線検出用のフォトダイオードとトランジスタとが同一の半導体基板に形成されている構造のＸ線センサにおいては、放射線入射時の検出感度を高くするため、Ｘ線検出用のフォトダイオードが形成されている半導体基板に低濃度高抵抗の半導体基板を使用したり、半導体基板裏面に数百Ｖのバイアスを印加する等の方法により、半導体基板全体を空乏化することがある。 In a semiconductor device having a structure in which a sensor and a peripheral circuit are formed on the same semiconductor substrate, an X-ray sensor having a structure in which a photodiode for X-ray detection and a transistor are formed on the same semiconductor substrate Uses a low-concentration, high-resistance semiconductor substrate on the semiconductor substrate on which an X-ray detection photodiode is formed, or a bias of several hundred volts is applied to the back surface of the semiconductor substrate in order to increase the detection sensitivity upon radiation incidence. The whole semiconductor substrate may be depleted by a method such as application.
この際、ＳＯＩ（Ｓｌｌｉｃｏｎ Ｏｎ ＩｎｓｕＩａｔｏｒ）基板を用いることにより、図１０のように、埋め込み酸化膜４の上側の第１の半導体層１１を回路動作用のＭＯＳトランジスタ１等の素子形成用の高濃度低抵抗基板、埋め込み酸化膜４の下側の第２の半導体層１５をフォトダイオード２形成用の低濃度高抵抗基板とすることで、１枚のウエハ１０上で周辺回路を含めたＸ線センサを構成することができる。 At this time, by using an SOI (Silicon On Insulator) substrate, as shown in FIG. 10, the first semiconductor layer 11 above the buried oxide film 4 has a high concentration for forming an element such as a MOS transistor 1 for circuit operation. An X-ray sensor including peripheral circuits on a single wafer 10 by using a low-resistance substrate and the second semiconductor layer 15 below the buried oxide film 4 as a low-concentration high-resistance substrate for forming the photodiode 2. Can be configured.
しかしながら、第２の半導体層１５を空乏化するために第２の半導体層１５の裏面に印加した電圧３が、埋め込み酸化膜４を介して埋め込み酸化膜４上に形成した第１の半導体層１１にも伝わり、第１の半導体層１１に形成したＭＯＳトランジスタ１において、本来、ポリシリコン膜で形成されたゲート電極５によってコントロールされる電流経路６とは別に、第２の半導体層１５から伝達した電圧によって埋め込み酸化膜４側のチャネル領域が電流経路７として動作してしまう問題点と、Ｘ線の照射によって埋め込み酸化膜４が正に帯電することで埋め込み酸化膜４側のチャネル領域が電流経路７として動作してしまう問題点があった。 However, the voltage 3 applied to the back surface of the second semiconductor layer 15 to deplete the second semiconductor layer 15 is formed on the buried oxide film 4 via the buried oxide film 4. In the MOS transistor 1 formed in the first semiconductor layer 11, the current is transmitted from the second semiconductor layer 15 separately from the current path 6 controlled by the gate electrode 5 originally formed of a polysilicon film. The problem is that the channel region on the buried oxide film 4 side operates as a current path 7 due to voltage, and the channel region on the buried oxide film 4 side becomes a current path because the buried oxide film 4 is positively charged by X-ray irradiation. There was a problem that it operated as 7.
これらの問題を解決するために、図１１に示すように、ＭＯＳトランジスタ１の直下の第２の半導体層１５の表面に、第２の半導体層１５にドーピングされている不純物とは逆の導電型を持ち、センサピクセルとして動作する拡散層８を形成し、更にその内側に拡散層８と逆の導電型を持つ拡散層９を形成し、これらの電位をＧＮＤに接地することで、第２の半導体層１５を空乏化するために第２の半導体層１５の裏面に印加した電圧３が第１の半導体層１１に伝わることを抑制し、さらに放射線耐性を高めることが考えられる。 In order to solve these problems, as shown in FIG. 11, the conductivity type opposite to the impurity doped in the second semiconductor layer 15 is formed on the surface of the second semiconductor layer 15 immediately below the MOS transistor 1. And a diffusion layer 8 having a conductivity type opposite to that of the diffusion layer 8 is formed on the inner side thereof, and these potentials are grounded to the GND, thereby forming the second layer. In order to deplete the semiconductor layer 15, it is conceivable that the voltage 3 applied to the back surface of the second semiconductor layer 15 is prevented from being transmitted to the first semiconductor layer 11 and the radiation resistance is further increased.
しかしながら、この構造においては、図１１に示すように、第１の半導体層１１と拡散層８との間に寄生容量１０１を持ってしまい、また、第２の半導体層１５中に形成したセンサピクセルとしてのダイオードにおいて、拡散層８と拡散層９との間に寄生容量１０２を持ってしまい、センサに対するノイズ増加や、速度低下の原因となってしまう。 However, in this structure, as shown in FIG. 11, there is a parasitic capacitance 101 between the first semiconductor layer 11 and the diffusion layer 8, and the sensor pixel formed in the second semiconductor layer 15. In the diode, the parasitic capacitance 102 is provided between the diffusion layer 8 and the diffusion layer 9, which causes an increase in noise and a decrease in speed for the sensor.
本発明の主な目的は、フォトダイオードとトランジスタとが絶縁膜を介して同一の半導体基板に形成され、寄生容量の小さい半導体装置を提供することにある。 A main object of the present invention is to provide a semiconductor device in which a photodiode and a transistor are formed on the same semiconductor substrate with an insulating film interposed therebetween and the parasitic capacitance is small.
本発明によれば、
一主面に、第１の領域と前記第１の領域に隣接する第２の領域と前記第１の領域に隣接すると共に前記第２の領域と離間する第３の領域とを備えた、一導電型の第２の半導体層と、
前記第１の領域の前記一主面に配置されると共に前記一導電型とは反対の導電型である反対導電型の第１半導体領域、を備えたフォトダイオードと、
前記一主面上に配置された第２の絶縁層と、
前記第２の領域に対応する前記第２の絶縁層の上面に配置されると共に、固定電位が与えられる第３の半導体層と、
前記第３の領域に対応する前記第２の絶縁層の前記上面に配置された第４の半導体層と、
前記第３の半導体層の上面と前記第４の半導体層の上面とを被覆する第１の絶縁層と、
前記第２の領域に対応する前記第１の絶縁層の上面に配置されると共に、トランジスタ素子を備えた第１の半導体層と、
前記第１半導体領域に接続された第１電極と、
を備える半導体装置が提供される。
According to the present invention,
One main surface includes a first region, a second region adjacent to the first region, and a third region adjacent to the first region and spaced from the second region. A conductive second semiconductor layer;
A photodiode having a first semiconductor region of an opposite conductivity type disposed on the one main surface of the first region and having a conductivity type opposite to the one conductivity type;
A second insulating layer disposed on the one principal surface;
A third semiconductor layer disposed on an upper surface of the second insulating layer corresponding to the second region and to which a fixed potential is applied;
A fourth semiconductor layer disposed on the upper surface of the second insulating layer corresponding to the third region;
A first insulating layer covering an upper surface of the third semiconductor layer and an upper surface of the fourth semiconductor layer;
A first semiconductor layer disposed on an upper surface of the first insulating layer corresponding to the second region and having a transistor element;
A first electrode connected to the first semiconductor region ;
A semiconductor device is provided.
本発明によれば、フォトダイオードとトランジスタとが絶縁膜を介して同一の半導体基板に形成され、寄生容量の小さい半導体装置が提供される。 According to the present invention, a photodiode and a transistor are formed on the same semiconductor substrate via an insulating film, and a semiconductor device having a small parasitic capacitance is provided.
以下、本発明の好ましい実施の形態について図面を参照しながら説明する。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
図１を参照すれば、本発明の好ましい実施の形態の半導体装置１００は、周辺回路用のＭＯＳトランジスタ４０が形成された第１の半導体層１１と、センサピクセルとして機能し、第２の半導体層１５と半導体領域２３１とを備えるフォトダイオード３０と、第１の半導体層１１と第２の半導体層１５との間に設けられた第３の半導体層１３と、第１の半導体層１１と第３の半導体層１３との間に設けられた埋め込み酸化膜１２と、第２の半導体層１１と第３の半導体層１３との間に設けられた埋め込み酸化膜１４とを備えている。 Referring to FIG. 1, a semiconductor device 100 according to a preferred embodiment of the present invention includes a first semiconductor layer 11 in which a peripheral circuit MOS transistor 40 is formed, a sensor pixel, and a second semiconductor layer. 15 and the semiconductor region 231, the third semiconductor layer 13 provided between the first semiconductor layer 11 and the second semiconductor layer 15, the first semiconductor layer 11 and the third semiconductor layer 231. A buried oxide film 12 provided between the semiconductor layer 13 and a buried oxide film 14 provided between the second semiconductor layer 11 and the third semiconductor layer 13.
第１の半導体層１１、第３の半導体層１３はＰ型半導体基板、第２の半導体層１５はＮ型半導体基板で形成している。第２の半導体層１５の主面１５１の領域５１には、Ｐ型の半導体領域２３１が設けられている。Ｐ型の半導体領域２３１とＮ型の第２の半導体層１５で、センサピクセルとして機能する、Ｘ線用のフォトダイオード３０が形成されている。なお、第２の半導体層１５の主面１５１の領域５１には、高濃度のＮ型の取り出し領域２３２が設けられている。第２の半導体層１５の主面１５１と反対側の主面１５２には、電極２８０が設けられている。ＭＯＳトランジスタ４０が形成された第１の半導体層１１のアクティブ領域１１１は、第２半導体層１５の主面１５１の領域５１とは異なる領域６１上に設けられている。第１の半導体層１１のアクティブ領域１１１と第２の半導体層１５との間に設けられた第３の半導体層１３には、高濃度のＰ型の取り出し領域２４が設けられている。 The first semiconductor layer 11 and the third semiconductor layer 13 are formed of a P-type semiconductor substrate, and the second semiconductor layer 15 is formed of an N-type semiconductor substrate. A P-type semiconductor region 231 is provided in the region 51 of the main surface 151 of the second semiconductor layer 15. The P-type semiconductor region 231 and the N-type second semiconductor layer 15 form an X-ray photodiode 30 that functions as a sensor pixel. Note that a high-concentration N-type extraction region 232 is provided in the region 51 of the main surface 151 of the second semiconductor layer 15. An electrode 280 is provided on the main surface 152 opposite to the main surface 151 of the second semiconductor layer 15. The active region 111 of the first semiconductor layer 11 in which the MOS transistor 40 is formed is provided on a region 61 different from the region 51 of the main surface 151 of the second semiconductor layer 15. The third semiconductor layer 13 provided between the active region 111 of the first semiconductor layer 11 and the second semiconductor layer 15 is provided with a high-concentration P-type extraction region 24.
Ｎ型の第２の半導体層１５は、第２の半導体層１５の主面１５２に設けられた電極２８０および第２の半導体層１５の主面１５１に設けられた高濃度のＮ型の取り出し領域２３２に接続された取り出し電極２７５を介して電源２８の正極側に接続されている。第２の半導体層１５の主面１５１に設けられたＰ型の半導体領域２３１は、取り出し電極２７４を介して電源２８の負極側およびＧＮＤ９０に接続されている。Ｐ型の第３の半導体層１３は、高濃度のＰ型の取り出し領域２４に接続された取り出し電極２７１を介してＧＮＤ９０に接続されている。 The N-type second semiconductor layer 15 includes an electrode 280 provided on the main surface 152 of the second semiconductor layer 15 and a high-concentration N-type extraction region provided on the main surface 151 of the second semiconductor layer 15. It is connected to the positive electrode side of the power supply 28 via the extraction electrode 275 connected to H.232. The P-type semiconductor region 231 provided on the main surface 151 of the second semiconductor layer 15 is connected to the negative electrode side of the power supply 28 and the GND 90 via the extraction electrode 274. The P-type third semiconductor layer 13 is connected to the GND 90 via an extraction electrode 271 connected to the high-concentration P-type extraction region 24.
Ｘ線用のフォトダイオード３０を構成するＮ型の第２の半導体層１５を空乏化するために、第２半導体層１５の裏面（主面１５２）と高濃度のＮ型の取り出し領域２３２（カソード電極）に電源２８より正の高電圧を印加する。この時、第３の半導体層１３とダイオードのアノード電極となるＰ型の半導体領域２３１はＧＮＤ９０に接地する。 In order to deplete the N-type second semiconductor layer 15 constituting the X-ray photodiode 30, the back surface (main surface 152) of the second semiconductor layer 15 and the high-concentration N-type extraction region 232 (cathode) A positive high voltage is applied to the electrode) from the power source 28. At this time, the third semiconductor layer 13 and the P-type semiconductor region 231 serving as the anode electrode of the diode are grounded to the GND 90.
Ｐ型基板で形成された第３の半導体層１３をＧＮＤ電位に固定することにより、第２の半導体層１５を空乏化するために第２の半導体層１５の裏面（主面１５２）に高電圧を印加した場合でも、第１の半導体層１１のアクティブ領域１１１の埋め込み酸化膜１２側の界面には第２の半導体層１５の裏面に印加した高電圧２８は伝達しない。 A high voltage is applied to the back surface (main surface 152) of the second semiconductor layer 15 in order to deplete the second semiconductor layer 15 by fixing the third semiconductor layer 13 formed of the P-type substrate to the GND potential. Even when is applied, the high voltage 28 applied to the back surface of the second semiconductor layer 15 is not transmitted to the interface of the active region 111 of the first semiconductor layer 11 on the buried oxide film 12 side.
このように、第１の半導体層１１のアクティブ領域１１１に形成したＭＯＳトランジスタ４０と第２の半導体層１５に形成したセンサピクセルとしてのダイオード３０の間にはＧＮＤに固定された第３の半導体層１３があるために、センサピクセルヘの寄生容量は非常に小さくなる。また、センサピクセルヘ信号が入力された際に第１の半導体層１１のＭＯＳトランジスタ４０へ影響を及ぼすクロストークも、ほぼ無視できる程度となる。 As described above, the third semiconductor layer fixed to GND is provided between the MOS transistor 40 formed in the active region 111 of the first semiconductor layer 11 and the diode 30 as the sensor pixel formed in the second semiconductor layer 15. 13, the parasitic capacitance to the sensor pixel is very small. In addition, crosstalk that affects the MOS transistor 40 of the first semiconductor layer 11 when a signal is input to the sensor pixel is almost negligible.
次に、本発明の好ましい実施の形態の半導体装置１００の製造方法について説明する。 Next, a method for manufacturing the semiconductor device 100 according to a preferred embodiment of the present invention will be described.
まず、図２に示すように１００〜２００ｎｍ程度の厚さの埋め込み酸化膜１０、１４を挟んで上側に１００ｎｍの厚さの第１の半導体層１１と、下側に７００μｍ程度の厚さの第２の半導体層１５、中央に１００ｎｍの厚さの第３の半導体層１３を有するＤｏｕｂｌｅ−ＳＯＩ（Ｄｏｕｂｌｅ−Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓｕｌａｔｏｒ）基板を用いる。この時、例えば第１の半導体層１１、第３の半導体層１３は比抵抗１０Ω・ｃｍのＰ型半導体基板、第２の半導体層１５は比抵抗１０ｋΩ・ｃｍのＮ型半導体基板で形成する。 First, as shown in FIG. 2, a first semiconductor layer 11 having a thickness of about 100 nm is sandwiched between the buried oxide films 10 and 14 having a thickness of about 100 to 200 nm, and a first semiconductor layer 11 having a thickness of about 700 μm is disposed on the lower side. A double-SOI (Double-Silicon On Insulator) substrate having two semiconductor layers 15 and a third semiconductor layer 13 having a thickness of 100 nm in the center is used. At this time, for example, the first semiconductor layer 11 and the third semiconductor layer 13 are formed of a P-type semiconductor substrate having a specific resistance of 10 Ω · cm, and the second semiconductor layer 15 is formed of an N-type semiconductor substrate having a specific resistance of 10 kΩ · cm.
第１の半導体層１１の表面に、パッド酸化膜（図示せず）と窒化膜（図示せず）を形成し、ＬＯＣＯＳ形成法によりフィールド酸化膜を形成した後に、図３に示すように、全ての窒化膜と、パッド酸化膜を除去する。これにより、第１の半導体層１１にアクティブ領域１１１が形成される。 After forming a pad oxide film (not shown) and a nitride film (not shown) on the surface of the first semiconductor layer 11 and forming a field oxide film by the LOCOS formation method, as shown in FIG. The nitride film and the pad oxide film are removed. As a result, an active region 111 is formed in the first semiconductor layer 11.
さらに、図４に示すように、第１の半導体層１１のアクティブ領域１１１の表面にゲート酸化膜１６を形成し、ポリシリコン膜を堆積、フォトレジスト（図示せず）でパターニングを行なったポリシリコン膜のドライエッチングを行い、ゲート電極１８を形成する。 Further, as shown in FIG. 4, a gate oxide film 16 is formed on the surface of the active region 111 of the first semiconductor layer 11, a polysilicon film is deposited, and polysilicon is patterned with a photoresist (not shown). The film is dry-etched to form the gate electrode 18.
その後、図５に示すように、フォトレジスト（図示せず）を除去した後に、第１の半導体層１１のアクティブ領域１１１にＬＤＤ（図示せず）のイオン注入を行い、サイドウォールスペーサ２０を形成したのちに、高濃度ソース・ドレイン１９のイオン注入工程を行い、ＭＯＳトランジスタ４０を形成する。 Thereafter, as shown in FIG. 5, after removing the photoresist (not shown), LDD (not shown) is ion-implanted into the active region 111 of the first semiconductor layer 11 to form the sidewall spacer 20. After that, an ion implantation process of the high concentration source / drain 19 is performed to form the MOS transistor 40.
その後、図６に示すように、第２の半導体層１５に形成するべきＰ型の半導体領域２３１、Ｎ型の取り出し領域２３２、第３半導体層１３の分離領域１３１以外の場所をフォトレジスト（図示せず）にて覆い、埋め込み酸化膜１２、１４、第３の半導体層１３をエッチングして、開口２１１、２１２、分離領域用溝２１３をそれぞれ形成した後に、フォトレジストを除去する。また、第３の半導体層１３に形成するべきＰ型の取り出し電極領域２４以外の場所をフォトレジスト（図示せず）にて覆い、埋め込み酸化膜１２をエッチングして、開口２２を形成した後にフォトレジストを除去する。 After that, as shown in FIG. 6, a photoresist (see FIG. 6) is provided except for the P-type semiconductor region 231, the N-type extraction region 232, and the third semiconductor layer 13 separation region 131 to be formed in the second semiconductor layer 15. The buried oxide films 12 and 14 and the third semiconductor layer 13 are etched to form the openings 211 and 212 and the isolation region trench 213, respectively, and then the photoresist is removed. Further, a portion other than the P-type extraction electrode region 24 to be formed in the third semiconductor layer 13 is covered with a photoresist (not shown), the buried oxide film 12 is etched, and the opening 22 is formed. Remove the resist.
ダイオードのカソードを兼ねたＮ型の取り出し領域２３２には、開口２１２を介して、例えば注入エネルギー６０ｋｅｖ、ドーズ量５．０×１０１５ｃｍ−２程度の不純物３１Ｐ＋を注入し、ダイオードのアノードを兼ねたＰ型の半導体領域２３１には、開口２１１を介して、例えば注入エネルギー４０ｋｅＶ、ドーズ量５．０×１０１５ｃｍ−２程度の不純物１１Ｂ＋を注入する。また、第３の半導体層１３のＰ型の取り出し領域２４には、開口２２を介して、例えば注入エネルギー１５ｋｅｖ、ドーズ量５．０×１０１５ｃｍ−２程度の不純物４９ＢＦ２ ＋を注入する。 For example, an impurity 31P + having an implantation energy of 60 kev and a dose of about 5.0 × 10 15 cm −2 is implanted through the opening 212 into the N-type extraction region 232 that also serves as the diode cathode. For example, an impurity 11B + having an implantation energy of 40 keV and a dose of about 5.0 × 10 15 cm −2 is implanted into the P-type semiconductor region 231 that also serves as the P-type semiconductor region 231. Further, an impurity 49BF 2 + having an implantation energy of 15 kev and a dose of about 5.0 × 10 15 cm −2 is implanted into the P-type extraction region 24 of the third semiconductor layer 13 through the opening 22.
この後、図７に示すように、ＣＶＤ膜２５の堆積によって層間膜を形成する。その後、第１の半導体層１１のアクティブ領域１１１と第２の半導体層１５、第３の半導体層１３の取り出し電極を形成する場所をエッチングすることによって、図８に示すように、コンタクトホール２６１、２６２、２６３、２６４、２６５を形成する。最後にスパッタによって形成したメタル層を、電極形成領域以外の部分をエッチングすることによって、図９に示すように、取り出し電極２７１、２７２、２７３、２７４、２７５を形成する。また、第２半導体層１５の裏面にも、電極２８０を形成する。 Thereafter, as shown in FIG. 7, an interlayer film is formed by depositing a CVD film 25. Thereafter, by etching the active region 111 of the first semiconductor layer 11, the second semiconductor layer 15, and the place where the extraction electrode of the third semiconductor layer 13 is formed, as shown in FIG. 262, 263, 264, and 265 are formed. Finally, the metal layer formed by sputtering is etched at portions other than the electrode formation region, thereby forming extraction electrodes 271, 272, 273, 274, 275 as shown in FIG. An electrode 280 is also formed on the back surface of the second semiconductor layer 15.
第３の半導体層１３に分離領域を形成する手法として、図７に示すように第２の半導体層１５の主面１５１にＰ型の半導体領２３１およびＮ型の取り出し領域を形成する際に、同時に第３の半導体層１３の分離領域１３１を形成する部分のエッチングを行うことで、特別な工程を行ったり、マスクなどを準備することなく、第３半導体層１３の分離領域１３１の形成を行うことが可能となり、第３の半導体層１３同士を電気的に分離することが可能となる。 As a method of forming the isolation region in the third semiconductor layer 13, when forming the P-type semiconductor region 231 and the N-type extraction region on the main surface 151 of the second semiconductor layer 15 as shown in FIG. At the same time, the portion of the third semiconductor layer 13 where the isolation region 131 is formed is etched, so that the isolation region 131 of the third semiconductor layer 13 is formed without performing a special process or preparing a mask or the like. Accordingly, the third semiconductor layers 13 can be electrically separated from each other.
なお、上記の実施の形態では、第２の半導体層１５がＮ型基板である場合について説明しているが、第２の半導体層１５がＰ型の半導体装置にも適用可能であり、その場合には、他の領域についても、Ｐ型とあったのをＮ型とし、Ｎ型とあったのをＰ型とする。 In the above embodiment, the case where the second semiconductor layer 15 is an N-type substrate is described. However, the second semiconductor layer 15 can also be applied to a P-type semiconductor device. In other regions, the P type is defined as the N type, and the P type is defined as the N type.
以上、本発明の種々の典型的な実施の形態を説明してきたが、本発明はそれらの実施の形態に限定されない。従って、本発明の範囲は、次の特許請求の範囲によってのみ限定されるものである。 While various typical embodiments of the present invention have been described above, the present invention is not limited to these embodiments. Accordingly, the scope of the invention is limited only by the following claims.
１１ 第１の半導体層
１２ 埋め込み酸化膜
１３ 第３の半導体層
１４ 埋め込み酸化膜
１５ 第２の半導体層
１６ ゲート酸化膜
１８ ゲート電極
１９ ソース・ドレイン
２２ 開口
２４ Ｐ型の取り出し領域
２８ 電源
３０ フォトダイオード
４０ ＭＯＳトランジスタ
５１、６１ 領域
９０ ＧＮＤ
１００ 半導体装置
１１１ アクティブ領域
１３１ 分離領域
１５１ 主面
１５２ 主面
２１１、２１２ 開口
２１３ 分離領域用溝
２３１ Ｐ型の半導体領域
２３２ Ｎ型の取り出し領域
２６１、２６２、２６３、２６４、２６５ コンタクトホール
２７１、２７２、２７３、２７４、２７５ 取り出し電極
２８０ 電極
11 First semiconductor layer 12 Buried oxide film 13 Third semiconductor layer 14 Buried oxide film 15 Second semiconductor layer 16 Gate oxide film 18 Gate electrode 19 Source / drain 22 Opening 24 P-type extraction region 28 Power supply 30 Photodiode 40 MOS transistors 51 and 61, region 90 GND
100 Semiconductor device 111 Active region 131 Isolation region 151 Main surface 152 Main surface 211, 212 Opening 213 Separation region groove 231 P-type semiconductor region 232 N-type extraction region 261, 262, 263, 264, 265 Contact holes 271, 272 273, 274, 275 Extraction electrode 280 Electrode
Claims (6)
前記第１の領域の前記一主面に配置されると共に前記一導電型とは反対の導電型である反対導電型の第１半導体領域、を備えたフォトダイオードと、
前記一主面上に配置された第２の絶縁層と、
前記第２の領域に対応する前記第２の絶縁層の上面に配置されると共に、固定電位が与えられる第３の半導体層と、
前記第３の領域に対応する前記第２の絶縁層の前記上面に配置された第４の半導体層と、
前記第３の半導体層の上面と前記第４の半導体層の上面とを被覆する第１の絶縁層と、
前記第２の領域に対応する前記第１の絶縁層の上面に配置されると共に、トランジスタ素子を備えた第１の半導体層と、
前記第１半導体領域に接続された第１電極と、
を備える半導体装置。 One main surface includes a first region, a second region adjacent to the first region, and a third region adjacent to the first region and spaced from the second region. A conductive second semiconductor layer;
A photodiode having a first semiconductor region of an opposite conductivity type disposed on the one main surface of the first region and having a conductivity type opposite to the one conductivity type;
A second insulating layer disposed on the one principal surface;
A third semiconductor layer disposed on an upper surface of the second insulating layer corresponding to the second region and to which a fixed potential is applied;
A fourth semiconductor layer disposed on the upper surface of the second insulating layer corresponding to the third region;
A first insulating layer covering an upper surface of the third semiconductor layer and an upper surface of the fourth semiconductor layer;
A first semiconductor layer disposed on an upper surface of the first insulating layer corresponding to the second region and having a transistor element;
A first electrode connected to the first semiconductor region;
A semiconductor device comprising:
前記第４の領域の前記一主面に配置された前記一導電型の第２半導体領域と、
前記第２半導体領域に接続された第２電極と、
を備え、
前記第４の半導体層は、前記第１電極と前記第２電極との間に配置される、
ことを特徴とする請求項１または２に記載の半導体装置。 The second semiconductor layer further includes a fourth region spaced apart from the second region and facing the first region across the third region on the one main surface,
The one-conductivity-type second semiconductor region disposed on the one main surface of the fourth region;
A second electrode connected to the second semiconductor region;
With
The fourth semiconductor layer is disposed between the first electrode and the second electrode;
The semiconductor device according to claim 1, wherein:
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