JP6463574B2 - Transmitting apparatus and receiving apparatus - Google Patents

Description

  The present invention relates to the technical fields of satellite broadcasting and terrestrial broadcasting, fixed communication, and mobile communication, and more particularly, to a digital signal transmitting apparatus and receiving apparatus in a digital transmission system.

  Conventionally, an LDPC (Low Density Parity Check) code is an error correction code having a performance approaching the Shannon limit, and a transmission system satellite broadcasting system of an advanced broadband satellite digital system of the standard ARIB STD-B44 (see, for example, Non-Patent Document 1). ) And DVB-S2 (Digital Video Broadcasting-Satellite-Second Generation).

  FIG. 8 shows a schematic configuration of a typical transmission apparatus 100 and reception apparatus 200 based on ARIB STD-B44. The transmission device 100 includes a TS multiplexer 11, a BCH encoder 12, an energy spread processor 13, an LDPC encoder 14, a bit interleave processor 15, and a modulator 16. The receiving apparatus 200 includes a demodulation unit 21, a bit deinterleave processing unit 22, an LDPC decoding unit 23, an energy despreading processing unit 24, a BCH decoding unit 25, and a TS separation unit 26.

  Briefly, in the transmission apparatus 100, the TS signal of one or more transport streams (hereinafter abbreviated as “TS”) to be transmitted is assigned to data of a plurality of slots mainly by the TS multiplexing unit 11. Then, a transmission frame in which the plurality of slots are multiplexed is generated. Each slot includes a slot header, data, BCH code parity, stuff bits ('1' for 6 bits), and LDPC code parity.

  Then, the BCH encoding unit 12 applies BCH encoding processing to the slot header and data of each slot to give a BCH parity to each slot, and the energy spreading processing unit 13 sets the slot header, data, and BCH parity of each slot. After the energy spreading process (bit randomization) is performed on the stuff bits, the LDPC encoding unit 14 performs the LDPC encoding process to give the LDPC code parity to each slot.

  Thereafter, the bit interleave processing unit 15 applies the modulation scheme (8PSK, 16APSK, 32APSK) and LDPC coding rate of each slot in the transmission frame to the bit sequence (code length of 48880 bits) to which the LDPC code parity is added. Corresponding to bit interleaving processing (energy dispersion associated with the difference in the modulation method), the symbol is configured by the modulation unit 16 according to the modulation method (π / 2 shift BPSK, QPSK, 8PSK, 16APSK, 32APSK). Then, a modulated wave is transmitted by inserting a predetermined symbol header and a burst signal serving as a phase reference.

  On the other hand, in the receiving device 200, the demodulating unit 21 receives and demodulates the modulated wave transmitted from the transmitting device 100 via the transmission path, and a bit deinterleave processing unit 22, an LDPC decoding unit 23, an energy despreading processing unit 24, and The BCH decoding unit 25 restores the TS signal of each slot by performing reverse processing of the bit interleaving processing unit 15, the LDPC encoding unit 14, the energy spreading processing unit 13, and the BCH encoding unit 12 of the transmission device 100, respectively. The TS separation unit 26 extracts the TS signal of each slot to restore the TS, and separates and outputs a plurality of TSs.

  Thus, in a typical transmitting apparatus 100 and receiving apparatus 200 based on ARIB STD-B44, a concatenated code with the BCH code as an outer code and the LDPC code as an inner code is used.

  As a characteristic of the LDPC code, a long code length is necessary to exhibit error correction performance, and the ARIB STD-B44 employs a code length of 48880 bits. Further, correction is possible for both random errors and burst errors, and a general satellite broadcast transmission path has sufficient correction capability. Since the LDPC code is not a deterministic error correction method, an error floor occurs. However, the error floor can be removed by using a concatenated code with the BCH code as an outer code and the LDPC code as an inner code. The parity bit length of the BCH code in ARIB STD-B44 is 192 bits, and error correction of 12 bits or less is possible.

  In addition, a bandwidth of 600 MHz in the 21 GHz band is internationally allocated for satellite broadcasting, and a service with a larger capacity than the transmission capacity of the ultra-high-definition television broadcasting that is scheduled to be serviced in the current 12 GHz band. Research aimed at achieving this is underway (see Non-Patent Document 2, for example). The transmission capacity of ultra-high-definition television broadcasting is about 680 Mbps at maximum by dividing the 600 MHz band into 300 MHz and using a concatenated code of LDPC code and BCH code based on ARIB STD-B44 and a modulation method of 8PSK. Can be transmitted. However, radio waves in the 21 GHz band are susceptible to attenuation due to rain and the like, and a technique for reducing the influence is necessary. Therefore, a technique for variably forming a radiation pattern by spatially synthesizing the power of a modulated wave to be relayed on the satellite side so as to increase the radiation power to a specific area has been studied.

"Transmission system of advanced broadband satellite digital broadcasting standard ARIB STD-B44 2.0 version", [online], revised July 31, 2014, ARIB, [searched January 5, 2015], Internet <URL: http : //www.arib.or.jp/english/html/overview/doc/2-STD-B44v2_0.pdf> "Research and development of effective frequency utilization technology for next-generation satellite broadcasting system", [online], Information Distribution Administration Bureau Broadcasting Technology Division, [January 5, 2015 search], Internet <URL: http: // www.tele.soumu.go.jp/resource/j/fees/purpose/pdf/26kenkyukaihatsu.pdf#page=23>

  As described above, in a transmission system composed of a digital signal transmitting device and a receiving device, by employing a concatenated code of a BCH code and an LDPC code, error correction with performance approaching the Shannon limit is possible, and error floor Although it can be removed, it is susceptible to attenuation due to rainfall, etc., and the radiation pattern can be varied by spatially synthesizing the power of the modulated wave to be relayed on the satellite side so as to increase the radiation power to a specific area to improve this. The technology to be formed is also studied.

  However, even with such a radiation pattern variable technique, when viewed from the receiving device side, the state during the radiation pattern change is undefined. For this reason, depending on the timing, the phase synchronization of the receiving device is lost, which causes a problem that a burst error of a certain period that cannot be corrected by the LDPC code is output.

  This burst error is difficult to correct with the error correction capability (12 bits) of the BCH code of the outer code introduced to correct the error floor. In addition, since it is not assumed that the radiation pattern is frequently changed, if transmission is always performed so as to reduce the coding rate of error correction, the transmission capacity of the entire transmission system is reduced.

  Such a burst error exceeding the error correction capability of the LDPC code is a problem to be considered even in the case of the satellite relay to which the radiation pattern variable technology is applied, and is improved as a transmission system including a digital signal transmission device and a reception device. Is desired.

  In view of the above problems, an object of the present invention is to provide a digital signal transmitting apparatus and receiving apparatus.

  In the present invention, the block interleaving process is performed in such a manner that the receiving side can grasp the head position of the interleave block during the error correction process of the concatenated code in which the LDPC code is the inner code and the block code such as the BCH code is the outer code. By adding, it is possible to correct a burst error exceeding the error correction capability of the LDPC code. In particular, the determination of the start position of the interleaved frame is strengthened by replacing a specific bit in the reading direction from the beginning of the frame of the block interleaving process with a known random pattern between transmission and reception. As a result, transmission without reducing the error correction coding rate while reducing the influence of burst errors, that is, transmission while maintaining the originally desired transmission capacity becomes possible.

In other words, the transmitting apparatus of the present invention is a digital signal transmitting apparatus that multiplexes a predetermined number of TS signals of a transport stream to be transmitted, and is a stuff that is a signal that enables identification of attributes of the multiplexed TS signals. A TS multiplexing means for generating a transmission frame provided with a parity area of a concatenated code composed of an outer code and an inner code by adding bits to the data, and performing a predetermined block coding process on the data A first error correction coding means for assigning an outer code parity to a transmission frame, and an interleave block formed by parallelly framing a frame made up of data to which the outer code parity is given in an arbitrarily determined number of frames; The first bit of each frame for the specified number of frames in order from the first frame is a random pattern that is known between sending and receiving Instead, and through the frame reconstruction means for reconstructing a frame of interleaved blocks, and the block interleaving means for performing block interleaving processing on reconstructed interleaved block by the frame reconstruction unit, the block interleaving A second error correction coding means for applying an LDPC coding process to the obtained bit sequence to give an inner code parity to the transmission frame, and a predetermined value based on the bit sequence of the transmission frame obtained through the LDPC coding process; Modulation means for forming a symbol and generating a modulated wave according to the modulation method.

  In the transmission apparatus of the present invention, the number of frames of the interleave block is determined according to an error correction capability of the predetermined block encoding process.

  In the transmission apparatus of the present invention, the stuff bits include a bit sequence in which a numerical value indicating a delimiter of the multiplexed TS signal with respect to a transport stream is repeated a plurality of times in a predetermined bit unit.

  In the transmitting apparatus of the present invention, the stuff bits are a plurality of numerical values indicating a delimiter of the multiplexed TS signal so that the predetermined number of bits at the beginning or the predetermined number of bits at the end is 0. It is characterized by being configured repeatedly.

  Furthermore, the receiving apparatus of the present invention is a digital signal receiving apparatus, which demodulates a modulated wave generated by the transmitting apparatus of the present invention in accordance with the predetermined modulation method, and a demodulation process by the demodulating means A first error correction decoding means for performing a decoding process corresponding to the LDPC encoding process on the bit sequence obtained through the decoding process, and a block deinterleaving process on the bit sequence obtained through the decoding process, Block deinterleave processing means for temporarily restoring a frame of a deinterleave block corresponding to the interleave block, and a first bit in which a known random pattern is described between the transmission and reception for the temporarily restored frame By replacing based on the bit sequence included in the range of the stuff bit, A frame restoring means for restoring the frame of the deinterleave block, and a second error correction decoding means for performing a decoding process corresponding to the predetermined block encoding process on the bit sequence of the frame restored by the frame restoring means And TS separation means for extracting each TS signal from the data obtained by the decoding process and restoring and separating the transport stream that has been transmitted.

  Further, in the receiving apparatus of the present invention, the block deinterleaving processing means includes an interleaving located at the highest level of the interleave block on the transmission side from the bit sequence obtained through the decoding process using a known random pattern between the transmission and reception. It has means for detecting a frame and temporarily restoring the frame of the deinterleave block by the block deinterleave process.

  Further, in the receiving apparatus of the present invention, the demodulating means includes means for demodulating the modulated wave generated by the transmitting apparatus of the present invention according to the predetermined modulation method, and the frame restoring means is the temporary restoring The bit pattern of the numerical value in which the first bit in which a known random pattern is described between the transmission and reception is repeatedly described in units of the predetermined bit within the range of the stuff bit in the frame is grasped Then, it has means for restoring the frame of the deinterleave block by replacing the bit pattern so as to maintain continuity.

  Transmission performance against burst errors exceeding the error correction capability of the LDPC code can be improved.

It is a block diagram which shows schematic structure of the transmission system which consists of the transmitter of one Embodiment by this invention, and a receiver. It is a figure explaining the process of each functional block in the transmitter of one Embodiment by this invention. It is a figure which illustrates the structure of the transmission frame by the concatenated code of the LDPC code and the BCH code in the transmission system which consists of the transmitter and receiver of one Embodiment by this invention. It is a figure which shows the detailed example of the transmission frame in the transmission system which consists of the transmitter of one Embodiment by this invention, and a receiver. It is a figure explaining the block interleaving process in the transmitter of one Embodiment by this invention. It is a figure explaining the block deinterleaving process in the receiver of one Embodiment by this invention. (A), (b), (c) is the figure explaining the effect of the transmission system which consists of the transmitting apparatus and receiving apparatus of one Embodiment by this invention in the normal time, the moment of a burst error, and before and after a burst error, respectively. It is. It is a block diagram which shows schematic structure of the transmission system which consists of a transmitter of a prior art, and a receiver.

  Hereinafter, a transmission device 10 and a reception device 20 according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a schematic configuration of a transmission system including a transmission device 10 and a reception device 20 according to an embodiment of the present invention. In FIG. 1, the same components as those in FIG. 8 are denoted by the same reference numerals.

(Transmission system)
The transmission apparatus 10 of this embodiment includes a TS multiplexing unit 17, a BCH encoding unit 12, a frame reconstruction unit 18, a block interleave processing unit 19, an energy spreading processing unit 13, an LDPC encoding unit 14, and a bit interleaving processing unit 15. And a modulation unit 16. In addition, the receiving apparatus 20 according to the present embodiment includes a demodulation unit 21, a bit deinterleave processing unit 22, an LDPC decoding unit 23, an energy despreading processing unit 24, a block deinterleaving processing unit 27, a frame restoration unit 28, and a BCH decoding unit 25. , And a TS separation unit 29.

  That is, the transmission device 10 of this embodiment includes a TS multiplexing unit 17 that generates a transmission frame by a process different from the TS multiplexing unit 11 as compared with the conventional transmission device 100 shown in FIG. The difference is that a frame reconstruction unit 18 and a block interleave processing unit 19 are provided between the error correction coding processing of the concatenated code composed of the BCH coding unit 12 and the LDPC coding unit 14.

  In addition, the receiving apparatus 20 according to the present embodiment has a block deinterleaving process between error correction decoding processes of a concatenated code including the LDPC decoding unit 23 and the BCH decoding unit 25, as compared with the conventional receiving apparatus 200 shown in FIG. And a frame restoration unit 28, and further includes a TS separation unit 29 that separates TS by a process different from that of the TS separation unit 26.

  Since the other functional blocks shown in FIG. 1 operate in the same manner as the functional block shown in FIG. 8, the above differences will be mainly described in detail.

(Transmitter)
With reference to FIG. 2 based on FIG. 1, processing of each functional block in the transmission device 10 of the present embodiment will be described. FIG. 2 is a diagram illustrating processing of each functional block in the transmission device 10 of the present embodiment. First, the TS multiplexing unit 17 in the transmission apparatus 10 of the present embodiment receives TS signals of one or more transport streams (TS) to be transmitted (for example, a TS packet of 187 bytes, illustrated as “TSP” in FIG. 2). A transmission frame having a parity area of concatenated codes of outer code and inner code is constructed by adding stuff bits that are multiplexed with a predetermined number and adding stuff bits, which are signals that make it possible to identify the attribute of the multiplexed TS signal. Generate. The transmission frame of this example is composed of data obtained by multiplexing a predetermined number of TS signals and adding 182 stuff bits to the head, BCH code parity, and LDPC code parity. FIG. 3 is a diagram illustrating the configuration of the transmission frame, and FIG. 4 shows a detailed example thereof. Note that a maximum transmission speed of 213 Mbps can be realized with one existing coaxial cable as an interface for inputting a signal to the modulator constituting the modulation unit 16, and the TS signal is multiplexed as shown in FIG. By continuously transmitting in the transmission frame format, it is possible to transmit a larger capacity than in the case of the prior art.

  The BCH encoding unit 12 performs BCH encoding processing on data consisting of TS signals multiplexed with 182 stuff bits added at the head, and adds BCH parity to the transmission frame. For example, as shown in FIG. 4, the BCH encoder 12 shortens BCH (65535, 65343, t = 12) based on ARIB STD-B44 with a bit length corresponding to the coding rate of the LDPC encoder 14. Encoding is performed and 192 parity bits are added. Note that t indicates a correction capability of 12 bits.

  The 182 stuff bits are added to enable the receiving side to identify the TS to which the multiplexed TS signal belongs. In this example, the stuff bit is a TS delimiter in the transmission frame. A numerical value indicating the position of the TS signal is repeated 36 times in 5-bit units. That is, it is possible to identify the position of the TS signal that becomes a TS break in one transmission frame by a 5-bit bit pattern, and this 5-bit bit pattern is repeated 36 times in one frame with the same contents. Yes. If the stuff bit is configured by repeating the numerical value indicating the delimiter of the TS signal 36 times in units of 5 bits so that the last 2 bits of the stuff bit (the 181st bit and the 182nd bit) are '0', The head of the TS signal multiplexed in the transmission frame can be clearly identified. Alternatively, if the stuff bit is configured by repeating the numerical value indicating the delimiter of the TS signal 36 times in units of 5 bits so that the first 2 bits (first bit and second bit) of the stuff bit are '0', It becomes possible to clearly identify the end of the TS signal multiplexed in the continuous preceding transmission frame. Note that the number of bits, which is a numerical value indicating the delimiter of the TS signal, can be arbitrarily determined as long as the receiving side can identify which TS the multiplexed TS signal belongs to, but at least three times. The above is predetermined so that it can be repeatedly described in the stuff bit. In other words, the number of bits of the stuff bit is also determined in advance as the number of bits that can be described repeatedly at least three times or more as the number of bits indicating the delimiter of the TS signal.

  By the way, as will be described later, the frame reconstructing unit 18 replaces the leading bit of the 182 stuff bits with a known random pattern on the receiving side. The intention is to configure the stuff bit so that the numerical value indicating the delimiter of the TS signal is repeated 36 times in units of 5 bits so that the first 2 bits (1st bit and 2nd bit) of the stuff bit become “0”. It is desirable.

The frame reconstruction unit 18 is a functional unit that performs preprocessing of the block interleave processing unit 19 at the subsequent stage. First, as shown in FIG. 5, the number of frames N _i that arbitrarily determines “frames consisting of data + BCH parity”. To form an interleave block, and replace the first bit for N frames (that is, the first bit × N from the reading direction) with a known random pattern (random pattern that can be restored on the receiving side) between transmission and reception, Reconstruct the frame of the interleave block. The value of N is preferably larger in number of frames _{N i,} but in the following description, and _{N = 32 (≦ N i)} . By reconstructing the frame in this way, it becomes easy to detect the head of the interleave block on the receiving side. As the random pattern known on the receiving side, any pseudorandom number (PN) signal that can be identified between transmission and reception can be used.

Block interleaving section 19, after performing block interleaving pretreatment by frame reconstruction unit 18 reads the interleaved blocks are arranged in parallel with the frame number N _i in order from the head to perform block interleaving, BCH code block N _bch The number of interleave frames corresponding to the number of bits is formed. That is, the bit sequence of the frame obtained by performing the block interleaving preprocessing is read out every N _bch bits and output to the energy spread processing unit 13. The processing method itself of the block interleaving process is the same as the bit interleaving process of the bit interleaving processing unit 15, but it should be noted that the operation / effect differs because it is provided between the concatenated codes.

In the block interleaving preprocessing, the number of frames N _i after BCH coding to be written to form an interleave block can be changed according to the period during which a burst error occurs. In this example for the error correction capability of the BCH code is 12 bits, so to accommodate the burst error to the 12 bits to determine the frame number N _i of the interleaved block.

For example, when an LDPC code has a coding rate of 109/120, if one frame of an LDPC code can cause an error due to a burst error, 40766 bits for one frame of the BCH code are dispersed by block interleaving, and one frame Within 12 bits or less. In that case,
40766 bits ÷ 12 bits = 3398 (rounded up)
Next, by constituting an interleaved block of the number of frames N _i or 3398 frames, it is possible to correct the burst error by the BCH code. Here, since 12 bits correctable by the BCH code also have a role of removing an error floor of the LDPC code, it is actually preferable to configure an interleave block with more than 3398 frames.

  Subsequently, the energy diffusion processing unit 13 performs energy diffusion processing based on ARIB STD-B44 on the bit sequence of one interleaved frame formed by block interleaving processing. In the transmission system of the present embodiment, the provision of the energy diffusion processing unit 13 between the concatenated codes is not the subject, and it is preferable to disperse the power related to the transmission of the digital signal as much as possible. Since the conversion rate is related to the modulation, an energy diffusion process is provided before the LDPC encoding process.

  Subsequently, the LDPC encoding unit 14 performs an LDPC encoding process based on ARIB STD-B44 on the bit sequence after the energy spreading process, adds an LDPC code parity to the transmission frame, and has a code length of 48880 bits. Generate a signal.

  Thereafter, the bit interleaving processing unit 15 performs bit interleaving processing conforming to ARIB STD-B44 on a signal having a code length of 44880 bits according to a predetermined modulation scheme (8PSK, 16APSK, 32APSK, etc.) and an LDPC coding rate. Apply.

  The modulation unit 16 divides and maps every 187 symbols according to the modulation scheme (π / 2 shift BPSK, QPSK, 8PSK, 16APSK, 32APSK, etc.), inserts a burst signal as a phase reference, and starts the modulation symbol A modulation symbol frame is generated by adding a symbol header which is a signal indicating, and a modulated wave is generated and transmitted in accordance with a modulation method (π / 2 shift BPSK, QPSK, 8PSK, 16APSK, 32APSK, etc.).

  As described above, the transmission apparatus 10 according to the present embodiment adds block interleave processing in such a manner that the reception side can grasp the head position of an interleave block between error correction processing of a concatenated code composed of an LDPC code and a BCH code. It has become a form.

(Receiver)
On the other hand, in the receiving apparatus 200, in accordance with ARIB STD-B44, the demodulating unit 21 receives and demodulates the modulated wave transmitted from the transmitting apparatus 10 via the transmission path, and a bit deinterleave processing unit 22, an LDPC decoding unit. 23 and the energy despreading processing unit 24 perform the reverse processing of the bit interleaving processing unit 15, the LDPC encoding unit 14, and the energy spreading processing unit 13 of the transmission apparatus 10, respectively, thereby obtaining an interleaved frame. Since each processing method of the demodulating unit 21, the bit deinterleave processing unit 22, the LDPC decoding unit 23, and the energy despreading processing unit 24 is the same as that of the prior art such as ARIB STD-B44, detailed description thereof is omitted. To do.

Next, operations of the block deinterleave processing unit 27 and the frame restoration unit 28 will be described with reference to FIG. First, the block deinterleave processing unit 27 performs matching processing with a known random pattern of N bits (32 bits in this example) on the interleaved frame obtained by the energy despreading processing unit 24, and performs the highest order of the interleave block on the transmission side. The interleaved frame located at is detected. Then, the block deinterleave processing unit 27 configures (temporarily restores) the deinterleave block so as to correspond to the transmission-side interleave block by block deinterleave processing that is reverse processing of the block interleave processing unit 19. That is, the bit sequence of the interleaved frame obtained by the energy despreading processing unit 24 is written out by N _bch bits through the matching process. As a result, the “frame consisting of data + BCH parity” constituting the deinterleave block is temporarily restored.

  Subsequently, the frame restoration unit 28 is a functional unit that performs post-processing of the block deinterleaving processing unit 27 in the previous stage. Among the temporarily restored “frame consisting of data + BCH parity”, N (= 32) bits of known The first bit of N frames in which the random pattern is described (that is, the first bit × N from the writing direction) is within the range of the number of stuff bits (182 bits) of each frame (at least 3 from the first bit). Replace the first '0' or '1' value of the bit sequence that is repeatedly written in 5-bit units (from the bit to the 180th bit) with the larger value, "Frame consisting of data + BCH parity" is completely restored.

  More specifically, the frame restoration unit 28 detects, from the regularity, a bit sequence that is repeatedly described in 5-bit units within the range of the number of stuff bits (182 bits) in one frame. '0' or '1' at the beginning of the bit sequence (for example, the 6th, 11th, 16th,..., 5k + 1,..., 176th bit (k is an integer from 1 to 35)) The number of values is totaled, and the leading bit of the one frame is replaced with the larger number of “0” or “1”. As a result, the “frame consisting of data + BCH parity” on the transmission side can be completely restored. Alternatively, the bit pattern in the stuff bit in this frame (in this example, a 5-bit bit pattern that is described repeatedly in a plurality of times between the 3rd bit and the 180th bit from the beginning) The first bit of one frame may be replaced.

  The BCH decoding unit 25 decodes the frame restored by the frame restoration unit 28 by an algebraic method using syndrome decoding.

  The TS separation unit 29 extracts each TS signal from the data obtained by decoding by the BCH decoding unit 25, restores the transmitted TS, separates it, and outputs it.

  A comprehensive description of the effects of the present invention is as shown in FIG. FIGS. 7A, 7B, and 7C show the effects of the transmission system including the transmission apparatus 10 and the reception apparatus 20 according to the embodiment of the present invention at the normal time, the burst error moment, and before and after the burst error, respectively. FIG. In FIG. 7, the transmission apparatus 10 includes a BCH encoding unit 12, a block interleave processing unit 19, and an LDPC encoding unit 14, and the receiving apparatus 20 includes an LDPC decoding unit 23 and a block deinterleaving process. A state in which the unit 27 and the BCH decoding unit 25 are provided is shown.

  As shown in FIG. 7A, in a normal time when there is no attenuation due to rain or the like, a modulated wave is transmitted from the transmission device 10 under the influence of so-called Gaussian noise on the transmission line, and the reception device 20 performs block deinterleaving. A random error corresponding to an error floor of LDPC decoding can be diffused by the processing unit 27, and the BCH decoding unit 25 operates as an error floor countermeasure of LDPC decoding.

  Then, as shown in FIG. 7B, at the moment of loss of a signal that occurs due to the state becoming indeterminate when the radiation pattern is changed, the transmission device 10 is affected by a so-called burst error on the transmission path. Even if the LDPC decoding unit 23 becomes unable to decode due to a burst error that exceeds the error correction capability and the influence of Gaussian noise is masked, the block deinterleave processing unit 27 performs a burst. The error becomes a random error, and the BCH decoding unit 25 can decode the burst error of the LDPC decoding.

  Then, as shown in FIG. 7C, before and after the burst error, the modulated wave from the transmission device 10 is transmitted under the influence of so-called Gaussian noise on the transmission line. In the reception device 20, the LDPC decoding unit 23 The block deinterleave processing unit 27 spreads the error floor and burst error of the LDPC decoding by the block deinterleave processing unit 27, and the BCH decoding unit 25 operates as a countermeasure against the error floor and the spread burst error.

  As described above, the block interleaving process is added in such a manner that the reception side can grasp the head position of the interleave block between the error correction processes of the concatenated code composed of the LDPC code and the BCH code on the transmission apparatus 10 side. The receiving device 20 can correct burst errors that exceed the error correction capability of the LDPC code. In particular, since a specific bit is replaced with a known random pattern in the reading direction from the head of the block interleave processing frame on the transmission device 10 side, the reception device 20 can reliably determine the start position of the interleave frame. . As a result, transmission without reducing the error correction coding rate while reducing the influence of burst errors, that is, transmission while maintaining the originally desired transmission capacity becomes possible.

  Although the above embodiment has been described based on a specific example, various applications are possible. For example, in the example of the above embodiment, the description has been made in accordance with the error correction method of ARIB STD-B44, but the number of data written in the interleave block is an integral multiple of the data used for the subsequent processing, so Does not affect the processing. Therefore, the present invention is applicable to a transmission system using a concatenated code of an arbitrary LDPC code and a block code composed of an arbitrary BCH code or Reed-Solomon (RS) code. In the example of the above-described embodiment, an example of block interleaving processing that configures an interleave block of a predetermined size has been described. However, block interleaving processing of an arbitrary size can be configured.

  According to the present invention, a burst error exceeding the error correction capability of an LDPC code can be corrected. Therefore, the present invention is useful for a transmission system using a concatenated code having an LDPC code as an inner code.

DESCRIPTION OF SYMBOLS 10 Transmitter 11 TS multiplexer 12 BCH encoder 13 Energy spread processor 14 LDPC encoder 15 Bit interleave processor 16 Modulator 17 TS multiplexer 18 Frame reconstructor 19 Block interleave processor 20 Receiver 21 Demodulation unit 22 Bit deinterleave processing unit 23 LDPC decoding unit 24 Energy despreading processing unit 25 BCH decoding unit 26 TS demultiplexing unit 27 Block deinterleaving processing unit 28 Frame reconstruction unit 29 TS demultiplexing unit 100 Transmitting device 200 Receiving device

Claims (7)

A digital signal transmission device,
The transport stream TS signal to be transmitted is multiplexed with a predetermined number, and stuff bits that make it possible to identify the attribute of the multiplexed TS signal are added to form data, and the concatenated code by the outer code and inner code TS multiplexing means for generating a transmission frame provided with a parity area;
First error correction encoding means for applying a predetermined block encoding process to the data to give an outer code parity to the transmission frame;
Frames consisting of data with the outer code parity added are arranged in parallel with an arbitrarily determined number of frames to form an interleave block, and the first bit of each frame for a predetermined number of frames in order from the first frame in the interleave block is transmitted and received A frame reconstruction means for reconstructing a frame of an interleave block by replacing with a known random pattern;
Block interleaving processing means for performing block interleaving processing on the interleaved block reconstructed by the frame reconstruction means;
Second error correction encoding means for applying an LDPC encoding process to the bit sequence obtained through the block interleaving process to give an inner code parity to the transmission frame;
Modulation means for generating a modulated wave by forming a symbol according to a predetermined modulation method based on a bit sequence of a transmission frame obtained through the LDPC encoding process;
A transmission device comprising:   The transmission apparatus according to claim 1, wherein the number of frames of the interleave block is determined according to an error correction capability of the predetermined block encoding process.   The transmission apparatus according to claim 1 or 2, wherein the stuff bits include a bit sequence in which a numerical value indicating a division of the multiplexed TS signal with respect to a transport stream is repeated a plurality of times in a predetermined bit unit. .   The stuff bits are configured by repeating a numerical value indicating a delimiter of the multiplexed TS signal a predetermined number of times so that the predetermined number of bits at the beginning or the predetermined number of bits at the end is 0. The transmission device according to claim 3, wherein: A digital signal receiving device,
Demodulating means for demodulating a modulated wave generated by the transmission device according to any one of claims 1 to 4 according to the predetermined modulation method;
First error correction decoding means for performing a decoding process corresponding to the LDPC encoding process on the bit sequence obtained through the demodulation process by the demodulation means;
Block deinterleave processing means for performing block deinterleave processing on the bit sequence obtained through the decoding processing, and temporarily restoring a frame of the deinterleave block corresponding to the interleave block;
By replacing the temporarily restored frame with the first bit in which a known random pattern is described between the transmission and reception based on the bit sequence included in the range of the stuff bit in the frame, A frame restoration means for restoring the frame of the interleave block;
Second error correction decoding means for performing a decoding process corresponding to the predetermined block encoding process on the bit sequence of the frame restored by the frame restoration means;
TS separation means for extracting each TS signal from the data obtained by the decoding process and restoring and separating the transport stream that has been transmitted;
A receiving apparatus comprising:   The block deinterleave processing means detects an interleave frame located at the highest level of the interleave block on the transmission side from the bit sequence obtained through the decoding process using a known random pattern between the transmission and reception, and the block deinterleave 6. The receiving apparatus according to claim 5, further comprising means for temporarily restoring a frame of the deinterleave block by processing. The demodulating means includes means for demodulating the modulated wave generated by the transmission device according to claim 3 or 4 according to the predetermined modulation method,
The frame restoration means repeatedly describes the first bit in which a known random pattern is described between the transmission and reception of the temporarily restored frame in the predetermined bit unit within the range of the stuff bit in the frame. 7. The reception according to claim 6, further comprising means for reconstructing a frame of the deinterleaved block by grasping a bit pattern of a numerical value that has been changed and replacing the bit pattern so as to maintain the continuity of the bit pattern. apparatus.