JP6467877B2 - Transmission frame conversion circuit - Google Patents

Description

  The present invention relates to a transmission frame conversion circuit applied to a transmission system such as an optical loop transmission system.

  The optical loop transmission system is a transmission system using an optical module, and is connected in a loop by an optical fiber. When connecting transmission media (transmission frames) with different communication protocols in an optical loop transmission system, it is necessary to convert the transmission frames, for example, convert HDLC (High-Level Data Link Control) frames into Ethernet (registered trademark) frames. .

  Frame conversion and protocol conversion of frames transmitted between different network systems are performed by software processing (for example, Patent Documents 1 to 3). In some cases, protocol conversion is performed by hardware processing in order to cope with a network system that increases in speed (for example, Patent Documents 4 to 6).

  In addition, fragment processing may be used to connect devices that support or do not support Ethernet jumbo frames in the same network (Patent Document 7).

JP-A-9-321821 JP-A-11-275170 Japanese Patent Laid-Open No. 7-235949 Japanese Patent Laid-Open No. 11-261622 JP-A-1-290346 JP-A-4-243347 JP2012-120079A

  In an optical loop transmission system, a loop master performs a loop termination process. Data transmitted from a certain node is looped around or terminated (discarded) by the loop master. Each node propagates transmission data to a subsequent node simultaneously with receiving data transmitted by a certain node. The propagation delay at this time is generally a very short time (nanosecond unit) only by the transmission / reception time of the optical module.

  When connecting different transmission media, it is necessary to convert the transmission frame. In the above-described case, since the protocol is processed by the HDLC protocol, processing for encapsulating the HDLC frame with the Ethernet frame is performed in the transmission frame conversion processing.

  The transmission speed of a network using the HDLC protocol is generally about 10 Mbps at maximum. On the other hand, the transmission speed of the network using the Ethernet protocol is as high as 100 Mbps and 1 Gbps. When the frame is converted from the HDLC frame to the Ethernet frame, the underrun problem must be taken into consideration in order to convert from a low transmission rate to a high transmission rate. In order not to cause an underrun, it is necessary to receive all HDLC frames with a low transmission rate and then convert them into Ethernet frames with a high transmission rate and output them.

  As mentioned above, when the transmission speed between different transmission media is significantly different, the transmission frame conversion time depends on the slower transmission speed, so the propagation delay of the transmission frame conversion section reduces the transmission performance of the entire network. There is a problem.

  The present invention has been made in view of the above circumstances, and an object thereof is to reduce the propagation delay between different transmission media.

  Therefore, the present invention provides a transmission frame conversion circuit that converts a received frame into a transmission frame having a communication protocol different from that of the frame, and receives the reception frame for each predetermined size and communicates the frame of the size with the reception frame. A reception frame control means for adding to a transmission frame with a different protocol and holding it in a frame conversion buffer, and a transmission frame to which a frame of the size held in the buffer is added based on a transmission request for the transmission frame from the frame conversion buffer Transmission frame control means for transmitting.

  According to the present invention described above, the propagation delay between different transmission media can be shortened.

The block diagram of the transmission frame conversion circuit in embodiment of this invention. The block diagram which showed an example of the optical loop transmission system in the embodiment. (A) Configuration example of frame conversion buffer in the embodiment, (b) Configuration example of Ethernet frame in the embodiment. The time chart explaining the operation example of the node in the same embodiment, and a transmission frame conversion circuit. The time chart explaining the operation example of the node in the conventional transmission system, and a transmission frame conversion circuit.

  Embodiments of the present invention will be described below with reference to the drawings.

  The transmission frame conversion circuit 1 illustrated in FIG. 1 is a circuit that converts an HDLC frame into an Ethernet frame. On the other hand, the transmission frame conversion circuit 2 is a circuit that converts an Ethernet frame into an HDLC frame.

  The transmission frame conversion circuits 1 and 2 are provided in an optical loop transmission system having nodes that employ different types of communication protocols illustrated in FIG. This system is based on the HDLC protocol, and the transmission medium different from this notification protocol is Ethernet. In other words, it is assumed that nodes connected by Ethernet are also processed for communication using the HDLC protocol.

  The transmission frame conversion circuit 1 includes a frame conversion buffer 10, a reception controller 11, a transmission controller 12, and a CPU 13 in an LSI in which a memory such as an FPGA and a hard logic device are integrated.

  The reception controller 11 holds the HDLC frame F1 in the HDLC frame area 101 of the frame conversion buffer 10. The HDLC frame area 101 is added with an Ethernet frame 102, encapsulated in the Ethernet frame area 100, and held in the frame conversion buffer 10.

  The Ethernet frame area 100 of the frame conversion buffer 10 is composed of hardware logic (registers). That is, the frame conversion buffer 10 is composed of a dual port memory and hardware logic (register).

  The transmission controller 12 causes the data in the Ethernet frame area 100 of the buffer 10 to be transmitted in response to a transmission command from the CPU 13 based on the transmission request for the transmission frame from the frame conversion buffer 10.

  Similarly to the transmission frame conversion circuit 1, the transmission frame conversion circuit 2 is also an LSI in which a memory and a hard logic device are integrated, and a frame conversion buffer 20, a reception controller 21, a transmission controller 22, and a CPU 23 are mounted thereon. The frame conversion buffer 20 is also composed of a dual port memory and hardware logic (register).

  The frame conversion buffer 20 can input data of the Ethernet frame F2 from the reception controller 21 while reading data of the HDLC frame F1 from the transmission controller 22. The frame conversion buffer 20 is composed of a dual port memory in the same manner as the frame conversion buffer 10.

  The reception controller 21 causes the frame conversion buffer 20 to hold the received data of the Ethernet frame F2. The Ethernet frame area 200 of the buffer 20 encapsulates an HDLC frame area 201 to which an Ethernet frame 202 is added.

  The transmission controller 22 causes the data in the HDLC frame area 201 included in the Ethernet frame area 200 of the frame conversion buffer 20 to be transmitted in response to a transmission command from the CPU 13.

  An example of the operation of the transmission system of this embodiment will be described with reference to FIG.

  When the reception controller 11 of the transmission frame conversion circuit 1 receives the HDLC frame F1 propagated through the nodes # 0, # 2, and # 3, the data is held in the HDLC frame area 101 of the frame conversion buffer 10. The Ethernet frame area 100 adds the MAC frame and IP frame of the Ethernet frame 102 and encapsulates the data of the HDLC frame F1 in the HDLC frame area 101.

  The conversion circuit 1 uses an IP frame fragment function (dividing function) in order to shorten the propagation delay between transmission media (between nodes # 3 and # 6). Detailed configurations of the frame conversion buffer 10 and the Ethernet frame are illustrated in FIGS. 3A and 3B, respectively.

  Specifically, every time the reception controller 11 receives HDLC frame F1 data of a certain size (128 bytes in the example of FIG. 3) in accordance with a reception processing command from the CPU 13, this data is transferred to the Ethernet frame 102 (MAC frame, IP frame). Is encapsulated and held in the frame conversion buffer 10. The frame conversion buffer 10 outputs an Ethernet transmission request to the CPU 13 (S1 in FIG. 1). When receiving the Ethernet transmission request from the frame conversion buffer 10 (S1), the CPU 13 outputs a control signal for transmission processing to the transmission controller 12 (S2 in the figure). The transmission controller 12 transmits data of the Ethernet frame area 100 of the frame conversion buffer 10.

  As described above, the transmission frame conversion circuit 1 transmits the Ethernet frame F2 in which the HDLC frame F1 is encapsulated while receiving the HDLC frame F1 for each fixed size. By this processing, it is possible to speed up the transmission frame conversion processing for frames exceeding a certain size.

  In particular, in the frame conversion buffer 10, a divided frame area is secured for each fixed size. As shown in FIGS. 3A and 3B, the frame conversion buffer 10 updates the IP frame flag and the fragment offset area in the Ethernet frame F2 every time it receives HDLC frame F1 data of a certain size.

  Thus, when a certain HDLC frame F1 data is received, a counter that counts up is provided, so that division, batch frame discrimination, and offset value updating can be performed. For example, if the received HDLC data is less than a certain size, the IP frame flag is set to batch (0). On the other hand, if the received HDLC data is larger than a certain size, the flag of the IP frame sets division (1). Then, the flag and fragment offset of the IP frame area to be updated every time HDLC frame F1 data of a certain size is received are also followed. When the final data of the HDLC frame F1 is received during the divided frame processing, the flag of the corresponding IP frame is set to 0 (flag indicating the end of division).

  Next, the reception controller 21 of the transmission frame conversion circuit 2 receives the Ethernet frame F2 data propagated through the nodes # 6, # 5, and # 4, and receives this data in the frame conversion buffer 20. As shown in FIG. 1, the transmission controller 22 outputs data in the HDLC frame area 201 obtained by removing the Ethernet frame 202 from the Ethernet frame area 200 as transmission data.

  As described above, frame conversion function processing can be speeded up by constructing the frame conversion buffers 10 and 20 with hardware.

  That is, in a conventional transmission system employing a plurality of types of communication protocols such as HDLC and Ethernet, a process of encapsulating the HDLC frame F1 by the Ethernet frame F2 and a process of extracting the HDLC frame F1 from the encapsulated frame are performed. . In the encapsulating process, since the Ethernet frame F2 is added to this frame after all the HDLC frames F1 are received, the propagation delay increases as in the time schedule shown in FIG.

  On the other hand, since the frame conversion buffer 10 of the transmission frame conversion circuit 1 can write from the reception controller 11 side and read from the transmission controller 12 side, the address from the transmission controller 12 is set to a certain boundary. By doing so, the transmission processing to the controller 12 by the CPU 13 is facilitated.

  In addition, the fragmentation function (division function) of the IP frame is used to divide the HDLC frame F1, convert it to an Ethernet frame F2, and output it. Therefore, the time schedule shown in FIGS. As is clear from the comparison, the propagation delay can be shortened. In particular, the propagation delay can be shortened as the division size is reduced.

  Note that the present invention is not limited to the above-described embodiments, and can be appropriately modified by a person skilled in the art, and these modified embodiments also belong to the technical scope of the invention. For example, a transmission frame conversion circuit corresponding to a transmission system having a node adopting a plurality of communication protocols other than HDLC and Ethernet can be cited, and this aspect also belongs to the technical scope of the present invention.

1, 2, ... Transmission frame conversion circuits 10, 20 ... Frame conversion buffers 11, 21 ... Reception controller (reception frame control means)
12, 22 ... Transmission controller (transmission frame control means)
13, 23 ... CPU
100, 200 ... Ethernet frame area 101, 201 ... HDLC frame area F1 ... HDLC frame F2, 102, 202 ... Ethernet frame # 0, # 2- # 6 ... node

Claims (3)

The received frame, the communication protocol and the frame are different, a transmission frame conversion circuit for converting the transmission frame consisting of an MAC header and the IP header,
A reception frame control means for holding the frame translation buffer and encapsulated by a frame the transmit frame of the size to receive the received frame for each fixed size,
A transmission frame conversion circuit comprising transmission frame control means for transmitting the encapsulated frame of the size from the buffer based on a transmission frame transmission request from the frame conversion buffer. The transmission frame conversion circuit according to claim 1, wherein the transmission frame has a fragment offset of the encapsulated frame. The reception frame control unit, when the received frame is less than a predetermined size, according to claim 1 or 2, characterized in that to hold the received frame to frame conversion buffer and encapsulated by the transmission frame Transmission frame conversion circuit.

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