JP6473405B2 - 配線構造体の製造方法 - Google Patents
配線構造体の製造方法 Download PDFInfo
- Publication number
- JP6473405B2 JP6473405B2 JP2015197522A JP2015197522A JP6473405B2 JP 6473405 B2 JP6473405 B2 JP 6473405B2 JP 2015197522 A JP2015197522 A JP 2015197522A JP 2015197522 A JP2015197522 A JP 2015197522A JP 6473405 B2 JP6473405 B2 JP 6473405B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring pattern
- boron
- along
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/18—Pretreatment of the material to be coated
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
- H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
- H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
- H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/657—Shapes or dispositions of interconnections on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/66—Conductive materials thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/69—Insulating materials thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/69—Insulating materials thereof
- H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
Landscapes
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemically Coating (AREA)
- Electrodes Of Semiconductors (AREA)
Description
Claims (4)
- 配線パターンが設けられた配線構造体の製造方法であって、
少なくとも前記配線パターンの形成予定領域に沿ってシリコン基板の表面に絶縁層を形成する第1ステップと、
前記形成予定領域に沿って前記絶縁層上にボロン層を形成する第2ステップと、
めっきにより前記ボロン層上に選択的且つ等方的に形成可能な金属層を、めっきにより前記ボロン層上に形成する第3ステップと、を含む、配線構造体の製造方法。 - 前記第2ステップでは、気相成長法により前記絶縁層上に前記ボロン層を等方的に形成し、その後に前記形成予定領域に沿って前記ボロン層をパターニングする、請求項1記載の配線構造体の製造方法。
- 配線パターンが設けられた配線構造体の製造方法であって、
少なくとも前記配線パターンの形成予定領域に沿ってシリコン基板の表面に絶縁層を形成する第1ステップと、
前記形成予定領域に沿って前記絶縁層上にボロン層を形成する第2ステップと、
めっきにより前記ボロン層上に金属層を形成する第3ステップと、を含み、
前記第3ステップでは、めっきにより前記ボロン層上にニッケル層を形成する、配線構造体の製造方法。 - 前記第2ステップでは、気相成長法により前記絶縁層上に前記ボロン層を等方的に形成し、その後に前記形成予定領域に沿って前記ボロン層をパターニングする、請求項3記載の配線構造体の製造方法。
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015197522A JP6473405B2 (ja) | 2015-10-05 | 2015-10-05 | 配線構造体の製造方法 |
| EP16853347.9A EP3361494B1 (en) | 2015-10-05 | 2016-09-01 | Method for producing wiring structure |
| US15/765,528 US11094547B2 (en) | 2015-10-05 | 2016-09-01 | Method for producing wiring structure |
| PCT/JP2016/075680 WO2017061193A1 (ja) | 2015-10-05 | 2016-09-01 | 配線構造体の製造方法 |
| CN201680058496.5A CN108140565B (zh) | 2015-10-05 | 2016-09-01 | 配线构造体的制造方法 |
| TW105129031A TWI715625B (zh) | 2015-10-05 | 2016-09-08 | 配線構造體之製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015197522A JP6473405B2 (ja) | 2015-10-05 | 2015-10-05 | 配線構造体の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2017073417A JP2017073417A (ja) | 2017-04-13 |
| JP6473405B2 true JP6473405B2 (ja) | 2019-02-20 |
Family
ID=58487433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015197522A Active JP6473405B2 (ja) | 2015-10-05 | 2015-10-05 | 配線構造体の製造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US11094547B2 (ja) |
| EP (1) | EP3361494B1 (ja) |
| JP (1) | JP6473405B2 (ja) |
| CN (1) | CN108140565B (ja) |
| TW (1) | TWI715625B (ja) |
| WO (1) | WO2017061193A1 (ja) |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5116589A (en) * | 1990-06-18 | 1992-05-26 | The United States Of America As Represented By The United States Department Of Energy | High density hexagonal boron nitride prepared by hot isostatic pressing in refractory metal containers |
| US5842387A (en) * | 1994-11-07 | 1998-12-01 | Marcus; Robert B. | Knife blades having ultra-sharp cutting edges and methods of fabrication |
| US6331483B1 (en) | 1998-12-18 | 2001-12-18 | Tokyo Electron Limited | Method of film-forming of tungsten |
| TW411569B (en) * | 1999-01-05 | 2000-11-11 | Ind Tech Res Inst | Method of using the electroless plating technology to fabricate the copper/gold connections in integrated circuits |
| JP3327244B2 (ja) * | 1999-03-12 | 2002-09-24 | 日本電気株式会社 | 半導体装置 |
| US6693356B2 (en) * | 2002-03-27 | 2004-02-17 | Texas Instruments Incorporated | Copper transition layer for improving copper interconnection reliability |
| US6933237B2 (en) * | 2002-06-21 | 2005-08-23 | Hewlett-Packard Development Company, L.P. | Substrate etch method and device |
| DE10308855A1 (de) | 2003-02-27 | 2004-09-16 | Infineon Technologies Ag | Elektronisches Bauteil und Halbleiterwafer, sowie Verfahren zur Herstellung derselben |
| US7144803B2 (en) | 2003-04-17 | 2006-12-05 | Semiconductor Research Corporation | Methods of forming boron carbo-nitride layers for integrated circuit devices |
| WO2006117884A1 (ja) * | 2005-04-26 | 2006-11-09 | Mitsui Mining & Smelting Co., Ltd. | Al-Ni-B合金配線材料及びそれを用いた素子構造 |
| TW201101476A (en) * | 2005-06-02 | 2011-01-01 | Sony Corp | Semiconductor image sensor module and method of manufacturing the same |
| JP2007113092A (ja) * | 2005-10-21 | 2007-05-10 | Seiko Epson Corp | めっき方法 |
| JP2008115448A (ja) * | 2006-11-07 | 2008-05-22 | Seiko Epson Corp | 無電解めっき方法 |
| KR20080061978A (ko) * | 2006-12-28 | 2008-07-03 | 주식회사 하이닉스반도체 | 반도체 소자의 배선 형성방법 |
| US7977791B2 (en) * | 2007-07-09 | 2011-07-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective formation of boron-containing metal cap pre-layer |
| US9653353B2 (en) * | 2009-08-04 | 2017-05-16 | Novellus Systems, Inc. | Tungsten feature fill |
| TWI509695B (zh) * | 2010-06-10 | 2015-11-21 | Asm國際股份有限公司 | 使膜選擇性沈積於基板上的方法 |
| JP2012077342A (ja) * | 2010-09-30 | 2012-04-19 | Yamato Denki Kogyo Kk | 金属パターンの形成方法 |
| JP2012119381A (ja) | 2010-11-29 | 2012-06-21 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
| US8461043B2 (en) * | 2011-04-11 | 2013-06-11 | Micron Technology, Inc. | Barrier layer for integrated circuit contacts |
| JP5559120B2 (ja) * | 2011-09-22 | 2014-07-23 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| CA3159109C (en) * | 2012-04-19 | 2024-10-22 | Carnegie Mellon University | METAL/SEMICONDUCTOR/METALLIC HETEROJUNCTION DIODE |
-
2015
- 2015-10-05 JP JP2015197522A patent/JP6473405B2/ja active Active
-
2016
- 2016-09-01 CN CN201680058496.5A patent/CN108140565B/zh active Active
- 2016-09-01 EP EP16853347.9A patent/EP3361494B1/en active Active
- 2016-09-01 WO PCT/JP2016/075680 patent/WO2017061193A1/ja not_active Ceased
- 2016-09-01 US US15/765,528 patent/US11094547B2/en active Active
- 2016-09-08 TW TW105129031A patent/TWI715625B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017073417A (ja) | 2017-04-13 |
| CN108140565B (zh) | 2022-08-05 |
| TWI715625B (zh) | 2021-01-11 |
| US20190080912A1 (en) | 2019-03-14 |
| CN108140565A (zh) | 2018-06-08 |
| TW201724434A (zh) | 2017-07-01 |
| WO2017061193A1 (ja) | 2017-04-13 |
| US11094547B2 (en) | 2021-08-17 |
| EP3361494A1 (en) | 2018-08-15 |
| EP3361494B1 (en) | 2020-06-17 |
| EP3361494A4 (en) | 2019-05-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9585254B2 (en) | Electronic device | |
| US9927499B2 (en) | Semiconductor device | |
| US10460989B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2009094409A (ja) | 半導体パッケージおよびその製造方法 | |
| US9899360B2 (en) | Semiconductor device | |
| JP6473405B2 (ja) | 配線構造体の製造方法 | |
| JP6450296B2 (ja) | 配線構造体、及び配線構造体の製造方法 | |
| US10163775B2 (en) | Electronic device | |
| JP2016157901A (ja) | 電子装置 | |
| JP2019140343A (ja) | 半導体装置および半導体装置の製造方法 | |
| JP2009267098A (ja) | 半導体装置及びその製造方法 | |
| JP2016139729A (ja) | 電子装置および電子装置の製造方法 | |
| JP2016100555A (ja) | 電子装置 | |
| JP2016151427A (ja) | 電子装置 | |
| JP2016100553A (ja) | 電子装置 | |
| JP2019197911A (ja) | 電子装置 | |
| JP2017135294A (ja) | 半導体装置用基板、半導体装置用基板の製造方法、半導体装置、半導体装置の製造方法 | |
| JP2017135294A6 (ja) | 半導体装置用基板、半導体装置用基板の製造方法、半導体装置、半導体装置の製造方法 | |
| JP2017017268A (ja) | 半導体装置およびその製造方法 | |
| JP2012209441A (ja) | 高密度配線構造及びその製造方法 | |
| JP2016127048A (ja) | 電子装置 | |
| JP2017050380A (ja) | 半導体装置およびその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180529 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181023 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181225 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190122 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190125 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 6473405 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |