JP6479697B2 - Video server device and memory read method - Google Patents

Description

  Embodiments described herein relate generally to a video server apparatus and a memory read method that perform retry read on a NAND flash memory.

  In recent years, the reliability of NAND flash memories has been demanded along with miniaturization and multi-leveling. For this reason, processing such as ECC (Error Check and Correction), randomization, and retry reading is necessary. In the retry read, when an uncorrectable data error due to ECC occurs, the data in which the error has occurred is read again. The number of retry reads tends to increase in order to improve reliability as the number of memory levels increases. For example, recently, there are products that require 10 retry leads.

  Increasing the number of retry reads causes the following problems.

  In a solid-state drive (SSD), an SD card, etc., the retry read processing time becomes longer as the number of retry reads (total number of times) increases. As a result, the total processing time for reads (normal read and retry read) becomes longer, and the waiting time for the user becomes longer.

  On the other hand, a video server device for a broadcasting station requires real-time performance for video playback processing (read processing). For this reason, an increase in read processing time due to an increase in the number of retry reads may lead to a broadcast accident.

  In the video server device, recording / playback processing is performed in synchronization with the video frame. In one video frame, a plurality of playback channels are controlled, and reading (one normal read and one retry read) is performed in each playback channel. For example, consider a case where 20 playback channels are controlled in one video frame of 33 ms, and one normal read and 10 retry reads are performed in each playback channel. At this time, if the processing time of one normal read and one retry read is 0.5 ms, the processing time of 20 playback channels is 0.5 × 11 × 20 = 110 ms. Therefore, when 10 retry reads are performed in each playback channel, 20 playback channels cannot be processed in one video frame (33 ms).

  In order to suppress the increase in the read processing time as described above, there are methods such as increasing the number of simultaneous processing parallel chips of the NAND flash memory, increasing the number of parallel processing parallel processing of ECC, and increasing the number of possible ECCs (correction ability). It is done.

  However, when the number of simultaneously processed parallel chips in the NAND flash memory increases, it is necessary to increase the number of chips mounted on the substrate, leading to an increase in cost and an increase in mounting area. In addition, the memory controller needs to increase the number of I / O (number of pins), and it is necessary to use a device corresponding to it. This increases the cost.

  On the other hand, when the number of parallel processing of ECC increases, the circuit scale of ECC increases. This increases the circuit scale of the entire memory controller. For this reason, if the memory controller is configured by an FPGA (Field Programmable Gate Array), the FPGA becomes a device with a large amount of logic, resulting in an increase in cost.

  In addition, when the ECC correction capability is increased, the ECC circuit scale is increased, resulting in a cost increase as described above.

  Thus, it is required to solve problems such as an increase in the read processing time and an associated increase in the cost of the apparatus.

Japanese Patent Application No. 2008-204114

  As described above, in the conventional video server apparatus, the problem of increase in the read time accompanying the increase in the number of retry reads cannot be solved without increasing the cost of the apparatus.

  Embodiments provide a video server device and a memory read method that suppress an increase in read time while suppressing an increase in cost of the device.

  The video server device according to the embodiment performs a first read on the memory and the first data in the memory, performs an ECC on the first data on which the first read is performed, and the ECC performs the first read on the first data. And a memory controller that performs a second read that is variable in number of times for the first data in the memory when an error occurs in one data.

The block diagram which shows the video server apparatus which concerns on 1st Embodiment. The figure which shows the memory controller and memory in the video server apparatus which concerns on 1st Embodiment in detail. The block diagram which shows the memory chip group of the memory in the video server apparatus which concerns on 1st Embodiment. The flowchart which shows the read in the video server apparatus which concerns on 1st Embodiment. 6 is a flowchart showing a retry read sequence in the video server device according to the first embodiment. The flowchart which shows the retry lead frequency | count determination sequence in the video server apparatus which concerns on 1st Embodiment. The figure which shows the 1st example of the image | video frame of the image processing by the video server apparatus which concerns on 1st Embodiment. The figure which shows the 2nd example of the video frame of the video processing by the video server apparatus which concerns on 1st Embodiment. The figure which shows the 3rd example of the video frame of the video processing by the video server apparatus which concerns on 1st Embodiment. The flowchart which shows the retry lead frequency determination sequence in the video server apparatus which concerns on 2nd Embodiment. The figure which shows the 4th example of the video frame of the video processing by the video server apparatus which concerns on 2nd Embodiment. The flowchart which shows the retry read frequency | count determination sequence in the video server apparatus which concerns on 3rd Embodiment. The figure which shows the 5th example of the video frame of the video processing by the video server apparatus which concerns on 3rd Embodiment. The flowchart which shows the retry read frequency | count determination sequence in the video server apparatus which concerns on 4th Embodiment. The flowchart which shows the retry lead frequency | count determination sequence in the video server apparatus which concerns on 5th Embodiment. The figure which shows the 1st example of the command and ready / busy state which are input into the memory controller in the video server apparatus which concerns on 5th Embodiment. The figure which shows the 2nd example of the command and ready / busy state which are input into the memory controller in the video server device concerning 5th Embodiment.

  The present embodiment will be described below with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals.

<First Embodiment>
The video server apparatus according to the first embodiment will be described below with reference to FIGS.

(Configuration in the first embodiment)
FIG. 1 is a block diagram showing a video server device 10 according to the first embodiment.

  As shown in FIG. 1, the video server device 10 includes a recording unit 100, a main controller 200, a playback unit 300, a memory controller 400, and a memory 500.

  The main controller 200 controls the entire apparatus. The recording unit 100 encodes a video signal input from a camera, a video deck or the like and a material file input from a content server or the like into video data, and executes a recording process. The memory controller 400 writes the video data from the recording unit 100 into the memory 500. Further, the memory controller 400 reads the video data stored in the memory 500. The memory 500 is a non-volatile memory, such as a NAND flash memory. The reproduction unit 300 decodes the video data read from the memory 500 into a video signal and outputs the video signal.

  FIG. 2 is a diagram showing in more detail the memory controller 400 and the memory 500 in the video server device 10 according to the first embodiment. FIG. 3 is a block diagram showing the memory chip group G of the memory 500 in the video server device 10 according to the first embodiment. Here, the case where the memory 500 is a NAND flash memory is shown.

  As shown in FIG. 2, the memory 500 includes a plurality of memory chip groups G1, G2,. Each memory chip group G has a plurality of memory chips 1 to M. The plurality of memory chips 1 to M are connected to the memory interface 440 in parallel. Therefore, in writing and reading, the plurality of memory chips 1 to M in each memory chip group G are accessed in parallel.

  As shown in FIG. 3, the memory chip group G in the NAND flash memory has a memory cell array composed of a plurality of memory blocks BLK0 to BLKi (hereinafter sometimes simply referred to as memory blocks BLK), and a page buffer 510. Each memory block BLK includes a plurality of memory cell transistors (not shown). The memory cell transistor of this example is a multi-value memory capable of recording multi-bit data.

  Data is erased in units of memory blocks BLK. That is, the data in the same memory block BLK is erased collectively. On the other hand, data writing and reading are performed for each set of a plurality of memory cell transistors, and this set of memory cell transistors is called a page PG.

  The page buffer 510 inputs / outputs data to / from the memory cell array and temporarily holds data. The data size that the page buffer 510 can hold is the same as the page size of each memory block BLK. At the time of data write or the like, the page buffer 510 performs data input / output processing for the memory cell array in units of one page corresponding to its own storage capacity.

  As shown in FIG. 2, the memory controller 400 controls writing to the memory 500 in accordance with a write command from the CPU 410. Further, the memory controller 400 controls reading (normal reading and retry reading) from the memory 500 in accordance with a read command from the CPU 410.

  The memory controller 400 is, for example, an FPGA, and includes an ECC circuit 430, a memory interface 440, and a retry read control circuit 450. The ECC circuit 430, the memory interface 440, and the retry read control circuit 450 are electrically connected to each other via an internal bus 460. The ECC circuit 430, the memory interface 440, and the retry read control circuit 450 are electrically connected to the CPU 410 and the buffer 420 outside the memory controller 400 via the internal bus 460. Note that the CPU 410 may be provided in the memory controller 400. Further, the CPU 410 and the buffer 420 are omitted in FIG.

  The CPU 410 controls the memory controller 400 in an integrated manner. The CPU 410 issues various commands and outputs them to the memory controller 400. For example, the CPU 410 issues a write command to instruct the memory interface 440 to write video data to the memory 500. Further, the CPU 410 issues a read command (normal read command and retry read command) to instruct the memory interface 440 to read the video data from the memory 500.

  The buffer 420 temporarily stores video data received from the outside until it is written to the memory 500, or temporarily stores video data read from the memory 500 until it is transmitted to the outside. The buffer 420 is a RAM (Random Access Memory), and is a general-purpose memory such as an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), or an MRAM (Magnetic Random Access Memory).

  The ECC circuit 430 adds an ECC code to the video data stored in the buffer 420 (ECC encoding). The ECC code system is arbitrary, and examples include BCH (Bose Chaudhuri Hocquenghem), RS (Reed Solomon), and LDPC (Low Density Parity Check). Further, the ECC circuit 430 performs error correction on the data to which the ECC code is added based on the ECC code (ECC decoding).

  The memory interface 440 writes video data or the like to or from the memory 500 based on a command from the CPU 410 (normal read and retry read). At this time, the memory interface 440 writes the video data in parallel to the plurality of memory chips 1 to M in each memory chip group G. The memory interface 440 reads video data in parallel from the plurality of memory chips 1 to M in each memory chip group G.

  The retry read control circuit 450 variably controls the number of retry reads according to various conditions. In the video processing, the retry read control circuit 450 determines the number of retry reads in accordance with the number of playback channels or recording channels in the video frame. For example, the retry read control circuit 450 reduces the number of retry reads in each playback channel when the number of playback channels is greater than a predetermined number, and sets the number of retry reads in each playback channel when the number of playback channels is equal to or less than the predetermined number. increase. The retry read control circuit 450 reduces the number of retry reads in each playback channel when the number of recording channels is greater than a predetermined number, and determines the number of retry reads in each playback channel when the number of recording channels is less than the predetermined number. increase. The retry read control circuit 450 stores the number of retry reads performed so far, and determines whether or not the maximum number has been reached.

(Lead in the first embodiment)
FIG. 4 is a flowchart showing a read in the video server device 10 according to the first embodiment.

  Here, the lead includes a normal read and a retry lead. The normal read is a data read performed first in response to a normal read command. The retry read is a read performed again on the data in which an error has occurred in response to a retry read command when an uncorrectable data error occurs in the ECC after normal reading.

  As shown in FIG. 4, first, normal reading is performed by the memory interface 440 in step S11. As a result, data for one page is read from the memory 500 to the FPGA 400.

  Next, in step S12, ECC is performed by the ECC circuit 430. That is, error correction is performed on the data read from the memory 500.

  Next, in step S13, it is determined whether ECC is possible. When ECC is impossible in step S13 (when an uncorrectable error occurs), a retry read sequence is performed in step S14. The retry read sequence will be described later with reference to FIG. On the other hand, if ECC is possible in step S13, the reading is terminated.

  FIG. 5 is a flowchart showing a retry read sequence (step S14 in FIG. 4) in the video server device 10 according to the first embodiment.

  As shown in FIG. 5, first, in step S21, the retry read control circuit 450 performs a retry read number determination sequence. Thus, the number of retry reads is determined according to various conditions. The retry read number determination sequence will be described later with reference to FIG.

  Next, retry read is performed by the memory interface 440 in step S22. As a result, the data for one page in which an error has occurred in the ECC in step S13 is read again from the memory 500 to the buffer 420.

  Next, in step S23, ECC is performed by the ECC circuit 430. That is, error correction is performed on the data read again from the memory 500.

  Next, in step S24, it is determined whether ECC is possible. When ECC is impossible in step S24 (when an error occurs), in step S25, the retry read control circuit determines whether or not the number of retry reads has reached the maximum number. On the other hand, if ECC is possible in step S24, the retry read sequence ends.

  If the number of retry reads has not reached the maximum number in step S25, the process returns to step S22 and retry read is performed. On the other hand, when the number of retry reads reaches the maximum number in step S25, the retry read sequence ends.

  In this example, normal read and retry read are performed with page-unit data, but the present invention is not limited to this. Normal reading and retry reading may be performed in ECC units (units in which ECC is performed) smaller than page units. Further, normal reading may be performed in units of pages, and retry reading may be performed in units of ECC. In this case, the retry read may be performed only on data in ECC units in which a correction error has occurred.

  FIG. 6 is a flowchart showing a retry read number determination sequence (step S21 in FIG. 5) in the video server device 10 according to the first embodiment.

  As shown in FIG. 6, first, in step S31, the retry read control circuit 450 determines whether or not the number of playback channels or the number of recording channels in the time-division multiplexed video frame is equal to or less than a predetermined number. The number of playback channels or recording channels in a video frame is determined by a request from an external system, that is, the number of controls from the external system.

  If the number of playback channels or the number of recording channels is less than or equal to the predetermined number in step S31, the retry read control circuit 450 determines that the number of retry reads for each playback channel is N in step S32. On the other hand, if the number of reproduction channels or the number of recording channels is larger than the predetermined number in step S31, the retry read control circuit 450 determines that the number of retry reads for each reproduction channel is M in step S33. Here, N> M.

  In other words, the retry read control circuit 450 sets the number of retry reads in each reproduction channel to be small when the number of reproduction channels is greater than the predetermined number, and the retry read in each reproduction channel when the number of reproduction channels is equal to or less than the predetermined number. Set a large number of times. Further, the retry read control circuit 450 sets the number of retry reads in each reproduction channel to be small when the number of recording channels is larger than the predetermined number, and when the number of recording channels is equal to or less than the predetermined number, Set a large number of times.

  In this example, the number of retry reads is two, N or M. However, the number is not limited to this, and three or more types of retry reads may be used.

  The retry read count determination sequence according to the first embodiment will be described in detail below with reference to FIGS.

  7 to 9 are diagrams illustrating first to third examples of video frames of video processing performed by the video server device 10 according to the first embodiment, respectively.

  Here, in FIGS. 7 to 9, the reproduction channel and the file output channel are channels on which reading is executed. That is, one normal read and a plurality of retry reads are performed in each reproduction channel and each file output channel. The recording channel is a channel on which writing is performed. The playback channel, recording channel, and file output channel in the same frame are time-division multiplexed channels.

  As shown in FIG. 7, in one video frame at time 10T in the first example, for example, playback channels CH1 to CH5, recording channels CH1 to CH3, and file output channels CH1 to CH2 are controlled. In each reproduction channel CH, one normal read and a plurality of retry reads (retry read sequence) shown in FIG. 4 are performed.

  In FIG. 7, the times allocated to the reproduction channels CH1 to CH5, the recording channels CH1 to CH3, and the file output channels CH1 to CH2 are times 5T, 3T, and 2T, respectively. Therefore, the time allocated to each reproduction channel CH is time T. Here, the time required for one normal read or one retry read is time T / 5. In this case, one normal read and four retry reads can be executed in each reproduction channel CH.

  On the other hand, as shown in FIG. 8, in the video frame in the second example, the number of recording channels CH and file output channels CH is not changed compared to the first example, but the number of reproduction channels CH is increased. Here, playback channels CH1 to CH10 are controlled. Therefore, the time allocated to each reproduction channel CH is shorter than that in the first example and is time T / 2. Since the time required for one normal read or one retry read is time T / 5, one normal read and one retry read can be executed in each reproduction channel CH.

  That is, as shown in FIGS. 7 and 8, as the number of playback channels increases, the time allocated to one playback channel CH becomes shorter. Therefore, in this example, when the number of playback channels increases, the number of retry reads in each playback channel is reduced in order to shorten the processing time of each playback channel.

  Also, as shown in FIG. 9, in the video frame in the third example, the number of playback channels CH and file output channels CH is not changed compared to the first example, but the number of recording channels CH is increased. For this reason, the times allocated to the reproduction channels CH1 to CH5, the recording channels CH1 to CH4, and the file output channels CH1 to CH2 are times 4T, 4T, and 2T, respectively. That is, the time for the recording channels CH1 to CH4 becomes longer, and the time for the reproduction channels CH1 to CH5 becomes shorter accordingly. Therefore, the time allocated to each reproduction channel CH is time 4 / 5T. Since the time required for one normal read or one retry read is time T / 5, one normal read and three retry reads can be executed in each reproduction channel CH.

  That is, as shown in FIGS. 7 and 9, as the number of recording channels increases, the time allocated to one reproduction channel CH becomes shorter. Therefore, in this example, when the number of recording channels increases, the number of retry reads in each reproduction channel is reduced in order to shorten the processing time of each reproduction channel.

(Effect in 1st Embodiment)
According to the first embodiment, the memory controller 400 includes the retry read control circuit 450. The retry read control circuit 450 variably controls the number of retry reads according to various conditions. That is, the number of retry reads can be appropriately reduced, and an increase in read time can be suppressed. In the first embodiment, a retry read control circuit 450 for controlling the number of retry reads is only additionally provided. For this reason, in order to suppress an increase in read time, the cost increase and the like can be minimized as compared with the case where the ECC circuit 430 is complicated or the number of chip stacks is increased.

  Also, according to the first embodiment, the number of retry reads is determined according to the number of playback channels or recording channels in a video frame. For example, the retry read control circuit 450 reduces the number of retry reads in each reproduction channel when the number of reproduction channels is large, and increases the number of retry reads in each reproduction channel when the number of reproduction channels is small. Thereby, the total processing time of all the playback channels in the video frame can be equalized regardless of the number of playback channels. Therefore, it is possible to secure the necessary number of reproduction channels in one video frame. As a result, in video processing that requires real-time performance, a predetermined number of playback channels required in the video frame can be appropriately processed, and broadcast accidents and the like can be prevented.

Second Embodiment
The video server device according to the second embodiment will be described below with reference to FIGS. 10 and 11. Note that in the second embodiment, description of the same points as in the first embodiment will be omitted, and different points will be mainly described.

(Configuration and Lead in Second Embodiment)
The second embodiment is different from the first embodiment in that the number of retry reads is variably controlled depending on whether the read in the video frame is reproduction or file output. Here, the reproduction indicates an operation of reading the video data in the memory 500 as a video to another reproduction medium. On the other hand, the file output indicates an operation of reading video data in the memory 500 as data to another storage medium.

  In the video processing, the retry read control circuit 450 determines the number of retry reads depending on whether the read in the video frame is a reproduction channel or a file output channel. The retry read control circuit 450 increases the number of retry reads when the read is a reproduction channel, and decreases the number of retry reads when the read is a file output channel. That is, in the same video frame (in a time-division multiplexed state), the number of times of retry reading of the playback channel is set to be larger than the number of times of retry reading of the file output channel. This is because reproduction is generally more important than file output as a read function of a video server device. That is, playback requires higher reliability than file output.

  FIG. 10 is a flowchart showing a retry read number determination sequence (step S21 in FIG. 5) in the video server device 10 according to the second embodiment.

  As shown in FIG. 10, first, in step S41, the retry read control circuit 450 determines whether the read in the video frame is a reproduction channel or a file output channel.

  If the read is a reproduction channel in step S41, the retry read control circuit 450 determines that the number of retry reads is N in step S42. On the other hand, if it is a file output channel in step S41, the retry read control circuit 450 determines that the number of retry reads is M in step S43. Here, N> M.

  The retry read number determination sequence according to the second embodiment will be described in detail below with reference to FIG. 11 and FIG. 7 shown in the first embodiment.

  FIG. 11 is a diagram illustrating a fourth example of a video frame of video processing performed by the video server device 10 according to the second embodiment.

  As shown in FIG. 11, in the video frame in the fourth example, the number of reproduction channels CH, recording channels CH, and file output channels CH does not change compared to the first example. However, the time of the reproduction channels CH1 to CH5 is lengthened (time 6T), and the time of the file output channels CH1 to CH2 is shortened (time T). Therefore, the time allocated to each reproduction channel CH is time T + T / 5, and the time allocated to each file output channel CH is time T. Since the time required for one normal read or one retry read is time T / 5, one normal read and five retry reads can be executed in each reproduction channel CH. On the other hand, one normal read and two retry reads can be executed in each file output channel CH.

  That is, as shown in FIG. 7 and FIG. 11, the time allocated to one reproduction channel CH becomes longer by reducing the number of retry reads of each file output channel CH. This increases the number of retry reads that can be performed on one reproduction channel CH.

(Effect in 2nd Embodiment)
According to the said 2nd Embodiment, the effect similar to 1st Embodiment can be acquired.

  According to the second embodiment, the number of retry reads is determined according to whether the read in the video frame is a reproduction channel or a file output channel. The retry read control circuit 450 increases the number of retry reads when the read is a reproduction channel, and decreases the number of retry reads when the read is a file output channel. As a result, it is possible to improve the reliability of highly important reproduction as a read function of the video server device.

<Third Embodiment>
Hereinafter, a video server device according to the third embodiment will be described with reference to FIGS. 12 and 13. Note that in the third embodiment, a description of the same points as in the first embodiment will be omitted, and different points will mainly be described.

(Configuration and Lead in Third Embodiment)
The third embodiment is different from the first embodiment in that the number of retry reads is variably controlled depending on whether the playback channel in the video frame is an on-air channel or a preview channel. . The on-air channel is a channel used in actual broadcasting. On the other hand, the preview channel is a channel used for confirming recorded material.

  In the video processing, the retry read control circuit 450 determines the number of retry reads depending on whether the playback channel in the video frame is an on-air channel or a preview channel. The retry read control circuit 450 increases the number of retry reads when the playback channel is an on-air channel, and decreases the number of retry reads when the playback channel is a preview channel. That is, in the same video frame (in a time-division multiplexed state), the number of on-air channel retry reads is set to be greater than the number of preview channel retry reads. Therefore, the number of retry reads differs between different playback channels in the same video frame. This is because the on-air channel of the playback channels is more important than the preview channel. That is, the on-air channel requires higher reliability than the preview channel.

  FIG. 12 is a flowchart showing a retry read number determination sequence (step S21 in FIG. 5) in the video server device 10 according to the third embodiment.

  As shown in FIG. 12, first, in step S51, the retry read control circuit 450 determines whether the playback channel in the video frame is an on-air channel or a preview channel.

  If the playback channel is an on-air channel in step S51, the retry read control circuit 450 determines that the number of retry reads in the on-air channel is N in step S52. On the other hand, if the playback channel is a preview channel in step S51, the retry read control circuit 450 determines that the number of retry reads in the preview channel is M in step S53. Here, N> M.

  The retry read number determination sequence according to the third embodiment will be described in detail below with reference to FIG. 13 and FIG. 7 shown in the first embodiment.

  FIG. 13 is a diagram illustrating a fifth example of a video frame of video processing by the video server device 10 according to the third embodiment. In FIG. 13, the reproduction channel CH1 is an on-air channel, and the reproduction channel CH5 is a preview channel.

  As shown in FIG. 13, in the video frame in the fifth example, the number of playback channels CH, recording channels CH, and file output channels CH does not change compared to the first example. However, the time of the reproduction channel CH1 is lengthened (time T + T / 2), and the time of the reproduction channel CH5 is shortened (time T / 2). Since the time required for one normal read or one retry read is time T / 5, one normal read and six retry reads can be executed on the reproduction channel CH1. On the other hand, one normal read and two retry reads can be executed on the reproduction channel CH5.

  That is, as shown in FIGS. 7 and 13, by reducing the number of retry reads of the reproduction channel CH5 that is a preview channel, the time allocated to the reproduction channel CH1 that is an on-air channel becomes longer. This increases the number of retry reads that can be performed on the reproduction channel CH1.

(Effect in 3rd Embodiment)
According to the said 3rd Embodiment, the effect similar to 1st Embodiment can be acquired.

  According to the third embodiment, the number of retry reads is determined according to whether the playback channel in the video frame is an on-air channel or a preview channel. The retry read control circuit 450 increases the number of retry reads when the playback channel is an on-air channel, and decreases the number of retry reads when the playback channel is a preview channel. Thereby, it is possible to improve the reliability of the on-air channel having high importance among the reproduction channels.

<Fourth embodiment>
The video server apparatus according to the fourth embodiment will be described below with reference to FIG. Note that in the fourth embodiment, a description of the same points as in the first embodiment will be omitted, and different points will mainly be described.

(Configuration and Lead in Fourth Embodiment)
The fourth embodiment is different from the first embodiment in that the number of retry reads is variably controlled according to various information of the memory 500 that is a NAND flash memory. These various types of information are managed in units of memory blocks BLK.

  The CPU 410 stores various types of information in units of memory blocks BLK in the memory 500. The various types of information include, for example, the number of times of writing and the number of times of reading (the number of times of normal reading and the number of retry readings) executed previously. Then, the CPU 410 outputs the information together with the read command to the memory controller 400 at the time of reading.

  The retry read control circuit 450 determines the number of times of retry reading of the memory block BLK according to the number of times of writing or reading previously executed on the memory block BLK. The retry read control circuit 450 reduces the number of retry reads of the memory block BLK when the number of writes or reads performed on the memory block BLK is small, and the number of writes or reads performed on the memory block BLK is large. In addition, the number of retry reads of the memory block BLK is increased. This is because the probability of a bit error occurring when the memory block BLK is read increases as the number of executed writes or reads increases, and many retry reads are required for such a memory block BLK. Because.

  FIG. 14 is a flowchart showing a retry read number determination sequence (step S21 in FIG. 5) in the video server device 10 according to the fourth embodiment.

  As shown in FIG. 14, first, in step S61, the retry read control circuit 450 determines whether or not the number of executed writes or the number of reads is equal to or less than a predetermined number.

  If the number of writes or the number of reads is greater than the predetermined number in step S61, the retry read control circuit 450 determines that the number of retry reads is N in step S62. On the other hand, if the number of writes or the number of reads is equal to or less than the predetermined number in step S61, the retry read control circuit 450 determines that the number of retry reads is M in step S63. Here, N> M.

(Effect in 4th Embodiment)
According to the said 4th Embodiment, the effect similar to 1st Embodiment can be acquired.

  Further, according to the fourth embodiment, the number of retry reads is determined according to the number of times of writing or reading performed previously in the memory 500 (memory block BLK). The retry read control circuit 450 increases the number of retry reads when the number of writes or the number of reads is greater than a predetermined number, and reduces the number of retry reads when the number of writes or the number of reads is equal to or less than the predetermined number. As a result, it is possible to increase the retry read for the memory block BLK that has a high probability of causing a bit error due to a large number of writes or reads.

  Note that the number of retry reads may be variably controlled according to the number of erases performed or the frequency of occurrence of retry reads, not limited to the number of performed writes and the number of reads. In this case, the retry read count is increased when the erase count is large, and the retry read count is decreased when the erase count is small. Further, the number of retry reads is increased when the retry read frequency is high, and the retry read frequency is decreased when the retry read frequency is low.

<Fifth Embodiment>
The video server device according to the fifth embodiment will be described below with reference to FIGS. 15 to 17. The fifth embodiment is a modification of the fourth embodiment. Note that in the fifth embodiment, a description of the same points as in the fourth embodiment will be omitted, and different points will mainly be described.

(Configuration and lead in the fifth embodiment)
The fifth embodiment is different from the fourth embodiment in that a write busy time or a normal read busy time is used as various information in the memory 500.

  The retry read control circuit 450 determines the number of retry reads according to the write busy time or the normal read busy time. The retry read control circuit 450 decreases the number of retry reads when the normal read busy time is long, and increases the number of retry reads of the memory block BLK when the normal read busy time is short. The retry read control circuit 450 reduces the number of retry reads when the write busy time is long, and increases the number of retry reads of the memory block BLK when the write busy time is short.

  FIG. 15 is a flowchart showing a retry read number determination sequence (step S21 in FIG. 5) in the video server device 10 according to the fifth embodiment.

  As shown in FIG. 15, first, in step S71, the retry read control circuit 450 determines whether or not the write busy time or the normal read busy time is equal to or shorter than a predetermined time.

  If the write busy time or the normal read busy time is equal to or shorter than the predetermined time in step S71, the retry read control circuit 450 determines that the number of retry reads is N in step S72. On the other hand, if the write busy time or normal read busy time is longer than the predetermined time in step S71, the retry read control circuit 450 determines that the number of retry reads is M in step S73. Here, N> M.

  The retry read number determination sequence according to the fifth embodiment will be described in detail below with reference to FIGS. 16 and 17.

  FIGS. 16 and 17 are diagrams showing a first example and a second example of commands and a ready / busy state input to the memory controller 400 in the video server device 10 according to the fifth embodiment, respectively. Here, the read / busy read / normal read / retry read state is shown.

  Note that the ready state of the memory controller 400 is a state of waiting for an operation and receiving a command or data. The busy state is a state in which an operation according to a command is being performed and a command or data is not accepted.

  As shown in FIG. 16, when receiving a normal command in the ready state (H level), the memory controller 400 becomes busy (L level) at time t1 and executes normal read. When the normal read is completed, the memory controller 400 enters a ready state at time t2.

  Thereafter, when receiving a retry read command in the ready state, the memory controller 400 becomes busy at time t4 and executes retry read 1. When retry read 1 is completed, the ready state is entered at time t5. Thereafter, similarly, retry leads 2 to 5 are executed. As described above, in this example, five retry reads are executed within the time allocated to the reproduction channel CH1 (until time t13). More specifically, the retry lead 1 is time t4 to t5, the retry lead 2 is time t6 to t7, the retry lead 3 is time t8 to t9, the retry lead 4 is time t10 to t11, and the retry lead 5 is time t12 to t13. Executed in

  The NAND flash memory data sheet includes busy time TYP (typical) and MAX values. Usually, the processing time for writing / reading (recording / reproducing) in one channel is set using the MAX value of the busy time. However, in the actual operation, the busy time is about the TYP value, so the busy time hardly reaches the MAX value. For this reason, the recording / playback processing time for one channel is shorter than the set time. Therefore, in this example, when the write / read busy time is about the TYP value, the number of retry reads is increased.

  As shown in FIG. 16, in the first example, the normal read busy time ends at the TYP value (time t2) without reaching the MAX value (time t3). For this reason, the subsequent busy state of the retry lead 1 is started from time t4. As a result, five retry reads can be executed until time t13 assigned to the reproduction channel CH1.

  On the other hand, as shown in FIG. 17, in the second example, the normal read busy time reaches the MAX value (time t3) and ends. For this reason, the subsequent busy state of the retry lead 1 is started from time t6. As a result, four retry reads can be executed until time t13 assigned to the reproduction channel CH1.

  That is, as shown in FIGS. 16 and 17, when the normal read busy time is increased in the playback channel, the time allocated to the subsequent retry read is shortened. Therefore, in this example, when the normal read busy time increases, the number of retry reads is reduced so that the retry read falls within the processing time of the reproduction channel.

  Although not shown, when the write busy time in the recording channel increases, the time allocated to the recording channel increases, and therefore the time allocated to the reproduction channel decreases. As a result, by reducing the number of retry reads in the playback channel, the processing of the playback channel is kept in time.

(Effect in 5th Embodiment)
According to the fifth embodiment, the number of retry reads is determined in accordance with the write busy time or the normal read busy time. For example, the retry read control circuit 450 reduces the number of retry reads when the normal read busy time is long, and increases the number of retry reads when the normal read busy time is short. Thereby, retry read can be executed by effectively using the processing time of the set reproduction channel.

  In this example, the number of retry reads is determined according to the write busy time or the normal read busy time, but the present invention is not limited to this. The number of retry reads may be determined according to the busy time of the retry read itself. For example, the number of retry reads after that may be adjusted according to the busy time of the retry lead 1.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Video server apparatus, 400 ... Memory controller, 500 ... Memory.

Claims (18)

Memory,
A first read is performed on the first data in the memory, an ECC is performed on the first data on which the first read is performed, and an error occurs in the first data in the ECC. A memory controller for performing a second read with a variable number of times for the first data
Equipped with,
The memory controller controls a plurality of time-division multiplexed playback channels, performs the first read and the second read at least once for each playback channel, and the playback channels according to the number of playback channels A video server device that determines the number of times of the second read for each . Memory,
A first read is performed on the first data in the memory, an ECC is performed on the first data on which the first read is performed, and an error occurs in the first data in the ECC. A memory controller for performing a second read with a variable number of times for the first data
Comprising
The memory controller controls a plurality of reproduction channels and a plurality of recording channels that are time-division multiplexed, performs the first read and the second read at least once for each reproduction channel, and sets the number of recording channels. depending on features and be ruby Deosaba device to determine the number of the second lead of each of the playback channels. Memory,
A first read is performed on the first data in the memory, an ECC is performed on the first data on which the first read is performed, and an error occurs in the first data in the ECC. A memory controller for performing a second read with a variable number of times for the first data
Comprising
The memory controller controls a plurality of reproduction channels and a plurality of file output channels that are time-division multiplexed, and performs the first read and one or more second reads for each reproduction channel or each file output channel. performed, wherein the second read count and the file the second lead, wherein the to ruby Deosaba apparatus be variable and the number of the output channel of the respective reproduction channels. Memory,
A first read is performed on the first data in the memory, an ECC is performed on the first data on which the first read is performed, and an error occurs in the first data in the ECC. A memory controller for performing a second read with a variable number of times for the first data
Comprising
The memory controller controls the time division multiplexed plurality of reproduction channels, performs the first lead and one or more of the second lead in each of the reproduction channels, air channel of the plurality of reproduction channels features and to ruby Deosaba apparatus be variable and the number of the second lead of the preview channel of the number and the plurality of reproduction channels of the second lead. Memory,
A first read is performed on the first data in the memory, an ECC is performed on the first data on which the first read is performed, and an error occurs in the first data in the ECC. A memory controller for performing a second read with a variable number of times for the first data
Comprising
The memory includes a plurality of memory blocks;
The memory controller determines the number of times of the second read of the first memory block according to the number of times of the previous write to the first memory block of the plurality of memory blocks. and be ruby Deosaba apparatus. Memory,
A first read is performed on the first data in the memory, an ECC is performed on the first data on which the first read is performed, and an error occurs in the first data in the ECC. A memory controller for performing a second read with a variable number of times for the first data
Comprising
The memory includes a plurality of memory blocks;
The memory controller determines the number of times of the second read of the first memory block according to the number of times of the first read performed previously on the first memory block of the plurality of memory blocks. features and to ruby Deosaba device that. Memory,
A first read is performed on the first data in the memory, an ECC is performed on the first data on which the first read is performed, and an error occurs in the first data in the ECC. A memory controller for performing a second read with a variable number of times for the first data
Comprising
The memory includes a plurality of memory blocks;
The memory controller determines the number of times of the second read of the first memory block according to the number of times of the second read performed previously on the first memory block of the plurality of memory blocks. features and to ruby Deosaba device that. Memory,
A first read is performed on the first data in the memory, an ECC is performed on the first data on which the first read is performed, and an error occurs in the first data in the ECC. A memory controller for performing a second read with a variable number of times for the first data
Comprising
The memory controller, in response to said first lead of busy time, the features and to ruby Deosaba device that the second determining the number of leads. Memory,
A first read is performed on the first data in the memory, an ECC is performed on the first data on which the first read is performed, and an error occurs in the first data in the ECC. A memory controller for performing a second read with a variable number of times for the first data
Comprising
The memory controller, said first perform read and the second lead and the time-division multiplexed lights, features and to ruby Deosaba determining the number of the second lead in response to the busy time of the light apparatus.   Perform a first read on the first data in the memory;
  ECC is performed on the first data subjected to the first read,
  When an error occurs in the first data in the ECC, a second read that is variable in number of times is performed on the first data in the memory;
  Controls a plurality of time-division multiplexed playback channels, performs the first read and one or more second reads for each playback channel, and performs the second read for each playback channel according to the number of playback channels. A method of reading a memory, wherein the number of reads is determined. Perform a first read on the first data in the memory;
ECC is performed on the first data subjected to the first read,
When an error occurs in the first data in the ECC, a second read that is variable in number of times is performed on the first data in the memory;
A plurality of playback channels and a plurality of recording channels that are time-division multiplexed are controlled, the first read and the second read at least once are performed for each of the playback channels, and the playback channels according to the number of recording channels A method of reading a memory , comprising determining the number of times of the second read for each . Perform a first read on the first data in the memory;
ECC is performed on the first data subjected to the first read,
When an error occurs in the first data in the ECC, a second read that is variable in number of times is performed on the first data in the memory;
Controlling a plurality of time-division multiplexed playback channels and file output channels, performing the first read and the second read at least once for each playback channel or each file output channel, and features and to Rume mori read method that the number of the second lead to the variable in number and the file output channel of the second lead in each. Perform a first read on the first data in the memory;
ECC is performed on the first data subjected to the first read,
When an error occurs in the first data in the ECC, a second read that is variable in number of times is performed on the first data in the memory;
Controls a plurality of time-division multiplexed playback channels, performs the first lead and the second lead at least once for each playback channel, and the second lead of the on-air channel of the plurality of playback channels features and to Rume mori read method that the number of and the number of the second lead of the preview channel of the plurality of reproduction channels variable. The number of times of the second read of the first memory block is determined according to the number of times of writing previously performed on the first memory block of the plurality of memory blocks included in the memory. The method for reading a memory according to claim 10 . Determining the number of times of the second read of the first memory block according to the number of times of the first read performed previously on the first memory block of the plurality of memory blocks included in the memory. 14. The memory reading method according to claim 10, wherein the memory reading method is a memory reading method. Determining the number of times of the second read of the first memory block according to the number of times of the second read performed previously on the first memory block of the plurality of memory blocks included in the memory. 14. The memory reading method according to claim 10, wherein the memory reading method is a memory reading method. In response to said first lead of busy time, before SL any memory read method according to one of claims 10 to 13, characterized by determining the number of the second lead. 14. The method according to claim 10 , wherein the time division multiplexed write is performed with the first read and the second read, and the number of times of the second read is determined according to a busy time of the write. 2. A memory reading method according to claim 1.