JP6488948B2 - Load control device - Google Patents

Description

  The present invention relates to a load control device that controls an inductive load.

  As shown in Patent Document 1, a power converter having an inverse conversion unit, a control unit, a safety function signal generation circuit, a gate command buffer circuit, and a gate control unit is known. The reverse conversion unit supplies power to the load, and the control unit generates a gate command for operating the reverse conversion unit. The safety function signal generation circuit generates a safety function signal, and the gate command buffer circuit generates a gate command signal based on the gate command and the safety function signal. And a gate control part produces | generates the gate signal of a reverse conversion part based on a gate command signal, and controls operation | movement of a reverse conversion part.

  The safety function signal generation circuit generates a safety function signal based on a safety function command input from the safety function generator. More specifically, the safety function signal generation circuit turns off the safety function signal when the safety function command is OFF. The safety function signal generation circuit turns on the safety function signal when the safety function command is ON.

  On the other hand, the gate command buffer circuit outputs a gate command signal synchronized with the gate command to the gate control unit when the safety function signal is OFF. On the contrary, the gate command buffer circuit cuts off the gate command signal when the safety function signal is ON.

  As described above, when each of the safety function signal generation circuit and the gate command buffer circuit is in a normal state, the output and blocking of the gate command signal to the gate control unit can be controlled. However, when at least one of the safety function signal generation circuit and the gate command buffer circuit is in an abnormal state, it becomes impossible to control the output and blocking of the gate command signal to the gate control unit.

  The power converter described in Patent Document 1 includes a safety function monitoring unit that determines failure of safety functions such as a safety function signal generation circuit and a gate command buffer circuit in addition to the above-described components. The safety function monitoring unit determines that the safety function has failed when the safety function signal is OFF even though the safety function command is ON.

JP 2014-215895 A

  As described above, in the power converter disclosed in Patent Document 1, a failure of a safety function (blocking circuit) that blocks the gate command signal is determined based on whether or not the safety function command and the safety function signal match. To do. In the case of this configuration, when the interruption circuit is out of order, a gate command signal is output to the gate control unit, whereby a gate signal is output from the gate control unit to the inverse conversion unit. As a result, a current flows through the load (inductive load).

  SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a load control device capable of diagnosing a failure of a breaking circuit while suppressing a current from flowing through an inductive load.

One of the disclosed inventions for achieving the above object is a load control device for controlling an inductive load (200, 200a, 200b),
A driver (60) for controlling the current flow of the inductive load;
A control unit (10) for controlling the driver by a control signal;
A cutoff circuit (20) for blocking transmission of the control signal from the control unit to the driver;
A monitoring circuit (70) for monitoring the control signal output from the control unit via the cutoff circuit,
The driver has a switch group forming a pair in which an upper switch (61, 63, 65, 91) and a lower switch (62, 64, 66, 92) are connected in series from the plus electrode to the minus electrode. Have at least one,
The monitoring circuit includes a determination circuit (72) that generates a determination signal based on the control signal output from the control unit via the cutoff circuit and the control signal output directly from the control unit,
The control unit
As an operation mode, it has a control mode for controlling the driver and a diagnosis mode for diagnosing a failure of the cutoff circuit,
In diagnostic mode,
While outputting a cut-off signal to cut off the transmission of the control signal to the driver to the cut-off circuit,
Determination signal output from determination circuit when one pulse of control signal is output to one of upper switch and lower switch, and determination when one pulse of control signal is output to the other of upper switch and lower switch The failure of the cutoff circuit is diagnosed based on the determination signal output from the circuit.

  When the control unit (10) outputs a control signal to the switch group while outputting a cutoff signal to the cutoff circuit (20), when the cutoff circuit (20) is normal, the monitoring circuit (70) includes the control unit (10 ), But no control signal is input from the cutoff circuit (20). However, in contrast to this, when the control signal cannot be interrupted due to an abnormality in the interrupting circuit (20), not only the control signal is input from the control unit (10) to the monitoring circuit (70) but also the interrupting circuit (20). A control signal is also input. Thus, there is a difference in the control signal input to the monitoring circuit (70) between when the cutoff circuit (20) is normal and when it is abnormal. Therefore, the monitoring circuit (70) generates a determination signal corresponding to this difference. Thereby, the control part (10) can perform failure diagnosis of the interruption | blocking circuit (20) based on the determination signal.

  In the present invention, a one-pulse control signal is output to one of the upper switch (61, 63, 65, 91) and the lower switch (62, 64, 66, 92). Thereafter, a one-pulse control signal is output to the other of the upper switches (61, 63, 65, 91) and the lower switches (62, 64, 66, 92). According to this, since the interruption circuit (20) has failed, even if the control signal is transmitted to the driver (60, 90), the flow of current to the inductive load (200, 220a, 200b) is suppressed. The

  As described above, the load control device (100) of the present invention can perform a failure diagnosis of the breaking circuit (20) while suppressing the current from flowing through the inductive loads (200, 200a, 200b).

Further, in the present invention , the cutoff circuit has an upper cutoff circuit corresponding to the upper switch, and a lower cutoff circuit corresponding to the lower switch,
The determination circuit uses a control signal directly output from the control unit as a clock signal, a control signal transmitted from the control unit via a cutoff circuit as an input signal, and the control unit outputs a 1-pulse control signal. Has a sequential circuit (76) for outputting an input signal as a determination signal when the state changes from the first level to the second level,
The determination circuit has an upper determination circuit corresponding to the upper switch, and a lower determination circuit corresponding to the lower switch,
The voltage level of the determination signal of each of the upper determination circuit and the lower determination circuit is fixed to the second level in the initial state for diagnosing the failure of the cutoff circuit,
In addition to the determination circuit, the monitoring circuit sets the output signal to one of the first level and the second level when at least one of the determination signals of the upper determination circuit and the lower determination circuit is at the second level. A comprehensive determination circuit (73) for setting the output signal to the other of the first level and the second level when all the determination signals of the respective side determination circuits are at the first level;
One output terminal of the comprehensive judgment circuit is connected to the control unit,
The control unit diagnoses a failure of the cutoff circuit based on the output signal of the comprehensive determination circuit.

  In the following, for the sake of simplicity of explanation, the general determination circuit 73 sets the output signal to the first level when at least one of the determination signals is at the second level, and outputs the output signal when all the determination signals are at the first level. The effect will be described as the second level.

  When the control unit (10) outputs a one-pulse control signal to the upper switch (61, 63, 65, 91) while outputting a cut-off signal to the upper cut-off circuit (20), the upper cut-off circuit (20) is normal. In this case, a one-pulse clock signal is input from the control unit (10) to the upper determination circuit (72), but no control signal is input from the upper cutoff circuit (20). The voltage level of the control signal is the first level when no pulse is output. Therefore, the input signal of the upper cutoff circuit (20) when the clock signal is input is at the first level. As a result, the voltage level of the determination signal of the upper determination circuit (72) changes from the second level in the initial state to the first level.

  However, unlike this, when the upper cut-off circuit (20) cannot cut off the control signal due to an abnormality, the upper determination circuit (72) receives a one-pulse clock signal from the control unit (10) and A one-pulse control signal is input from the cutoff circuit (20). The voltage level of the control signal changes from the first level to the second level according to the output of the pulse. Therefore, the input signal of the upper cutoff circuit (20) when the clock signal is input is at the second level. As a result, the voltage level of the determination signal of the upper determination circuit (72) remains the second level in the initial state and does not change.

  The same applies when the control unit (10) outputs a control signal of one pulse to the lower switch (62, 64, 66, 92) while outputting a cutoff signal to the lower cutoff circuit (20). That is, when the lower cutoff circuit (20) is normal, the voltage level of the determination signal of the lower determination circuit (72) changes from the second level to the first level. However, when the lower cutoff circuit (20) is abnormal, the voltage level of the determination signal of the lower determination circuit (72) remains at the second level and does not change.

  Therefore, when each of the upper cutoff circuit (20) and the lower cutoff circuit (20) is normal, all the judgment signals of the upper judgment circuit (72) and the lower judgment circuit (72) are changed from the second level to the first level. Change. As a result, the output signal of the comprehensive determination circuit (73) changes from the first level to the second level.

  In contrast, when at least one of the upper cutoff circuit (20) and the lower cutoff circuit (20) is abnormal, at least one of the determination signals of the upper determination circuit (72) and the lower determination circuit (72) 2 levels remain unchanged. Therefore, the output signal of the comprehensive determination circuit (73) remains at the first level and does not change.

  As described above, when the upper cutoff circuit (20) and the lower cutoff circuit (20) are normal, and when at least one of the upper cutoff circuit (20) and the lower cutoff circuit (20) is abnormal, The voltage level of the output signal of the comprehensive judgment circuit (73) is different. For this purpose, the control unit (10) outputs a control signal of one pulse to each of the upper cutoff circuit (20) and the lower cutoff circuit (20), and then the voltage of the output signal of the comprehensive judgment circuit (73) based on the judgment signal. Determine whether the level has changed. By doing so, the control unit (10) can determine whether or not the interruption circuit (20) is abnormal.

  Further, one output terminal of the comprehensive judgment circuit (73) is connected to the control unit (10). According to this, the number of input terminals of the control unit (10) is increased as compared with the configuration in which the output terminals of the upper determination circuit (72) and the lower determination circuit (72) are connected to the control unit (10). Is suppressed.

In another disclosed invention, the driver has a plurality of switch groups,
The cutoff circuit has a plurality of upper cutoff circuits and lower cutoff circuits corresponding to a plurality of switch groups,
The determination circuit has a plurality of upper determination circuits and lower determination circuits corresponding to a plurality of switch groups,
The determination signal of each of the plurality of upper determination circuits and the plurality of lower determination circuits is input to the comprehensive determination circuit,
The control unit
In diagnostic mode,
While outputting a cutoff signal to each of the plurality of upper cutoff circuits and the plurality of lower cutoff circuits,
When one control pulse is simultaneously output to one of the upper switches and lower switches of all switch groups, and then one pulse of the control signal is simultaneously output to the other of the upper switches and lower switches of all switch groups. Based on the output signal output from the comprehensive determination circuit, the failure of the cutoff circuit is diagnosed.

  According to this, the operation in which the control unit (10) outputs one pulse of the control signal is performed twice. Therefore, it is cut off as compared with the configuration in which a plurality of upper switches (61, 63, 65, 91) and a plurality of lower switches (62, 64, 66, 92) are individually shifted in time to output one control signal individually. The failure diagnosis time of the circuit (20) is shortened.

  In addition, the code | symbol with the parenthesis is attached | subjected to the element as described in the claim as described in a claim, and each means for solving a subject. The reference numerals in parentheses are for simply indicating the correspondence with each component described in the embodiment, and do not necessarily indicate the element itself described in the embodiment. The description of the reference numerals with parentheses does not unnecessarily narrow the scope of the claims.

It is a block diagram which shows schematic structure of the motor control apparatus which concerns on 1st Embodiment. It is a circuit diagram which shows the site | part in connection with the U-phase upper arm switch in a motor control apparatus. It is a timing chart which shows the signal of the motor control apparatus in a failure diagnosis process. It is a timing chart which shows the signal of the motor control apparatus in a failure diagnosis process. It is a flowchart which shows a failure diagnosis process. It is a block diagram which shows schematic structure of the motor control apparatus which concerns on 2nd Embodiment. It is a timing chart which shows the signal of the motor control apparatus in a failure location specific process. It is a flowchart which shows a failure location specific process. It is a block diagram which shows schematic structure of the motor control apparatus which concerns on 3rd Embodiment. It is a circuit diagram which shows a driver. It is a circuit diagram which shows a driver determination circuit and a comprehensive determination circuit. It is a circuit diagram for demonstrating a selection circuit.

Hereinafter, an embodiment in which a load control device of the present invention is applied to a motor control device that controls a motor generator mounted on a hybrid vehicle will be described with reference to the drawings.
(First embodiment)
A motor control device according to the present embodiment will be described with reference to FIGS. In FIG. 1, in addition to the motor control device 100, a motor generator 200 is also illustrated. In FIG. 1, the symbol and name of the signal are shown. The asterisk * shown in the symbol indicates indefiniteness. 3 and 4, the indefinite signal level is indicated by hatching.

  The motor control device 100 is mounted on the hybrid vehicle together with the motor generator 200. Motor generator 200 functions as a power source and a power generation source for the hybrid vehicle. Although not shown, the hybrid vehicle has another engine as a power source and another motor generator as a power generation source. The engine constituting these power source and power generation source and the two motor generators are connected via a power distribution mechanism. The generated power is distributed to vehicle travel and power generation by this power distribution mechanism. The motor generator 200 corresponds to an inductive load.

  The engine generates power by being driven to burn, and the motor generator 200 generates power by rotating the output shaft with electric power. The motor generator 200 generates electricity by rotating the output shaft by the rotational energy of the wheels. Other motor generators generate electricity by rotating the output shaft by the power of the engine. In the following, in order to avoid complication, the motor generator is simply abbreviated as a motor.

  Although not shown, the motor 200 includes the output shaft, a rotor provided on the output shaft, and a stator coil provided around the rotor. As described above, when the output shaft is rotated by the rotational energy of the wheel, the magnetic field generated from the rotor intersects the stator coil, and an induced voltage is generated in the stator coil. As a result, a current flows through the stator coil, and this current is supplied to the vehicle battery by the motor control device 100. This will generate electricity. In contrast, when a three-phase alternating current is supplied to the stator coil by the motor control device 100, a three-phase rotating magnetic field is generated from the stator coil. Thereby, rotational torque is generated in the rotor, and the output shaft rotates.

  Next, the motor control apparatus 100 will be outlined based on FIG. The motor control device 100 includes a control unit 10, a cutoff circuit 20, a buffer circuit 30, an insulation circuit 40, a drive circuit 50, a driver 60, and a monitoring circuit 70. The control unit 10, the cutoff circuit 20, the buffer circuit 30, and the monitoring circuit 70 constitute a low voltage system, and the drive circuit 50 and the driver 60 constitute a high voltage system. The isolation circuit 40 functions to transmit signals from the low pressure system to the high pressure system. Each of the cutoff circuit 20, the buffer circuit 30, and the monitoring circuit 70 is formed in the same integrated circuit.

  In the low pressure system, the control unit 10 is electrically connected to the buffer circuit 30 via the cutoff circuit 20, and the buffer circuit 30 is electrically connected to the transmission side of the insulating circuit 40. On the other hand, in the high voltage system, the receiving side of the insulating circuit 40 and the drive circuit 50 are electrically connected, and the drive circuit 50 is electrically connected to the driver 60. The driver 60 is electrically connected to the stator coil of the motor 200.

  With the above connection configuration, the control signal output from the control unit 10 is input to the buffer circuit 30 via the cutoff circuit 20. The buffer circuit 30 amplifies the control signal, the amplified signal (hereinafter referred to as an amplified signal) is transmitted to the drive circuit 50 through the insulating circuit 40, and the drive circuit 50 generates a gate drive signal. The This gate drive signal is input to the driver 60. As a result, the driver 60 is driven and the motor 200 is controlled.

  The control unit 10 outputs a cutoff signal to the cutoff circuit 20 in addition to the control signal. When receiving the cutoff signal, the cutoff circuit 20 stops outputting the control signal to the buffer circuit 30. As a result, the output of the amplified signal to the insulating circuit 40 is stopped, and the output of the gate drive signal to the driver 60 is stopped. As a result, the driving of the driver 60 is stopped and the control of the motor 200 is also stopped.

  As described above, the motor control device 100 includes the monitoring circuit 70. As shown in FIG. 1, the monitoring circuit 70 is electrically connected to the control unit 10 and the buffer circuit 30. A control signal and a cutoff signal are directly input from the control unit 10 to the monitoring circuit 70. The monitor circuit 70 receives the amplified signal from the buffer circuit 30. In other words, the control signal amplified by the buffer circuit 30 is indirectly input to the monitoring circuit 70 via the cutoff circuit 20.

  As will be described later, the monitoring circuit 70 generates a comprehensive determination signal corresponding to the failure of the cutoff circuit 20 based on the control signal, the cutoff signal, and the amplified signal. This comprehensive determination signal is input to the control unit 10. The control unit 10 diagnoses a failure of the cutoff circuit 20 based on the comprehensive determination signal.

  Next, the driver 60 will be described in detail. As shown in FIG. 1, the driver 60 of this embodiment is an inverter having three switch groups in which an upper arm switch and a lower arm switch are connected in series. The three switch groups are connected in parallel between the power supply and the ground.

  Motor 200 has a U-phase stator coil, a V-phase stator coil, and a W-phase stator coil as stator coils. The three switch groups correspond to each of these three-phase stator coils.

  The switch group corresponding to the U-phase stator coil has a U-phase upper arm switch 61 and a U-phase lower arm switch 62, the middle point of which is electrically connected to the U-phase stator coil. Similarly, the switch group corresponding to the V-phase stator coil has a V-phase upper arm switch 63 and a V-phase lower arm switch 64, and the middle point thereof is electrically connected to the V-phase stator coil. The switch group corresponding to the W-phase stator coil has a W-phase upper arm switch 65 and a W-phase lower arm switch 66, and the middle point thereof is electrically connected to the W-phase stator coil.

  With this connection configuration, when at least one of the upper arm switches 61, 63, 65 and at least one of the lower arm switches 62, 64, 66 are driven by the gate drive signal, the stator coil is connected to the power source and the ground. And connected to. As a result, a current flows through the stator coil.

  Each of the switches 61 to 66 of the present embodiment is an IGBT. Therefore, diodes 61a to 66a are connected in reverse parallel to the switches 61 to 66, respectively. The upper arm switches 61, 63, 65 correspond to upper switches, and the lower arm switches 62, 64, 66 correspond to lower switches.

  Next, the signals of the motor control device 100 and the number of components will be outlined. As described above, the driver 60 has six switches 61 to 66. Therefore, in order to control the current flow of the driver 60 by individually controlling the six switches 61 to 66, the control unit 10 generates six control signals SIMup to SIMmwn shown in FIG. On the other hand, there are six cutoff circuits 20 for each of the six switches 61 to 66 in order to output and cut off the six control signals SImup to SImwn. Similarly, there are six buffer circuits 30, insulation circuits 40, drive circuits 50, and voltage level conversion circuits 71 and determination circuits 72 of the monitoring circuit 70 described later for each of the six switches 61-66. However, the total determination circuit 73 of the monitoring circuit 70 is not limited to the number of switches of the driver 60, but is one.

  The six control signals SImup to SImwn are input to the six buffer circuits 30 via the six cutoff circuits 20, respectively. Corresponding to this, the six buffer circuits 30 generate six amplified signals SOmup to SOmwn and output them to the six insulating circuits 40. In response to this, the six isolation circuits 40 control the current flow of the six drive circuits 50 as will be described later. The six drive circuits 50 generate six gate drive signals Gmup to Gmwn corresponding to the current flow, and output them to the switches 61 to 66.

  The control unit 10 also outputs a cutoff signal SDNm to the cutoff circuit 20. The control circuit 10 receives six control signals SImup to SImwn and one cutoff signal SDNm from the control unit 10. The monitor circuit 70 also receives six amplified signals SOmup to SOmwn from the buffer circuit 30. More specifically, the control signals SImup to SImwn, the cutoff signal SDNm, and the amplified signals SOmup to SOmwn are input to the six voltage level conversion circuits 71 and the determination circuit 72, respectively.

  The six voltage level conversion circuits 71 generate the six conversion signals DAmup to DAmwn shown in FIG. 3 based on the amplified signals SOmup to SOmwn. Then, the six determination circuits 72 generate six determination signals DBmup to DAmwn based on the conversion signals DAmup to DAmwn, the control signals SImup to SImwn, and the cutoff signal SDNm. Finally, the comprehensive determination circuit 73 generates one comprehensive determination signal DOUT based on the determination signals DBmup to DAmwn. This comprehensive determination signal DOUT is input to the control unit 10.

  Next, details of the motor control device 100 will be described with reference to FIG. The voltage level conversion circuit 71 and the determination circuit 72 of the cutoff circuit 20, the buffer circuit 30, the insulation circuit 40, the drive circuit 50, and the monitoring circuit 70 shown in FIG. 2 are parts related to the U-phase upper arm switch 61. The cutoff circuit 20, the buffer circuit 30, the insulation circuit 40, the voltage level conversion circuit 71, and the determination circuit 72 each have a configuration corresponding to FIG. Yes. However, the overall determination circuit 73 of the monitoring circuit 70 is common to each of the six switches 61 to 66.

  The control unit 10 has a control mode for controlling the driver 60 and a diagnostic mode for diagnosing a failure of the cutoff circuit 20 as operation modes. When the ignition switch IG switches from the off state to the on state, the control unit 10 enters the diagnosis mode. Thereby, the control unit 10 diagnoses the failure of the cutoff circuit 20. After the failure diagnosis, the control unit 10 switches to the control mode, and controls the driver 60 based on an instruction from a host ECU such as a hybrid ECU or a power management ECU mounted on the vehicle and the rotation state of the motor 200. To do. Note that the control unit 10 of the present embodiment performs failure diagnosis of not only the cutoff circuit 20 but also the monitoring circuit 70.

  Each of the six cutoff circuits 20 corresponding to the switches 61 to 66 cuts off the control signals SIMup to SIMmwn when the cutoff signal SDNm output from the control unit 10 is at the Lo level. On the contrary, when the cutoff signal SDNm is at the Hi level, each of the six cutoff circuits 20 outputs the control signals SImup to SImwn to the buffer circuit 30. Each of the three cutoff circuits 20 corresponding to the upper arm switches 61, 63, 65 corresponds to an upper cutoff circuit. Each of the three cutoff circuits 20 corresponding to the lower arm switches 62, 64, 66 corresponds to a lower cutoff circuit. The Lo level corresponds to the first level, and the Hi level corresponds to the second level.

  Each of the six buffer circuits 30 corresponding to the switches 61 to 66 outputs the Lo level amplified signals SOmup to SOmwn when the control signals SImup to SIMmwn output from the cutoff circuit 20 are at the Lo level. On the other hand, when the control signals SImup to SImwn are at the Hi level, each of the six buffer circuits 30 outputs the amplified signals SOmup to SOmwn at the Hi level.

  As shown in FIG. 2, the buffer circuit 30 includes an amplification switch 31 provided in a power supply wiring that connects the power supply on the low-voltage system side and the ground. In addition to the amplification switch 31, the power supply wiring is provided with a photodiode 41 of the insulating circuit 40 and a current limiting resistor 42. A photodiode 41, a current limiting resistor 42, and an amplification switch 31 are connected in series in order from the power supply to the ground. The amplification switch 31 is an N-channel MOSFET, and the gate electrode of the amplification switch 31 is electrically connected to the control unit 10 via the cutoff circuit 20.

  When the first control signal SImup is not blocked by the cutoff circuit 20 corresponding to the U-phase upper arm switch 61, the first control signal SImup is input to the gate electrode of the amplification switch 31 corresponding to the U-phase upper arm switch 61. . When the first control signal SImup becomes Hi level, the amplification switch 31 is turned on. On the other hand, when the first control signal SIMup becomes Lo level, the amplification switch 31 is turned off. Even when the first control signal SIMup is cut off, the amplification switch 31 is turned off. The middle point of the current limiting resistor 42 corresponding to the U-phase upper arm switch 61 and the amplification switch 31 is connected to the monitoring circuit 70. This midpoint potential corresponds to the first amplified signal SOmup. The behavior of the buffer circuit 30 corresponding to the U-phase upper arm switch 61 described above is the same in the five buffer circuits 30 corresponding to the other switches 62 to 66.

  The insulation circuit 40 is a photocoupler. Each of the six insulating circuits 40 corresponding to the switches 61 to 66 does not emit light when the amplified signals SOmup to SOmwn are at the Lo level, and emits light when the amplified signals SOmup to SOmwn are at the Hi level.

  As shown in FIG. 2, the insulating circuit 40 includes a light receiving element 43 and an insulating switch 44 in addition to the photodiode 41 and the current limiting resistor 42 described above. The photodiode 41 and the current limiting resistor 42 belong to a low voltage system, and the light receiving element 43 and the insulation switch 44 belong to a high voltage system. The photodiode 41 and the light receiving element 43 face each other with a predetermined interval, and the insulation switch 44 controls the electrical connection between the power supply on the high voltage system side and the drive circuit 50.

  Hereinafter, the behavior of the insulating circuit 40 and the drive circuit 50 corresponding to the U-phase upper arm switch 61 will be described. When the amplification switch 31 corresponding to the U-phase upper arm switch 61 is turned on, a current flows through the photodiode 41, thereby causing the photodiode 41 to emit light. When the light receiving element 43 receives the light, the light receiving element 43 generates an electrical signal. The insulation switch 44 is turned on by this electric signal. Then, the power supply on the high voltage system side is connected to the drive circuit 50 via the insulation switch 44. As a result, the high-level first gate drive signal Gmup is output from the drive circuit 50 to the U-phase upper arm switch 61. As a result, the U-phase upper arm switch 61 is turned on.

  On the other hand, when the amplification switch 31 corresponding to the U-phase upper arm switch 61 is turned off, no current flows through the photodiode 41 and the photodiode 41 does not emit light. Therefore, no electrical signal is generated by the light receiving element 43, and the insulation switch 44 is turned off. For this reason, the drive circuit 50 is not connected to the power supply on the high voltage system side, and the Lo-level first gate drive signal Gmup is output from the drive circuit 50 to the U-phase upper arm switch 61. As a result, the U-phase upper arm switch 61 is turned off. The behavior of the insulating circuit 40 and the driving circuit 50 corresponding to the U-phase upper arm switch 61 described above is the same in the five insulating circuits 40 and the driving circuit 50 corresponding to the other switches 62 to 66.

  As described above, the monitoring circuit 70 includes the six voltage level conversion circuits 71 and the determination circuit 72 corresponding to the switches 61 to 66, respectively. In addition, the monitoring circuit 70 has one general determination circuit 73 that is common to the switches 61 to 66. Each of the three determination circuits 72 corresponding to the upper arm switches 61, 63, 65 corresponds to an upper determination circuit. Each of the three determination circuits 72 corresponding to the lower arm switches 62, 64, and 66 corresponds to a lower determination circuit.

  As shown in FIG. 2, the voltage level conversion circuit 71 includes a threshold voltage generation unit 74 and a comparator 75. The inverting input terminal of the comparator 75 is connected to the middle point of the current limiting resistor 42 and the amplification switch 31, and the non-inverting input terminal is connected to the power source on the low voltage system side via the threshold voltage generation unit 74. As a result, the amplified signal is input to the inverting input terminal of the comparator 75, and the threshold voltage Vth generated by the threshold voltage generating unit 74 is input to the non-inverting input terminal. The voltage level of the threshold voltage Vth is higher than the ground potential and lower than the power supply voltage on the low voltage system side. For example, the threshold voltage generation unit 74 may employ a configuration in which a resistor and a constant current circuit are connected in series in order from the power supply on the low-voltage system side to the ground. The middle point potential of this resistor and constant current circuit corresponds to the threshold voltage Vth.

  Hereinafter, the behavior of the amplification switch 31 and the comparator 75 corresponding to the U-phase upper arm switch 61 will be described. When the first control signal SImup is not blocked by the cutoff circuit 20 corresponding to the U-phase upper arm switch 61 and the first control signal SImup is at the Hi level, the amplification switch 31 is turned on. As a result, the first amplified signal SOmup becomes the ground potential, and the comparator 75 outputs the first converted signal DAmup at the Hi level.

  In contrast, when the first control signal SImup is blocked by the blocking circuit 20 corresponding to the U-phase upper arm switch 61, or when the first control signal SIMup is at the Lo level, the amplification switch 31 is turned off. . As a result, the first amplified signal SOmup becomes the power supply voltage on the low voltage system side, and the first conversion signal DAmup at the Lo level is output from the comparator 75. This first conversion signal DAmup is input to determination circuit 72 corresponding to U-phase upper arm switch 61. The behavior of the amplification switch 31 and the voltage level conversion circuit 71 corresponding to the U-phase upper arm switch 61 described above is the same in the five amplification switches 31 and the voltage level conversion circuit 71 corresponding to the other switches 62 to 66. It is.

  The determination circuit 72 includes a sequential circuit 76, an OR gate 77, and a delay circuit 78. The sequential circuit 76 is a D flip-flop that outputs an input signal when a pulse included in the clock signal rises. A control signal as a clock signal is input to the sequential circuit 76 via a delay circuit 78. A conversion signal is input to the sequential circuit 76 as an input signal.

  Hereinafter, the behavior of the buffer circuit 30 and the determination circuit 72 corresponding to the U-phase upper arm switch 61 will be described. As will be described later, the control unit 10 outputs the control signals SIMun, SImvn, and SIMmwn at the same time while outputting the control signals SImup, SImvp, and SImwp while setting the cutoff signal SDNm to Lo level at the time of failure diagnosis of the cutoff circuit 20. Simultaneously outputs one pulse. When the cutoff circuit 20 corresponding to the U-phase upper arm switch 61 is normal, the output of the first control signal SIMup to the buffer circuit 30 is cut off. Therefore, the Lo-level first conversion signal DAmup is input to the sequential circuit 76. At this time, when the first control signal SImup for one pulse is input via the delay circuit 78, the sequential circuit 76 outputs the first determination signal DBmup at the Lo level.

  However, if the cutoff circuit 20 corresponding to the U-phase upper arm switch 61 is broken and the first control signal SImup is not cut off, one pulse worth of the first control signal SImup of the control unit 10 is output. The first conversion signal DAmup is input to the sequential circuit 76. The input timing of the first conversion signal DAmup to the sequential circuit 76 is delayed by the propagation time Td from the timing at which one pulse of the first control signal SImup is output from the control unit 10. The delay circuit 78 delays the input of the first control signal SIMup to the sequential circuit 76 by the propagation time Td. Therefore, the first control signal SIMup for one pulse is input as a clock signal to the sequential circuit 76 at the timing when the first conversion signal DAmup for one pulse is input. At this time, the sequential circuit 76 outputs the first determination signal DBmup at the Hi level. The behavior of the buffer circuit 30 and the determination circuit 72 corresponding to the U-phase upper arm switch 61 described above is the same in the buffer circuit 30 and the determination circuit 72 corresponding to the other switches 62 to 66.

  The voltage levels of the output signals (determination signals DBmup to DBmwn) of the six sequential circuits 76 are uniformly set to the Hi level by the Hi level SET signal. The sequential circuit 76 is connected to the OR gate 77 described above, and the output of the OR gate 77 is a SET signal. The cutoff signal SDNm and the power-on reset signal POR are input to the OR gate 77. The power-on reset signal POR is interlocked with the ignition switch IG, and when the ignition switch IG changes from the off state to the on state, the power on reset signal POR becomes the Lo level after being at the Lo level for a predetermined time.

  The OR gate 77 is active when the cutoff signal SDNm is at the Hi level, and is active when the power-on reset signal POR is at the Lo level. Therefore, when the cutoff signal SDNm is at the Hi level or the power-on reset signal POR is at the Lo level, the OR gate 77 outputs a Hi level SET signal. In contrast, when the cutoff signal SDNm is at the Lo level and the power-on reset signal POR is at the Hi level, the OR gate 77 outputs a Lo level SET signal.

  When the ignition switch IG is in the OFF state, the cutoff signal SDNm is at Lo level and the power-on reset signal POR is indefinite. However, when the ignition switch IG changes from the off state to the on state, the power-on reset signal POR is at the Lo level for a predetermined time. Therefore, the SET signal becomes Hi level at the start of failure diagnosis. As a result, the determination signals DBmup to DBmwn output from each of the six sequential circuits 76 are fixed to the Hi level as an initial state. However, when a predetermined time elapses after the power-on reset signal POR becomes Lo level, the power-on reset signal POR changes from Lo level to Hi level. Therefore, the SET signal changes from the Hi level to the Lo level, and the determination signals DBmup to DBmwn are released from the Hi level fixation. Thereby, the determination signals DBmup to DBmwn can be changed according to the conversion signals DAmup to DAmwn and the control signals SIMup to SIMmwn.

  With the above configuration, the signal from the motor control device 100 behaves as shown in FIG. The control unit 10 simultaneously outputs one pulse of the control signals SImup, SImvp, and SImwp corresponding to the upper arm switches 61, 63, and 65 at the beginning of the failure diagnosis while setting the cutoff signal SDNm to the Lo level. Then, when each of the three cutoff circuits 20 is normal, the amplified signals SOmup, SOmvp, and SOmwp remain at the Hi level and do not change as indicated by the solid line in FIG. Therefore, the conversion signals DAmup, DAmvp, DAmwp remain at the Lo level and do not change as shown by the solid line in FIG. On the other hand, the determination signals DBmup, DBmvp, DBmwp change from the Hi level to the Lo level as shown by the solid line in FIG.

  On the other hand, when each of the three cutoff circuits 20 is abnormal, the amplified signals SOmup, SOmvp, and SOmwp temporarily have a voltage level lower than the threshold voltage Vth as shown by a one-dot chain line in FIG. Along with this, the conversion signals DAmup, DAmvp, DAmwp temporarily change from the Lo level to the Hi level as shown by the one-dot chain line in FIG. On the other hand, the determination signals DBmup, DBmvp, and DBmwp remain at the Hi level and do not change as shown by the one-dot chain line in FIG.

  Similarly, the control unit 10 simultaneously outputs one pulse of the control signals SImun, SImvn, and SImwn corresponding to the lower arm switches 62, 64, and 66 while setting the cutoff signal SDNm to the Lo level. Then, when each of the three cutoff circuits 20 is normal, the determination signals DBmun, DBmvn, DBmwn change from the Hi level to the Lo level as shown by the solid line in FIG. On the other hand, when each of the three cutoff circuits 20 is abnormal, the determination signals DBmun, DBmvn, DBmwn remain at the Hi level and do not change as indicated by the one-dot chain line in FIG.

  As described above, each of the six determination signals DBmup to DBmwn changes in voltage level according to the state of each of the six cutoff circuits 20. Next, the comprehensive determination circuit 73 to which these six determination signals DBmup to DBmwn are input will be described.

  The total determination circuit 73 includes a total OR gate 79 and an open drain circuit 80. Six determination signals DBmup to DBmwn are input to the total OR gate 79, and the output of the total OR gate 79 is input to the open drain circuit 80.

  The total OR gate 79 outputs the Hi level when at least one of the six determination signals DBmup to DBmwn is at the Hi level, and outputs the Lo level when all the six determination signals DBmup to DBmwn are at the Lo level. The open drain circuit 80 outputs a Lo-level comprehensive determination signal DOUT when the output of the total OR gate 79 is at a Hi level, and outputs a Hi-level total determination signal DOUT when the output of the total OR gate 79 is at a Lo level. .

  In the open drain circuit 80, a resistor 81 and a switch 82 are connected in series in this order from the power supply on the low voltage system side to the ground. The middle point of the resistor 81 and the switch 82 is output to the control unit 10 as a comprehensive determination signal DOUT. The switch 82 is an N-channel MOSFET, and the output of the total OR gate 79 is input to the gate electrode of the switch 82.

  As described above, when the ignition switch IG is switched from the OFF state to the ON state, the output signals (determination signals DBmup to DBmwn) of the six sequential circuits 76 are all set to the Hi level as an initial state. Therefore, the Hi level is output from the total OR gate 79, and the total determination signal DOUT is at the Lo level as shown by the solid line in FIG.

  On the other hand, when the Hi level fixing of the determination signals DBmup to DBmwn is released and one pulse of the control signals SImup to SImwn is output, the six determination signals DBmup to DBmwn are at the Hi level according to the state of each of the six cutoff circuits 20. Or it becomes Lo level. When all of the six cutoff circuits 20 corresponding to the switches 61 to 66 are normal, all of the six determination signals DBmup to DBmwn change from the Hi level to the Lo level. Therefore, the output of the total OR gate 79 changes from the Hi level to the Lo level, and the total determination signal DOUT changes from the Lo level to the Hi level as shown by the solid line in FIG.

  However, when at least one of the six cutoff circuits 20 is abnormal, at least one of the six determination signals DBmup to DBmwn remains at the Hi level and does not change. For this reason, the output of the total OR gate 79 remains at the Hi level, and the total determination signal DOUT also remains at the Lo level as shown by the one-dot chain line in FIG.

  As described above, the output of the total OR gate 79 and the voltage level of the total determination signal DOUT behave differently depending on the states of the six cutoff circuits 20. Even when the monitoring circuit 70 is malfunctioning instead of the shut-off circuit 20, the comprehensive determination signal DOUT shows a behavior corresponding to the state.

  Next, failure diagnosis processing of the interruption circuit 20 will be described with reference to FIG. Note that the upper arm control signal SImp, the upper arm amplification signal SOmp, the upper arm conversion signal DAmp, and the upper arm determination signal DBmp shown in FIG. 4 are signals corresponding to the upper arm switches 61, 63, and 65, respectively. Similarly, the lower arm control signal SImn, the lower arm amplification signal SOmn, the lower arm conversion signal DAmn, and the lower arm determination signal DBmn are signals corresponding to the lower arm switches 62, 64, and 66, respectively.

  For example, the upper arm control signal SImp corresponds to three control signals SImup, SImvp, and SImwp. When all of the three control signals SImup, SImvp, and SImwp are at the Hi level, the upper arm control signal SImp is at the Hi level. However, when at least one of the three control signals SImup, SImvp, and SImwp is at Lo level, the upper arm control signal SImp is at Lo level. The signals are collectively shown in this way for the sake of simplicity.

  At time t1, the ignition switch IG of the vehicle is switched from the off state to the on state. At this time, the power-on reset signal POR temporarily becomes Lo level. Therefore, the SET signal temporarily becomes Hi level, and the determination signals DBmp and DBmn become Hi level. As a result, the comprehensive determination signal DOUT becomes Lo level. The cutoff signal SDNm is at Lo level.

  From time t1 to time t2, the power-on reset signal POR changes from Lo level to Hi level. Further, the cutoff signal SDNm remains at the Lo level. Therefore, the SET signal changes from the Hi level to the Lo level, and each of the six sequential circuits 76 can switch the output signal according to the input signal and the clock signal. However, at this time, the control unit 10 does not output the control signals SImp and SImn. Therefore, each of the determination signals DBmp and DBmn is still at the Hi level, and the comprehensive determination signal DOUT is still at the Lo level.

  However, if there is an abnormality such as a power fault at this time in the monitoring circuit 70, the comprehensive determination signal DOUT may be at the Hi level as shown by a one-dot chain line in FIG. Therefore, the control unit 10 determines whether or not the comprehensive determination signal DOUT is at the Lo level at time t3 after time t2. The control unit 10 determines that an abnormality has not yet been detected when the comprehensive determination signal DOUT is at the Lo level, and determines that an abnormality has occurred in the monitoring circuit 70 when the comprehensive determination signal DOUT is at the Hi level.

  When the time t3 reaches the time t4, the control unit 10 starts a failure diagnosis of the cutoff circuit 20. The control unit 10 temporarily switches the voltage level of the upper arm control signal SImp from the Lo level to the Hi level while keeping the cutoff signal SDNm at the Lo level. That is, the control unit 10 outputs three pulses of the three control signals SImup, SImvp, and SImwp simultaneously to the upper arm switches 61, 63, and 65 while keeping the cutoff signal SDNm at the Lo level. As a result, each of the upper arm switches 61, 63, 65 is temporarily turned on. However, the lower arm switches 62, 64, and 66 are still in an off state. Therefore, the driver 60 is not driven by the one-pulse output of the upper arm control signal SImp, and no current flows through the motor 200.

  When the cutoff circuit 20 corresponding to each of the upper arm switches 61, 63, 65 is normal, the output of the upper arm control signal SImp to the buffer circuit 30 is cut off. Therefore, the input signal of the sequential circuit 76 remains at the Lo level. In this input state, one pulse of the upper arm control signal SImp delayed by the propagation time Td by the delay circuit 78 is input to the sequential circuit 76 as a clock signal. As a result, the output of the sequential circuit 76 changes from the Hi level to the Lo level. That is, as shown by a solid line in FIG. 4, the upper arm determination signal DBmp changes from the Hi level to the Lo level at time t5.

  On the other hand, when the cutoff circuit 20 corresponding to each of the upper arm switches 61, 63, 65 is abnormal, the output of the upper arm control signal SImp to the buffer circuit 30 is not cut off. Therefore, when the upper arm control signal SImp is input, the upper arm amplification signal SOmp is indicated by a one-dot chain line in FIG. 4 as the channel of the amplification switch 31 of the buffer circuit 30 corresponding to the upper arm switches 61, 63, 65 is formed. To temporarily decline. When the upper arm amplification signal SOmp falls below the threshold voltage Vth generated by the threshold voltage generator 74, the output level of the comparator 75 is temporarily inverted. In other words, the voltage level of the upper arm conversion signal DAmp temporarily changes from the Lo level to the Hi level as shown by the one-dot chain line in FIG. Therefore, the input signal of the sequential circuit 76 temporarily changes from Lo level to Hi level. In this input state, one pulse of the upper arm control signal SImp delayed by the propagation time Td by the delay circuit 78 is input to the sequential circuit 76 as a clock signal. As a result, the output of the sequential circuit 76 is maintained at the Hi level. That is, as shown by the one-dot chain line in FIG. 4, the voltage level of the upper arm determination signal DBmp does not change at time t5 and is maintained at the Hi level.

  At this time, the lower arm control signal SImn is not yet output to the lower arm switches 62, 64, and 66, respectively. Therefore, when the monitoring circuit 70 is normal, the comprehensive determination signal DOUT is expected to be at the Lo level. However, even in this state, for example, if the monitoring circuit 70 has an abnormality such as a short circuit between the input and output terminals of the total OR gate 79, the total determination signal DOUT may be at the Hi level as shown by a one-dot chain line in FIG. There is sex. Therefore, the control unit 10 determines whether or not the comprehensive determination signal DOUT is at the Lo level at time t6 after time t5. The control unit 10 determines that an abnormality has not yet been detected when the comprehensive determination signal DOUT is at the Lo level, and determines that an abnormality has occurred in the monitoring circuit 70 when the comprehensive determination signal DOUT is at the Hi level.

  Thereafter, from time t6 to time t7, the control unit 10 temporarily switches the voltage level of the lower arm control signal SImn from the Lo level to the Hi level while keeping the cutoff signal SDNm at the Lo level. That is, the control unit 10 simultaneously outputs one pulse of the control signals SImun, SImvn, and SImwn to the lower arm switches 62, 64, and 66 while keeping the cutoff signal SDNm at the Lo level. By this output, the lower arm switches 62, 64 and 66 are temporarily turned on. However, each of the upper arm switches 61, 63, 65 is already in the off state from the on state. Therefore, the driver 60 is not driven by the one-pulse output of the lower arm control signal SImn, and no current flows through the motor 200. The time between the time t4, which is one pulse output timing of the upper arm control signal SImp, and the time t7, which is one pulse output timing of the lower arm control signal SImn, is the time when the upper arm switches 61, 63, 65 are off from the on state. It is determined longer than the time for switching to the state.

  When the cutoff circuit 20 corresponding to each of the lower arm switches 62, 64, 66 is normal, the output of the lower arm control signal SImn to the buffer circuit 30 is cut off. Therefore, the input signal of the sequential circuit 76 remains at the Lo level. In this input state, one pulse of the lower arm control signal SImn delayed by the propagation time Td by the delay circuit 78 is input to the sequential circuit 76 as a clock signal. As a result, the output of the sequential circuit 76 changes from the Hi level to the Lo level. That is, as indicated by the solid line in FIG. 4, the lower arm determination signal DBmn changes from the Hi level to the Lo level at time t8.

  On the other hand, when the cutoff circuit 20 corresponding to the lower arm switches 62, 64, 66 is abnormal, the output of the lower arm control signal SImn to the buffer circuit 30 is not cut off. Therefore, when the lower arm control signal SImn is input, the lower arm amplified signal SOmn is indicated by a one-dot chain line in FIG. 4 as the channel of the amplification switch 31 of the buffer circuit 30 corresponding to the lower arm switches 62, 64, 66 is formed. To temporarily decline. When the lower arm amplification signal SOmn falls below the threshold voltage Vth, the voltage level of the lower arm conversion signal DAmn temporarily changes from the Lo level to the Hi level as indicated by a one-dot chain line in FIG. Therefore, the input signal of the sequential circuit 76 temporarily changes from Lo level to Hi level. In this input state, one pulse of the lower arm control signal SImn delayed by the propagation time Td by the delay circuit 78 is input to the sequential circuit 76 as a clock signal. As a result, the output of the sequential circuit 76 is maintained at the Hi level. That is, as indicated by the one-dot chain line in FIG. 4, the voltage level of the lower arm determination signal DBmn does not change at time t8 and is maintained at the Hi level.

  At this time, when all of the cutoff circuit 20 and the monitoring circuit 70 corresponding to each of the switches 61 to 66 are normal, the comprehensive determination signal DOUT is expected to be at the Hi level. However, when at least one of the cutoff circuit 20 and the monitoring circuit 70 corresponding to each of the switches 61 to 66 is abnormal, the comprehensive determination signal DOUT is maintained at the Lo level. Therefore, the control unit 10 determines whether or not the comprehensive determination signal DOUT is at the Hi level at time t9 after time t8. The controller 10 determines that there is no abnormality when the comprehensive determination signal DOUT is at the Hi level, and determines that an abnormality has occurred in the cutoff circuit 20 or the monitoring circuit 70 when the comprehensive determination signal DOUT is at the Lo level.

  Next, failure diagnosis processing by the control unit 10 will be described with reference to FIG. As described above, the control unit 10 enters the diagnosis mode when the ignition switch IG is turned on from the off state. In this diagnosis mode, the control unit 10 keeps the cutoff signal at the Lo level.

  In step S10, the control unit 10 first determines whether or not the comprehensive determination signal DOUT is at the Lo level. If the controller 10 determines that the overall determination signal DOUT is at the Lo level, the process proceeds to step S20. On the contrary, if it is determined that the overall determination signal DOUT is at the Hi level, the control unit 10 proceeds to step S70. The determination process of the comprehensive determination signal DOUT in step S10 is performed at time t3 in FIG. 4 when the power-on reset signal is switched from the Lo level to the Hi level.

  In step S20, the control unit 10 outputs one pulse of the upper arm control signal SImp. Then, the process proceeds to step S30. One pulse output of the upper arm control signal SImp in step S20 is performed at time t4 in FIG.

  In step S30, the control unit 10 determines whether or not the comprehensive determination signal DOUT is at the Lo level. If the controller 10 determines that the overall determination signal DOUT is at the Lo level, the process proceeds to step S40. On the contrary, if it is determined that the overall determination signal DOUT is at the Hi level, the control unit 10 proceeds to step S70. The determination process of the comprehensive determination signal DOUT in step S40 is performed at time t6 in FIG.

  In step S40, the control unit 10 outputs one pulse of the lower arm control signal SImn. Then, the process proceeds to step S50. One pulse output of the lower arm control signal SImn in step S50 is performed at time t7 in FIG.

  In step S50, the control unit 10 determines whether or not the comprehensive determination signal DOUT is at the Hi level. If the controller 10 determines that the overall determination signal DOUT is at the Hi level, the process proceeds to step S60. On the contrary, if it is determined that the overall determination signal DOUT is at the Lo level, the control unit 10 proceeds to step S70. The determination process of the comprehensive determination signal DOUT in step S50 is performed at time t9 in FIG.

  In step S60, the control unit 10 determines that all of the cutoff circuit 20 and the monitoring circuit 70 corresponding to the six switches 61 to 66 are normal. Then, the control unit 10 proceeds to step S80, and notifies the host ECU of the result diagnosed as normal.

  In step S70, the control unit 10 determines that at least one of the cutoff circuit 20 and the monitoring circuit 70 corresponding to the six switches 61 to 66 is abnormal. Then, the control unit 10 proceeds to step S80, and notifies the result of diagnosis of the abnormality to the host ECU.

  Next, functions and effects of the motor control device 100 according to the present embodiment will be described. As described above, the control unit 10 outputs one pulse of the control signals SImup, SImvp, and SImwp to the upper arm switches 61, 63, and 65, respectively, when determining the failure (failure diagnosis) of the cutoff circuit 20 and the monitoring circuit 70. Thereafter, the control unit 10 outputs one pulse of the control signals SImun, SImvn, and SImwn to the lower arm switches 62, 64, and 66, respectively. And the control part 10 determines whether the interruption | blocking circuit 20 and the monitoring circuit 70 are abnormal based on the voltage level of the subsequent comprehensive determination signal DOUT. According to this, it is possible to perform failure diagnosis of the interruption circuit 20 while suppressing the current from flowing through the motor 200.

  One output terminal of the comprehensive determination circuit 73 is connected to the control unit 10. According to this, an increase in the number of input terminals of the control unit 10 is suppressed as compared with the configuration in which the output terminals of the six determination circuits are connected to the control unit. That is, the number of output terminals of the monitoring circuit 70 connected to the control unit 10 can be made one regardless of the number of switches of the driver 60.

  When diagnosing the failure of the interrupting circuit 20, the control unit 10 outputs one pulse of the control signals SImup, SImvp, and SImwp, and then outputs one pulse of the control signals SImun, SImvn, and SImwn simultaneously. According to this, the operation in which the control unit 10 outputs one pulse of the control signal is performed twice. Therefore, the failure diagnosis time of the interruption circuit 20 is shortened as compared with the configuration in which the control unit individually outputs one pulse of the six control signals SImup to SIMmwn.

  When the ignition switch IG is turned on, the control unit 10 performs failure diagnosis of the interruption circuit 20. As a result, failure diagnosis can be performed when the vehicle is started.

  The comprehensive determination circuit 73 has an open drain circuit 80. According to this configuration, a switch corresponding to an IC logic circuit different from the general OR gate 79 is connected in parallel to the switch 82, and the output of the IC logic circuit is input to the gate of the switch. The output can be output to the control unit 10. As a result, an increase in the number of input terminals of the control unit 10 with the addition of other IC logic circuits is suppressed.

  The controller 10 detects the comprehensive determination signal DOUT before and after outputting one pulse of the control signals SImup, SImvp, and SImwp, and diagnoses a failure of the monitoring circuit 70 based on the voltage. According to this, not only the interruption circuit 20 but also the failure of the monitoring circuit 70 can be diagnosed.

  Each of the cutoff circuit 20, the buffer circuit 30, and the monitoring circuit 70 is formed in the same integrated circuit. According to this, an increase in the number of parts is suppressed as compared with a configuration in which the cutoff circuit, the buffer circuit, and the monitoring circuit are formed in different integrated circuits.

  In the embodiment, in the failure diagnosis process, the control unit 10 outputs one pulse of the three control signals SImup, SImvp, and SImwp, and then outputs one pulse of the three control signals SImun, SImvn, and SImwn simultaneously. However, unlike this, in the failure diagnosis process, the control unit 10 may sequentially output one pulse of the six control signals SImup to SIMmwn.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. The motor control device according to the second embodiment has much in common with the above-described embodiment. Therefore, in the following description, description of common parts is omitted, and different parts are mainly described. In the following description, the same reference numerals are given to the same elements as those described in the above embodiment.

  In the first embodiment, an example in which failure diagnosis of the six shut-off circuits 20 is performed all together is shown. On the other hand, the present embodiment is characterized in that when one of the six cutoff circuits 20 is diagnosed as having a possibility of failure, it is specified which of the six cutoff circuits 20 is faulty. .

  The control unit 10 generates a clear signal CLR in addition to the control signals SImup to SImwn and the cutoff signal SDNm, and outputs it to the monitoring circuit 70. The clear signal CLR is input to each of the six sequential circuits 76 of the monitoring circuit 70. When the clear signal CLR is input to each of the six sequential circuits 76, the determination signals DBmup to DBmwn are fixed to the Lo level regardless of the input signal and the clock signal.

  When the control unit 10 diagnoses that there is a failure in the cutoff circuit 20 or the monitoring circuit 70 as shown in the first embodiment, the control unit 10 performs the following failure location specifying process. As shown in FIG. 7, the control unit 10 outputs a clear signal to each of the six monitoring circuits 70 at time t10 while keeping the cutoff signal SDNm at the Lo level. As a result, all of the determination signals DBmup to DBmwn are set to Lo level, and the total determination signal DOUT is set to Hi level.

  However, if there is an abnormality in the monitoring circuit 70 at this time, the comprehensive determination signal DOUT may be at the Lo level as shown by a one-dot chain line in FIG. Therefore, the control unit 10 determines whether or not the comprehensive determination signal DOUT is at the Hi level at time t11 after time t10. The controller 10 determines that no abnormality has been detected yet when the overall determination signal DOUT is at the Hi level. On the other hand, when the overall determination signal DOUT is at the Lo level, the control unit 10 determines that an abnormality has occurred in the monitoring circuit 70.

  From time t11 to time t12, the control unit 10 outputs a one-pulse signal to the U-phase upper arm switch 61 while keeping the cutoff signal SDNm at the Lo level. Although the U-phase upper arm switch 61 is temporarily turned on by this output, the other arm switches 62 to 66 are still in the off state. Therefore, the driver 60 is not driven by one pulse output of the first control signal SIMup, and no current flows through the motor 200.

  When the cutoff circuit 20 corresponding to the U-phase upper arm switch 61 is normal, the output of the first control signal SIMup to the buffer circuit 30 is cut off. Therefore, the input signal of the sequential circuit 76 remains at the Lo level. In this input state, one pulse of the first control signal SImup delayed by the propagation time Td by the delay circuit 78 is input to the sequential circuit 76 as a clock signal. In this case, the output of the sequential circuit 76 is maintained at the Lo level. That is, as indicated by a solid line in FIG. 7, the voltage level of the first determination signal DBmup does not change at time t13 and is maintained at the Lo level. In this case, since each of the six determination signals DBmup to DBmwn remains at the Lo level, the overall determination signal DOUT remains at the Hi level.

  In contrast, when the cutoff circuit 20 corresponding to the U-phase upper arm switch 61 is abnormal, the output of the first control signal SIMup to the buffer circuit 30 is not cut off. Therefore, with the input of the first control signal SImup, the first amplified signal SOmup is lowered as shown by the one-dot chain line in FIG. 7 as the channel of the amplification switch 31 of the buffer circuit 30 corresponding to the U-phase upper arm switch 61 is formed. To do. When the first amplification signal SOmup falls below the threshold voltage Vth, the voltage level of the first conversion signal DAmup temporarily changes from the Lo level to the Hi level as indicated by a one-dot chain line in FIG. Therefore, the input signal of the sequential circuit 76 temporarily changes from Lo level to Hi level. In this input state, one pulse of the first control signal SImup delayed by the propagation time Td by the delay circuit 78 is input to the sequential circuit 76 as a clock signal. As a result, the output of the sequential circuit 76 changes from the Lo level to the Hi level. That is, as indicated by a dashed line in FIG. 7, the voltage level of the first determination signal DBmup changes from the Lo level to the Hi level at time t13. In this case, the overall determination signal DOUT changes from the Hi level to the Lo level.

  As described above, when the cutoff circuit 20 corresponding to the U-phase upper arm switch 61 is normal, the overall determination signal DOUT is expected to be at the Hi level. However, when the cutoff circuit 20 corresponding to the U-phase upper arm switch 61 is abnormal, the comprehensive determination signal DOUT becomes Lo level. Therefore, the control unit 10 determines whether or not the comprehensive determination signal DOUT is at the Hi level at time t14 after time t13. The control unit 10 determines that there is no abnormality when the comprehensive determination signal DOUT is at the Hi level, and that an abnormality has occurred in the cutoff circuit 20 corresponding to the U-phase upper arm switch 61 when the comprehensive determination signal DOUT is at the Lo level. judge.

  The failure location specifying process described above is performed only for the cutoff circuit 20 corresponding to the U-phase upper arm switch 61 out of the six cutoff circuits 20 corresponding to the six switches 61 to 66. The control unit 10 sequentially performs the same failure location specifying process for the other five cutoff circuits 20. As a result, the control unit 10 identifies which of the six cutoff circuits 20 is faulty.

  Next, the failure location specifying process by the control unit 10 will be described with reference to FIG. If the control unit 10 determines that there is an abnormality in the failure diagnosis processing shown in the first embodiment, the control unit 10 performs failure location specifying processing shown in FIG. In this failure location specifying process, the control unit 10 keeps the cutoff signal at the Lo level.

  In step S110, the control unit 10 outputs one pulse of the clear signal CLR. By doing so, the control unit 10 uniformly sets the determination signals DBmup to DBmwn to the Lo level and sets the total determination signal DOUT to the Hi level. Thereafter, the control unit 10 proceeds to step S120.

  In step S120, the control unit 10 determines whether or not the comprehensive determination signal DOUT is at the Hi level. If the controller 10 determines that the overall determination signal DOUT is at the Hi level, the process proceeds to step S130. On the contrary, if it is determined that the overall determination signal DOUT is at the Lo level, the control unit 10 proceeds to step S160. The determination process of the comprehensive determination signal in step S120 is performed at time t11 in FIG.

  In step S130, the control unit 10 outputs one pulse of one control signal for the cutoff circuit 20 to be inspected among the six control signals SImup to SImwn. Then, the process proceeds to step S140. One pulse output of one control signal in step S130 is performed at time t12 in FIG.

  In step S140, the control unit 10 determines whether or not the comprehensive determination signal DOUT is at the Hi level. If the controller 10 determines that the overall determination signal DOUT is at the Hi level, the process proceeds to step S150. On the contrary, if it is determined that the overall determination signal DOUT is at the Lo level, the control unit 10 proceeds to step S160. The determination process of the comprehensive determination signal in step S150 is performed at time t14 in FIG.

  In step S150, the control unit 10 determines that the cutoff circuit 20 to be inspected is normal. Then, the control unit 10 proceeds to step S170, and outputs the diagnosis result determined to be normal to the host ECU. After this, the control unit 10 proceeds to step S180.

  In step S160, the control unit 10 determines that at least one of the cutoff circuit 20 and the monitoring circuit 70 to be inspected is abnormal. Then, the control unit 10 proceeds to step S170, and outputs the diagnosis result determined to be abnormal to the host ECU. After this, the control unit 10 proceeds to step S180.

  In step S180, the control unit 10 determines whether or not failure diagnosis has been performed for each of the six cutoff circuits 20 individually as inspection targets. When all the fault diagnosis of the six interruption circuits 20 is completed, the control unit 10 ends the fault location specifying process. On the other hand, when all the fault diagnosis of the six cutoff circuits 20 has not been completed, the control unit 10 returns to step S130 and switches the cutoff circuit 20 to be inspected. As a result, the control unit 10 sequentially performs failure diagnosis for all of the six cutoff circuits 20.

  As described above, according to the motor control device 100 according to the present embodiment, it is possible to specify which of the six shut-off circuits 20 is out of order.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. The motor control device according to the third embodiment has much in common with the above-described embodiment. Therefore, in the following description, description of common parts is omitted, and different parts are mainly described. In the following description, the same reference numerals are given to the same elements as those described in the above embodiment.

  In the first embodiment, an example in which the motor control device 100 controls one motor 200 has been described. In contrast, in the present embodiment, the motor control device 100 is configured to control the two motors 200a and 200b. The two motors 200a and 200b have the same configuration.

  The motor control device 100 includes two inverters 60a and 60b as a driver 60, and a boost converter 90 that applies a boost voltage VH to the two inverters 60a and 60b. As shown in FIG. 10, the two inverters 60a and 60b are connected to the two motors 200a and 200b, respectively, and the boost converter 90 is connected to each of the two inverters 60a and 60b. The boost converter 90 corresponds to a boost circuit. As shown in FIG. 10, the inverters 60a and 60b have exactly the same configuration as the driver 60 (inverter) shown in the first embodiment.

  The monitoring circuit 70 includes a voltage level conversion circuit 71 and a determination circuit 72 corresponding to each of the two inverters 60a and 60b and one boost converter 90, and an overall determination circuit 73. The monitoring circuit 70 according to the present embodiment also includes three driver determination circuits 83 corresponding to the two inverters 60a and 60b and one boost converter 90, respectively. The driver determination circuit 83 corresponds to a logic gate.

  In the following, boost converter 90 will be described first. Thereafter, the three driver determination circuits 83 and the comprehensive determination circuit 73 will be described.

  As shown in FIG. 10, the boost converter 90 includes two boost switches 91 and 92 connected in series, and a smoothing capacitor 93 connected in parallel with the two boost switches 91 and 92. Boost converter 90 also includes a boost coil 94 provided between the midpoint of two boost switches 91 and the positive electrode of the battery, and a midpoint between the positive electrode and boost coil 94 and the negative electrode of the battery. And a smoothing capacitor 95 provided therebetween. Each of the boost switches 91 and 92 is an IGBT, and diodes 91a and 92a are connected in antiparallel to these. The collector electrode of the upper arm boosting switch 91 is connected to the collector electrodes of the upper arm switches 61, 63, 65 of the two inverters 60a, 60b, respectively. The emitter electrode of the lower arm boost switch 92 is connected to the collector electrodes of the lower arm switches 62, 64, 66 and the negative electrode of the battery, respectively, of the two inverters 60a, 60b.

  Boost converter 90 functions to boost battery voltage VL and apply boosted voltage VH to each of two inverters 60a and 60b in order to cancel the induced voltage generated in motors 200a and 200b. Boost converter 90 has a normal mode and a boost mode as operation modes. Boost converter 90 is in a normal mode until the vehicle speed reaches a threshold value, and enters a boost mode when the vehicle speed exceeds the threshold value.

  Boost converter 90 is controlled by control signals SIcp and SIcn output from control unit 10. The control signals SIcp and SIcn are input to the insulation circuit 40 via the corresponding cutoff circuit 20 and buffer circuit 30. The drive circuit 50 generates boost gate drive signals Gcp and Gcn, thereby controlling the boost converter 90.

  In the normal mode, the first boost gate drive signal Gcp has a duty ratio of 100%, and the second boost gate drive signal Gcn has a duty ratio of 0%. Thereby, the battery voltage VL is applied to each of the two inverters 60a and 60b.

  On the other hand, in the boost mode, the two boost switches 91 and 92 are alternately turned on / off. For example, when the duty ratio of the first boost gate drive signal Gcp is 50%, the duty ratio of the second boost gate drive signal Gcn is also 50%, and the voltage level is inverted. As described above, the two boost switches 91 and 92 are complementarily turned on / off, whereby a current is supplied to the boost coil 94 to store energy. Thereby, a boosted voltage VH obtained by boosting the battery voltage VL is generated, and this boosted voltage VH is applied to each of the two inverters 60a and 60b.

  Next, the driver determination circuit 83 will be described. As shown in FIG. 11, the driver determination circuit 83 is an OR gate. Six determination signals DBmup to DBmwn are input to the driver determination circuit 83 corresponding to the first motor 200a. Then, six determination signals DBgup to DBgwn are input to the driver determination circuit 83 corresponding to the second motor 200b. Finally, two determination signals DBcp and DBcn are input to the driver determination circuit 83 corresponding to the boost converter 90.

  In the same manner as in the first embodiment, at the beginning of the failure diagnosis process, the six determination signals DBmup to DBmwn, the six determination signals DBgup to DBgwn, and the two determination signals DBcp and DBcn are at the Hi level. However, if all of the six determination signals DBmup to DBmwn change from the Hi level to the Lo level as a result of the failure diagnosis process, the output of the driver determination circuit 83 (driver signal DOUTm) corresponding to the first motor 200a changes from the Hi level to the Lo level. To change. In contrast, if at least one of the six determination signals DBmup to DBmwn remains at the Hi level due to a failure, the driver signal DOUTm remains at the Hi level.

  Similarly, when all of the six determination signals DBgup to DBgwn change from the Hi level to the Lo level as a result of the failure diagnosis processing, the output of the driver determination circuit 83 (driver signal DOUTg) corresponding to the second motor 200b is at the Hi level. Changes from Lo to Lo level. In contrast, if at least one of the six determination signals DBgup to DBgwn remains at the Hi level due to a failure, the driver signal DOUTg remains at the Hi level.

  Finally, when all of the two determination signals DBcp and DBcn change from the Hi level to the Lo level as a result of the failure diagnosis process, the output (DOUTc) of the driver determination circuit 83 corresponding to the boost converter 90 changes from the Hi level to the Lo level. And change. On the other hand, if at least one of the two determination signals DBc and DBcn remains at the Hi level due to a failure, the driver signal DOUTc remains at the Hi level. Each of the three driver signals DOUTm, DOUTg, DOUTc described above is input to the comprehensive determination circuit 73.

  Similar to the first embodiment, the total determination circuit 73 includes a total OR gate 79 and an open drain circuit 80. However, three driver signals DOUTm, DOUTg, and DOUTc are input to the total OR gate 79 instead of the determination signal. Since the driver signals DOUTm, DOUTg, and DOUTc are at the Hi level at the beginning of the failure diagnosis process, the output of the total OR gate 79 is also at the Hi level. Therefore, the overall determination signal DOUT is at the Lo level. As a result of the failure diagnosis process, when each of the driver signals DOUTm, DOUTg, DOUTc changes from the Hi level to the Lo level, the output of the total OR gate 79 also changes from the Hi level to the Lo level. Therefore, the overall determination signal DOUT changes from the Hi level to the Lo level. When the control unit 10 detects that the total determination signal DOUT has changed from the Hi level to the Lo level, it determines that all the cutoff circuits 20 and the monitoring circuits 70 are normal. However, if at least one of the driver signals DOUTm, DOUTg, DOUTc remains at the Hi level as a result of the failure diagnosis process, the overall determination signal DOUT remains at the Hi level. Therefore, when detecting this, the control unit 10 determines that at least one of the cutoff circuit 20 and the monitoring circuit 70 is abnormal.

  As described above, even if the number of objects to be controlled (motors 200a and 200b) increases and the number of drivers (inverters 60a and 60b and boost converter 90) increase accordingly, the control unit 10 gives a comprehensive determination signal. Only DOUT is input. As a result, an increase in the number of input terminals of the control unit 10 is suppressed.

  The control unit 10 monitors the absolute value of the difference between the boost voltage VH and the battery voltage VL, and performs a failure diagnosis process when the absolute value is lower than a predetermined value stored therein. According to this, when at least one of the cutoff circuit 20 and the monitoring circuit 70 corresponding to the boost converter 90 is out of order, the boost voltage VH is suppressed from being excessively increased by the current flowing through the boost coil 94. Therefore, when the control unit 10 performs overvoltage protection in which the operation of the driver 60 is forcibly stopped when the boosted voltage VH increases excessively, the control unit 10 is suppressed from performing the overvoltage protection.

  When there are a plurality of drivers as described in the present embodiment, the modification shown in FIG. 12 may be employed. In this modification, the monitoring circuit 70 further includes a selection circuit 96. The selection circuit 96 is an AND gate that is active when the driver signal is at the Hi level and is active when the cutoff signal is at the Lo level. Therefore, when the driver signal is at the Hi level and the cutoff signal is at the Lo level, the output of the selection circuit 96 is at the Hi level. However, when the driver signal is at the Lo level or the cutoff signal is at the Hi level, the output of the selection circuit 96 is at the Lo level. The selection circuit 96 corresponds to a selection logic gate.

  The selection circuit 96 is provided corresponding to each of the two inverters 60a and 60b and one boost converter 90. The selection signal 96 corresponding to the first motor 200a receives the driver signal DOUTm and the cutoff signal SDNm of the cutoff circuit 20 corresponding to the first motor 200a. Similarly, the selection signal 96 corresponding to the second motor 200b receives the driver signal DOUTg and the cutoff signal SDNg of the cutoff circuit 20 corresponding to the second motor 200b. Finally, the driver signal DOUTc and the cutoff signal SDNc of the cutoff circuit 20 corresponding to the boost converter 90 are input to the selection circuit 96 corresponding to the boost converter 90. The outputs of the three selection circuits 96 are input to the total OR gate 79.

  The control unit 10 selects one driver to be diagnosed and outputs a Lo level cutoff signal to the cutoff circuit 20 corresponding to the driver. Then, the control unit 10 outputs a Hi level cutoff signal to the other cutoff circuit 20.

  For example, the control unit 10 sets the cutoff signal SDNm of the cutoff circuit 20 corresponding to the first motor 200a to Lo level, and sets the other cutoff signals SDNg and SDNc to Hi level. Thus, the Lo level cutoff signal SDNm is input to the selection circuit 96 corresponding to the first motor 200a. Then, the Hi level cutoff signal SDNg is input to the selection circuit 96 corresponding to the second motor 200b, and the Hi level cutoff signal SDNc is input to the selection circuit 96 corresponding to the boost converter 90. As a result, the output of the selection circuit 96 to which the cutoff signal SDNm is input is determined by the driver signal DOUTm, but the outputs of the other two selection circuits 96 to which the cutoff signals SDNg and SDNc are input are the driver signals DOUTg and DOUTc. Regardless of the Lo level.

  As described above, the output level of the total OR gate 79 and the voltage level of the total determination signal DOUT are determined by the driver signal DOUTm. That is, the voltage level of the comprehensive determination signal DOUT is determined by the presence or absence of a failure in the cutoff circuit 20 corresponding to the first motor 200a to be diagnosed. In this way, by selecting the voltage level of the cutoff signal corresponding to a plurality of drivers by the control unit 10, it is possible to select the cutoff circuit 20 to be diagnosed and perform failure diagnosis thereof individually. Such individual failure diagnosis is performed in a state where the vehicle is stopped.

  In the present embodiment, an example in which the motor control device 100 includes two inverters 60 a and 60 b and one boost converter 90 as the driver 60 is shown. However, the motor control device 100 does not have to include the boost converter 90.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

(First modification)
In each embodiment, an example in which the amplified signal output from the buffer circuit 30 is input to the monitoring circuit 70 has been described. However, unlike this, a configuration in which the control signal output from the cutoff circuit 20 is input to the monitoring circuit 70 may be employed. In this case, the monitoring circuit 70 does not have the voltage level conversion circuit 71. The control signal output from the cutoff circuit 20 is input to the sequential circuit 76.

(Second modification)
In each embodiment, an example in which the total determination circuit 73 includes the total OR gate 79 and the open drain circuit 80 is shown. However, the comprehensive determination circuit 73 may have an open collector circuit instead of the open drain circuit 80. In this case, the switch 82 is not a MOSFET but a transistor.

  Further, the comprehensive determination circuit 73 may not have the open drain circuit 80. In this case, the output terminal of the total OR gate 79 is connected to the control unit 10.

  Furthermore, the monitoring circuit 70 does not have to have the comprehensive determination circuit 73. In this case, the output terminals of the six determination circuits 72 are connected to the control unit 10 in the first embodiment and the second embodiment. In the third embodiment, the output terminals of the three driver determination circuits 83 are connected to the control unit 10. When the monitoring circuit 70 does not have the driver determination circuit 83, the output terminals of the 14 determination circuits 72 are connected to the control unit 10.

(Third Modification)
In each embodiment, an example in which not only the interruption circuit 20 but also the monitoring circuit 70 is diagnosed is shown. However, failure diagnosis of the monitoring circuit 70 may not be performed. In this case, steps S10 and S30 shown in FIG. 5 are omitted. Further, step S120 shown in FIG. 8 is also omitted.

(Other variations)
In each embodiment, the example which applied the load control apparatus of this invention to the motor control apparatus which controls the motor mounted in the hybrid vehicle was shown. However, the application of the load control device is not limited to the above example, and can be applied to, for example, a control ECU that controls a motor that is a power source of variable valve timing. As the load control device of the present invention, any device that controls an inductive load such as a motor can be adopted as appropriate.

  In each embodiment, an example in which the cutoff circuit 20, the buffer circuit 30, and the monitoring circuit 70 are formed in the same integrated circuit has been described. However, it is also possible to employ a configuration in which the cutoff circuit 20, the buffer circuit 30, and the monitoring circuit 70 are formed in separate integrated circuits.

  In each embodiment, the example which the various switches which comprise the driver 60 are IGBT was shown. However, the switch is not limited to the above example, and, for example, a MOSFET may be employed. The MOSFET has a parasitic diode. Therefore, a diode connected in reverse parallel to the switch is not required in this modification.

  In each embodiment, the Lo level corresponds to the first level, and the Hi level corresponds to the second level. However, on the contrary, it is possible to adopt a configuration in which the Lo level corresponds to the second level and the Hi level corresponds to the first level. In this case, for example, the total OR gate 79 becomes an AND gate.

  In each embodiment, an example in which the insulating circuit 40 is a photocoupler has been described. However, the insulating circuit 40 is not limited to the above example, and for example, a configuration in which a low voltage system and a high voltage system are connected using magnetism may be employed.

DESCRIPTION OF SYMBOLS 10 ... Control part, 20 ... Shut-off circuit, 60 ... Driver, 61, 63, 65 ... Upper arm switch, 62, 64, 66 ... Lower arm switch, 70 ... Monitoring circuit, 72 ... Judgment circuit, 91 ... Upper arm boost switch , 92 ... Lower arm boost switch, 100 ... Motor controller, 200 ... Motor, 200a ... First motor, 200b ... Second motor

Claims (16)

A load control device for controlling an inductive load (200, 200a, 200b),
A driver (60) for controlling the current flow of the inductive load;
A control unit (10) for controlling the driver by a control signal;
An interruption circuit (20) for interrupting transmission of the control signal from the control unit to the driver;
A monitoring circuit (70) for monitoring the control signal output from the control unit via the cutoff circuit,
The driver includes a pair of switches in which an upper switch (61, 63, 65, 91) and a lower switch (62, 64, 66, 92) are sequentially connected in series from the plus electrode to the minus electrode. Having at least one
The monitoring circuit includes a determination circuit (72) that generates a determination signal based on the control signal output from the control unit via the cutoff circuit and the control signal output directly from the control unit. And
The controller is
As an operation mode, it has a control mode for controlling the driver, and a diagnostic mode for diagnosing a failure of the cutoff circuit,
In the diagnostic mode,
While outputting a cut-off signal to cut off transmission of the control signal to the driver to the cut-off circuit,
The determination signal output from the determination circuit when one pulse of the control signal is output to one of the upper switch and the lower switch, and the control signal to the other of the upper switch and the lower switch And diagnosing a failure of the cutoff circuit based on the determination signal output from the determination circuit when one pulse is output .
The cutoff circuit has an upper cutoff circuit corresponding to the upper switch, and a lower cutoff circuit corresponding to the lower switch,
The determination circuit uses the control signal directly output from the control unit as a clock signal, the control signal transmitted from the control unit via the cutoff circuit as an input signal, and the control unit performs the one-pulse control. A sequential circuit (76) for outputting the input signal as the determination signal when the clock signal is changed from the first level to the second level as a result of outputting the signal;
The determination circuit includes an upper determination circuit corresponding to the upper switch, and a lower determination circuit corresponding to the lower switch,
The voltage level of the determination signal of each of the upper determination circuit and the lower determination circuit is fixed to the second level in an initial state for diagnosing a failure of the cutoff circuit,
In addition to the determination circuit, the monitoring circuit outputs an output signal of the first level and the second level when at least one of the determination signals of the upper determination circuit and the lower determination circuit is at the second level. On the other hand, when all of the determination signals of the upper determination circuit and the lower determination circuit are at the first level, the overall determination circuit (73) sets the output signal to the other of the first level and the second level. Have
One output terminal of the comprehensive judgment circuit is connected to the control unit,
The said control part is a load control apparatus which diagnoses the failure of the said interruption | blocking circuit based on the said output signal of the said comprehensive determination circuit . The driver has a plurality of the switch groups,
The cut-off circuit has a plurality of the upper cut-off circuit and the lower cut-off circuit corresponding to each of the plurality of switch groups,
The determination circuit includes a plurality of the upper determination circuits and the lower determination circuits corresponding to the plurality of switch groups,
The determination signal of each of the plurality of upper determination circuits and the plurality of lower determination circuits is input to the comprehensive determination circuit,
The controller is
In the diagnostic mode,
While outputting the cutoff signal to each of the plurality of upper cutoff circuits and the plurality of lower cutoff circuits,
After one pulse of the control signal is simultaneously output to one of the upper switch and the lower switch of all the switch groups, the control signal is output to the other of the upper switch and the lower switch of all the switch groups. wherein on the basis of the output signal outputted from the overall judgment circuit upon simultaneously one pulse output, the load control device according to claim 1 for diagnosing a failure of the shutoff circuit. When the control unit diagnoses that the interruption circuit is out of order, the determination signal of each of the plurality of upper determination circuits and the plurality of lower determination circuits is uniformly set to the first level. After the output signal is set to the other one of the first level and the second level, the comprehensive determination is performed when one pulse of the control signal is output to one of the plurality of upper switches and the plurality of lower switches. Whether or not the output signal output from the circuit changes from the other of the first level and the second level to one of the plurality of upper cutoff circuits and the plurality of lower cutoff circuits sequentially The load control device according to claim 2 , wherein the load control device individually diagnoses a failure of each of the plurality of upper cutoff circuits and the plurality of lower cutoff circuits. The driver, load control device of claim 2 or claim 3 is an inverter. The overall determination circuit outputs the second level signal when at least one of the determination signals of the upper determination circuit and the lower determination circuit is at the second level, and the upper determination circuit and the lower determination circuit output the second determination signal. A total OR gate (79) for outputting the first level signal when all the determination signals of the respective circuits are at the first level; a resistor (81) provided between a power source and ground; and the resistor And a switch (82) that is switched between an on state and an off state by an output of the total OR gate, and a midpoint potential between the resistor and the switch is It is the output signal of the comprehensive judgment circuit,
The switch is
When the output of the total OR gate is at the second level, the on state is set, and the output signal of the total determination circuit is at the first level,
Wherein the output of the overall OR gate becomes the off state when the first level, the load control device according to claim 1 any one of the output signal becomes the second level of the total determination circuit . There are a plurality of inductive loads,
A plurality of load control apparatus according to claim 1 any one having a plurality of said cut-off circuit respectively with said driver corresponding to each of the inductive load. The monitoring circuit includes a plurality of the determination circuits corresponding to each of the plurality of cutoff circuits and one comprehensive determination circuit, and a plurality of logic gates (83) corresponding to the plurality of determination circuits,
Each of the plurality of logic gates outputs the second level signal when at least one of the determination signals of the upper determination circuit and the lower determination circuit of the corresponding determination circuit is the second level, When all of the determination signals of the upper determination circuit and the lower determination circuit are at the first level, the first level signal is output,
The overall determination circuit sets the output signal to one of the first level and the second level when at least one of the signals of each of the plurality of logic gates is at the second level, and sets the signal of each of the plurality of logic gates. The load control device according to claim 6 , wherein when all the signals are at the first level, the output signal is set to the other of the first level and the second level. The comprehensive determination circuit outputs the second level signal when at least one of the signals of the plurality of logic gates is at the second level, and all of the signals of the plurality of logic gates are at the first level. A total OR gate (79) that sometimes outputs the first level signal, a resistor (81) provided between a power source and the ground, and a total OR gate provided between the resistor and the ground. A switch (82) that is switched between an on state and an off state by the output of, and a midpoint potential between the resistor and the switch is the output signal of the comprehensive determination circuit,
The switch is
When the output of the total OR gate is at the second level, the on state is set, and the output signal of the total determination circuit is at the first level,
8. The load control device according to claim 7 , wherein when the output of the total OR gate is at the first level, the load control device is in the off state, and the output signal of the total determination circuit is at the second level. Each of the plurality of cutoff circuits cuts off the input of the control signal to the driver when the cutoff signal is at the first level,
The monitoring circuit includes a plurality of the determination circuits corresponding to each of the plurality of cutoff circuits and one comprehensive determination circuit, a plurality of logic gates (83) corresponding to each of the plurality of determination circuits, and a plurality of A plurality of select logic gates (95) corresponding to each of the logic gates;
Each of the plurality of logic gates outputs the second level signal when at least one of the determination signals of the upper determination circuit and the lower determination circuit of the corresponding determination circuit is the second level, When all of the determination signals of the upper determination circuit and the lower determination circuit are at the first level, the first level signal is output,
Each of the plurality of selection logic gates has the second level signal when the output of the corresponding logic gate is at the second level and the cutoff signal input to the corresponding cutoff circuit is at the first level. Otherwise, the first level signal is output,
The overall determination circuit sets the output signal to the other of the first level and the second level when at least one of the signals of each of the plurality of selection logic gates is at the second level, The load control device according to claim 6 , wherein when all the outputs are at the first level, the output signal is set to the other of the first level and the second level. The comprehensive determination circuit outputs the second level signal when at least one of the outputs of the plurality of selection logic gates is at the second level, and all of the outputs of the plurality of selection logic gates are the first. A total OR gate (79) for outputting the first level signal at a level, a resistor (81) provided between a power source and the ground, and provided between the resistor and the ground. A switch (82) that is switched between an on state and an off state by an output of an OR gate, and a midpoint potential between the resistor and the switch is the output signal of the comprehensive determination circuit,
The switch is
When the output of the total OR gate is at the second level, the on state is set, and the output signal of the total determination circuit is at the first level,
10. The load control device according to claim 9 , wherein when the output of the total OR gate is at the first level, the load control device is in the off state, and the output signal of the total determination circuit is at the second level. The load control device according to any one of claims 6 to 10 , wherein the plurality of drivers are a plurality of inverters (60a, 60b) corresponding to the plurality of inductive loads, respectively. The plurality of drivers are a plurality of inverters (60a, 60b) corresponding to the plurality of inductive loads, and a booster circuit (90) for supplying a boosted voltage obtained by boosting a power supply voltage to each of the plurality of inverters. Item 12. The load control device according to any one of Items 6 to 11 . The load control device according to claim 12 , wherein the control unit diagnoses a failure of the cutoff circuit when an absolute value of a difference between the boosted voltage and the power supply voltage is lower than a predetermined value. The control unit diagnoses a failure of the cutoff circuit and the monitoring circuit based on the output signal of the comprehensive determination circuit every time the control signal is output to the upper switch and the lower switch by one pulse. The load control apparatus according to any one of 1 to 13 . The inductive load is mounted on a vehicle;
The load control device according to any one of claims 1 to 14 , wherein the control unit enters the diagnosis mode when an ignition switch of the vehicle is switched from an off state to an on state. The blocking circuit and the monitoring circuit, the same load control device according to any one of claims 1 to 15, which is formed in an integrated circuit.

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