JP6497258B2 - Semiconductor memory device and semiconductor memory device access control method - Google Patents

Description

  The embodiments referred to in this specification relate to a semiconductor memory device and an access control method for the semiconductor memory device.

  Conventionally, semiconductor memory devices (for example, RAM (Random Access Memory) and flash memory (Flash Electrically Erasable Programmable Read-Only Memory)) are provided with an error checking and correction (ECC) function. is there.

  That is, by providing an error detection / correction circuit (ECC circuit), it is possible to detect that an incorrect value is recorded in a memory (for example, a RAM), correct it to a correct value, and output it. ECC may be an abbreviation of “Error Correcting Code” or “Error Check and Correct”.

  In this way, for example, in RAM, when a soft error occurs in read data or a data error due to aging degradation, the error is detected and corrected by the ECC circuit, and the error-corrected data is output. It becomes possible to do.

  Conventionally, various proposals have been made as a semiconductor memory device capable of simplifying the ECC function or reducing redundant data and circuits.

JP 2000-040036 A Japanese Patent No. 4160625

  As described above, as a semiconductor memory device having an ECC function, for example, an ECC circuit is mounted on a RAM, and read data from the RAM is output via the ECC circuit, thereby detecting and correcting error data. Things are in practical use.

  However, since the RAM having such a configuration passes through the ECC circuit every time data is read, the latency is increased as compared with a RAM that directly reads data without providing the ECC circuit. Furthermore, since the redundant ECC data is used for correcting the error data, for example, the RAM capacity is excessively consumed, and the actually usable memory capacity is reduced.

  According to one embodiment, a semiconductor memory device having a memory unit, a first rearrangement circuit, and a second rearrangement circuit is provided. The first rearrangement circuit receives a plurality of bits of data, rearranges the first bit in which an error is detected in the data into a second bit in which no error is detected, and stores the second bit in the memory unit.

The second rearrangement circuit receives data read from the memory unit, rearranges the second bit data with the first bit data, and outputs the rearranged data. The first bit is a bit higher than the second bit, the second bit is the least significant bit of the data, and when there are a plurality of the first bits, the second bit Are selected in order from the least significant bit to the higher order.

  The disclosed semiconductor memory device and the access control method for the semiconductor memory device have an effect of suppressing an increase in latency and a decrease in data capacity that can actually be used in the memory.

FIG. 1 is a block diagram illustrating an example of a semiconductor memory device. FIG. 2 is a block diagram illustrating an example of the semiconductor memory device according to this embodiment. FIG. 3 is a flowchart (part 1) for explaining the process in the semiconductor memory device shown in FIG. FIG. 4 is a flowchart (part 2) for explaining the process in the semiconductor memory device shown in FIG. FIG. 5 is a flowchart (No. 3) for explaining the process in the semiconductor memory device shown in FIG. FIG. 6 is a diagram (part 1) for explaining an example of processing in the semiconductor memory device shown in FIG. FIG. 7 is a diagram (No. 2) for explaining an example of the process in the semiconductor memory device shown in FIG. FIG. 8 is a diagram (No. 3) for explaining an example of the process in the semiconductor memory device shown in FIG.

  First, before describing in detail an embodiment of a semiconductor memory device and an access control method for the semiconductor memory device according to the present embodiment, an example of the semiconductor memory device and problems in the semiconductor memory device will be described with reference to FIG. To do.

  FIG. 1 is a block diagram illustrating an example of a semiconductor memory device, and illustrates an example of a RAM provided with an ECC function. As shown in FIG. 1, the semiconductor memory device 100 includes a RAM (memory unit) 101 and an error detection / correction circuit (ECC circuit) 102.

  First, when data is written to the RAM 101, write data (write) is input to the RAM 101 and written. When reading data written in the RAM 101, the data from the RAM 101 is input to the ECC circuit 102, errors are detected and corrected, and error-corrected read data (read) is output from the ECC circuit 102. Is done.

  As described above, the semiconductor memory device 100 shown in FIG. 1 can output error-corrected correct data (read) by outputting the data read from the RAM 101 via the ECC circuit 102. Here, an error in data read from the RAM 101 occurs due to various factors such as a software error in the RAM 101 or a data error due to deterioration over time.

  However, in the semiconductor memory device 100 shown in FIG. 1, for example, when data is read from the RAM 101, the data always passes through the ECC circuit 102, and the latency is higher than that in which data is directly read without providing the ECC circuit. It gets bigger.

  Further, in order to correct the error data by the ECC circuit 102, redundant ECC data is used, so that, for example, the capacity of the RAM 101 is excessively consumed. That is, by using ECC data, the memory capacity that can actually be used is reduced. Such a problem is not limited to the RAM, and similarly exists in various other semiconductor memory devices including a flash memory.

  Hereinafter, embodiments of a semiconductor memory device and an access control method for the semiconductor memory device will be described in detail with reference to the accompanying drawings. FIG. 2 is a block diagram illustrating an example of the semiconductor memory device according to this embodiment.

  As shown in FIG. 2, the semiconductor memory device 1 includes a RAM (memory unit) 11, a write side bit rearrangement circuit (first rearrangement circuit) 21, an error detection circuit 22, and a rearrangement information generation circuit 23. Further, the semiconductor memory device 1 includes an information storage register 24, an information reflection register 25, and a read side bit rearrangement circuit (second rearrangement circuit) 26.

  The write side bit rearrangement circuit 21 receives data to be written in the RAM 11, performs bit rearrangement (data rearrangement) described in detail later, and outputs write data (write) to the RAM 11.

  The error detection circuit 22 detects errors in the data read from the RAM 11, and the rearrangement information generation circuit 23 generates rearrangement information based on the output of the error detection circuit 22 and stores it in the information storage register 24.

  Here, the error detection and the generation of the rearrangement information may always be performed, but may be performed every predetermined period, for example. Note that the period during which error detection and rearrangement information are generated can be set according to the environment in which the RAM 11 is used.

  The information reflection register 25 receives the rearrangement information stored in the information storage register 24, feeds it back to the write side bit rearrangement circuit 21, and outputs it to the read side bit rearrangement circuit 26.

  Here, the data read from the RAM 11 does not pass through the ECC circuit 102 as described with reference to FIG. 1, but passes through the read-side bit rearrangement circuit 26 that performs simple bit rearrangement processing, so that the data is read at high speed. Can be Further, the error detection circuit 11 is operated separately from the data reading process from the RAM 11 to specify a defective bit in the RAM 11.

  The defective bit information specified by the error detection circuit 11 is output to the rearrangement information generation circuit 23, and is used, for example, when the RAM 11 is used next time. That is, the rearrangement information generation circuit 23 generates rearrangement information such as replacing the lower bits with normal bits only when a defective bit is located in the upper part of the multi-bit data, and stores the rearrangement information in the information storage register 24.

  Further, for example, when the RAM 11 is used next time, the rearrangement information generated last time stored in the information storage register 24 is loaded into the information reflection register 25 before data writing to the RAM 11 is started.

  Then, the rearrangement information generated last time loaded in the information reflection register 25 is output to the write side bit rearrangement circuit 21 and the read side bit rearrangement circuit 26 to reflect the rearrangement information.

  Note that the rearrangement information (previous rearrangement information) generated by the rearrangement information generation circuit 23 is saved in a nonvolatile storage device such as a flash memory, and the data of the nonvolatile storage device is reflected in the information. You may make it load to the register | resistor 25. FIG. In this case, for example, the bit rearrangement process can be performed immediately after the power is turned on.

  Here, the application of the present embodiment is limited to, for example, data processing in which single-bit defects such as image data do not significantly affect the whole. That is, in this embodiment, as will be described in detail later, when an error occurs in the upper bits of the multi-bit data, a bit rearrangement process is performed in which the error bits are replaced with lower bits in which no error has occurred. is there.

  Also, for example, in image data, error detection target bits for error detection are only upper bits (for example, upper 8 bits in 16-bit data) that have a great influence on data quality among multi-bit data. This is preferable for speeding up the processing. Next, each process described above will be described in detail with reference to FIGS.

  3 to 5 are flowcharts for explaining processing in the semiconductor memory device shown in FIG. Here, FIG. 3 is for explaining an example of data writing processing to the RAM (memory unit) 11, and FIG. 4 is for explaining an example of data reading processing from the RAM 11. FIG. 5 is a diagram for explaining an example of processing for generating rearrangement information based on data read from the RAM 11.

  First, as shown in FIG. 3, when the data writing process to the RAM 11 is started, the bit rearrangement information is reflected from the information storage register to each arrangement circuit in step ST11, and the process proceeds to step ST12.

  That is, in step ST11, the rearrangement information stored in the information storage register 24 is loaded into the information reflection register 25 and reflected on the write side bit rearrangement circuit 21 and the read side bit rearrangement circuit 26.

  In step ST12, it is determined whether or not the bit rearrangement information (write side) exists. If it is determined that the bit rearrangement information (write side) does not exist, the process proceeds to step ST14, and the RAM is read. Write data.

  For example, when there is no bit rearrangement information to be processed by the write side bit rearrangement circuit 21 due to the first write processing of the RAM 11 or no defect in the upper bits of the RAM 11, the input write data is Then, it is written in the RAM 11 as it is.

  If it is determined in step ST12 that bit rearrangement information (write side) is present, the process proceeds to step ST13, after bit rearrangement, the process proceeds to step ST14, and the data subjected to bit rearrangement is stored in the RAM 11 Write to.

  For example, if bit rearrangement information exists due to a defect detected in the upper bits in the first write processing of the RAM 11, the write side bit rearrangement circuit 21 performs bit rearrangement processing according to the bit rearrangement information. After that, the data is written into the RAM 11. In step ST14, when data is written to the RAM 11, the data writing process to the RAM 11 is completed.

  Next, as shown in FIG. 4, when the data read process from the RAM 11 is started, the error read circuit checks the RAM read data in step ST21, and the process proceeds to step ST22.

  That is, in step ST21, the data read from the RAM 11 is checked by the error detection circuit 22, and the process proceeds to step ST22 to determine whether or not there is a bit error in the read data.

  If it is determined in step ST22 that there is no bit error in the read data, the process proceeds to step ST25. On the other hand, if it is determined that there is a bit error in the read data, the process proceeds to step ST23 to determine whether a bit error exists in the upper bits. judge.

  If it is determined in step ST23 that a bit error does not exist in the upper bits, the process proceeds to step ST25, whereas if it is determined that a bit error exists in the upper bits, the process proceeds to step ST24.

  In step ST24, rearrangement information of the error target bit and the normal bit is generated, stored in the information storage register, and the process proceeds to step ST25. The generation of the rearrangement information of the error target bit and the normal bit in step ST24 will be described in detail later with reference to FIGS.

  In step ST24, it is determined whether or not the data reading is completed. If it is determined that the data reading is not completed, the process returns to step ST21 to repeat the same processing. Otherwise, the data reading processing from the RAM 11 is terminated. .

  Further, as shown in FIG. 5, when the process of generating the rearrangement information based on the data read from the RAM 11 is started, the bit rearrangement information is reflected from the information storage register to each arrangement circuit in step ST31, and step ST32 is performed. Proceed to

  That is, in step ST31, the rearrangement information stored in the information storage register 24 is loaded into the information reflection register 25 and reflected in the write side bit rearrangement circuit 21 and the read side bit rearrangement circuit 26.

  In step ST32, it is determined whether or not the bit rearrangement information (reading side) exists. If it is determined that the bit rearrangement information (reading side) does not exist, the process proceeds to step ST34 as it is and data transmission is performed to the subsequent stage. To do.

  For example, when there is no defective bit in the RAM 11 or there is no defect in the upper bits of the RAM 11, the read data is read when there is no bit rearrangement information to be processed by the read side bit rearrangement circuit 26. Is output to the subsequent stage as it is.

  If it is determined in step ST32 that the bit rearrangement information (reading side) is present, the process proceeds to step ST33 to perform bit rearrangement, and then proceeds to step ST34 to transmit data to the subsequent stage.

  For example, when there is a defect in the upper bits of the RAM 11 and there is bit rearrangement information processed by the read side bit rearrangement circuit 26, the read side bit rearrangement circuit 26 performs a bit rearrangement process according to the bit rearrangement information. I do.

  The bit rearrangement processing by the read side bit rearrangement circuit 26 will be described in detail below with reference to FIGS. 6 to 8 together with the generation of the rearrangement information of the error target bit and the normal bit in step ST24.

  6 to 8 are diagrams for explaining an example of processing in the semiconductor memory device shown in FIG. That is, FIGS. 6 to 8 illustrate an example of generation of rearrangement information by the rearrangement information generation circuit 23 and rearrangement processing by the write side bit rearrangement circuit 21 and the read side bit rearrangement circuit 26. Is.

  Here, FIGS. 6 to 8 are for explaining processing when writing / reading the write data of the hexadecimal number “5555” to / from the memory unit (RAM 11), but this is merely an example. It goes without saying that various modifications and changes are possible. The hexadecimal number “5555” corresponds to the binary number “0101010101010101”.

  FIG. 6 shows a storage area of 16-bit data in the memory (RAM 11) for displaying the binary number “0101010101010101” corresponding to the hexadecimal number “5555”. In the following description, error detection and countermeasures are performed on the upper 8 bits (bit: “15” to “8”) out of 16 bits, and the lower 8 bits (bit: “7” to “0”) are It will be described as not subject to error detection.

  Specifically, for example, in the YCBCR system, the amount of information of the chromaticity signal can be reduced based on the property that “the human eye is sensitive to changes in brightness but insensitive to changes in color”. . For such image parameters that are relatively insignificant, it is considered that the influence on the image quality is small even if error detection is limited to some upper bits. In addition, it is known that in the case of moving images, for example, even if a pixel error exists in an image of several tens of frames per second, it is difficult to determine.

  For this reason, for example, even if the error bit detection range is narrowed to a certain upper bit for continuous data of an image, it is difficult to notice visually. In other words, when a bit error is detected, bit rearrangement is performed in the next frame, so there is little concern. The same applies to a still image used as a live view before shooting.

  That is, when error detection and rearrangement information generation are always performed, for example, correction (rearrangement of bits) is performed for each frame, so that pixel errors in the frame are not continuous and are not conspicuous.

  In addition, since the camera performs live view display before shooting, for example, pixel errors at that time are not recorded, and there is no problem from that aspect. For example, if the first few frames of the live view flow, it will settle in the optimal state (all errors are collected in the lower bits), so the error will not be noticeable when recording a video or shooting a still image. Become.

  As described above, in the application of this embodiment, among multi-bit data (for example, 16-bit data), the upper bits (for example, the upper 8 bits) greatly affect the data quality, but the lower bits (for example, the least significant bits) Etc.) is preferably image data that hardly affects the data quality.

  In addition, as described above, the number of bits for error correction (error target bits) can be further reduced. For example, even if the probability of error occurrence in a 16-bit RAM is estimated to be 4 bits, If the check is divided into four at times, the optimum state can be maintained in four frames. The application of the present embodiment is not limited to such live view image data of the camera.

  Thus, for example, even if a bit error occurs in image data, the higher the bit is, the greater the influence on the image quality, and the lower the bit, the less the influence on the image quality. Based on this, in the following description, it is assumed that error detection and handling are performed on the upper 8 bits of 16-bit image data that have a large influence on image quality.

  That is, in FIGS. 7 and 8, the second bit (bit: “14”) from the most significant bit in the 16-bit memory area (RAM 11) is a failure bit. Specifically, the data is fixed to “0”. Will be described.

  FIG. 7 shows the first processing (first access) to the RAM 11 and shows a case where the hexadecimal number “5555” is written to the RAM 11 (16-bit memory area) and then read. .

  First, in the first process, as shown in FIG. 7A, for example, a hexadecimal number “0000” is written, or the initial 16-bit memory area (11) is changed to FIG. As shown in (b), hexadecimal data “5555” is written.

  At this time, as shown in FIG. 7C, the second bit from the most significant bit (bit: “14”) is faulty (fixed to “0”), so the original binary data “0101010101010101” is , “00010101010101” is stored in the memory area.

  Further, as shown in FIG. 7D, when reading is performed, “0001010101010101” in which the second-bit data from the most significant bit is “0” is read from the memory area. The binary number data “0001010101010101” corresponds to the hexadecimal number data “1555”.

  By this first processing, it can be confirmed that there is an error in the upper bits (second bit from the most significant bit). The error bit can be detected by an error detection circuit 22 (for example, an error detection unit in the ECC circuit). Alternatively, the error bit can be easily detected by comparing the write data “5555” and the read data “1555” as the initial process.

  When a failure of the upper bit is detected in the first process, rearrangement information for replacing the upper bit of the failure with a normal lower bit is generated. Then, it is reflected in the write side bit rearrangement circuit 21 and the read side bit rearrangement circuit 26 in the second and subsequent processes (second and subsequent accesses).

  That is, in the present embodiment, the error detection circuit 22 simply detects an error bit and does not require an error bit correction function like an ECC circuit, and thus can be realized with a simple circuit configuration. Further, since it is not necessary to output read data via the ECC circuit every time, an increase in latency can be reduced.

  The reflection of the rearrangement information by the write side bit rearrangement circuit 21 and the read side bit rearrangement circuit 26 is different from the error detection / correction processing by the ECC circuit, and is simply a bit (data) as described in detail below. It will be enough to rearrange.

  FIG. 8 shows the second and subsequent processing for the RAM 11. For example, if the rearrangement information generated by the rearrangement information generation circuit 23 in the first process is saved in a nonvolatile storage device such as a flash memory, the rearrangement information can be used. Bits can be rearranged from the beginning (at startup).

  Also in FIG. 8, similarly to the first process for the memory area described with reference to FIG. 7, the process when the hexadecimal data “5555” is written and then read is shown.

  First, in the second and subsequent processing, as shown in FIGS. 8A to 8C, for example, the second bit (bit: “14” from the most significant bit that has failed (fixed to “0”) is used. ”) Data (“ 1 ”) is written in the normal least significant bit (bit:“ 0 ”). Note that data (“1”) that is originally written to the least significant bit is written to the second bit from the most significant failure.

  That is, the rearrangement information generation circuit 23 replaces the least significant bit with the second most significant bit based on, for example, information that the second most significant bit detected by the error detection circuit 22 is the error bit. Generate sort information for (sort).

  The rearrangement information generated by the rearrangement information generation circuit 23 is stored in the information storage register 24 and is loaded from the information storage register 24 to the information reflection register 25 when the second and subsequent processes are performed.

  When data is written, the write side bit rearrangement circuit 21 rearranges the second bit from the most significant bit and the least significant bit based on the rearrangement information held in the information reflection register 25 and then writes the data. .

  When a plurality of error bits, for example, two bits “14” and “13” are detected, the bits “14” and “0” are rearranged and the bits “13” and “1” are rearranged. "Is also rearranged.

  Here, as lower bits (rearrangement bits) for replacing the detected upper error bits, “1, 2,...” Is set (selected) from the least significant bit “0” to the upper order. Is preferred. However, from the viewpoint of the error occurrence probability, in most cases, only the rearrangement by the least significant bit “0” is usually sufficient.

  Again, when only the bit “14”) is defective, for example, when the hexadecimal data “5555” is written, the binary data “010101010101010101” in which the bits “14” and “0” are rearranged is written. Is written.

  Here, as shown in FIG. 8D, the bit “14” (second bit from the most significant bit) in the 16-bit memory area is an error bit and its data is fixed to “0”. That is, as shown in FIG. 8E, the data stored in the memory area is “0001010101010101”.

  Then, as shown in FIG. 8 (f), when reading is performed, the data “0001010101010101” read from the memory area (RAM 11) is input to the read-side bit rearrangement circuit 26, and the bit “14” is obtained. Rearrangement of “0” is performed.

  That is, the read-side bit rearrangement circuit 26 performs rearrangement for returning the rearrangement at the time of writing based on the rearrangement information held in the information reflection register 25, that is, bits “14” and “0”. Replace the data of and output.

  As a result, the data (binary number data) output from the read side bit rearrangement circuit 26 becomes “0101010101010100”. This corresponds to hexadecimal data “5554”.

  As described above, the rearrangement information held in the information reflection register 25 is reflected on the write side bit rearrangement circuit 21 and the read side bit rearrangement circuit 26, whereby the hexadecimal data “5555” is read as “5554”. be able to.

  According to this embodiment, the write side and read side bit rearrangement circuits simply perform bit rearrangement (data rearrangement). For example, error detection / correction via the ECC circuit. Data can be read out much faster than the above.

  Also, by excluding lower-order bits that are less affected from multi-bit data from error detection, redundant data stored in the ECC RAM can be reduced, resulting in a reduction in the capacity of the mounted RAM. It becomes possible to do.

  That is, according to the present embodiment, it is possible to increase the reading speed of the RAM data, reduce the area occupied by the circuit and reduce the power consumption by reducing the mounted RAM. Further, for example, even when a specific bit of the RAM becomes unusable during use due to deterioration over time, the data bit rearrangement can suppress the influence on the data quality at the next use.

  The application of the present embodiment is not limited to the write / read processing for the RAM, and can be applied to various other semiconductor memory devices such as a flash memory.

  Furthermore, the data to which the present embodiment is applied is not limited to image data. For example, single-bit defects do not have a significant effect on the whole, and the effect is that the upper bits of the multi-bit data are larger and the lower bits. It may be various data such as small.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention. Nor does such a description of the specification indicate an advantage or disadvantage of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
A memory section;
A first rearrangement circuit that receives a plurality of bits of data, rearranges a first bit in which an error is detected in the data into a second bit in which no error is detected, and stores the first bit in the memory unit;
A second rearrangement circuit that receives data read from the memory unit and outputs the second bit data rearranged with the first bit data;
A semiconductor memory device.

(Appendix 2)
The first bit is a higher order bit than the second bit.
2. The semiconductor memory device according to appendix 1, wherein:

(Appendix 3)
The second bit is the least significant bit of the data.
The semiconductor memory device as set forth in Appendix 2, wherein

(Appendix 4)
When there are a plurality of the first bits,
The second bits are selected in order from the least significant bit to the higher order.
The semiconductor memory device according to appendix 3, wherein

(Appendix 5)
further,
An error detection circuit for receiving data read from the memory unit and detecting an error in the memory unit;
The first and second rearrangement circuits operate based on the output of the error detection circuit.
The semiconductor memory device according to any one of appendix 1 to appendix 4, which is characterized in that.

(Appendix 6)
further,
A rearrangement information generation circuit for generating rearrangement information for controlling operations of the first and second rearrangement circuits based on an output of the error detection circuit;
An information storage register for storing the rearrangement information generated by the rearrangement information generation circuit;
The semiconductor memory device according to appendix 5, wherein:

(Appendix 7)
further,
An information reflecting register that reads out the rearrangement information stored in the information storage register and reflects the rearrangement information in the first rearrangement circuit and the second rearrangement circuit;
The semiconductor memory device according to appendix 6, wherein:

(Appendix 8)
The plurality of bits of data is image data;
The memory unit is a RAM.
8. The semiconductor memory device according to any one of appendix 1 to appendix 7, which is characterized in that.

(Appendix 9)
Receiving a plurality of bits of data for the memory unit, rearranging the first bit in which an error is detected in the data into a second bit in which no error is detected, and storing the second bit in the memory unit;
Receiving data read from the memory unit and outputting the second bit data rearranged with the first bit data;
An access control method for a semiconductor memory device.

(Appendix 10)
The first bit is a higher order bit than the second bit.
The access control method for a semiconductor memory device according to appendix 9, wherein:

(Appendix 11)
The second bit is the least significant bit of the data.
12. The access control method for a semiconductor memory device according to appendix 10, wherein:

(Appendix 12)
When there are a plurality of the first bits,
The second bits are selected in order from the least significant bit to the higher order.
The access control method for a semiconductor memory device according to appendix 11, wherein

(Appendix 13)
further,
Receiving data read from the memory unit, detecting errors in the memory unit;
The first and second rearrangement circuits operate based on the output of the error detection circuit.
13. The access control method for a semiconductor memory device according to any one of appendix 9 to appendix 12, wherein the access control method is used.

(Appendix 14)
The plurality of bits of data is image data;
The memory unit is a RAM.
14. The access control method for a semiconductor memory device according to any one of appendix 9 to appendix 13, which is characterized in that

1,100 Semiconductor memory device 11,101 RAM (memory unit)
21 Write side bit rearrangement circuit (first rearrangement circuit)
22 error detection circuit 23 rearrangement information generation circuit 24 information storage register 25 information reflection register 26 read side bit rearrangement circuit (second rearrangement circuit)
102 Error detection / correction circuit

Claims (5)

A memory section;
A first rearrangement circuit that receives a plurality of bits of data, rearranges a first bit in which an error is detected in the data into a second bit in which no error is detected, and stores the first bit in the memory unit;
Receiving said data read out from the memory unit, the data of the second bit, have a, a second rearrangement circuit which outputs instead data and arrangement of the first bit,
The first bit is a bit higher than the second bit;
The second bit is the least significant bit of the data;
When there are a plurality of the first bits,
The second bit is Ru are selected in this order toward the top from the least significant bit,
A semiconductor memory device. further,
An error detection circuit for receiving data read from the memory unit and detecting an error in the memory unit;
The first and second rearrangement circuits operate based on the output of the error detection circuit.
The semiconductor memory device according to claim 1 . The plurality of bits of data is image data;
The memory unit is a RAM.
The semiconductor memory device according to claim 1 , wherein: Receiving a plurality of bits of data for the memory unit, rearranging the first bit in which an error is detected in the data into a second bit in which no error is detected, and storing the second bit in the memory unit;
Receives data read from the memory unit, outputs the second bit data rearranged with the first bit data ,
The first bit is a bit higher than the second bit;
The second bit is the least significant bit of the data;
When there are a plurality of the first bits,
The second bit is Ru are selected in this order toward the top from the least significant bit,
An access control method for a semiconductor memory device. further,
Receiving data read from the memory unit, detecting errors in the memory unit;
The first and second rearrangement circuits operate based on the output of the error detection circuit.
The method of controlling access to a semiconductor memory device according to claim 4 .

Images