JP6499602B2 - AD conversion result reading circuit - Google Patents

Description

  The present invention relates to an AD conversion result reading circuit for reading an AD conversion result from an AD converter.

  In a conventional general ΔΣ type AD converter, when an AD conversion result is read from a CPU (Central Processing Unit) or the like by an SPI (Serial Peripheral Interface), the DRDY signal indicating the conversion state is monitored, and the falling of the DRDY signal is detected. The specification is that the SPI master must be designed so that the AD conversion result is read out after detection until the next conversion is completed (see Non-Patent Document 1 and Non-Patent Document 2).

  There is such a restriction because if the falling edge of the DRDY signal is detected, the timing of reading the conversion result of the SPI master is delayed due to other processing factors, and the next update of the AD conversion result and the SPI master This is because the read AD conversion result becomes an indeterminate value if the reading of the data is collided. Furthermore, since there is no method for determining / confirming that the value has been destroyed and an indeterminate value is provided in the AD converter, there is absolutely no delay in timing when reading the AD conversion result, and the CPU designer is extremely strict. Time management had to be done.

“24-bit A / D converter ADS1248 for temperature sensors”, Texas Instruments Japan, 2011, <http://www.tij.co.jp/jp/lit/ds/symlink/ads1248.pdf> “20 μs settling, 250 kSPS 24-bit Σ-Δ ADC AD7176-2”, Analog Devices, Inc., 2012, <http://www.analog.com/media/jp/technical-documentation/data-sheets/AD7176 -2_en.pdf>

  As described above, conventionally, a designer who wants to design an SPI master that reads out the AD conversion result has to perform extremely strict time management, and the burden of timing design is large. I had to select my CPU.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an AD conversion result reading circuit that can reduce a designer's timing design burden and can reduce the required performance of a CPU. .

  The AD conversion result reading circuit of the present invention makes the detection signal valid when it receives a high-order bit of a command from an external device that is a transmission destination of the AD conversion result of the AD converter and determines that it is a read command. A detection circuit that validates the transmission permission signal when all the commands are received and confirmed as a read command, and an internal register synchronized with the clock of the AD converter in accordance with the detection signal synchronized with the clock of the external device AD conversion of the AD converter when the clock change circuit for outputting the value change prohibition signal and the data preparation completion signal from the AD converter are valid and the internal register value change prohibition signal is invalid A first AD conversion result register for fetching a result and the first AD conversion result register when the transmission permission signal is valid; It is characterized in further comprising a data transmitting circuit for transmitting read the AD conversion result to the external device from the data.

Further, according to one configuration example of the AD conversion result reading circuit of the present invention, when the data preparation completion signal from the AD converter is valid and the internal register value change prohibiting signal is valid, A second AD conversion result register for fetching an AD conversion result of the converter; and the first AD conversion result register is configured to store the second AD conversion result signal when the internal register value change prohibition signal becomes invalid. The output of the conversion result register is fetched.
Further, in one configuration example of the AD conversion result reading circuit of the present invention, when the data preparation completion signal from the AD converter is valid and the internal register value change prohibition signal is invalid, A first identification data register for fetching identification data associated with a conversion result from the AD converter; and the data transmission circuit includes the first AD conversion result when the transmission permission signal is valid. The AD conversion result is read from the register for use and transmitted to the external device, and the identification data is read from the first register for identification data and transmitted to the external device.
The AD conversion result read circuit according to the present invention further includes a configuration example in which when the data preparation completion signal from the AD converter is valid and the internal register value change prohibition signal is valid, the identification A second identification data register for fetching data; and the first identification data register fetches an output of the second identification data register when the internal register value change prohibition signal becomes invalid. It is characterized by this.

In one configuration example of the AD conversion result read circuit according to the present invention, when the detection circuit receives all commands from the external device and determines that the command is not a read command after enabling the detection signal, The detection signal is invalidated.
In one configuration example of the AD conversion result reading circuit according to the present invention, the identification data is data indicating the number of executions of AD conversion processing by the AD converter.
In one configuration example of the AD conversion result reading circuit according to the present invention, the identification data is data indicating a time when AD conversion processing is executed by the AD converter.
In one configuration example of the AD conversion result reading circuit of the present invention, the identification data is 1-bit data whose logic level is inverted every time AD conversion processing is executed by the AD converter.
In one configuration example of the AD conversion result reading circuit of the present invention, the identification data is data based on a count value of a free-run counter.

  According to the present invention, by providing the detection circuit, the clock transfer circuit, the first AD conversion result register, and the data transmission circuit, the AD conversion result can be transferred to the external device without giving any special restriction to the external device. It is possible to reduce the burden on the timing design of the designer, and the required performance of the external device (CPU) can be relaxed. Further, according to the present invention, the AD conversion result can be prevented from becoming an indefinite value, and the AD conversion result can be protected without increasing the frequency of the clock of the AD converter.

  Also, in the present invention, by providing the second AD conversion result register, it is possible to avoid occurrence of missing AD conversion results.

  In the present invention, the first identification data register is provided, and when the data transmission circuit has a valid transmission permission signal from the detection circuit, the identification data is read from the first identification data register and sent to the external device. By transmitting, it is possible for the external device side to determine whether or not the AD conversion results are redundantly acquired and whether or not the AD conversion results are missed.

  Further, in the present invention, by providing the second identification data register, it is possible to avoid occurrence of missing identification data.

1 is a block diagram showing a configuration of an AD conversion result read circuit according to a first embodiment of the present invention. 5 is a flowchart for explaining the operation of the READ detection circuit of the AD conversion result reading circuit according to the first embodiment of the present invention. 5 is a timing chart for explaining the operation of each part of the AD conversion result read circuit according to the first embodiment of the present invention. It is a block diagram which shows the structural example of the clock transfer circuit of the AD conversion result reading circuit which concerns on the 1st Embodiment of this invention. It is a timing chart explaining the timing relationship for preventing a metastable state. It is a timing chart explaining the timing relationship for preventing a metastable state. 10 is a timing chart showing an operation when the clock frequency on the AD converter side is increased in the conventional AD conversion result reading circuit. 6 is a timing chart for explaining the operation of each part of the AD conversion result read circuit according to the second embodiment of the present invention. It is a block diagram which shows the structure of the AD conversion result read-out circuit based on the 3rd Embodiment of this invention.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an AD conversion result reading circuit according to the first embodiment of the present invention. The AD conversion result reading circuit of the present embodiment includes AD conversion result registers 2 and 3 for temporarily storing the AD conversion result of the AD converter (hereinafter referred to as ADC) 1 and an SPI master 7 which is an external device. A READ detection circuit 4 that validates a detection signal when receiving a high-order bit of a command and determines that the command is a read command, and validates a transmission permission signal when all commands from the SPI master 7 are received and confirmed as a read command; In response to a detection signal synchronized with the clock of the SPI master 7, a clock transfer circuit 5 that outputs an internal register value change prohibition signal synchronized with the clock of the ADC 1, and an AD conversion result when the transmission permission signal is valid It comprises a data transmission circuit 6 that reads the AD conversion result from the register 2 and transmits it to the SPI master 7.

  In the present invention, providing two AD conversion result registers is not an essential component. First, the operation of the AD conversion result reading circuit when only the AD conversion result register 2 is used will be described with reference to FIGS. FIG. 2 is a flowchart for explaining the operation of the READ detection circuit 4. FIG. 3 is a timing chart for explaining the operation of each part of the AD conversion result reading circuit.

  In this embodiment, the clock of ADC 1 is CLK_REG, and the clock of SPI master 7 is SCLK. In the configuration of the AD conversion result readout circuit shown in FIG. 1, the AD conversion result registers 2 and 3 and the clock transfer circuit 5 operate in synchronization with CLK_REG, and the READ detection circuit 4 and the clock transfer circuit 5 The data transmission circuit 6 operates in synchronization with SCLK.

  In FIG. 3, CS is a chip select signal, MOSI (Master Out Slave In) and MISO (Master In Slave Out) are signal lines of the SPI master 7, SCLK_INV is an inverted signal of the clock SCLK, READ_ACT is a detection signal of a read command, and RDATA_EN is RDATA_EN AD conversion result transmission permission signal, READ_ACT_SYNC is an internal register value change prohibition signal, DRDY is a data preparation completion signal of ADC1, RESULT is an AD conversion result output from ADC1, and RESULT_BUF is an AD conversion result stored in the AD conversion result register 3 The conversion result, RESULT_LATCH, is the AD conversion result stored in the AD conversion result register 2.

  First, when a command is sent from the SPI master 7 comprising the CPU via the signal line MOSI, the READ detection circuit 4 receives the upper 3 bits of the command (step S1 in FIG. 2), and the upper 3 of the command. It is determined whether the bit matches the upper 3 bits of the RDATA * command, that is, the upper 3 bits of the read command of the AD conversion result (step S2 in FIG. 2). In the example of FIG. 3, C7 to C5 are the upper 3 bits of the command, and determination is performed at time t1. The reason for performing the determination with the upper 3 bits will be described later.

  When the upper 3 bits of the command from the SPI master 7 match the upper 3 bits of the read command (Y in step S2), the READ detection circuit 4 sets the detection signal READ_ACT to “1” (valid) (FIG. 2). Step S3).

  Further, when the READ detection circuit 4 receives the lower 5 bits of the command from the SPI master 7, it means that all of the 8-bit commands have been received (step S4 in FIG. 2), so that the 8-bit command is an RDATA * command, That is, it is determined whether or not the read command of the AD conversion result matches (step S5 in FIG. 2). In the example of FIG. 3, C4 to C0 are the lower 5 bits of the command.

  When the 8-bit command from the SPI master 7 matches the read command (Y in step S5), the READ detection circuit 4 keeps the detection signal READ_ACT to “1” (step S6 in FIG. 2), and the transmission enable signal RDATA_EN. 1 pulse is issued.

  When one pulse of the transmission enable signal RDATA_EN is issued, the data transmission circuit 6 reads the AD conversion result for 8 bits from the AD conversion result register 2 (step S7 in FIG. 2), and the AD conversion result for 8 bits is obtained. Serial transmission is performed to the SPI master 7 via the signal line MISO (step S8 in FIG. 2). In the example of FIG. 3, the AD conversion result for 8 bits D0 to D7 is transmitted to the SPI master 7 in response to the transmission permission signal RDATA_EN at time t3.

  Next, the READ detection circuit 4 determines whether or not the transmission of the number of data corresponding to the command has been completed (step S9 in FIG. 2). If the transmission has not been completed (N in step S9), step S7 is performed. , The transmission permission signal RDATA_EN is issued again by one pulse, and the data transmission circuit 6 reads the AD conversion result for 8 bits from the AD conversion result register 2 and serially transmits it to the SPI master 7 (step S8). In the example of FIG. 3, the AD conversion result for 8 bits D8 to D15 is transmitted to the SPI master 7 in response to the transmission permission signal RDATA_EN at time t4.

  Thus, the processes in steps S7 and S8 are repeatedly executed until the transmission of the number of data corresponding to the command is completed. In this embodiment, the AD conversion result sent in response to the read command from the SPI master 7 is 24 bits. Accordingly, when the transmission permission signal RDATA_EN is issued three times and the transmission of the 24-bit data D0 to D23 is completed, step S9 becomes a determination Y (time t5).

When the data transmission is completed, the READ detection circuit 4 sets the detection signal READ_ACT to “0” (invalid) (step S10 in FIG. 2).
The READ detection circuit 4 sets the detection signal READ_ACT to “0” even when the 8-bit command from the SPI master 7 does not match the read command (N in step S5 in FIG. 2). That is, even if the upper 3 bits of the command from the SPI master 7 coincide with the upper 3 bits of the read command in the determination in step S2, there is a possibility that the determination is incorrect. Therefore, if the command from the SPI master 7 is not a read command as a result of analyzing all 8-bit commands in step S5, the detection signal READ_ACT is set to “0” and the determination result obtained in steps S2 and S3. Cancel.

  Next, a configuration that operates in synchronization with the clock CLK_REG of the ADC 1 will be described. When the data preparation completion signal DRDY output from the ADC 1 falls from “1” (invalid) to “0” (valid), the AD conversion result register 2 is notified that the data preparation of the ADC 1 is completed. Since the internal register value change prohibition signal READ_ACT_SYNC at this time is “0” (invalid), indicating that a read command is not detected, the AD conversion result RESULT from the ADC 1 is fetched. As described above, the AD conversion result RESULT is 24 bits. Thus, the output RESULT_LATCH of the AD conversion result register 2 is updated. In the example of FIG. 3, it can be seen that RESULT_LATCH is updated from “OLD” indicating the old conversion result to “NEW” indicating the newly acquired conversion result.

  Next, the clock transfer circuit 5 generates an internal register value change prohibiting signal READ_ACT_SYNC synchronized with the clock CLK_REG in accordance with the detection signal READ_ACT output from the READ detection circuit 4. FIG. 4 is a block diagram showing a configuration example of the clock transfer circuit 5. The clock transfer circuit 5 includes two flip-flops 50 and 51.

  As described above, a method of receiving two stages with the clock on the receiving side is often used for the clock transposing process for a 1-bit signal. When such a method is used, the internal register value change prohibition signal READ_ACT_SYNC is delayed by a maximum of twice the period of CLK_REG with respect to the detection signal READ_ACT. In the example of FIG. 3, after the detection signal READ_ACT becomes “1” (valid) at time t1, the internal register value change prohibition signal READ_ACT_SYNC becomes “1” (valid) at time t2. Further, after the detection signal READ_ACT becomes “0” (invalid) at time t5, the internal register value change prohibition signal READ_ACT_SYNC becomes “0” (invalid) at time t6. The time difference between the times t1 and t2 and the time difference between the times t5 and t6 are delays due to the clock changing circuit 5 in FIG.

  If the SPI master 7 reads out the conversion result without considering the conversion cycle of the ADC 1, correct data may not be read out. The reason why the data is destroyed is that the relationship between the clock SCLK of the SPI master 7 and the clock CLK_REG of the ADC 1 is asynchronous, and when the data is transferred between different clocks, the rising edges of the two clocks happen to approach each other. This is because the setup / hold timing of the flip-flop cannot be satisfied. This phenomenon is called metastable. As for metastable, for example, the document “Column: Asynchronous Clock and Verification Method-2”, Altima Co., Ltd., <http://www.altima.jp/products/software/mentor/fv/column/cdc-2.html > ”.

  FIGS. 5 and 6 are timing charts for explaining the timing relationship for preventing the metastable state. FIG. 5 shows a case where the clock transfer time is short (when the clock CLK_REG rises immediately after the rise of the detection signal READ_ACT). FIG. 6 shows a case where the clock transfer time becomes long (when the detection signal READ_ACT rises immediately after the rise of the clock CLK_REG).

  In order to prevent the metastable state, the internal register value change prohibition signal READ_ACT_SYNC is set to “1” (valid) before the transmission timing of the AD conversion result to the SPI master 7, and the register value changes during transmission of the AD conversion result. Therefore, T1> T2 must be satisfied in FIGS. 5 and 6. T1 is a time from when the detection signal READ_ACT becomes “1” until the transmission permission signal RDATA_EN becomes “1” (valid), and T2 is a time required for clock switching.

In other words, when the determination execution cycle of the detection signal READ_ACT is N, it is necessary to determine the detection signal READ_ACT at a timing that satisfies the following expression (1).
SCLK cycle × (8−N)> CLK_REG cycle × 2 (1)
Here, since the command is 8 bits, the maximum value of N is 8.

  If the relationship between the frequency of the clock SCLK of the SPI master 7 and the clock CLK_REG of the ADC 1 is, for example, SCLK: CLK_REG = 1: 10, the detection signal READ_ACT is determined after receiving all commands (8 bits) from the SPI master 7. Even so, the AD conversion result can be transmitted to the SPI master 7 without giving any special restriction to the SPI master 7.

  FIG. 7 shows the operation when the frequency of the clock CLK_REG is sufficiently increased in the conventional AD conversion result reading circuit. In the example of FIG. 7, the detection signal READ_ACT is set to “1” after all the 8-bit commands C7 to C0 are read. In this way, if the clock CLK_REG is made sufficiently fast, the detection signal READ_ACT need not be set to “1” by prefetching. However, since the clock CLK_REG becomes high speed, there is a problem that power consumption increases.

  On the other hand, when the relationship between the frequency of SCLK and CLK_REG is SCLK: CLK_REG = 2: 1 as in the present embodiment, it is detected after simply receiving all 8 bits of the command in consideration of the time T2 required for clock replacement. The determination of the signal READ_ACT is not in time for the conversion result transmission timing. Therefore, in the present embodiment, the detection signal READ_ACT is determined in advance before receiving all the 8-bit commands. Assuming that the maximum frequency of the clock SCLK is twice the frequency of the clock CLK_REG as in the present embodiment, it is necessary to satisfy N <4 from Equation (1). Therefore, in this embodiment, N = 3. The above is the reason why the determination is made with the upper 3 bits of the command in step S2 of FIG.

  By determining the detection signal READ_ACT prior to receiving all 8-bit commands, the internal register value change prohibition signal READ_ACT_SYNC is always “1” when the transmission permission signal RDATA_EN becomes “1” (valid). Therefore, the output RESULT_LATCH of the AD conversion result register 2 does not change at the AD conversion result transmission timing (t3 and t4 in the example of FIG. 3). That is, no metastable occurs.

With the above configuration, in the present embodiment, it is possible to transmit the AD conversion result to the SPI master 7 without giving any special restriction to the SPI master 7, thereby reducing the timing design burden on the designer. And the required performance of the SPI master 7 (CPU) can be relaxed. In the present embodiment, the AD conversion result becomes an indeterminate value by not changing the output RESULT_LATCH of the AD conversion result register 2 at the timing when the transmission permission signal RDATA_EN becomes “1”. It is possible to prevent the AD conversion result without increasing the frequency of the clock CLK_REG of the ADC 1.
In the present embodiment, the determination in step S2 is performed with upper multiple bits, specifically, the upper 3 bits. However, the present invention is not limited to this. It is possible.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. In this embodiment, the AD conversion result register 3 is used in addition to the AD conversion result register 2 in the first embodiment. Also in this embodiment, the configuration of the AD conversion result reading circuit is the same as that of the first embodiment, and therefore, description will be made using the reference numerals in FIG. FIG. 8 is a timing chart for explaining the operation of each part of the AD conversion result readout circuit of this embodiment.

The operations of the READ detection circuit 4, the clock transfer circuit 5, and the data transmission circuit 6 are as described in the first embodiment.
As described in the first embodiment, the AD conversion result register 2 has an internal register in which the data preparation completion signal DRDY output from the ADC 1 falls from “1” (invalid) to “0” (valid). If the value change prohibition signal READ_ACT_SYNC is “0” (invalid), the AD conversion result RESULT of the ADC 1 is fetched (the output RESULT_LATCH of the AD conversion result register 2 is updated).

  However, in the example of the present embodiment, when the data preparation completion signal DRDY falls from “1” to “0”, the internal register value change prohibition signal READ_ACT_SYNC is already “1” (valid). The AD conversion result register 2 cannot take in the AD conversion result RESULT of the ADC 1 (the output RESULT_LATCH of the AD conversion result register 2 cannot be updated). That is, in the first and second embodiments, the interval in which the internal register value change prohibition signal READ_ACT_SYNC is “1” (valid) is the internal register value change prohibition interval.

  Therefore, in this embodiment, the AD conversion result register 3 is used. That is, in the AD conversion result register 3, the data preparation completion signal DRDY output from the ADC 1 falls from “1” (invalid) to “0” (valid), and the internal register value change prohibition signal READ_ACT_SYNC is “1”. If (valid), the AD conversion result RESULT of the ADC 1 is taken in. Thus, the output RESULT_BUF of the AD conversion result register 3 is updated. In the example of FIG. 8, it is understood that RESULT_BUF is updated to “NEW” indicating the newly acquired conversion result.

When the internal register value change prohibition signal READ_ACT_SYNC changes from “1” (valid) to “0” (invalid), the AD conversion result register 2 takes in the output RESULT_BUF of the AD conversion result register 3 (time t7). Thus, the output RESULT_LATCH of the AD conversion result register 2 is updated. In the example of FIG. 8, it can be seen that RESULT_LATCH is updated from “OLD” indicating the old conversion result to “NEW” indicating the newly acquired conversion result.
Other configurations are the same as those described in the first embodiment.

  In the first embodiment, when the data preparation completion signal DRDY output from the ADC 1 falls from “1” to “0”, the internal register value change prohibition signal READ_ACT_SYNC is already “1”. Then, since the AD conversion result register 2 cannot capture the AD conversion result of the ADC 1, there is a possibility that the AD conversion result may be missed. On the other hand, in the present embodiment, in a situation where the AD conversion result register 2 cannot capture the AD conversion result, the AD conversion result register 3 captures the AD conversion result. Occurrence of the result missing can be avoided.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 9 is a block diagram showing a configuration of an AD conversion result reading circuit according to the third embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The AD conversion result reading circuit according to the present embodiment includes AD conversion result registers 2 and 3, a READ detection circuit 4 a, a clock transfer circuit 5, a data transmission circuit 6 a, and identification data registers 8 and 9. Composed.

The ADC 1 of the present embodiment outputs identification data DID associated with the AD conversion result RESULT in addition to the AD conversion result RESULT.
The READ detection circuit 4a according to the present embodiment issues one pulse of a transmission permission signal RDATA_EN for transmitting, for example, 8-bit identification data DID after completing transmission of the AD conversion result for 24 bits (step S7 in FIG. 2). ). In response to the transmission permission signal RDATA_EN, the data transmission circuit 6a reads the identification data DID from the identification data register 8 and serially transmits it to the SPI master 7 (step S8 in FIG. 2).

  Thus, in the present embodiment, the processes of steps S7 and S8 in FIG. 2 are repeatedly executed until transmission of 8-bit identification data DID, that is, a total of 32 bits of data, in addition to the 24-bit AD conversion result is completed. become. In the example of FIGS. 3 and 8, for example, 8-bit identification data DID is transmitted after the transmission of 24-bit data D0 to D23. Other operations of the READ detection circuit 4a are the same as those of the READ detection circuit 4 of the first and second embodiments.

  Next, the operation of the identification data registers 8 and 9 will be described. In the identification data register 8, the data preparation completion signal DRDY output from the ADC 1 falls from “1” (invalid) to “0” (valid), and the internal register value change prohibition signal READ_ACT_SYNC is “0” (invalid). If so, the identification data DID output from the ADC 1 is captured. Thus, the output DID_LATCH of the identification data register 8 is updated.

  However, like the AD conversion result register 2, the identification data register 8 is already prohibited from changing the internal register value when the data preparation completion signal DRDY output from the ADC 1 falls from "1" to "0". When the signal READ_ACT_SYNC is “1” (valid), the identification data DID cannot be captured.

On the other hand, if the data preparation completion signal DRDY output from the ADC 1 falls from “1” to “0” and the internal register value change prohibition signal READ_ACT_SYNC is “1”, the identification data register 9 outputs from the ADC 1 The identification data DID is captured. Thus, the output DID_BUF of the identification data register 9 is updated.
The identification data register 8 takes in the output DID_BUF of the identification data register 9 when the internal register value change prohibition signal READ_ACT_SYNC changes from “1” to “0”.

  Thus, the identification data register 8 performs the same operation as the AD conversion result register 2 for the identification data DID, and the identification data register 9 performs the same operation as the AD conversion result register 3.

  Next, the identification data DID will be described in detail. Examples of the method for generating the identification data DID include the following four methods.

  The first example is a technique in which data based on the number of executions of AD conversion processing is used as identification data DID. Specifically, the number of executions of the AD conversion process may be counted in the ADC 1 and the count value may be used as the identification data DID. Thus, by recording the number of executions of the AD conversion process as the identification data DID, the AD conversion result by the AD conversion process executed at a certain timing and the AD conversion result by the AD conversion process executed at the timing before and after the AD conversion process are obtained. Can be identified.

  The second example is a technique in which data based on the execution time of AD conversion processing is used as identification data DID. Specifically, the ADC 1 may set the execution time (time stamp) of the AD conversion process as the identification data DID.

  As specific methods using the execution time of the AD conversion process, the following two examples can be exemplified. One is a method of providing a real-time clock inside or outside the ADC 1. The other is a method of providing a counter that is incremented at regular intervals, for example, at time 0 when the power is turned on, inside or outside the ADC 1 instead of the real-time clock.

  With either of the two methods described above, it is possible to distinguish between an AD conversion result by an AD conversion process executed at a certain timing and an AD conversion result by an AD conversion process executed at a timing before and after that. Furthermore, according to the above-described method using the real-time clock, it is possible to record the accurate time when the AD conversion process is executed. On the other hand, according to the technique that does not use the real-time clock described above, an increase in circuit scale can be suppressed.

  A third example is a technique in which 1-bit data whose logic level is inverted every time AD conversion processing is executed is used as identification data DID. According to this method, it is possible to identify an AD conversion result by an AD conversion process executed at a certain timing and an AD conversion result by an AD conversion process executed at a timing before and after the AD conversion process. Further, since the identification data DID is 1 bit, the necessary hardware resources can be reduced, and an increase in circuit scale can be suppressed.

  The fourth example is a technique in which data based on the count value of the free-run counter is used as identification data DID. For example, an 8-bit free-run counter may count pulses input continuously regardless of the execution process of the AD conversion process, and the count value may be used as the identification data DID. According to this, since a counter having a large bit width is not required, an increase in circuit scale can be suppressed. Note that the data stored as the identification data DID does not have to be the count value (numerical value) of the free-run counter itself, but may be an alphabet (character code) whose order is known, such as AZ.

  As described above, according to the present embodiment, identification data is assigned to each AD conversion result, and the AD conversion result and the identification data are output as a set, so that the acquired AD AD is received on the SPI master 7 side that received the AD conversion result. It is possible to determine whether or not the continuity of the conversion result is maintained.

  For example, by comparing the identification data corresponding to the acquired AD conversion result with the identification data corresponding to the AD conversion result acquired immediately before it, duplicate acquisition of AD conversion results in the same AD conversion cycle or missing of the AD conversion results It is possible for the SPI master 7 side to determine whether or not there is, that is, whether or not the continuity of the acquired AD conversion results is maintained.

  In this embodiment, the case where both the AD conversion result registers 2 and 3 are used is described. However, as described in the first embodiment, only the AD conversion result register 2 may be used. Good. As described above, in the first embodiment, there is a possibility that the AD conversion result may be missed. According to this embodiment, the SPI master 7 determines whether such a miss has occurred or not. Is possible.

  The present invention can be applied to a technique of reading an AD conversion result without considering the conversion cycle of the AD converter.

  DESCRIPTION OF SYMBOLS 1 ... AD converter, 2, 3 ... AD conversion result register, 4, 4a ... READ detection circuit, 5 ... Clock transfer circuit, 6, 6a ... Data transmission circuit, 7 ... SPI master, 8, 9 ... Identification data Registers, 50, 51 flip-flops.

Claims (9)

When the upper bit of the command from the external device that is the transmission destination of the AD conversion result of the AD converter is received and determined as a read command, the detection signal is validated, and all the commands from the external device are received and confirmed as the read command A detection circuit that validates the transmission permission signal when
A clock transfer circuit that outputs an internal register value change prohibition signal synchronized with the clock of the AD converter in response to the detection signal synchronized with the clock of the external device;
A first AD conversion result register for fetching an AD conversion result of the AD converter when a data preparation completion signal from the AD converter is valid and the internal register value change prohibition signal is invalid;
An AD conversion result reading circuit comprising: a data transmission circuit that reads an AD conversion result from the first AD conversion result register and transmits the AD conversion result to the external device when the transmission permission signal is valid. The AD conversion result read circuit according to claim 1,
Further, when a data preparation completion signal from the AD converter is valid and the internal register value change prohibition signal is valid, a second AD conversion result register for fetching the AD conversion result of the AD converter With
The AD conversion result read circuit, wherein the first AD conversion result register takes in an output of the second AD conversion result register when the internal register value change prohibition signal becomes invalid. The AD conversion result readout circuit according to claim 1 or 2,
Further, when the data preparation completion signal from the AD converter is valid and the internal register value change prohibition signal is invalid, the identification data associated with the AD conversion result is taken from the AD converter. A first identification data register;
The data transmission circuit reads an AD conversion result from the first AD conversion result register and transmits the AD conversion result to the external device when the transmission permission signal is valid, and from the first identification data register. An AD conversion result reading circuit, wherein identification data is read and transmitted to the external device. The AD conversion result read circuit according to claim 3,
And a second identification data register that takes in the identification data when the data preparation completion signal from the AD converter is valid and the internal register value change prohibition signal is valid,
The AD conversion result read circuit, wherein the first identification data register takes in an output of the second identification data register when the internal register value change prohibition signal becomes invalid. The AD conversion result read circuit according to claim 3 or 4 ,
The AD conversion result reading circuit, wherein the identification data is data indicating the number of times of AD conversion processing by the AD converter. The AD conversion result read circuit according to claim 3 or 4 ,
The AD conversion result reading circuit, wherein the identification data is data indicating a time when AD conversion processing is executed by the AD converter. The AD conversion result read circuit according to claim 3 or 4 ,
The AD conversion result reading circuit, wherein the identification data is 1-bit data whose logic level is inverted every time AD conversion processing is executed by the AD converter. The AD conversion result read circuit according to claim 3 or 4 ,
The AD conversion result reading circuit, wherein the identification data is data based on a count value of a free-run counter. In the AD conversion result read circuit according to any one of claims 1 to 8 ,
The detection circuit invalidates the detection signal when it receives all the commands from the external device and determines that the detection signal is not a read command after the detection signal is validated. .

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