JP6502829B2 - Gaming machine - Google Patents

Description

  The present invention relates to a gaming machine including a plurality of group unit control means for controlling an effect device divided into groups, and a group general control means for controlling a plurality of group unit control means.

  A conventional gaming machine is provided with a rendering device for rendering a game (see, for example, Patent Document 1).

JP, 2010-119669, A

  In the conventional gaming machine, the wiring between the group unit control means for controlling the rendering device and the group general control means for controlling the group unit control means can not be sufficiently reduced.

  An object of the present invention is to provide a gaming machine capable of reducing wiring between group general control means and group unit control means.

In one representative form of the present invention, a plurality of rendering devices are divided into a plurality of groups, group unit control means for controlling the rendering devices belonging to the divided groups are provided in each group, and the group unit control is performed Means for comprehensively controlling each of the means, and a power supply voltage is supplied to the data signal line and the timing signal line between the group general control means and the group unit control means, and the group unit control means The group general control means can transmit data to each of the group unit control means by connecting through a connector with a harness including a power supply line for supplying, and the group unit control means performs the data signal processing. When the initialization signal is input to the initialization signal input terminal provided separately from the line, the group First initialization means for initializing the control means, and, when the power supply to the group-unit control unit is started from the power supply line constituting the harness by reconnection of the harness, power the group-unit control unit itself A second initialization means for initializing based on a voltage rise due to supply is provided, and the group general control means is connected to an arithmetic processing means for performing arithmetic processing related to control of the rendering device, and the group unit control means And signal level control means for controlling each signal level of the data signal line with the group unit control means and the timing signal line based on a command from the arithmetic processing means. the signal level control means, the third initialization means for performing the power supply to the signal level control means starts its initialization, and the arithmetic processing hand The between the signal level control means, by providing an initialization signal line capable of transmitting an initialization signal, a fourth initializing means allowing the initialization of the signal level control means by said processing means and An effect control means capable of controlling an effect relating to a game based on a command from the game control means for controlling the game in an integrated manner is configured as the group unification control means.

  According to one aspect of the present invention, wiring between the group general control means and the group unit control means can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing of the game machine of the 1st Embodiment of this invention. FIG. 2 is a front view of the game board of the first embodiment of the present invention. It is an exploded perspective view of a center case of a 1st embodiment of the present invention. It is a figure which shows the state before the movable presentation apparatus of the 1st Embodiment of this invention operate | moves. As a result of the movable effect apparatus of the first embodiment of the present invention operating and the first effect unit and the second effect unit operating, the contact portions (the first contact portion and the second contact portion) It is a figure which shows the state which has touched. It is a disassembled perspective view of the 1st presentation member of the 1st Embodiment of this invention. It is an exploded perspective view of the second effect member of the first embodiment of the present invention. It is a figure explaining wiring of game machine 1 of a 1st embodiment of the present invention. FIG. 1 is a block diagram showing a configuration of a game machine 1 according to a first embodiment of the present invention. It is a block diagram which shows the structure of the presentation control apparatus of the 1st Embodiment of this invention. It is a block diagram showing composition of the 1st master IC with which the production control device of a 1st embodiment of the present invention was equipped, and the effect device with which the game board was equipped. It is a block diagram which shows the structure of the 2nd master IC with which the presentation control apparatus of the 1st Embodiment of this invention was equipped, and the presentation apparatus with which the front frame was equipped. It is a figure showing composition of a game board of a 1st embodiment of the present invention. It is a figure which shows the structure of the front frame of the 1st Embodiment of this invention. It is a figure explaining the connection state of the relay control board contained in the production control apparatus of the 1st Embodiment of this invention, and a game board, and a decoration control apparatus. It is a figure explaining the connection state of the production control apparatus of the 1st Embodiment of this invention, the simple relay board contained in the normal version front frame, and a decoration control apparatus. It is a block diagram of a decoration control device of a 1st embodiment of the present invention. It is a block diagram showing a configuration of a first embodiment of the I ² CI / O expander of the present invention. It is a circuit diagram of a I ² CI / O expander neighborhood decorative control device for controlling the decoration apparatus according to a first embodiment of the present invention. A circuit diagram of a peripheral I ² CI / O expander of the first embodiment of the decoration control device of the present invention, showing a case of controlling the motor or a solenoid. It is a figure for demonstrating the circuit structure of the decoration control apparatus of the 1st Embodiment of this invention, a relay board, and a simple relay board, and, in particular, for demonstrating the connection state regarding the input-output of a signal wire or a power wire. FIG. It is explanatory drawing of the slave address contained in the data output to a decoration control apparatus from the presentation control apparatus of the 1st Embodiment of this invention. It is an explanatory view of I ² CI / O expander address table according to the first embodiment of the present invention. It is a diagram for explaining a first embodiment of the I ² CI / O Aix work register assigned to the output setting register provided in expander of the present invention. FIG. 6 is an explanatory diagram of start and stop conditions in which the master IC according to the first embodiment of the present invention outputs data via a connection line SDA and a connection line SCL. It is a timing chart in which a decoration control device to which data output from a master IC of the first embodiment of the present invention is input outputs a response signal. It is a timing chart of the signal level of connecting line SDA and connecting line SCL when the master IC of the first embodiment of the present invention outputs the effect control data. In the case where the master IC according to the first embodiment of the present invention specifies the individual address of the slave and sets the rendering control data in the decoration control device, transmission and reception is performed between the master IC and the I ² CI / O expander. It is a figure explaining the format of the data to be sent. In the case where the master IC according to the first embodiment of the present invention specifies the individual address of the slave and sets the rendering control data in the decoration control device, transmission and reception is performed between the master IC and the I ² CI / O expander. It is the figure which applied the concrete numerical value to the production control data which are done. It is a figure explaining the order which transmits production control data of master IC of a 1st embodiment of the present invention. When the first embodiment of the master IC of the present invention initializes the I ² CI / O expander, describing the format of the initialization instruction data transmitted to the I ² CI / O expander from the master IC FIG. It is a figure explaining the abnormality determination table of 1st master IC of the 1st Embodiment of this invention. It is a figure explaining the abnormality determination table of 2nd master IC of the 1st Embodiment of this invention. The information transmitted / received between the CPU and the master IC (first master IC or second master IC) when initializing (resetting) each decoration control device (slave) according to the first embodiment of the present invention will be described. FIG. When transmitting effect control data to each decoration control device (slave) according to the first embodiment of this invention, the information transmitted and received between the CPU and the master IC (first master IC or second master IC) is It is a figure explaining. It is a figure explaining the step which transmits production control data to master IC (1st master IC or 2nd master IC) from a production control device of a 1st embodiment of the present invention. It is a flowchart which shows the procedure of the process by the presentation control apparatus of the 1st Embodiment of this invention. It is a flow chart which shows a procedure of slave initialization start processing by the side of the 1st master IC of a 1st embodiment of the present invention, and slave initialization start processing by the side of the 2nd master IC. It is a flowchart which shows the procedure of the production control periodic process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the process at the time of the transmission interruption interruption generation | occurrence | production of the 1st master IC side of the 1st Embodiment of this invention, and a timeout interruption generation. It is a flowchart which shows the procedure of the process at the time of the transmission interruption interruption generation | occurrence | production of the 2nd master IC side of the 1st Embodiment of this invention, and a timeout interruption generation | occurrence | production. It is a flowchart which shows the procedure of the transmission restart process of initialization instruction | command data of the 1st Embodiment of this invention. It is a flow chart which shows a procedure of transmission resumption processing of performance control data of a 1st embodiment of the present invention. It is a figure which shows an example of the transmission process continuation determination table for judging continuation of the transmission restart process of the data of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the data transmission process by the master IC of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the start condition output process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the SCL release monitoring processing of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the SDA release monitoring process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the data transmission process to the I ² CI / O expander of the slave side of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the stop condition output process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the process in the I ² CI / O expander of the slave side of the 1st Embodiment of this invention. It is a flowchart which shows procedures, such as an address recognition process in the I ² CI / O expander of the slave side of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the read-out process of the data in the I ² CI / O expander of the slave side of the 1st Embodiment of this invention. It is a timing chart which shows the state where processing by the 1st master IC and the 2nd master IC is performed in parallel by the directions from CPU of a production control device at the time of VDP interruption of a 1st embodiment of the present invention. A first I ² CI / O expander decoration control device in an embodiment of the present invention, a view showing a connection example of a decoration device, two 8-set amount of LED I ² CI / O expander Is a diagram showing a configuration controlled by The decoration control apparatus in the 1st Embodiment of this invention is a figure which shows the timing which receives data, and controls a presentation apparatus, It is a figure explaining the case where the data received at the time of outputting stop condition are reflected is there. It is a figure which shows the timing which the decoration control apparatus in the 1st Embodiment of this invention receives data, and controls a light-emitting device. In the first embodiment of the present invention, a state occurs in which the I ² CI / O expander 615 starting to occupy the connection line SDA is waiting for the falling of the connection line SCL. I ² CI / O expander which occupies the line SDA has to reset itself, is a diagram for explaining a procedure to attempt to release the bus. In the first embodiment of the present invention, a state occurs in which connection line SDA is occupied for some reason, and the I ² CI / O expander that detects the occupation of connection line SDA resets itself, and the bus It is a figure explaining the procedure which tries to release. When the bus by I ² CI / O expander slave in the first embodiment of the present invention has been occupied, I ² CI / O expander slave releases the bus in response to a command from the master IC It is a figure explaining a procedure. In the first embodiment of the present invention, when a read mode is generated in the slave side I ² CI / O expander due to an erroneous instruction from the master IC and the bus is occupied, the instruction from the master IC It is a figure explaining the procedure in which the I ² CI / O expander by the side of a slave releases a bus | bath by this. It is a block diagram showing a configuration of a second embodiment of the I ² CI / O expander of the present invention. It is a figure which shows an example of the mode register 1 of 2nd Embodiment of this invention, and the mode register 2. FIG. It is a flow chart which shows a procedure of transmission restart processing of initialization indication data of a 2nd embodiment of the present invention. It is a figure which shows a response | compatibility with the initialization step number of the 2nd Embodiment of this invention, and the output buffer setting value set to the buffer for output. It is a figure explaining the structure of the data transmitted to each slave of the 2nd Embodiment of this invention, and is a figure which shows the case where an individual address is specified and a parameter is set. It is a figure explaining the structure of the data transmitted to each slave of the 2nd Embodiment of this invention, and is a figure which shows the case where an all call address is designated and a parameter is set. It is a figure explaining the timing which transmits / receives data between a master IC and a slave in a 2nd embodiment of the present invention. It is a block diagram which shows the structure of the presentation control apparatus of the 3rd Embodiment of this invention. It is a flowchart which shows the procedure of the process at the time of the transmission interruption interruption generation | occurrence | production of the 1st master IC side of the 3rd Embodiment of this invention, and a timeout interruption generation | occurrence | production. FIG. 17 is a diagram for describing a procedure for releasing a bus when the bus is occupied by the slave side I ² CI / O expander in the third embodiment of the present invention. It is a figure which shows the example of a connection of the decoration control apparatus in the 4th Embodiment of this invention, and is a figure which shows the structure which controls five sets of LED by one decoration control apparatus. When transmitting effect control data to each decoration control device (slave) according to the fourth embodiment of the present invention, the information transmitted and received between the CPU and the master IC (first master IC or second master IC) It is a figure explaining. It is a flowchart which shows the procedure of the production control periodic process of the 4th Embodiment of this invention. It is a flow chart which shows a procedure of transmission resumption processing of performance control data of a 4th embodiment of the present invention. It is a figure explaining the structure of the data transmitted to each slave of the 4th Embodiment of this invention. It is a figure explaining the timing which transmits / receives data between a master IC and a slave in the 4th Embodiment of this invention. It is a figure explaining the case where the received data is reflected in the light emission state of LED at the time of outputting ACK to a master IC, when a decoration control apparatus receives data in the 4th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First Embodiment
FIG. 1 is an explanatory view of a gaming machine 1 according to a first embodiment of this invention.

  The front frame (game frame) 3 of the gaming machine 1 is assembled to the main frame (outer frame) 2 via the hinge 4 so as to be able to open and close in the front of the gaming machine 1. On the front side of the front frame 3, the game board 10 (see FIG. 2) is accommodated. Further, a glass frame 18 provided with a cover glass (transparent member) covering the front of the game board 10 is attached to the front frame 3.

  Around the cover glass of the glass frame 18, decorative members 9a and 9b for emitting decorative light are provided. Inside the decoration members 9a and 9b, a decoration device composed of a lamp, an LED or the like is provided. By making the decoration device emit light in a predetermined light emission mode, the decoration members 9a and 9b emit light in a predetermined light emission mode.

  At the left and right of the glass frame 18, speakers 30 for emitting sound (for example, sound effects) are provided. Further, a lighting unit 11 is provided above the glass frame 18.

  In the illumination unit 11, a first movable illumination 13 and a second movable illumination 14 are disposed on the left and right. The first movable illumination 13 and the second movable illumination 14 are provided with an illumination driving first motor (MOT) 13a and an illumination driving second motor (MOT) 14a in addition to the illumination members such as the LEDs, It is controlled to operate according to the contents of the effect.

  An abnormality notification LED 29 for notifying that an abnormality has occurred in the gaming machine 1 is provided at the lower right of the lighting unit 11.

  The opening and closing panel 20 at the lower part of the front frame 3 is provided with an upper plate for supplying gaming balls to a striking ball launch device (not shown), and the fixed panel 22 is provided with a lower tray 23 and an operation unit 24 of the striking ball launch device. The lower tray 23 is provided with a lower tray ball removing mechanism 16 for discharging the gaming balls stored in the lower plate 23. A key 25 for locking the glass frame 18 is provided on the lower right side of the front frame 3.

  In addition, when the player rotates the operation unit 24, the ball hitting and launching device shoots the game ball supplied from the upper tray 21.

  Further, at the upper edge portion of the upper tray 21, an effect button 17 for receiving an operation input from the player is provided. The player operates the effect button 17 to select the effect contents of the special view variation display game on the display device 53 (see FIG. 2) provided on the game board 10, and the special view variation display game on the display device 53 In addition, it is possible to produce an effect in which the player's operation is made to intervene.

  The special view variation display game is started when the launched game ball wins the starting opening 36 (see FIG. 2) provided on the gaming board 10. In the special view variable display game, a plurality of identification information is variably displayed on the display device 53. Then, when the identification information which has been variably displayed is stopped, and the result mode of the stopped identification information is a specific result mode, the state of the gaming machine 1 is advantageous to the player (the state in which a bonus is given) Transition to the special game state that is.

In the upper right portion of the upper tray 21, there are provided a ball lending button 26 operated when the player borrows a game ball, and a discharge button 27 operated to eject a prepaid card from a card unit (not shown). . Further, a balance display unit 28 for displaying the balance of the prepaid card is provided between the ball lending button 26 and the discharge button 27.

  FIG. 2 is a front view of the game board 10 according to the first embodiment of this invention.

  The gaming machine 1 shown in FIG. 1 is to play a game by firing a gaming ball into the internal gaming area 10a (playing a ball), and on the back side of the cover glass of the glass frame 18, the gaming area 10a is The game board 10 which comprises is installed.

  The game board 10 includes a flat game board body 10b (made of wood or synthetic resin) serving as a mounting base for various members, and has a game area 10a surrounded by guide rails 32 on the front of the game board body 10b. ing. A front component 33 is attached to the front of the game board main body 10b and to the outside of the guide rail 32. Then, a game ball (ball: game medium) is fired from the launch device into the game area 10a surrounded by the guide rails 32 to play a game.

  At the approximate center of the game area 10a, a center case 51 is attached, which forms a window 52 serving as a display area of the special view variable display game. Behind the window portion 52 formed in the center case 51, a display device 53 as an effect display device capable of executing an effect of a special view variable display game in which a plurality of identification information is variably displayed is disposed. The display device 53 includes, for example, a liquid crystal display, and is arranged such that the display portion 53a whose display content can be changed can be viewed from the front side of the game board 10 through the window portion 52 of the center case 51. The display device 53 is not limited to one provided with a liquid crystal display, but may be provided with a display such as an EL, a CRT or the like.

  Further, a reliability notification device 15 for notifying of the possibility (reliability) of the big hit is provided at the upper part of the center case 51. The reliability notification device 15 is provided with LEDs of a plurality of colors (for example, red, blue, and green LEDs), and is controlled to emit light in a color and manner according to the reliability.

  Further, on the left portion of the center case 51, a ball introduction path (warp flow path) 50 through which gaming balls can flow is provided, and is opened in a state in which the entrance 50a is opened toward the game area 10a. The ball introduction path 50 communicates with the inside of the center case 51, and the gaming balls flowing from the inlet 50a pass through the back side of the center case 51 and are discharged onto the unit side stage portion 49b. Further, the game balls rolled on the unit side stage 49b can flow down onto the base side stage 49a disposed below the unit side stage 49b.

  At the periphery of the center case 51, a plurality of ornaments 47 are disposed. A decoration lamp 48 is disposed at the lower left portion of the center case 51. A plurality of decoration pieces 46 are disposed above the center case 51 so as to be capable of moving up and down. The decoration 47, the decoration lamp 48 and the decoration piece 46 perform the rendering operation in accordance with an instruction from the rendering control device 550 described later. The configuration of the center case 51 will be described in more detail with reference to FIG.

  Further, below the center case 51 in the gaming area 10a, a starting opening 36 for starting a special figure variation display game capable of accepting (winning possible) gaming balls is disposed. Further, a common drawing start gate 34 for starting the common drawing fluctuation display game is disposed on the side (left side) of the center case 51.

Furthermore, in the game area 10a, side lamps 45 for displaying various decorations by light emission are disposed in the lower left and lower right of the center case 51. Further, the side lamp 45 is provided with a general winning opening 44.

  Furthermore, a big winning opening 42 is disposed below the starting opening 36, and an out opening for collecting gaming balls which have flown down without winning at the lower edge of the gaming area 10a below the large winning opening 42. 43 will be opened. The special winning opening 42 is provided with an open / close door 42 a of the attacker type that can be opened by turning in the direction in which the upper end side falls to the front side. Depending on the result of the special view variation display game, the state in which the open / close door 42a is closed (state disadvantageous to the player) is converted to the open state (state advantageous to the player).

  In addition, in the game area 10a except for the attachment portion such as the center case 51, the start opening 36 and the side lamp 45, in the game area 10a, a windmill (not shown) as a hitting direction conversion member The obstacle nails (not shown) etc. are arranged. A vertically long arc-shaped game ball passage 57 is formed between the center case 51 and the front component 33 located on the opposite side of the center case 51 from the common view starting gate 34.

  Furthermore, the game board 10 is provided with a common drawing / special drawing display 35 for executing a special drawing fluctuation display game and a common drawing fluctuation display game. The common drawing / special drawing display 35 displays the number of unprocessed times of the special drawing fluctuation display game (number of special drawing starting memories) and the number of non-processing of the common drawing fluctuation display game (number of common drawing starting memories). The common view / special view display 35 is provided as a segment LED together with a game state display LED (not shown) indicating a game state.

  In the drawing start gate 34, a gate SW 34a (see FIG. 9) for detecting the gaming ball having passed through the drawing start gate 34 is provided. Then, when the gaming ball driven into the gaming area 10a passes through the common drawing start gate 34, the common drawing variation display game is started.

  In addition, when the game ball passes the common drawing start gate 34 in a state where the common drawing fluctuation display game can not be started, if the common drawing start memory number is less than the upper limit number, the common drawing start memory number is incremented by one, A random number indicating whether or not the common drawing variation display game is hit is stored as one common drawing start memory.

  The state in which the common drawing fluctuation display game can not be started means, for example, a state in which the common drawing fluctuation display game has already been played and the common drawing fluctuation display game is not finished, or the common drawing fluctuation display game is won Means the state in which it is converted to the open state.

  Note that the common drawing variation display game may display the common drawing variation display game in part of the display area of the display device 53. In this case, for example, numbers, symbols, character symbols, etc. may be displayed as identification symbols. It is made to carry out by making it stop display, after using this identification symbol for a predetermined period of time and displaying it.

  When the stop display of the common drawing fluctuation display game is a special result mode, the opening / closing member 36a of the starting opening 36 is opened for a predetermined time (for example, 0.5 seconds) on the assumption that the common drawing fluctuation display game is won. Be done. As a result, the game ball can be easily won in the starting opening 36, and the start of the special view variation display game can be facilitated. The opening / closing member 36a of the starting opening 36 normally holds a closed state (a disadvantage for the player) with an interval of about the diameter of the gaming ball, but the result of the common drawing variation display game is predetermined. When it becomes the stop display mode (when it is won in the common view variable display game), by the solenoid (Pu SOL 36b, see FIG. 9), it opens in a reverse "C" shape and the game ball is in the starting opening 36 It is changed to an easy-to-flow state (a state advantageous to the player).

Further, the gaming machine 1 according to the first embodiment of the present invention reduces time for displaying the fluctuation of the special view fluctuation display game on the display device 53 as the gaming state based on the result mode of the special view fluctuation display game. An operation state (second operation state) can be generated. The time saving operation state (second operation state) is a state in which the open / close member 36a of the starting opening 36 is likely to be open as compared with the normal operation state (first operation state).

  In the short time operation state, the execution time of the common view variation display game is controlled to be shorter than the execution time in the normal operation state (for example, 10 seconds is 1 second), and the number of opening of the starting opening 36 per unit time is It is controlled to increase substantially. Further, in the short time operation state, when the starting opening 36 is opened by winning the common drawing variable display game, the opening time is controlled to be longer than the opening time of the normal operation state (for example, 0) .3 seconds is 1.8 seconds). Further, in the time saving operation state, the starting opening 36 is opened a plurality of times (for example, twice) instead of one time for one winning result of the common drawing variable display game. Further, in the time-saving operation state, the probability of being a winning result of the common drawing variable display game is controlled to be higher than that in the normal operation state. That is, the number of times the start opening 36 is opened is increased more than in the normal operation state, the gaming ball is more likely to win in the start opening 36, and the start of the special view variation display game becomes easier.

  In addition, inside the starting opening 36, a starting opening SW 36d (see FIG. 9) for detecting the gaming ball having passed through the starting opening 36 is provided. When the game ball is detected by the start opening SW 36d, a start right to start a special view variation display game as an auxiliary game is generated. At this time, the start right to start the special view variation display game is stored as a special view start storage within a predetermined upper limit number (for example, 4).

  If the special view variation display game can not be started immediately, for example, the special view variation display game has already been played and the special view variation display game has not ended, or the special game state is in effect, the starting opening 36 If the game ball wins, the special figure start memory number is less than the upper limit number (for example, less than 4), the special figure start memory number is incremented by 1, and the game ball is extracted at the timing when the game ball wins One random number is stored as a special view start memory. Then, when the special figure variation display game is ready to be started, the special figure variation display game is started based on the special figure start memory.

  The special figure variation display game as the auxiliary game is executed by the general drawing / special figure display 35 provided on the game board 10, and after variably displaying a plurality of identification information, the predetermined result mode is stopped and displayed. To be done. In addition, a plurality of types of identification information (for example, numbers, symbols, character patterns, etc.) are variably displayed on the display device 53 in response to the special view variation display game. And, as a result of the special figure fluctuation display game, when the display mode of the common figure / special figure display 35 becomes the special result mode, it becomes the big hit and becomes the special game state (so-called, big hit state). In addition, in response to this, the display mode of the display device 53 is also a special result mode (for example, any of Zoro's numeral such as "7, 7, 7"). In addition, you may be comprised so that a special figure change display game may be performed only with the display apparatus 53 instead of the common drawing and the special figure display 35. FIG.

  Further, the gaming machine 1 according to the first embodiment of the present invention is capable of generating a probability change state (second probability state) as a game state based on the result mode of the special view change display game. The probability variation state (second probability state) is a state in which the probability of being a hit result in the special figure variation display game is higher than that of the normal probability state (first probability state). It should be noted that the probability variation state and the above-described short time operation state can be generated independently of each other, and both can be generated simultaneously or only one can be generated.

  FIG. 3 is an exploded perspective view of the center case 51 according to the first embodiment of this invention.

The center case 51 has a frame decoration portion 65 disposed as a front structure on the front surface side of the game board main body 10b (game board 10) and a frame base 60 disposed as a back surface structure portion on the back surface side of the game board main body 10b. And are composed by polymerizing before and after. The frame decoration portion 65 includes an annular decoration base 66 fixed to the surface of the game board main body 10b. The back surface side of the decorative base 66 is provided with a decorative panel unit 67 formed in a circular shape with substantially the same size as the decorative base 66, and the frame decorative portion 65 polymerizes the decorative base 66 and the decorative panel unit 67 back and forth Is configured.

  At the lower part of the decoration base 66, a base side stage portion 49a capable of rolling the game ball in the front and rear direction and the left and right direction is disposed on the upper surface, and a decoration lamp is provided between the base side stage portion 49a and the game ball passage 57 48 are arranged (see FIG. 2). A ball introducing passage (warp passage) 50 through which the game balls can flow is provided on the opposite side of the base side stage portion 49a to the decoration lamp 48, and the entrance 50a of the ball introducing passage 50 is used as a decoration base 66 And the outlet 50b of the ball introduction passage 50 is in communication with the back side of the decorative panel unit 67 described later.

  The decorative panel unit 67 includes a cover panel portion 69 formed of a substantially circular transparent resin plate, and a plurality of ornaments 47 are disposed on the front edge of the cover panel portion 69. When the decorative panel unit 67 and the decorative base 66 are polymerized, the accessory 47 is set to be arranged along the inner peripheral edge of the decorative base 66 (see FIG. 2). In addition, a reliability notification device 15 is disposed on the top of the cover panel 69.

  Further, at the lower part on the back surface side of the cover panel part 69, a unit side stage part 49b capable of rolling the gaming ball in the front and back direction and the left and right direction is arranged on the upper surface. The unit side stage portion 49 b is disposed above the base side stage portion 49 a of the decoration base 66.

  Further, a ball inlet 68 is opened at a position overlapping with the outlet 50b of the ball introduction passage 50 in the cover panel portion 69, and the ball introduction passage 50 and the unit side stage portion 49b are communicated via the ball inlet 68 doing. Therefore, when a game ball flowing down the game area 10a flows into the ball introduction path 50, the ball introduction path 50 is configured to be able to introduce the game ball onto the unit side stage portion 49b.

  The frame base 60 is provided with a frame-like base case 61 fixed to the back side of the game board 10 in a state where the front side is open, and the frame case base 60 is opened inside the base case 61 (in other words, inside the center case 51). The portion 62a forms a recessed chamber 62 provided on the front side.

  Further, a rectangular window portion 52 is penetrated in the back and forth direction behind the concave chamber 62 of the base case 61 and the display device 53 is attached from the rear of the base case 61, and the display portion of the display device 53 53 a is made to face the front of the center case 51 through the window 52 and the recessed chamber 62.

  Furthermore, on the front side of the upper edge of the window 52, a plurality of decorative pieces 46 which can be moved up and down by a gift driving solenoid (not shown) are arranged. A movable effect device 58 is provided which moves forward in a direction 53a to perform an effect operation.

  Then, when the frame decoration portion 65 is superposed on the front of the frame base portion 60, the opening 62a and the window 52 of the recessed chamber 62 are covered from the front by the cover panel 69, and the display 53a of the display device 53 is the frame decoration The front case 65 is configured to be exposed to the front of the center case 51 from the inside of the portion 65 (where the cover panel portion 69 is exposed).

  FIG.4 and FIG.5 is a figure explaining the structure of the movable presentation apparatus 58 of the 1st Embodiment of this invention.

The movable effect device 58 includes the first effect unit 63 and the second effect unit 64 at mutually spaced positions, and the first effect unit 63 and the second effect unit 64 cooperate to execute the effect operation. .

  FIG. 4 is a view showing a state before the movable effect device 58 operates. FIG. 5 is a contact as a result of the movable effect device 58 operating and the first effect unit 63 and the second effect unit 64 operating. It is a figure which shows the state contact | abutted in the part (The 1st contact part 121 and the 2nd contact part 122).

  The first effect unit 63 is disposed on the left side of the center case 51, that is, on the left side of the periphery of the window 52 of the base case 61. In addition, the second effect unit 64 is disposed on the right side of the center case 51. The recessed chamber 62 and the window 52 are disposed between the first effect unit 63 and the second effect unit 64 as viewed from the front of the center case 51.

  The first effect unit 63 includes a first effect member 70 movable forward of the display unit 53a, and an accessory driving first motor as a first effect drive source that generates a driving force for the first effect member 70 (MOT 71) and a first effect transmission mechanism (a first main arm member 73 and a first sub arm member 74) for transmitting the driving force (rotational force) generated from the first character drive MOT 71 to the first effect member 70. .

  Further, the output shaft (first output shaft) 71a of the first MOT 71 for product driving extends in the front-rear direction of the center case 51, and the first drive gear 76 is rotatably mounted on the first output shaft 71a. There is.

  The first main arm member 73 is formed with a first main arm gear 77 meshed with the first drive gear 76, and is pivotally mounted above the first drive gear 76. The first auxiliary arm member 74 is formed with a first auxiliary arm gear 78 engaged with the first drive gear 76, and is pivotally mounted below the first drive gear 76. The first main arm member 73 and the first sub arm member 74 are pivotally attached to the first effect member 70 at different positions of the end opposite to the end that is pivotally attached to the base case 61, and the first effect member It supports 70.

  When the first effect unit 63 drives the accessory drive first MOT 71 and rotates the first drive gear 76 clockwise from the front of the center case 51, the driving force (rotational force) of the accessory drive first MOT 71 is calculated. The first main arm member 73 is transmitted to the first main arm member 73 via the first drive gear 76 and the first main arm gear 77, and the first main arm member 73 rotates counterclockwise as viewed from the front of the center case 51 by this driving force. Do. Further, the driving force of the first article driving member MOT 71 is transmitted to the first auxiliary arm member 74 through the first driving gear 76 and the first auxiliary arm gear 78, and the driving force of the first auxiliary arm member 74 becomes the first main arm. It rotates in the same counterclockwise direction as the arm member 73. As a result, the first effect member 70 is lifted while being supported by the first main arm member 73 and the first sub arm member 74.

  Then, when the first main arm member 73 and the first sub arm member 74 are extended upward by the driving force of the first character driving member MOT 71 and set in the vertical orientation, as shown in FIG. In the first effect stop state where it is positioned away from the front of the display unit 53a, the first effect member 70 is located to the side of the window 52 and is hidden behind the frame decoration unit 65 and behind the game board main body 10b (See Figure 2).

  On the other hand, when the first drive gear 76 is turned counterclockwise as viewed from the front of the center case 51 by driving the first product drive MOT 71 from the first effect stop state, the drive force of the first product drive MOT 71 (rotation power Is transmitted to the first main arm member 73 through the first drive gear 76 and the first main arm gear 77, and the driving force causes the first main arm member 73 to rotate clockwise as viewed from the front of the center case 51. Move.

Further, the driving force of the first article driving member MOT 71 is transmitted to the first auxiliary arm member 74 through the first driving gear 76 and the first auxiliary arm gear 78, and the driving force of the first auxiliary arm member 74 becomes the first main arm. It rotates in the same clockwise direction as the arm member 73. As a result, the first effect member 70 is lowered while being supported by the first main arm member 73 and the first sub arm member 74.

  Then, when the first main arm member 73 and the first sub arm member 74 are extended to the front of the display portion 53a by the driving force of the first MOT 71 and set to the sideways posture, as shown in FIG. In the first effect execution state in which the member 70 is positioned forward of the display unit 53a, the first effect member 70 is in front of the central portion of the display unit 53a in the space between the display unit 53a and the cover panel unit 69. To position.

  The second effect unit 64 includes a second effect member 80 movable to the front of the display unit 53a, and a second product drive second motor as a second effect drive source that generates a driving force for the second effect member 80 (MOT And 81) and a second effect transmission mechanism (a second main arm member 83 and a second sub arm member 84) for transmitting the driving force (rotational force) generated from the second character driving member MOT 81 to the second effect member 80. .

  Further, the second drive gear 86 is rotatably mounted on the second output shaft 81a so that the second drive gear 86 is rotatably mounted on the second output shaft 81a. There is.

  The second main arm member 83 is formed with a second main arm gear 87 engaged with the second drive gear 86, and is axially attached to a position closer to the first effect unit 63 than the second drive gear 86. The second auxiliary arm member 84 is formed with a second auxiliary arm gear 88 engaged with the second drive gear 86, and is pivotally mounted below the second drive gear 86. The second main arm member 83 and the second sub arm member 84 are pivotally attached to the second effect member 80 at positions different from each other at the opposite ends of the end portion pivotally attached to the base case 61, and the second effect member It supports 80.

  When the second effect unit 64 drives the accessory drive second MOT 81 and rotates the second drive gear 86 clockwise from the front of the center case 51, the driving force (rotational power) of the accessory drive second MOT 81 is calculated. The second main arm member 83 is transmitted to the second main arm member 83 via the second drive gear 86 and the second main arm gear 87, and the second main arm member 83 is rotated counterclockwise as viewed from the front of the center case 51 by this driving force. Do. Further, the driving force of the accessory driving second MOT 81 is transmitted to the second subsidiary arm member 84 through the second driving gear 86 and the second subsidiary arm gear 88, and the driving force of the second subsidiary arm member 84 is the second main arm. It rotates in the same counterclockwise direction as the arm member 83. As a result, the second effect member 80 is lowered while being supported by the second main arm member 83 and the second sub arm member 84.

  Then, the second main arm member 83 and the second sub arm member 84 are rotated by the driving force of the second article driving member MOT 81 to cause the second effect member 80 to reach the bottom dead center, and the second main arm member 83 and As shown in FIG. 4, when the second auxiliary arm member 84 is turned to extend obliquely downward and set in the vertical orientation, and the second effect member 80 is slightly raised from the bottom dead center, as shown in FIG. In the second effect stop state in which the member 80 is positioned away from the front of the display unit 53a, the second effect member 80 is hidden behind the frame decoration unit 65 and behind the gaming board main body 10b (see FIG. 2).

  On the other hand, when the second drive gear 86 is turned in the counterclockwise direction when the second drive gear 86 is viewed from the front of the center case 51 from the second effect stop state by driving the second drive gear MOT 81, the driving force of the second product drive MOT 81 ) Is transmitted to the second main arm member 83 via the second drive gear 86 and the second main arm gear 87, and the second main arm member 83 is rotated clockwise as viewed from the front of the center case 51 by this driving force. Move.

  Further, the driving force of the accessory driving second MOT 81 is transmitted to the second subsidiary arm member 84 through the second driving gear 86 and the second subsidiary arm gear 88, and the driving force of the second subsidiary arm member 84 is the second main arm It rotates in the same clockwise direction as the arm member 83. As a result, the second effect member 80 ascends while being supported by the second main arm member 83 and the second sub arm member 84.

  Then, when the second main arm member 83 and the second sub arm member 84 are extended to the front of the display portion 53a by the driving force of the second MOT 81 for driving the product and set to the sideways posture, as shown in FIG. In the second effect execution state in which the member 80 is positioned forward of the display 53a, the second effect member 80 is in front of the central portion of the display 53a in the space between the display 53a and the cover panel 69. To position.

  FIG. 6 is an exploded perspective view of the first effect member 70 according to the first embodiment of this invention.

  The first effect member 70 is a substantially semicircular member when viewed from the front of the center case 51, and is set in a posture in which an arc surface is disposed on the first effect unit 63 side.

  The first effect member 70 is provided with a first effect base 100 as a base. The first effect base 100 is formed of a transparent resin. A first main arm shaft attachment portion 101 for pivotally mounting the first main arm member 73 from the front of the first effect base 100 is formed in the upper portion of the first effect base 100, and in the lower portion of the first effect base 100 A first sub arm shaft attachment portion 102 is formed to pivotally attach the first sub arm member 74 from the rear of the first effect base 100.

  A first light diffusion sheet 103 capable of transmitting light while diffusing light is polymerized on the front surface of the first effect base 100. Furthermore, the transparent first protection panel 104 is polymerized on the front surface of the first light diffusion sheet 103 to prevent the first light diffusion sheet 103 from falling off the first effect member 70.

  Further, the rear portion of the first effect base 100 is recessed forward to form a first substrate storage space portion 105, and a light emitting device such as an LED (refer to FIG. 17) is formed in the first substrate storage space portion 105. The mounted first light emitting substrate 106 is housed. Furthermore, in this state, the first substrate storage space portion 105 is closed by the first base cover portion 107, and the first light emitting substrate 106 is prevented from dropping off from the first effect member 70.

  Then, when light is generated from the light emitting device of the first light emitting substrate 106, this light is transmitted through the first effect base 100, the first light diffusion sheet 103, and the first protection panel 104 and is irradiated to the front of the center case 51. Is configured as.

  Furthermore, the first effect magnet holder 124 whose rear is open is formed on the first substrate storage space portion 105 side of the first contact portion 121 so as to be recessed. In the first effect magnet holder 124, the first magnet 125 is a first contact portion 121 (first effect) in a posture in which the magnetic pole of the first magnet 125 formed of a button-shaped permanent magnet faces the second effect member 80 side. It is stored so as not to drop out of the magnet holder 124).

An I ² CI / O expander 615 (see FIG. 17) for controlling light emission of the decoration device 620 is mounted on the first light emitting substrate 106, and a control signal (electric signal) output from the effect control device 550, etc. Data lines (data signal lines) and clock lines (signal lines) for transmission are connected. Furthermore, a power supply line or the like for supplying power necessary to cause the decoration device 620 to emit light is connected. These connection lines are collectively connected as a cable 108.

  FIG. 7 is an exploded perspective view of the second effect member 80 according to the first embodiment of this invention.

The second effect member 80 has a substantially parallelogram shape having a cutout portion at the top as viewed from the front of the center case 51. In the second effect stop state, the upper and lower sides of the second effect member 80 are inclined downward from the second effect unit 64 side to the first effect unit 63 side (see FIG. 4), and in the second effect execution state The left and right side surfaces of the second effect member 80 are set to be inclined downward from the second effect unit 64 side to the first effect unit 63 side (see FIG. 5).

  The second effect member 80 is provided with a second effect base 110 as a base. The second effect base 110 is formed of a transparent resin. A second main arm shaft attachment portion 111 for pivotally mounting the second main arm member 83 from the front of the second effect base 110 is formed on the upper portion of the second effect base 110, and the lower portion of the second effect base 110 is A second sub-arm shaft attachment portion 112 is formed to pivotally attach the second sub-arm member 84 from the rear of the second effect base 110.

  Furthermore, the second light diffusion sheet 113 capable of transmitting light while diffusing light is polymerized on the front surface of the second effect base 110. By polymerizing the transparent second protection panel 114 on the front surface of the second light diffusion sheet 113, the second light diffusion sheet 113 is prevented from dropping off from the second effect member 80.

  In addition, the rear of the second effect base 110 is recessed forward to form a second substrate storage space portion 115, and a light emitting device (decorative device 620) such as an LED is mounted on the second substrate storage space portion 115. 2 The light emitting substrate 116 is housed, and in this state, the second substrate housing space portion 115 is closed by the second base lid portion 117 to prevent the second light emitting substrate 116 from falling off from the second effect member 80 .

  Then, when light is generated from the light emitting device of the second light emitting substrate 116, this light is transmitted through the second effect base 110, the second light diffusion sheet 113, and the second protection panel 114 and is irradiated to the front of the center case 51. Is configured as.

  Furthermore, the second effect magnet holder 128 whose rear portion is opened is formed on the second substrate storage space 115 side of the second contact portion 122 so as to be recessed. A second magnet 129 formed of a button-shaped permanent magnet is stored in the second effect magnet holder 128 at a position symmetrical to the first magnet 125 with the first contact portion 121 and the second contact portion 122 interposed therebetween. It is done.

Similar to the first light emitting substrate 106, the second light emitting substrate 116 is mounted with an I ² CI / O expander 615 (see FIG. 17) for controlling light emission of the decoration device 620, and output from the effect control device 550 Data lines and clock lines (signal lines) for transmitting the control signals and the like are connected. Furthermore, a power supply line or the like for supplying power necessary to cause the decoration device 620 to emit light is connected. These connection lines are collectively connected as a cable 118.

  The movable effect device 58 includes the first contact portion 121 in the first effect member 70 and the second contact portion 122 in the second effect member 80. Then, when the first effect unit 63 is converted to the first effect execution state and the second effect unit 64 is converted to the second effect execution state, the first contact portion 121 and the second contact portion 122 contact with each other. The first effect member 70 and the second effect member 80 form one decorative body. At this time, the first magnet 125 and the second magnet 129 are arranged to generate a suction force between the first magnet 125 and the second magnet 129. Furthermore, the formed decorative body is configured to be positioned in front of the central portion of the display portion 53a.

  FIG. 8 is a diagram for explaining the wiring of the gaming machine 1 according to the first embodiment of this invention.

FIG. 8 shows a state before the center case 51 is attached to the game board main body 10 b and the display device 53 is attached to the center case 51. In addition, the effect control device 550 is attached to the back of the display device 53. The effect control device 550 is provided with a connection terminal 90, and transmits control signals and supplies power to the effect device to be controlled via the connection terminal 90. Specifically, it is connected to a relay board 600 described later via a cable 91.

  In addition, a control unit 700 including a game control device 500 and various control boards is disposed at the lower rear of the game board main body 10b. The control substrate mounted on the control unit 700 includes a relay substrate 600 for relaying the control signal transmitted from the effect control device 550 to the decoration control device 610 (see FIG. 11). Although the decoration control device 610 will be described later in detail, the decoration control device 610 controls a rendering device such as a light emitting device (for example, an LED) or a movable object (for example, a motor) for producing a game. Further, similarly to the decoration control device 610, the relay substrate 600 can connect a light emitting device and a movable object.

  The relay board 600 is provided with an upstream connector 601 connected to the effect control device 550 via the cable 91. One connector 91 a of the cable 91 is connected to the connection terminal 90 of the effect control device 550 as described above. The other connector 91 b of the cable 91 is connected to the upstream connector 601 of the relay substrate 600. Furthermore, connectors 602 a to 602 e for connecting to the decoration control device 610 that controls the respective rendering devices provided in the gaming machine 1 are provided.

  Furthermore, the relay board 600 is provided with a vacant terminal monitor 603 which indicates the connection state of the connected cable. Details of the free terminal monitor 603 will be described with reference to FIG.

  Although not shown, units constituting the gaming control device 500 are provided so as to cover the connector mounting surface of the relay board 600. Therefore, the game control device 500 is arranged and attached after the necessary cables are attached to the connectors of the relay board 600.

  The front frame 3 is connected to a speaker 30 disposed on the front frame 3 and a cable 3b for transmitting a signal for controlling the decorative members 9a, 9b and the like. The connector of the cable 3 b is connected to the connection terminal 92 of the effect control device 550.

  An opening 45b for attaching the side lamp 45 is formed in the game board main body 10b. The side lamp 45 is connected with a cable 45 a for transmitting power and signals, and is introduced to the back side of the game board 10 from the opening 45 b. The cable 45a introduced to the back side of the game board 10 is connected to the relay board 600, and is connected to, for example, the connector 602d.

  Further, as shown in FIG. 2, the starting opening 36 and the big winning opening 42 are disposed at the lower part of the game board 10. On the back side of the game board 10 where the starting opening 36 is arranged, a common power solenoid (SOL) 36 b for opening and closing an opening / closing member 36 a which is opened when the common drawing variation display game is won is arranged. Further, when the special figure variation display game is won, a large winning opening SOL 42 b for opening and closing the large winning opening 42 is also disposed on the back side of the gaming board 10. A cable (not shown) for receiving an input of a control signal is connected to the general electric charge SOL 36 b and the large winning opening SOL 42 b, and the cable is connected to the game control device 500. In addition, the cable 42C is connected to the relay substrate 600 as a cable for transmitting power and a signal for lighting the LED for effect provided inside the big winning opening 42, and is connected to, for example, the connector 602f.

As described above, the center case 51 is attached to the central portion of the game board 10. Inside the center case 51, a movable effect device 58 configured by the first effect member 70 and the second effect member 80 is provided. In FIG. 8, the first effect member 70 and the second effect member 80 are in contact with each other at the contact surfaces (121, 122).

  Further, as described above, the first effect unit 63 and the second effect unit 64 of the movable effect device 58 are motors for operating the first effect member 70 and the second effect member 80 (a first product driving motor) 71, a bonus product driving second motor 81) is provided. A cable 652 for supplying signals for controlling these motors and power for driving the motors is connected to the movable effect device 58. In addition, the movable effect device 58 is provided with a motor position detection sensor (not shown) for detecting the operation state of these motors, and a cable 651 for receiving a sensing result is connected. The cable 652 and the cable 651 extend from the opening 51 b of the center case 51 to the back side of the game board 10 and are connected to the relay substrate 600. For example, the cable 652 is connected to the connector 602C, and the cable 651 is connected to the connector 602e.

  Furthermore, a cable 653 is connected to transmit the control signal output from the effect control device 550 to the decoration control device 610 (see FIG. 11) for controlling the effect device such as an LED disposed inside the center case 51. Ru. The cable 653 is connected from the opening 51a provided in the center case 51 to the relay substrate 600 on the back side of the game board 10, and is connected to, for example, the connector 602a.

  FIG. 9 is a block diagram showing the configuration of the gaming machine 1 according to the first embodiment of this invention.

  The gaming machine 1 includes a game control device 500 for controlling the game in an integrated manner, a presentation control device 550 for controlling the display device 53 and the speaker 30 to perform various effects, and a payout motor (not shown) to pay out the gaming ball. It has a payout control device 580 to control.

  First, the configuration of the game control device 500 will be described. The effect control device 550 will be described with reference to FIG.

  The game control device 500 includes a gaming microcomputer 501, an input I / F (Interface) 505, an output I / F (Interface) 506, and an external communication terminal 507.

  The gaming microcomputer 501 includes a CPU 502, a read only memory (ROM) 503, and a random access memory (RAM) 504.

  The CPU 502 is a main control device that controls the game in an integrated manner, and controls the game control. The ROM 503 stores invariable information (program, data, etc.) for game control. The RAM 504 is used as a work area at the time of game control.

  The external communication terminal 507 connects the game control device 500 to an external device such as an inspection device that inspects setting information and the like of the game control device 500.

  The CPU 502 receives various input devices (starting opening SW 36 d, general winning opening SW 44 a to 44 n, gate SW 34 a, count SW 42 d, glass frame opening SW 18 a, front frame opening SW 3 a, ball breakage SW 54, vibration sensor 55, and the like) via the input I / F 505. In response to the detection signal from the magnetic sensor 56), various processes such as a big hit lottery are performed.

  The starting opening SW 36 d is a switch for detecting that the gaming ball has won the starting opening 36. The general winning opening SWs 44 a to 44 n are switches for detecting that the gaming ball has won the general winning opening 44.

  The gate SW 34 a is a switch for detecting that the gaming ball has passed through the common view starting gate 34. The count SW 42 d is a switch for detecting that the gaming ball has won the large winning opening 42.

  The glass frame opening switch 18a is a switch for detecting that the glass frame 18 has been opened. The front frame opening switch 3a is a switch that detects that the front frame 3 has been opened.

  The out-of-ball SW 54 is a switch that is stored inside the gaming machine 1 and detects that the number of gaming balls used for payout has become equal to or less than a predetermined number.

  The vibration sensor 55 is a sensor that detects a vibration given to the gaming machine 1 and detects a fraudulent act such as vibrating the gaming machine 1. The magnetic sensor 56 is a sensor provided in the vicinity of the second start winning opening of the starting opening 36, the general winning opening 44, the big winning opening 42, and the common drawing start gate 34 to detect a magnetic force. The magnetic sensor 56 brings a magnet close to each winning opening and detects an injustice leading the gaming balls fired to the game area 10a to each winning opening.

  In addition, the CPU 502 transmits a command signal to the common drawing / special drawing display 35, the common electric SOL 36b, the special winning opening SOL 42b, the payout control device 580, and the effect control device 550 via the output I / F 506 to play the game. Control the

  As described above, the special view variation display game and the general view variation display game are executed on the common view / special view display 35. Furthermore, the number of unprocessed times of the special figure fluctuation display game (number of special drawing start memories) and the number of unprocessed games of the common drawing fluctuation display game (number of common drawing start memories) are displayed. A common drawing start memory including a random number indicating whether the common drawing fluctuation display game is a hit and a special drawing start memory including a random number indicating whether the special drawing fluctuation display game is to be hit are stored.

  When the stop display of the common drawing variation display game results in a special result mode, the common electric charge SOL 36 b opens the opening / closing member 36 a to make the gaming ball easy to win in the starting opening 36.

  When the special game variation display game results in a special result mode and becomes a special game state (big hit state), the special winning opening SOL 42b opens the open / close door 42a of the special winning opening 42, and the game ball Convert to a state that is easy to win.

  The game control device 500 outputs game machine data to a game arcade management device (not shown) from an external information terminal 508 via an information collection terminal device (not shown). The game arcade management device is a computer that collects and manages game data of the game machine 1 installed in the game arcade.

  The payout control device 580 receives, from the game control device 500, a payout command for the number of gaming balls corresponding to the winning openings that have won when the gaming ball has won the general winning opening 44 or the large winning opening 42. In addition, the game control device 500 receives a payout command for paying out a predetermined number of gaming balls even when the ball lending button 26 is operated. The payout control device 580 controls a payout motor (not shown) based on the received payout command, and pays out the number of gaming balls specified in the payout command.

  The game control device 500, through the output I / F 506, as a game data indicating the status of the game, such as a change start command, a customer wait demo command, a fanfare command, a probability information command, and an error designation command. Send to

FIG. 10 is a block diagram showing a configuration of the effect control device 550 according to the first embodiment of this invention.

  Based on the game data input from the game control device 500, the effect control device 550 determines the contents of the effect, controls the display device 53, and controls various effect devices provided in the game board 10 and the front frame 3. Do. The rendering device includes a light emitting device such as an LED or the like, and a movable object such as a motor or a solenoid.

  The effect control device 550 includes a CPU 551, control ROM 552, RAM 553, image ROM 554, sound ROM 555, VDP 556, sound LSI 557, input I / F 558 b, output I / F 558 a, power on detection circuit 559, first master IC 570 a, second master IC 570 b, A NOR gate circuit 561 and a monitoring timer circuit 562 are provided. Furthermore, the effect control device 550 includes a connection terminal 90 connected to the game board 10 and a connection terminal 92 connected to the front frame 3. The function common to the first master IC 570a and the second master IC 570b will be described simply as "master IC".

  The CPU 551 receives a command signal transmitted from the game control device 500 as an interrupt signal (INT) as a communication interrupt, and controls various effects based on the input command signal. The CPU 551 also receives an interrupt signal (INT) as a master interrupt from the first master IC 570a and the second master IC 570b, and also receives an interrupt signal (INT) as an image update interrupt from the VDP 556. Be done.

  Further, the CPU 551 also receives an interrupt signal (INT) from the monitoring timer circuit 562 as a time-out interrupt. The monitoring timer circuit 562 incorporates a plurality of types of monitoring timers, and outputs an interrupt signal to the CPU 551 when the monitoring timer value set by the CPU 551 is timed up. When receiving the input of the interrupt signal, the CPU 551 interrupts the process being executed and executes the process corresponding to the input interrupt signal.

  The control ROM 552 stores invariable information (program, data, etc.) for effect control. The RAM 553 is used as a work area at the time of effect control.

  The image ROM 554 is connected to the VDP 556 and stores image data to be displayed on the display device 53. The VDP 556 is a processor that controls image output to the display device 53.

  The VDP 556 also includes synchronization signal generating means for generating a synchronization signal synchronized with a cycle (33 ms cycle) for updating the image displayed on the display device 53. The synchronization signal generation means inputs the generated synchronization signal as an interrupt signal to the CPU 551 each time the synchronization signal is generated.

  The sound ROM 555 is connected to the sound LSI 557 and stores sound data outputted from the speaker 30 provided in the front frame 3. The sound LSI 557 is a circuit that controls the audio output from the speaker 30.

  The input I / F 558 b is an interface that receives information input from the outside via the filters 565 a and 565 b. Specifically, the input of a signal indicating that the effect button 17 provided on the front frame 3 has been operated is accepted, or the position information of each motor detected by the motor position detection sensor provided on the game board 10, etc. Accept the input of

  The power-on detection circuit 559 generates a reset signal for initializing the registers of the first master IC 570a and the second master IC 570b to the default state (all 0) when power is supplied to the effect control device 550, thereby generating a NOR gate. It outputs to the circuit 561.

  In addition, the CPU 551 outputs a reset signal to the output I / F 558 a through the bus 563 when a predetermined condition is satisfied. Then, the output I / F 558a outputs the input reset signal to the NOR gate circuit 561, and further, the NOR gate circuit 561 outputs the reset signal to the first master IC 570a and the second master IC 570b. The predetermined condition is, for example, a case where the error flag is set to “ON” in all the decoration control devices 610 (see FIGS. 32 and 33).

  Further, the output I / F 558a outputs a control signal to a rendering device (rendering device driven by a movable object such as a motor or a solenoid) provided on the game board 10 or the front frame 3 via the driver 564a and the driver 564b. .

  The reset signal input from the power on detection circuit 559 to the NOR gate circuit 561 and the reset signal input from the CPU 551 to the NOR gate circuit 561 via the output I / F 558a are in the state of LOW level in either case. Functions as a signal to command a reset. Therefore, if a reset signal is output to NOR gate circuit 561 from at least one of power on detection circuit 559 and CPU 551, the reset signal is input to first master IC 570a and second master IC 570b via NOR gate circuit 561. .

  FIG. 11 is a block diagram showing a configuration of a first master IC 570a provided in the effect control device 550 according to the first embodiment of this invention and effect devices provided in the game board 10.

  The game board 10 includes a relay board 600 connected to the first master IC 570 a, a decoration device board 625 connected to the relay board 600, and an auxiliary game machine unit 12.

  The relay board 600 transmits (relays) the electric signal transmitted from the first master IC 570 a to the decoration control device 610 provided on the game board 10. Further, similar to the decoration control device 610, the relay substrate 600 has a function of controlling the rendering device, and controls the decoration device substrate 625 directly connected to the relay substrate 600.

The decoration device 620 is a light emitting device that is controlled by the I ² CI / O expander 615 (see FIG. 17) included in the decoration control device 610, and performs light by flashing light when current flows, for example, an LED It is. The decoration device substrate 625 is a substrate provided on the side lamp 45 (see FIG. 8), and the light emitting device (LED) of the side lamp 45 is mounted. The light emitting device of the side lamp 45 is directly controlled by the I ² CI / O expander 615 provided on the relay substrate 600.

  The auxiliary gaming device unit 12 includes a decoration device 620 which is a light emitting device such as an LED, a first product driving motor (MOT) 71 which is a movable object, and a second product driving second MOT 81. The decoration device 620 in the auxiliary gaming device unit 12 is controlled by the decoration control device 610 included in the auxiliary gaming device unit 12. In the first embodiment of the present invention, the accessory driving first MOT 71 and the accessory driving second MOT 81 are configured to be controlled by the relay substrate 600, but like the decoration device 620, the auxiliary gaming device unit It may be configured to be controlled by the decoration control device 610 included in 12.

The accessory driving first MOT 71 and the accessory driving second MOT 81 are driving devices that perform rendering operations by rotating when current flows. Since the first product drive MOT 71 and the second product drive MOT 81 are directly controlled by the driver 564 of the effect control device 550 via the relay board 600, the process of interposing the I ² CI / O expander 615 is not performed. .

  In the first embodiment of the present invention, the first symbol driving MOT 71 and the second symbol driving second MOT 81 are included in the movable effect device 58, and more specifically, the first symbol driving MOT 71 is a first effect unit 63, The object drive second MOT 81 is included in the second rendering unit 64.

  The effect control device 550 executes the effect operation in which the first effect unit 63 and the second effect unit 64 are interlocked by controlling the first object drive MOT 71 and the second object drive MOT 81.

The first master IC 570a designates the address individually assigned to the decoration control device 610 that controls the decoration device 620 to be controlled, and outputs the control content of the decoration device 620 to the decoration control device 610 of the specified individual address Do. The individual address of the decoration control device 610 is exactly the individual address of the I ² CI / O expander 615 (see FIG. 17) included in the decoration control device 610.

  The first master IC 570a has a relay substrate (decorative control device) through seven types of connection lines of connection line SDA, connection line SCL, connection line GND, connection line Vcc, connection line Vled, connection line Vms, and connection line Vse. ) Connected to 600). These connection lines are constituted by a cable 91 (see FIG. 8) connecting the first master IC 570a and the relay substrate 600.

  The connection line SDA is a connection line for transmitting and receiving data signals between the effect control device 550 and the decoration control device 610, and functions as a data line in the first embodiment of the present invention. The connection line SCL is a connection line for inputting and outputting a clock signal used for data communication in the connection line SDA, and functions as a timing signal line in the first embodiment of the present invention. The connection line GND is a ground of the power supplied by the connection line Vcc, the connection line Vled, the connection line Vms, and the connection line Vse.

  The connection line Vcc is a connection line for supplying the relay substrate 600 and the decoration control device 610 with a power supply for logic. The connection line Vled is a connection line for supplying power for causing the LED (decorative device 620) to emit light. The connection line Vms is a connection line for supplying power to a motor or a solenoid (specifically, the first product drive MOT 71 and the second product drive MOT 81) included in the auxiliary gaming apparatus unit 12. The connection line Vse is a connection line for supplying power to various sensors (state detection sensors that detect the state of the motor included in the rendering device, specifically, the motor position detection sensor 560a). is there.

  Seven types of connection lines for connecting the effect control device 550 and the relay substrate 600 are connected between the relay substrate 600 and the auxiliary gaming device unit 12. In the first embodiment of the present invention, since the motor position detection sensor 560a, the article drive first MOT 71 and the article drive second MOT 81 are directly controlled by the relay substrate 600, among the seven types of connection lines described above, Five types of connection lines other than the connection line Vms and the connection line Vse are connected to the decoration control device 610 disposed on the uppermost stream of the auxiliary gaming apparatus unit 12. Specifically, the connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, and the connection line GND are connected between the relay substrate 600 and the decoration control device 610.

  When the wires (cables) shown in FIG. 8 correspond to the connection lines, various connection lines (connection line Vcc, connection line Vled, connection line SDA, connection line SCL) delivered from the effect control device 550 to the relay substrate 600 The connection line Vms, the connection line Vse, and the connection line GND) are included in the cable 91.

Further, these various connection lines are branched from the relay substrate 600 and delivered to another substrate, and the connection line Vcc, the connection line Vled, the connection line SDA, and the connection line SCL which are branched from the relay substrate 600 are connected to the cable 653. The connection line Vms is included in the cable 652, and the connection line Vse is included in the cable 651. Further, the connection lines GND branched from the relay substrate 600 are included in all of the cables 651 to 653.

  The first master IC 570 a and the decoration control device 610 perform two-line bi-directional communication through the connection line SDA and the connection line SCL. The first master IC 570a functions as a (first) signal level control unit that controls each signal level of the connection line SDA and the connection line SCL connected with the decoration control device 610 based on an instruction from the CPU 551. Do.

  When transmitting data to the relay substrate 600 and the decoration control device 610, the first master IC 570a changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH. As a result, a start condition for starting data output to the decoration control device 610 is established (a start condition is issued (outputted) to the decoration control device 610).

  Thereafter, the first master IC 570a changes the signal level of the connection line SCL to LOW, and sets the signal level of the connection line SDA to the level of the first bit of transmission data while the signal level of the connection line SCL is LOW. After a predetermined time, the signal level of the connection line SCL is changed from LOW to HIGH. When the signal level of the connection line SCL changes to HIGH, the decoration control device 610 acquires the signal level of the connection line SDA and recognizes it as the first bit of the transmission data. Then, the first master IC 570a returns the signal level of the connection line SCL from HIGH to LOW.

  When this procedure is executed once, 1-bit data is transmitted from the first master IC 570a to the decoration control device 610, and by repeating this procedure 8 times finally, all 8 bits of transmission data become the first master. It is transmitted from IC 570a to decoration control device 610 (one byte of data is transmitted).

  Then, when the first master IC 570a finishes the data transmission of the final eighth bit, when the signal level of the connection line SCL is returned from HIGH to LOW, the first master IC 570a releases the connection line SDA and returns a response from the decoration control device 610. It waits for the signal to be received to be in the reception standby state.

  In the reception standby state, the decoration control device 610 returns a 1-bit response signal (ACK or NACK described later) to the first master IC 570a via the connection line SDA. Next, the first master IC 570a changes the signal level of the connection line SCL from LOW to HIGH to fetch the level of the response signal, and after a predetermined time changes the signal level of the connection line SCL from HIGH to LOW, the decoration control device 610 releases connection line SDA.

  The first master IC 570a alternately repeats such data transmission of 1 byte (transmission of downlink data) and reception of 1 bit of response signal (reception of uplink data), and outputs the same to the decoration control device 610. Continue until all data to be output is output. When the first master IC 570a finishes outputting the data to be output, the decoration control is performed by changing the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH. A stop condition for ending data output to the device 610 is satisfied (a stop condition is issued to the decoration control device 610).

  The input buffer 571 is a storage device for temporarily storing data input from the decoration control device 610 via the connection line SDA.

  Specifically, when the first master IC 570a is set to the input mode, the data transmitted from the decoration control device 610 to the first master IC 570a is temporarily removed by the filter 575a by the noise removed by the filter 575a. Is stored in

  The output buffer 572 temporarily stores data to be output to the decoration control device 610 via the connection line SDA.

  The reset register (REG) 573 is connected to the bus 563, receives an instruction from the CPU 551 of the effect control device 550, and outputs a reset signal to the controller 574. The controller 574 centrally controls the first master IC 570a and executes various processes.

  The filter 575a removes noise of data input from the connection line SDA. When the driver 576a outputs data from the connection line SDA, the driver 576a applies a voltage at which the transistor 578a can operate to the transistor 578a.

  The connection line SDA is applied with a predetermined voltage by the pull-up resistor R (see FIG. 21), and is connected to the filter 575a and the transistor 578a.

  The transistor 578a uses a field effect transistor (FET) to reduce power consumption. The gate of the transistor 578a is connected to the driver 576a, the drain is connected to the connection line SDA to which a predetermined voltage is applied by the pull-up resistor R, and the source is grounded.

  If the voltage applied to the gate of the transistor 578a is smaller than the predetermined value for operating the transistor 578a, no current flows between the drain and the source, so the voltage applied to the connection line SDA does not drop, as a result The connection line SDA goes high. On the other hand, if the voltage applied to the gate of the transistor 578a is equal to or higher than the predetermined value for operating the transistor 578a, a current flows from the drain to which the voltage of the predetermined value is applied to the source grounded. As a result, the voltage on the connection line SDA goes low.

Note that the transistor 578a has a specification which is not damaged even when a current of about 10 milliamperes flows from the drain to the source. For this reason, it is possible to flow a current of about 10 milliamperes, which is much larger than the current value used in the normal I ² C bus use, to the connection line SDA. The data transmission between them is configured to withstand the disturbance due to noise.

  When the driver 576a outputs data from the connection line SDA, the driver 576a applies a voltage at which the transistor 578a can operate so that a current flows between the drain and the source of the transistor 578a. Then, the driver 576a outputs data from the connection line SDA by setting the voltage of the connection line SDA to the HIGH level or the LOW level.

  In addition, the filter 575 b removes noise of data input from the connection line SCL. When the driver 576 b outputs data from the connection line SCL, the driver 576 b applies a voltage at which the transistor 578 b can operate to the transistor 578 b.

  A predetermined voltage is applied to the connection line SCL by the pull-up resistor R (see FIG. 21), and the connection line SCL is connected to the filter 575 b and the transistor 578 b.

  The transistor 578 b uses a field effect transistor (FET) to reduce power consumption. The gate of the transistor 578b is connected to the driver 576b, the drain is connected to the connection line SCL to which a predetermined voltage is applied by the pull-up resistor R, and the source is grounded.

  If the voltage applied to the gate of the transistor 578b is smaller than the predetermined value for operating the transistor 578b, no current flows between the drain and the source, so the voltage applied to the connection line SCL does not drop, as a result The connection line SCL goes high. On the other hand, if the voltage applied to the gate of the transistor 578b is equal to or higher than the predetermined value for operating the transistor 578b, a current flows from the drain to which the voltage of the predetermined value is applied to the source grounded. The voltage drops, as a result, the connection line SCL goes low.

Note that the transistor 578 b has a specification which is not broken even when a current of about 10 milliamperes flows from the drain to the source. Therefore, it is possible to pass a current of about 10 milliamperes, which is much larger than the current value used in the normal I ² C bus use, to the connection line SCL, and between the effect control device 550 and the decoration control device 610. The data transmission of the configuration is able to withstand noise interference.

  When the driver 576 b outputs a clock signal from the connection line SCL, the driver 576 b applies a voltage with an operable value to the gate of the transistor 578 b in order to flow current between the drain and the source in the transistor 578 b. Then, the driver 576 b outputs a clock signal from the connection line SCL by repeatedly changing the voltage of the connection line SCL between the HIGH level and the LOW level.

  The power on reset circuit 577 defaults storage areas such as the input buffer 571 and the output buffer 572 when the first master IC 570 a is powered on and the voltage in the power on reset circuit 577 reaches a predetermined value. A reset signal for setting the state is output to the controller 574. The power-on reset circuit 577 may be provided outside the first master IC 570a and may be common to a second master IC 570b described later.

  The command register (REG) 581 is a register for receiving a command from the CPU 551 of the effect control device 550. In the first embodiment of the present invention, each bit of STA, STO, SI, and MODE is assigned to the command register 581 in advance, and "0" or "1" is individually assigned to each bit by the CPU 551. It can be set.

  The STA is a bit for instructing the decoration control device 610 to be controlled by the first master IC 570a to output a start condition (start condition). When “1” is set to STA, the first master IC 570a issues (outputs) a start condition to the decoration control device 610 to be controlled, and the start condition is satisfied.

  STO is a bit for the first master IC 570a to instruct the decoration control device 610 to be controlled to output a stop condition (stop condition). When "1" is set to STO, the first master IC 570a issues (outputs) a stop condition to the decoration control device 610 to be controlled, and the stop condition is satisfied.

The SI is a bit set when the rendering controller 550 generates an interrupt from the first master IC 570a. When an interrupt is generated from the first master IC 570 a to the CPU 551, the controller 574 sets SI to “1”, and an interrupt signal (INT) is input to the CPU 551. After that, while the first master IC 570a interrupts the process while the SI is set to "1", the first master IC 570a interrupts the process when the CPU 551 sets "0" to the SI. Suspend and resume processing.

  MODE is a bit for designating a mode for transmitting data, and "buffer mode" is designated when "1" is set, and "byte mode" is designated when "0" is set. . The buffer mode is a mode in which continuous plural bytes of data are transmitted at one time and transmitted, and a maximum of 68 bytes of data can be transmitted. The byte mode is a mode in which only one byte of data can be transmitted in one transmission, and is used to transmit and receive data in units of bytes.

  The status register (REG) 582 stores information indicating the status of the first master IC 570a. The lower 2 bits are always set to "0" and the upper 5 bits are set to the status code.

  The own address setting register (REG) 583 is a register which is set when the first master IC 570a functions as a slave (decorative control device). A commercially available master IC usually has a function as a master and a function as a slave, and is used according to the application. When the first master IC 570 a functions as a slave, an address for specifying itself is set in the self address setting REG 583.

  FIG. 12 is a block diagram showing the configuration of the second master IC 570 b provided in the effect control device 550 according to the first embodiment of this invention and the effect device provided in the front frame 3.

  The front frame 3 includes a simple relay substrate 1600 connected to the second master IC 570b, a decoration control device 610 connected to the simple relay substrate 1600, a speaker 30, a motor position detection sensor 560b, a first lighting drive MOT 13a, and a second lighting drive 2 MOT 14a etc. are included.

The simple relay substrate 1600 transmits (relays) the electric signal transmitted from the second master IC 570 b to the decoration control device 610 provided on the front frame 3. Note that, unlike the relay board 600, the simple relay board 1600 does not include the I ² CI / O expander 615. Therefore, for the electronic components provided in the simple relay board 1600, arithmetic processing for controlling the rendering device Does not have the ability to perform Therefore, since the first lighting MOT 13a and the second lighting MOT 14a directly connected to the simple relay substrate 1600 can not be controlled by their own judgment, the simple relay substrate 1600 receives the electric signal received from the second master IC 570b. It plays a role of relaying to the illumination drive first MOT 13a and the illumination drive second MOT 14a.

  The illumination drive first MOT 13 a and the illumination drive second MOT 14 a drive the light emitting members provided internally based on the signal transmitted from the effect control device 550 to execute various effects.

  Further, the effect control device 550 receives a signal indicating that the effect button 17 has been operated from the effect button 17 via the simple relay board 1600. Further, position information of the illumination driving first MOT 13 a and the illumination driving second MOT 14 a detected by the motor position detection sensor 560 b is input through the simple relay substrate 1600.

  Furthermore, the simple relay board 1600 receives a signal from the sound LSI 557 of the effect control device 550, and outputs the signal from the speaker 30.

Since the configuration of the second master IC 570b is the same as that of the first master IC 570a, the same reference numerals are assigned to the respective components of the second master IC 570b and the description will be omitted. Also,
Similarly to the first master IC 570a, the second master IC 570b controls each signal level of the connection line SDA and the connection line SCL connected to the decoration control device 610 based on a command from the CPU 551 (second Functions as signal level control means).

  The connection method between the effect control device 550 and the relay substrate 600 and the connection method between the relay substrate 600 and the decoration control device 610 other than the relay substrate 600 will be described later in detail with reference to FIGS. Further, the configurations of the relay substrate 600 and the decoration control device 610 will be described later in detail with reference to FIGS.

  The decoration control device 610 is mainly attached to the game board 10 and the front frame 3. The decoration device (LED) 620 controlled by the decoration control device 610 attached to the front frame 3 irradiates the decoration members 9a and 9b, the illumination unit 11, and the abnormality notification LED 29. On the other hand, the decoration control device 610 attached to the game board 10 is included in the auxiliary gaming device unit 12 configured by integrating the center case 51, the display device 53, and the effect control device 550.

  In FIG. 13, the configuration and connection of the relay board 600 provided on the game board 10 and the decoration control device 610 included in the auxiliary game device unit 12 will be described. In FIG. 14, configurations and connection forms of the simple relay substrate 1600 and the decoration control device 610 provided in the front frame 3 will be described.

  FIG. 13 is a view showing the configuration of the game board 10 according to the first embodiment of this invention.

  As described above, the center case 51 constituting the auxiliary gaming apparatus unit 12 is configured by combining the frame decoration portion 65 and the frame base portion 60.

  The frame decoration unit 65 includes a plurality of effect devices for producing effects of auxiliary games such as a variable display game, a plurality of decoration control devices 610 for controlling the effect devices, and the like. The frame decorative portion 65 is integrally configured by mutually connecting the decoration control devices 610 with each other by a predetermined signal cable and further connecting a rendering device controlled by the decoration control device 610 with a cable.

  In addition, the frame base 60 is also provided with a plurality of effect devices for producing effects of auxiliary games such as a variable display game, and a plurality of decoration control devices 610 for controlling the effect devices. The frame base 60 is integrally configured by mutually connecting the decoration control devices 610 with a predetermined signal cable and further connecting a rendering device controlled by the decoration control device 610 with a cable.

  Therefore, the frame decoration part 65 and the frame base 60 constitute an integrated effect unit in the present embodiment. On the other hand, since the side lamp 45 etc. is a single effect device not included in the integrated effect unit, it constitutes a separate effect device.

  It is not necessary that all of the rendering devices included in the auxiliary gaming device unit 12 be controlled by the decoration control device 610 inside the auxiliary gaming device unit 12. For example, in the first embodiment of the present invention, the movable object disposed in the center case 51 is directly controlled by the effect control device 550 via the relay substrate 600.

The decoration controller 610, as described above, is mounted ^I 2 CI / O expander 615 for controlling the decoration device ^620, the I 2 CI / O expander 615, individual ^I 2 CI / O An individual address for identifying the expander 615 is assigned. In the first embodiment of the present invention, as described above, the individual address of the I ² CI / O expander 615 is used as the individual address of the decoration control device 610.

By specifying the individual address of the I ² CI / O expander 615 and transmitting a control signal, the effect control device 550 can individually control the decoration device 620 to execute the effect operation. In principle, each decoration control device 610 is assigned a different individual address (indicated by “ad =” in the figure).

  Further, the decoration control device 610 is classified into three types of a branch type (branch substrate), a connection type (connection substrate) and a termination type (termination substrate) according to the connection form. The decoration device 620 can be connected to any of the branched, coupled and terminal decoration control devices 610, and the connected decoration device 620 can be controlled.

  The branch type decoration control device 610 is directly connected to the plurality of decoration control devices 610 on the downstream side, and transmits the received control signal to the plurality of decoration control devices 610. The connected decoration control device 610 is connected to one decoration control device 610 on the downstream side, and transmits the received control signal to the connected decoration control device 610. The decoration control device 610 of the terminal type does not have the decoration control device 610 connected downstream, and only controls the decoration device 620. Details of the branch type, connection type, and end type decoration control device 610 will be described later with reference to FIG.

  Note that the upstream side is a side that transmits an electric signal in a configuration in which an electric signal is transmitted from the effect control device 550 to the decoration control device 610 at the end via the decoration control device 610 on the way. On the contrary, the downstream side is the side that receives this electrical signal.

  That is, when the signal cable from the effect control device 550 to the decoration control device 610 at the end is traced in order, the decoration control device 610 connected to the side closer to the effect control device 550 becomes the upstream side, and the decoration at the end more The decoration control device 610 connected to the side close to the control device 610 is the downstream side. For example, the decoration control devices 610A and 610C are disposed upstream of the decoration control device 610H, and the decoration control devices 610I and 610J are disposed downstream of the decoration control device 610H.

  Here, in the first embodiment of the present invention, as described above, the decoration control device 610 is disposed at the movable portion of the first effect member 70 and the second effect member 80 that constitute the movable effect device 58. . In other words, in FIG. 6, the decoration control device 610 (the first light emitting substrate 106) is disposed on the movable portion (the first effect base 100) of the first effect member 70, and in FIG. The decoration control device 610 (second light emitting substrate 116) is disposed on the (second effect base 110).

  At this time, if the decoration control devices 610 are wired in a daisy chain as in the conventional shift register, only one of the decoration control devices 610 at the end of the daisy chain can be connected by only connecting the input cable. It's over. However, it is necessary to connect a cable for input and a cable for output to the other decoration control device 610 configured to be connected in the middle of the daisy chain. When a plurality of cables are connected to the movable portion, the decoration control device 610 (the first light emitting substrate 106, the second light emitting substrate 116) itself is movable together with the movable portion, and the cables are also moved. It may be difficult. Furthermore, the movement of the cable may cause a break in the connecting wire constituting the cable, which may affect the effect.

In the first embodiment of the present invention, the decoration control device 610 disposed in the first effect member 70 and the second effect member 80 is a terminal type, and a decoration control device of a branch type upstream of the decoration control device 610. 610 is arranged. Therefore, a signal is sent to the other decoration control device 610 provided outside the first effect member 70 and the second effect member 80 in the terminal decoration control device 610 (the first light emitting substrate 106, the second light emitting substrate 116). It becomes the structure where the cable which transmits is not connected. By arranging the decoration control device 610 in this way, it is sufficient to connect only the input cable to the decoration control device 610 arranged in the movable part. Therefore, the wiring can be easily routed and the possibility of disconnection can be reduced, as compared to the case of wiring in a daisy chain.

  If the destination address of the received control signal is not addressed to itself, the decoration control device 610 transmits the received control signal if the decoration control device 610 is further connected downstream. If there is no destination, the received control signal is discarded.

The decoration control device 610 can control LEDs corresponding to 16 ports, and the LEDs mounted on the decoration control device 610 and the external decoration device substrate 625 connected to the decoration control device 610 If the total number with the mounted LEDs is 16 or less, it is possible to control both LEDs. That is, in the integrated decoration control device 610 (corresponding to a main movement type substrate on which both the I ² CI / O expander 615 and the decoration device 620 are disposed), the decoration device substrate 625 (the I ² CI / O expander 615 is arranged It is possible to control both the internally provided decoration device 620 and the externally connected decoration device 620 by further connecting the driven substrate on which the decoration device 620 is disposed.

  By doing so, the remotely located decoration devices 620 can be controlled by one decoration control device 610, and the number of decoration control devices 610 can be minimized.

The relay substrate 600 is connected to the first master IC 570a mounted on the effect control device 550 on the upstream side, and receives the control signal transmitted from the first master IC 570a. Further, on the downstream side, it is connected to the decoration control device 610A (specifically, the decoration control device 610A included in the frame base 60 which is an integrated effect unit) included in the auxiliary gaming device unit 12. Furthermore, the relay substrate 600 is connected to a decoration device substrate 625 (a substrate provided on the side lamp 45 (see FIG. 8)) which is a separated type rendering device provided on the game board 10 and provided on the relay substrate 600. The I ² CI / O expander 615 controls the decoration device 620 mounted on the decoration device substrate 625.

  The auxiliary gaming device unit 12 includes decoration control devices 610A to 610J. The decoration control device 610A is a branch type decoration control device, and transmits the control signal received from the first master IC 570a to the decoration control device 610B and the decoration control device 610C. Further, a decoration device substrate 625B is connected to the decoration control device 610B, and a rendering device (decoration device 620) such as an LED disposed on the decoration device substrate 625B is controlled by the decoration control device 610B.

  The decoration control device 610C is a branch-type decoration control device 610, and transmits the received control signal to the decoration control device 610D and the decoration control device 610H on the downstream side. The decoration control device 610D is connected to the branch-type decoration control device 610E, and further controls the decoration device 620D included in the decoration device substrate 625D.

  A decoration control device 610F for controlling the first effect member 70 and a decoration control device 610G for controlling the second effect member 80 are connected to the decoration control device 610E. In the first effect member 70 and the second effect member 80, the effect operation is performed in conjunction. The decoration control device 610F is disposed on the first light emitting substrate 106 included in the first effect member 70 (FIG. 6), and the decoration control device 610G is disposed on the second light emitting substrate 116 included in the second effect member 80 (Figure 7).

  The first light emitting substrate 106 may function as the decoration control device 610F, and the second light emitting substrate 116 may function as the decoration control device 610G.

  In the first embodiment of the present invention, the decoration control device 610F controls the LEDs and the like included in the first effect member 70, and the decoration control device 610G controls the LEDs and the like included in the second effect member 80. Incidentally, the first product driving first MOT 71 and the second product driving second MOT 81 for outputting the driving force for moving the first effect member 70 and the second effect member 80 to the front of the display unit 53 a are controlled by the relay substrate 600 Be done.

  The effect control device 550 controls the first effect unit 63 (the first effect member 70) and the second effect unit 64 (the second effect member 80) when a predetermined condition is satisfied, such as during the variable display game. Execute the action. Specifically, the individual address ("0000") of the relay substrate 600 is used to control the bonus item drive second MOT 81 included in the bonus item drive first MOT 71 and the second bonus unit 64 included in the first effect unit 63. Designate and transmit control signals for operating these motors. Furthermore, a control signal for controlling a light emitting device such as an LED included in the first effect member 70 is transmitted by specifying the individual address (“0110”) of the decoration control device 610F for controlling the first effect member 70. Similarly, a control signal for controlling a light emitting device such as an LED included in the second effect member 80 is transmitted by specifying an individual address (“0111”) of the decoration control device 610G for controlling the second effect member 80. After that, a stop condition is issued.

  The decoration control device 610H is a connection-type decoration control device 610, and further, the connection-type decoration control device 610I and the end-type decoration control device 610J are connected. The termination type decoration control device 610J controls the decoration device 620J included in the decoration device substrate 625J.

  In the first embodiment of the present invention, the decoration control device 610H and the decoration control device 610I control a rendering device (LED) included in the reliability notification device 15. When the predetermined condition is satisfied, a control signal for indicating a predetermined aspect is transmitted from the first master IC 570a of the effect control device 550, and effects are performed in the designated aspect.

  FIG. 14 is a diagram showing the configuration of the front face frame 3 according to the first embodiment of this invention.

  The gaming machine 1 according to the first embodiment of the present invention has a plurality of specifications, and includes a normal version gaming machine 1 and an inexpensive version gaming machine 1. The normal version game machine 1 includes a front frame 3 (hereinafter, referred to as a normal version front frame 3) provided with a decorative member of a standard specification. The low price plate game machine 1 includes a front frame 3 (hereinafter referred to as a low price plate front frame 3 ′) provided with a decorative member configured at a cost lower than that of a standard specification decorative member. The upper part of FIG. 14 shows the configuration of the normal version front frame 3 and the lower side shows the configuration of the low price version front frame 3 ′. In the gaming machine 1, only the front frame 3 of either one of the specifications is shown. Is attached and connected to the effect control device 550, so either the normal plate front frame 3 or the inexpensive plate front frame 3 'is connected to the second master IC 570b.

The number of decoration devices 620 included in the decoration members 9a and 9b is different between the normal plate front frame 3 and the low price plate front frame 3 ', and the number of decoration control devices 610 for controlling the decoration device 620 is also different. Specifically, the decoration members 9a and 9b of the normal version front frame 3 are controlled by seven decoration control devices 610, and the decoration members 9a 'and 9b' of the low price plate front frame 3 'are controlled by five decoration control devices 610. Be done. Since the decorative members 9a and 9b are irradiated by more LEDs than the decorative members 9a 'and 9b', the normal plate front frame 3 is brighter than the low price plate front frame 3 ', and the variation of the feasible effects is increased It is also possible. Therefore, the control of the decoration device 620 when the normal version front frame 3 is attached is different from the control of the decoration device 620 when the low price version front frame 3 ′ is attached.

  Therefore, when the same address is assigned to the individual address of the decoration control device 610 attached to the normal version front frame 3 and the individual address of the decoration control device 610 attached to the low price version front frame 3 ', the effect control device 550 Since the effect control data to be transmitted to the decoration control device 610 needs to be different between the case of the normal version front frame 3 and the case of the low price version front frame 3 ', according to the front frame 3 attached to the game machine 1, The presentation control device 550 for the plate and the presentation control device 550 for the low price version must be prepared respectively. Therefore, when the manufacturer ships the gaming machine 1, the presentation control device 550 for the normal version and the presentation control device 550 for the low price version have to be prepared, and the manufacturing cost increases.

  Therefore, in the first embodiment of the present invention, different addresses are assigned to the individual addresses of the decoration control device 610 having different controls in the normal version front frame 3 and the low price version front frame 3 ′. By configuring the effect control data to be transmitted to the decoration control device 610 to be common to the case of the normal version front frame 3 and the case of the low price version front frame 3 ′, one effect control device 550 can be used for the normal version. It is configured to be able to carry out the control of and the control for the low price version. By doing this, it is not necessary to prepare the effect control device 550 for the normal version and the effect control device 550 for the low price version, respectively, and the manufacturing cost can be suppressed. In the first embodiment of the present invention, the configuration of the game board 10 is the same whether it is a normal version or an inexpensive version.

  The configurations of the normal plate front frame 3 and the inexpensive plate front frame 3 ′ will be specifically described below.

  The normal plate front frame 3 includes a simple relay board 1600 connected to the second master IC 570 b. A branch type decoration control device 610K and illumination drive motors (13a, 14a) are connected to the simple relay substrate 1600.

  The decoration control device 610K is disposed in the lighting unit 11, and controls the decoration device 620 provided on the decoration device substrate 625K. Specifically, the LEDs included in the lighting unit 11, the abnormality notification LED 29 and the like are controlled.

  The decoration control device 610K is a branch-type decoration control device, and transmits the received control signal to the decoration control device 610L and the decoration control device 610P. The decoration control devices 610 </ b> L to 610 </ b> N control the decoration member 9 a of the left side portion of the normal plate front frame 3. The decoration control devices 610P to 610R also control the decoration member 9b on the right side of the normal plate front frame 3.

  The decoration member 9a of the left side portion of the normal plate front frame 3 includes a combination-type decoration control device 610L, 610M and an end-type decoration control device 610N. The decoration control device 610L receives a control signal transmitted from the second master IC 570b of the effect control device 550 from the decoration control device 610K, and transmits it to the decoration control devices 610M and 610N.

  The decorative member 9b on the right side portion of the normal plate front frame 3 includes, as described above, the connected decoration control devices 610P and 610Q and the end decoration control device 610R. The decoration control device 610P receives the control signal transmitted from the second master IC 570b of the effect control device 550 from the decoration control device 610K, and transmits it to the decoration control devices 610Q and 610R.

Further, different individual addresses are assigned to the decoration control devices 610L to 610R included in the decoration member 9a and the decoration member 9b, and different rendering operations are performed based on the control signals transmitted from the second master IC 570b. Can be run. Specifically, the individual address of the decoration control device 610 K included in the lighting unit 11 is “0000
“Individual addresses of decoration control devices 610L, 610M and 610N included in the decoration member 9a“ 0001 ”“ 0010 ”and“ 0011 ”, individual addresses of decoration control devices 610P, 610Q and 610R included in the decoration member 9b Are assigned "0100", "0101" and "0110".

  On the other hand, the low price plate front frame 3 'is a substrate having almost the same function as the simple relay substrate 1600 connected to the second master IC 570b like the normal plate front frame 3 (hereinafter, the low price simple relay substrate 1600 'To have). However, in the low-priced printing front frame 3 ', only the branch-type decoration control device 610S is connected to the simple relay substrate 1600', and the cost reduction is achieved without the illumination drive motor (13a, 14a).

  The decoration control device 610S is disposed in the lighting unit 11, and controls the decoration device 620 provided on the decoration device substrate 625S. Specifically, the LEDs included in the lighting unit 11, the abnormality notification LED 29 and the like are controlled, and are similar to the normal version front frame 3. Further, the decoration control device 610S is the same substrate as the decoration control device 610K that controls the lighting unit 11 of the normal version frame 3 and is assigned the same individual address ("0000"). Therefore, the same control is executed in the decoration control device 610K of the normal version front frame 3 and the decoration control device 610S of the low price version front frame 3 ′.

  The decoration control device 610S is a branch-type decoration control device, and transmits the received control signal to the decoration control device 610T and the decoration control device 610V. The decoration control devices 610T and 610U control the decoration member 9a 'of the left side portion of the normal plate front frame 3. In addition, the decoration control devices 610V and 610W control the decoration member 9b 'of the right side portion of the normal plate front frame 3.

  In addition, in the low price front frame 3 ', decoration control devices 610T and 610U that control the decoration member 9a' on the left side and decoration control devices 610V and 610W that control the decoration member 9b 'on the right side are attached. The decoration control device 610T is the same substrate as the decoration control device 610L of the normal version front frame 3, and the same individual address ("0001") is assigned. Similarly, the decoration control device 610V is the same substrate as the decoration control device 610P of the normal version frame 3 and is assigned the same individual address ("0001"). Therefore, the same control is executed in the decoration control device 610L of the normal version front frame 3 and the decoration control device 610T of the low price version front frame 3 ′. The decoration control device 610P of the normal version front frame 3 and the low price version front surface 3 The same control is performed in the 'decorative control device 610V'.

  The same individual address ("0111") is assigned to the decoration control devices 610U and 610W. Therefore, in the low-priced printing front frame 3 ', the same control is performed by the decoration control devices 610U and 610W with the left and right decoration members, that is, the illumination by the LEDs to be controlled is performed at the same timing. Further, individual addresses not assigned to the decoration control device 610 of the normal version front frame 3 are assigned to the decoration control devices 610U and 610W.

And, even in the case of being used for any of the normal plate front frame 3 and the low price plate front frame 3 ', the effect control device 550 is a decoration control device included in the decoration members 9a, 9b, 9a', 9b ' Effect control data is transmitted to all the individual addresses assigned to the I ² CI / O expander 615 of 610.

As described above, among the decoration control devices provided in the low-priced version frame front frame 3 ', one corresponding to the decoration control devices 610M, 610N, 610Q and 610R (first specification dependent group unit control means) Does not exist, and instead, decoration control devices 610U and 610W (second specification dependent group unit control means) are attached. While the decoration control devices 610M, 610N, 610Q and 610R (first specification-dependent group unit control means) are attached to the normal version front face frame 3, the inexpensive front face frame 3 'is less A number of decoration control devices 610U and 610W (second specification dependent group unit control means) are attached.

  Also, the decoration control device 610K and decoration control device 610S, decoration control device 610L and decoration control device 610T, and decoration control device 610V and decoration control device 610P are common to the normal version front frame 3 and the low price version front frame 3 '. It is configured as a usable substrate.

  Therefore, the effect control device 550 according to the first embodiment of the present invention can share the control for the normal version and the control for the inexpensive version, and there is no need to change the control for each front frame. , And the manufacturing cost of the presentation control device 550 can be reduced.

  In the following description, it is assumed that the front frame of the normal version is attached to the gaming machine 1 according to the first embodiment of the present invention unless otherwise specified.

In the low price front frame 3 ′, the I ² CI / O expander 615 whose individual addresses are “0010”, “0011”, “0101” and “0110” is not used. The I ² CI / O expander 615 whose individual address is “0111” is not used. Therefore, in any abnormality determination table 3300 (see FIG. 33), there is an I ² CI / O expander 615 which is not connected to any front frame 3. However, as described later, if data transmission is normally performed between at least one I ² CI / O expander 615 registered in the abnormality determination table 3300 and the second master IC 570 b, the data transmission is normally performed. Since it is judged that it is operating, this does not interrupt the process.

  FIG. 15 is a view for explaining a connection state of the effect control device 550 of the first embodiment of the present invention and the relay substrate 600 and the decoration control device 610 included in the game board 10.

  In FIG. 15, connection of the effect control device 550, the relay substrate 600, and the decoration control devices 610A, 610B, and 610C will be described. Further, for convenience of explanation, the description of one relay substrate 600 and each decoration control device (610D to 610J) connected downstream of the decoration control device 610C as the decoration control device 610 will be omitted. The connection between the decoration control devices 610 is the same.

  The effect control device 550 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, a connection line GND, a connection line M11 to M14, a connection line M21 to M24, a connection line M31 to M34, a connection line SL1, a connection line The relay substrate 600 is connected to the relay substrate 600 by SL2, the connection lines SE1 to 3, the connection line Vms, and the connection line Vse.

  The connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, the connection line GND, the connection line Vms, and the connection line Vse are as described in FIG.

  The connection lines M11 to M14 transmit signals for controlling the first to fourth phases of the accessory driving first MOT 71 included in the first effect unit 63. The connection lines M21 to M24 transmit signals for controlling the first to fourth phases of the accessory driving second MOT 81 included in the second rendering unit 64. The first product driving unit MOT 71 and the second product driving unit MOT 81 use four-phase driving stepping motors.

Although connection lines M31 to M34 are connection lines for controlling the motor, in the first embodiment of the present invention, since the motor corresponding to relay board 600 is not connected, the vacant terminal monitor for displaying the connection state 603 is connected. The free terminal monitor 603 is composed of four LEDs corresponding to the connection lines M31 to M34, and can check whether or not each connection line is broken. Therefore, when a part or all of the connection lines are broken, a part of the free terminal monitor 603 will not light up, so it can be judged that the quality of the cable is bad.

  In particular, as in the gaming machine 1 according to the first embodiment of the present invention, the cable 91 connecting the first master IC 570a and the relay substrate 600 includes the connection line GND for supplying power, the connection line Vcc, The connection line Vled, the connection line Vms, and the connection line Vse are included (see FIG. 11 or FIG. 15). As a line for supplying these powers, in order to realize stable operation, a large (thick) cable having a large cross-sectional area that can ensure a sufficient amount of current is originally used.

  However, in the case of using a flat-shaped cable such as the cable 91, it is necessary to equalize (make common) the size of the cross-sectional area of each cable because the connectors are connected. Therefore, it is conceivable to supply power by using a plurality of connecting wires instead of a cable having a large cross-sectional area. For example, six cables are used as the connecting wire GND and three cables are used as the connecting wire Vms. The configuration to be used can be realized.

  At this time, even if a part of the connection line for supplying power is broken, if all the connection lines are not broken, the LED operates with no problem in appearance, so the LED is lighted, Although it is possible to drive the motor, since a sufficient amount of current can not be secured, abnormal heat generation may occur on the cable. In such a case, by connecting a power supply line to the free terminal monitor 603, a poor quality cable is detected in which some of the connection lines are broken even though they seem to be operating normally. It will be possible to replace and perform necessary maintenance before a failure occurs.

  Further, the relay substrate 600 supplies the electric power supplied from the connection line Vms to each motor in order to drive the character product drive motor (character product drive first MOT 71, character product second MOT 81). The electric power supplied to the accessory driving solenoid for moving the decorative piece 46 up and down is also supplied from the connection line Vms.

  Further, to relay board 600, a motor position detection sensor 560a for detecting a rotational position of the accessory drive motor is connected. The connection lines SE1 to SE3 are connection lines for receiving the detection result by the motor position detection sensor 560, and the relay board 600 is a connection line for the rotational position of the accessory drive motor detected by the motor position detection sensor 560a. It transmits to the production | presentation control apparatus 550 via SE1-3.

  The connection line SL1 and the connection line SL2 are connection lines for controlling the item driving solenoid. Similarly to the connection lines M31 to M34 described above, the connection line SL1 and the connection line SL2 are also connected to the vacant terminal monitor 603 for displaying the connection state when the accessory drive solenoid is not used.

  The decoration control device 610 including the relay substrate 600 includes the connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, and the connection line GND (hereinafter, a bundle of these five types of connection lines is referred to as one harness). Are connected to each other.

  A decoration control device 610B and a decoration control device 610C are connected to the decoration control device 610A via a harness, and a decoration control device 610D (not shown) is connected to the decoration control device 610C via a harness.

Each decoration control device 610 is provided with a connector serving as a mounting port for connecting the harness to itself. Since this connector is common to each decoration control device 610, the connection order of the connection lines is common, and erroneous wiring can be prevented.

  FIG. 16 is a diagram for explaining the connection state of the effect control device 550 according to the first embodiment of this invention, and the simple relay substrate 1600 and the decoration control device 610 included in the normal version frame 3.

  16, the connection of the effect control device 550, the simple relay board 1600, and the decoration control devices 610K, 610L, and 610P will be described. Further, for convenience of description, the description of the decoration control devices 610 connected to the downstream of the decoration control device 610L and the decoration control device 610P as the decoration control device 610 will be omitted.

  The effect control device 550 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, a connection line GND, a connection line M11 to M14, a connection line M21 to M24, a connection line M31 to M34, a connection line SL1, a connection line In addition to SL2, connection lines SE1 to 3, connection lines Vms, and connection lines Vse, a connection line for receiving a button signal from the effect button 17 and a connection line for transmitting a sound signal are connected to the simplified relay substrate 1600 Ru.

  As for the connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, the connection line GND, the connection line Vms, and the connection line Vse, as described in FIG. As in the case of connection, various signals are transmitted to and received from the decoration control devices 610 disposed downstream.

  The connection lines M <b> 11 to M <b> 14 transmit signals for controlling the illumination drive first MOT 13 a of the first movable illumination 13 included in the illumination unit 11. The connection lines M21 to M24 transmit signals for controlling the illumination drive second MOT 14a of the second movable illumination 14 included in the illumination unit 11.

  Although connection lines M31 to M34 are connection lines for controlling the motor, in the first embodiment of the present invention, since the corresponding motor is not connected to simplified relay board 1600, like relay board 600, An idle terminal monitor 603 is connected to display the connection state.

  Furthermore, in order to drive the illumination drive motor (the illumination drive first MOT 13a and the illumination drive second MOT 14a), the power supplied from the connection line Vms is supplied to each motor.

  In addition, a motor position detection sensor 560 b for detecting the rotational position of the illumination drive motor is connected to the simple relay substrate 1600. Simple relay substrate 1600 transmits the rotational position of the illumination drive motor detected by motor position detection sensor 560b to effect control device 550 via connection lines SE1 to SE3.

Here, a method in which the I ² CI / O expander 615 (described later in FIG. 18) provided in the decoration control device 610 controls the decoration device 620 will be described.

The effect control device 550 determines the output mode of the effect device (decorative device 620) based on the game data input from the game control device 500. Then, the effect control device 550 includes effect control data (effect control) including the individual address of the decoration control device 610 to be controlled (the individual address of the I ² CI / O expander 615) such that the determined output mode is obtained. Information) is output to the relay board 600. At this time, the effect control data is output from the relay substrate 600 to all the decoration control devices 610 to be controlled via the connection line SDA.

In the first embodiment of the present invention, since the effect device controlled by the decoration control device 610 is mainly a light emitting device such as an LED, the light emission aspect of the LED corresponds to the output aspect of the effect device. In this case, the on / off / on / off of the LED is instructed by the effect control data, and the on / off cycle of the LED or the on / off luminance is also instructed.

As described above, a unique address is previously set in each decoration control device 610, and when the effect control data is input, the address included in the input effect control data and the set individual address It is determined whether or not there is a match. When it is determined that the address included in the input effect control data matches the set individual address, the I ² CI / O expander 615 of the decoration control device 610 takes in the effect control data. Then, while controlling the output mode of the corresponding decoration device 620, immediately after the data of the 8th bit is input, the reply signal is output to the master IC (first master IC 570a, second master IC 570b).

  As described above, the master IC transmits effect control data to all the decoration control devices 610 connected to the master IC, and requests the decoration control device 610 corresponding to the individual address included in the effect control data. The rendering device can be controlled to be in the output mode.

In addition to the individual addresses, reset addresses for initializing the I ² CI / O expander 615 of the decoration control device 610 are set in each decoration control device 610. The reset address is an address commonly provided to all the I ² CI / O expanders 615 and can not be used as an individual address. Further, the value of the reset address can not be changed (the details will be described later).

When the presentation control device 550 initializes the decoration control device 610 (more precisely, the I ² CI / O expander 615 of the decoration control device 610), the initialization instruction data including the common address for this reset is , And the relay board 600 or the simple relay board 1600. At this time, the initialization instruction data effect control data is output from the connection line SDA to all the decoration control devices 610 connected to the effect control device 550 through the relay substrate 600 or the simple relay substrate 1600.

Since a reset common address is set in advance in each decoration control device 610, it is determined whether the address included in the input data matches the reset common address. If it is determined that they match, the I ² CI / O expander 615 of the decoration control device 610 outputs a response signal to the master IC, and captures input data as initialization instruction data, and then the I ² CI / O ex Initialize the panda 615 itself.

When the I ² CI / O expander 615 is initialized, the effect device controlled by the initialized I ² CI / O expander 615 is turned off.

Thus, since the decoration control device 610 performs control based on a command from the effect control device 550, the relationship between the effect control device 550 and the decoration control device 610 can be determined by the first master IC 570a of the effect control device 550 and the second master IC 570a. The master IC 570 b is a master, and the I ² CI / O expander 615 of each decoration control device 610 is a slave.

In FIGS. 15 and 16, the control target of the decoration control device 610 other than the relay substrate 600 is the decoration device 620 which is a light emitting device such as an LED, but it is also possible to control movable objects such as a motor and a solenoid. It is. In this case, since the effect device is a drive source such as a motor or a solenoid, the operation mode of these drive sources corresponds to the output mode of the effect device. The effect control data includes an operation / stop instruction of the drive source, and it is also possible to specify an operation speed.

  Even when the low price plate front frame 3 ′ is provided instead of the normal version front frame 3 as the configuration of the gaming machine 1, the connection state of the various substrates included in the low price plate front frame 3 ′ is almost the same as FIG. 16. It becomes the composition of

  However, since the illumination drive motor (the illumination drive first MOT 13a and the illumination drive second MOT 14a) is not provided in the low price plate front frame 3 ', the illumination drive motor is connected to the low price plate simple relay substrate 1600' There is no connector, and the connection lines M11 to M14 and the connection lines M21 to M24 are also not used. Therefore, the vacant terminal monitor 603 is also connected to the connection lines M11 to M14 and the connection lines M21 to M24 in the low-priced simple relay substrate 1600 '.

  Further, since the motor position detection sensor 560b is not provided in the low price plate front frame 3 ', in the low price version simple relay substrate 1600', the connection lines SE1 to SE3 are connected to the ground and a signal of a certain level is provided. Is configured to be constantly input to the effect control device 550.

  FIG. 17 is a block diagram of a decoration control device 610 according to the first embodiment of this invention.

  As described above, the decoration control device 610 according to the first embodiment of the present invention is classified into three types of branch type, connection type and termination type based on the connection form. FIG. 17 shows an example in which a termination type decoration control device 610Y is connected to the branch type decoration control device 610X. Further, a decoration device substrate 625 is connected to the decoration control device 610Y.

The branch-type decoration control device includes an I ² CI / O expander 615, a connector (upstream connector) for receiving a signal received by the I ² CI / O expander 615, and a signal received from the upstream connector. A connector (downstream connector) for transmitting to a plurality of decoration control devices 610 is provided. For example, as in the decoration control device 610X in the figure, the device internally includes an I ² CI / O expander 615 and an LED (decorative device 620), and further includes one upstream connector 611 and two downstream connectors 612A and 612B. .

The connection line SDA and the connection line SCL are branched into two in the decoration control device 610, and one is directly connected to the downstream connector 612B for outputting to the next decoration control device 610Y. The other branches further, one is connected to the I ² CI / O expander 615, and the other is connected to another downstream connector 612A.

The decoration device 620 to be controlled is connected to the output side of the I ² CI / O expander 615 of the decoration control device 610X. The output side of the I ² CI / O expander 615 is configured by ports 0 to 15 described in FIG. Furthermore, all ports of the decoration control device 610 are connected to the internal LEDs via current limiting resistors R0 to R15 described later in FIG. The current limiting resistors R0 to R15 are also included in the decoration control device 610.

As described above, the I ² CI / O expander 615 includes the address included in the effect control data input from the effect control device 550 and the individual address set in the I ² CI / O expander 615. Only when it matches, the decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the presentation control data.

In addition, since only one downstream connector is provided, the decoration control device capable of transmitting the signal received from the upstream connector to only one decoration control device 610 is a coupled decoration control device. For example, in the decoration control device 610X described above, only the downstream connector 612B is provided, and the downstream connector 612A is not present.

The termination type decoration control device has an I ² CI / O expander 615 and a connector (upstream connector) for receiving a signal received by the I ² CI / O expander 615, but receives from an upstream connector Signals are not transmitted to other decoration control devices 610. For example, the decoration control device 610Y in the figure includes an I ² CI / O expander 615 and an LED (decorative device 620), and supplies current to the LED provided on the decorative device substrate 625 connected to the outside of the decorative control device 610Y. The decoration control device 610 and the decoration device substrate 625 are connected via a connection line for supplying power, a power supply voltage to the LED of the decoration device substrate 625, and a connection line connected to ground.

The decoration device substrate 625 is a substrate that does not include the I ² CI / O expander 615 but includes only a light emitting device such as an LED. In this case, a current limiting resistor connected to the LED provided on the decoration device substrate 625 is provided on the decoration device substrate 625, but provided on the decoration control device 610 provided with the I ² CI / O expander 615. It is also good.

It should be noted that the number of connection lines for causing current to flow to the decoration device substrate 625 is determined corresponding to the number of LEDs provided on the decoration device substrate 625. . For example, when the decoration device substrate 625 is provided with two LEDs, two control lines for connecting the port of the I ² CI / O expander 615 to the corresponding LEDs, and the power supplied from Vled And at least one power supply line for supplying

The I ² CI / O expander 615 provided in the decoration control device 610 Y is also set to the address included in the effect control data input from the effect control device 550 and to the I ² CI / O expander 615. The decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the presentation control data only when the address matches the address. In this case, both the decoration device 620 provided in the central decoration control device 610 and the decoration device 620 provided in the decoration device substrate 625 are controlled by the I ² CI / O expander 615.

Thus, by providing the decoration device substrate 625 and separating some decoration devices (LEDs) from the decoration control device 610, the common I ² CI / is obtained even if the LEDs are arranged at a distant place. It can be controlled by O expander 615.

  As described above, the decoration control device 610 can control movable objects such as solenoids and motors instead of light emitting devices such as LEDs, and will be specifically described later with reference to FIG.

FIG. 18 is a block diagram showing the configuration of the I ² CI / O expander 615 according to the first embodiment of this invention.

The I ² CI / O expander 615 includes a transistor 630 connected to the connection line SDA, a filter 631 connected to the connection line SDA, a driver 632 connected to the connection line SDA, and a filter 633 connected to the connection line SCL A bus controller 634, an output setting register 635, an output controller 636, a driver 637 connected to each port 0 to 15 on the output side of the I ² CI / O expander 615, and a transistor 638A to 638 P connected to each port 0 to 15 And a reset signal generation circuit 639. Furthermore, in the first embodiment of the present invention, a bus monitoring WDT (watchdog timer) 640 for determining whether or not the connection line SDA is occupied by another I ² CI / O expander 615, and I ²
A self-occupied WDT 641 is provided to determine whether the CI / O expander 615 itself occupies the connection line SDA.

  The filter 631 is connected to the connection line SDA, removes noise of the data input from the connection line SDA, and outputs the data from which the noise is removed to the bus controller 634. When the driver 632 outputs a response signal from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

  When the driver 632 outputs data (a response signal) from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

  In the transistor 630, a field effect transistor (FET) is used to reduce power consumption, the gate of the transistor 630 is connected to the driver 632 and the drain is a connection line SDA to which a predetermined voltage is applied by the pull-up resistor R. And the source is grounded.

  If the voltage applied to the gate of the transistor 630 is smaller than the predetermined value for operating the transistor 630, no current flows between the drain and the source. On the other hand, if the voltage applied to the gate of the transistor 630 is equal to or higher than the predetermined value for operating the transistor 630, a current flows from the drain to which the voltage of the predetermined value is applied to the grounded source. The voltage drops. Note that the transistor 630 has a specification which is not broken even when a current of about 10 milliamperes flows from the drain to the source.

  The driver 632 applies a voltage having an operable value of the transistor 630 to the gate of the transistor 630 in order to flow current between the drain and the source in the transistor 630 when outputting data (a response signal) from the connection line SDA. Do. Then, the driver 632 outputs data from the connection line SDA by repeatedly changing the voltage of the connection line SDA from HIGH to LOW.

  The filter 633 is connected to the connection line SCL, removes noise of data input from the connection line SCL, and outputs the data from which the noise is removed to the bus controller 634.

In ^addition, the I 2 CI / O expander 615, is set a unique address by the address setting terminals A0~A3 provided in the ^I 2 CI / O expander 615 is input to the bus controller 634. Furthermore, an address for resetting the I ² CI / O expander 615 is also preset.

The bus controller 634 determines whether the address of the data input from the connection line SDA matches the unique address set in the I ² CI / O expander 615, and if it matches, the data is Captured as effect control data.

Further, the bus controller 634 determines whether the address of the data input from the connection line SDA matches the reset address set in the I ² CI / O expander 615, and if the addresses match. The data is taken as initialization instruction data, and the I ² CI / O expander 615 is initialized.

In addition, when the number of times the signal level of the connection line SCL changes from LOW to HIGH reaches eight times and the data of the eighth bit is taken, the bus controller 634 changes the signal level of the connection line SCL from HIGH to LOW. , And outputs a response signal from the connection line SDA to the first master IC 570a. Further, it is confirmed that the signal level of the connection line SCL changes from LOW to HIGH, and when the signal level of the connection line SCL changes from HIGH to LOW again, the connection line SDA is released. That is, the response signal is output at the timing when the number of changes from LOW to HIGH of the signal level of the connection line SCL is nine.

In the output setting register 635, the operation mode of the I ² CI / O expander 615 and the output state of the ports 0 to 15 are set. When the bus controller 634 takes in initialization instruction data from the connection line SDA and the I ² CI / O expander 615 is initialized, the output setting register 635 causes current to flow to all the ports 0-15. It is set to the initial state so as not to.

  The output controller 636 actually sends the current to the rendering device connected to each of the ports 0 to 15 through the port driver 637 based on the data set in the output setting register 635 to actually output the rendering device. Control. This output state is updated to the contents specified in the effect control data when the bus controller 634 takes in the effect control data from the connection line SDA.

That is, based on the rendering control data received from the first master IC 570a, it is set in the output setting register 635, and when the stop condition is received, the output state of each port 0 to 15 is updated and reflected on the rendering device. Therefore, as in the shift register, the effect control can be performed without the need to receive the LAT signal, that is, without the need for wiring for receiving the LAT signal. In particular, it is effective when the port output state needs to be simultaneously updated by a plurality of I ² CI / O expanders 615, and even a rendering device controlled by different I ² CI / O expanders 615, At the same time, since the rendering operation can be controlled to be performed, the rendering effect can be further enhanced.

The output state of each of the ports 0 to 15 may not be updated and reflected on the rendering device when the stop condition is received, but may be reflected on the rendering device when the response signal is output. When a rendering device that is required to execute the rendering operation at the same time is controlled by one I ² CI / O expander 615, it may be reflected on the rendering device when the response signal is output. By doing this, the master IC does not have to output a stop condition, and it is possible to transmit presentation control information continuously, so that presentation control can be performed at high speed.

  The driver 637 applies a voltage to which the transistors 638A to 638P, which are connected to the port through which current flows, can operate when the current flows through the port.

  The gates of the transistors 638A to 638P are connected to the driver 637, the drain is connected to the port terminal connected to the connection line to which the voltage for operating the rendering device is applied as shown in FIGS. 19 and 20, and the source is grounded It is done.

  If the voltage applied to the gates of the transistors 638A to 638P is smaller than a predetermined value for operating the transistors 638A to 638P, no current flows between the drain and the source. On the other hand, if the voltage applied to the gates of 638A to 638P is equal to or higher than the predetermined value for operating transistor 638, the predetermined voltage applied to the gate from power supply Vled shown in FIG. 19 or power supply Vmot or power supply Vsol shown in FIG. When the voltage of the current flows through the drain of the transistor 638 to the grounded source, the output state of the rendering device connected to the port terminal can be controlled.

In addition, the I ² CI / O expander 615 of the decoration control device 610 is connected to the port terminal of the I ² CI / O expander 615 (all decoration devices 620 such as LEDs)
Can be controlled simultaneously, so that one rendering device connected to the port terminal of the I ² CI / O expander 615 can be controlled as one group.

And since I ² CI / O expanders 615 provided in each decoration control device 610 are assigned different individual addresses, the rendering device is divided into a plurality of groups. That is, the I ² CI / O expander 615 included in each decoration control device 610 is configured as group unit control means capable of controlling the rendering device in group units.

  Therefore, the effect control device 550 that controls each decoration control device 610 functions as a group general control device that controls the group unit control device.

The reset signal generation circuit 639 is connected to a Vcc terminal connected to a connection line Vcc for supplying power to the I ² CI / O expander 615, and a RESET terminal for receiving an external reset signal.

The reset signal generation circuit 639 generates a reset signal when the I ² CI / O expander 615 is powered on and the voltage rises to a predetermined value, and the generated reset signal is output to the bus controller 634, the output setting register 635, And the output controller 636 for initialization.

Therefore, when the harness (FIG. 15) is removed, the connection line Vcc is temporarily disconnected, and when the harness is reinserted, the power supply is restored, and the reset signal generating circuit 639 outputs a reset signal. That is, when repairing or checking the gaming machine, the I ² CI / O expander 615 can be reset by inserting and removing the harness.

  Since the reset signal generation circuit 639 outputs the reset signal when the reset signal at the LOW level is externally input, the CPU 551 of the effect control device 550 passes the NOR gate circuit 561 to the RESET terminal. The reset signal may be input. When the RESET terminal is not used, the RESET terminal may be pulled up to HIGH as shown in FIG. 19 and FIG.

The bus monitoring WDT 640 is used to detect that the other I ² CI / O expander 615 occupies the connection line SDA. The bus monitoring WDT 640 is connected between the filter 631 and the bus controller 634, takes in the signal level of the connection line SDA, and measures the time during which the level is continuously LOW. Further, the bus monitoring WDT 640 is connected to the reset signal generation circuit 639, and operates a reset signal generation circuit 639 of its own when a predetermined time elapses after the connection line SDA is occupied, and the I ² CI / O Expander 615 is initialized.

The connection line SDA is because it is connected to other ^I 2 CI / O expander 615, in all of the ^I 2 CI / O expander 615 where the connecting line SDA is connected, occupancy of the connection line SDA Will be detected. Then, the reset signal generation circuit 639 provided in the inside of the I ² CI / O expander 615 operates to initialize all the I ² CI / O expanders 615 to which the connection line SDA is connected. Be done.

Self-occupied WDT 641 is used to detect occupancy of connection line SDA by itself (I ² CI / O expander 615). The bus controller 634 operates the driver 632 to drive the connection line SDA to low level, operates the self-occupied WDT 641, and stops the self-occupied WDT 641 while the connection line SDA is not driven to the low level. . Then, when the self-occupied WDT 641 operates continuously for a fixed time, the self-occupied WDT 641 generates a reset signal in the reset signal generation circuit 639 to initialize the I ² CI / O expander 615.

Thus, it is possible to monitor a period in which the bus controller 634 itself is driving the connection line SDA to a low level (a period in which the I ² CI / O expander 615 occupies the connection line SDA). Self-occupied WDT 641 starts measuring time at the timing of occupying connection line SDA to transmit a reply signal (ACK, NACK) to data received from the master IC, and when a predetermined time passes, a reset signal generation circuit 639 generates a reset signal. According to this configuration, when occupancy of connection line SDA is detected by self-occupation WDT 641, only its own I ² CI / O expander 615 is reset.

FIG. 19 is a circuit diagram around the I ² CI / O expander 615 of the decoration control device 610 that controls the decoration device 620 according to the first embodiment of this invention.

The I ² CI / O expander 615 includes an NC terminal, a RESET terminal, an SCL terminal, an SDA terminal, a Vcc terminal, an A0 to A3 terminal, and a GND terminal as input terminals, and PORT0 to PORT15 as output terminals.

The power supply supplied to the I ² CI / O expander 615 via the pull-up resistor R is connected to the RESET terminal. Therefore, the voltage applied to the reset terminal is always maintained at HIGH.

  The SCL terminal is connected to the connection line SCL, and the SDA terminal is connected to the connection line SDA.

The power supply supplied to the I ² CI / O expander 615 is connected to the Vcc terminal. Further, a capacitor CP for removing power supply noise is connected to the Vcc terminal.

Terminals A0 to A3 are terminals for setting an individual address in the I ² CI / O expander 615. The individual address of the I ² CI / O expander 615 is usually expressed by 4 bits, and when the power of the I ² CI / O expander 615 is applied to this terminal, the bus controller 634 Is set, and when this terminal is connected to the ground, the bus controller 634 is set to “0”.

Therefore, the individual address of the I ² CI / O expander 615 shown in FIG. 19 is “0100”. The GND terminal is a terminal for grounding a voltage.

  The PORT0 terminal to the PORT15 terminal are connected to the decoration device 620 including the LED0 to the LED15 via the current limiting resistors R0 to R15. As in PORT0, one LED may be connected to one port, but as in PORT 1-15, a plurality of LEDs may be connected to one port.

If one LED is provided for every port, one I ² CI / O expander 615 can control up to 16 LEDs. In addition, when the number of LEDs connected to each port is different, if all LEDs connected in series to one port are one type of LED, one I ² CI / O expander With 615, up to 16 types of LEDs can be controlled.

  When a voltage is applied from the driver 637 to the gates of the transistors 638A to 638P (see FIG. 18) connected to the PORT0 terminal to the PORT15 terminal, a current flows from the drain to the source of the transistors 638A to 638P to which the voltage is applied. It becomes possible, current flows to LED0-LED15 connected to PORT0 terminal-PORT15 terminal, and each LED0-LED15 lights.

  On the other hand, if the driver 637 does not apply a voltage to the gates of the transistors 638A to 638P, no current flows in the LEDs 0 to 15 and the LEDs 0 to 15 do not light.

  Since the connection line Vled is disconnected while the harness (FIG. 15) is removed from the connector, no current is supplied to the LEDs 0 to 15 and the light is turned off. Since the power supply from the connection line Vled can be interrupted simply by removing the harness, repair and inspection of the gaming machine can be performed safely.

In addition, it is also possible to connect a motor or a solenoid to the PORT0 terminal to the PORT15 terminal of the I ² CI / O expander 615 instead of the LED, and configure the motor or the solenoid as a rendering device using for gaming . Hereinafter, a case where a motor or a solenoid is controlled using the I ² CI / O expander 615 will be described with reference to FIG.

FIG. 20 is a circuit diagram around the I ² CI / O expander 615 of the decoration control device 610 according to the first embodiment of this invention, showing a case of controlling a motor and a solenoid.

  The motor used here is constituted by a stepping motor, and is rotated by sequentially applying a predetermined voltage to signal terminals of respective phases which drive the stepping motor. In the first embodiment of the present invention, signal terminals of respective phases of the motor are connected to PORT0 terminal to PORT3 terminal.

  When a voltage is applied from the driver 637 to the gate of any of the transistors 638A to 638D connected to the PORT0 terminal to the PORT3 terminal connected to the motor, the drain to source of the transistors 638A to 638D to which the voltage is applied It becomes possible for the current to flow to the motor connected to the PORT0 terminal to the PORT3 terminal, and the motor for driving the accessory is driven.

  The connection lines connecting the PORT0 terminals to the PORT3 terminals and the motor are branched, and one branched connection line is connected to the power supplied to the motor via the diode D and the Zener diode ZD.

  Also, the PORT terminal 15 is connected to a solenoid to be used. When a voltage is applied from the driver 637 to the gate of the transistor 638P connected to the PORT 15 terminal connected to the solenoid, a current can flow from the drain to the source of the transistor 638P to which the voltage is applied. A current flows to the solenoid connected to the PORT 15 terminal, and a rendering device (not shown) driven by the solenoid is driven.

Although both the motor and the solenoid are connected to the I ² CI / O expander 615 in FIG. 20, only one of the motor and the solenoid is connected to one I ² CI / O expander 615. It may be a configuration.

For example, the I ² CI / O expander 615 as a group controlling only a stepping motor is provided exclusively, or the I ² CI / O expander 615 as a group controlling only a solenoid is provided exclusively. It is also good. With such a configuration, it is possible to control the rendering devices belonging to the same group at the same timing, and it is also possible to group only the rendering devices that require high-speed processing for efficient control.

  FIG. 21 is a diagram for explaining a circuit configuration of the decoration control device 610, the relay substrate 600 and the simple relay substrate 1600 according to the first embodiment of the present invention, and in particular, relates to input / output of signal lines and power supply lines. It is a figure for demonstrating a connection state.

  In the figure, among the decoration control device 610, the relay substrate 600, and the simple relay substrate 1600, the branch-type decoration control device 610 (for example, the decoration control device 610A etc.) will be described. The differences from the decoration control device 610, the terminal decoration control device 610, the relay substrate 600, and the simple relay substrate 1600 will be described.

  In the drawing, the description will be given with the same reference numerals as the parts provided in the above-described branch type decoration control device 610X.

The branch-type decoration control device 610 includes an upstream connector 611, a downstream connector 612 (612A, 612B), and an I ² CI / O expander 615.

  The upstream connector 611 is a connector connected to the decoration control device 610 upstream of the decoration control device 610. The downstream connectors 612A and 612B are connected to the decoration control device 610 on the downstream side of the decoration control device 610.

  In order to connect the connection line SDA to the two downstream connectors 612A and 612B, the internal connection line SDA2111 extending from the upstream connector 611 branches into a first connection line SDA2121 and a second connection line SDA2131 at a branch 2101. The first connection line SDA2121 is connected to the downstream connector 612A, and the second connection line SDA2131 is connected to the downstream connector 612B.

  Similarly, the internal connection line SCL2112 extending from the upstream connector 611 branches into a first connection line SCL2122 and a second connection line SCL2132 at a branch 2102. The first connection line SCL2122 is connected to the downstream connector 612A, and the second connection line SCL2132 is connected to the downstream connector 612B.

Further, in order to connect the connection line SDA to the I ² CI / O expander 615, the second connection line SDA 2131 branches at a branch 2103, and the branched second connection line SDA 2131 is a diagram of the I ² CI / O expander 615. 19 and the SDA terminal shown in FIG. Also, in order to connect the connection line SCL to the I ² CI / O expander 615, the second connection line SCL 2132 branches at a branch 2104, and the branched second connection line SCL ² 132 is a diagram of the I ² CI / O expander 615. It is connected to the SCL terminal shown in FIG. Hereinafter, the connection line SDA connected to the I ² CI / O expander 615, the branch 2103 to the I ² CI / O expander 615, and the connection line SCL connected to the I ² CI / O expander 615 from the branch 2104 A configuration to be included is an I ² CI / O expander unit 2181.

The I ² CI / O expander 615 is supplied with a voltage Vcc which is a power supply voltage of the I ² CI / O expander 615. Although not shown in FIG. 21, the I ² CI / O expander 615 sends signal lines (shown in FIG. 19) to the ports 0 to 15 for driving the LED (decorative device 620) provided in the ornamental control device 610. Reference is output.

Furthermore, from the signal output from the I ² CI / O expander 615 of the decoration control device 610 to the upstream decoration control device 610 via the connection line SDA, and from the upstream decoration control device 610,
In order to remove noise of a signal input to the I ² CI / O expander 615 of the decoration control device 610 via the connection line SDA, a Zener diode ZD 2141 is connected to the internal connection line SDA 2111.

  Specifically, the internal connection line SDA2111 branches at a branch 2105, the branched internal connection line SDA2111 is connected to the cathode side of the Zener diode ZD2141, and the anode side of the Zener diode ZD2141 is grounded.

  Therefore, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SDA2111 is released by the Zener diode ZD2141.

In addition, in order to remove noise of a signal input from the upstream decoration control device 610 to the I ² CI / O expander 615 of the decoration control device 610 via the connection line SCL, the internal connection line SCL 2112 is a Zener. The diode ZD2142 is connected.

  Specifically, the internal connection line SCL2112 branches at a branch 2106, the branched internal connection line SCL2112 is connected to the cathode side of the Zener diode ZD2142, and the anode side of the Zener diode ZD2142 is grounded.

  Therefore, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SCL2112 is dissipated by the Zener diode ZD2142.

Further, the I ² CI / O expander 615 of the decoration control device 610 outputs a signal output to the decoration control device 610 connected to the downstream connector 612A via the connection line SDA, and the decoration control connected to the downstream connector 612A. A Zener diode ZD2143 is connected to the first connection line SDA2121 in order to remove noise of a signal input from the device 610 to the I ² CI / O expander 615 of the decoration control apparatus 610 through the connection line SDA. .

  Specifically, the first connection line SDA2121 branches at a branch 2107, the branched first connection line SDA2121 is connected to the cathode side of the Zener diode ZD2143, and the anode side of the Zener diode ZD2143 is grounded.

  Therefore, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the first connection line SDA2121 is released by the Zener diode ZD2143.

  Further, similarly to the Zener diode ZD2143 connected to the first connection line SDA2121, the Zener diode ZD2145 is connected to the second connection line SDA2131.

In addition, in order to remove noise of a signal input from the I ² CI / O expander 615 of the decoration control device 610 to the decoration control device 610 connected to the downstream connector 612A via the connection line SCL, the first connection line The Zener diode ZD2144 is connected to the SCL2122.

  Specifically, the first connection line SCL2122 branches at a branch 2108, the branched first connection line SCL2122 is connected to the cathode side of the Zener diode ZD2144, and the anode side of the Zener diode ZD2144 is grounded.

  Therefore, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the first connection line SCL2122 is dissipated by the Zener diode ZD2144.

  Further, similarly to the Zener diode ZD2144 connected to the first connection line SCL2122, the Zener diode ZD2146 is also connected to the second connection line SCL2132.

Furthermore, an internal connection line Vcc 2171 extending from the Vcc terminal of the upstream connector 601 connected to the connection line Vcc supplying the power supply voltage to the I ² CI / O expander 615 of the decoration control device 610 and a GND terminal of the upstream connector 601 The extended and grounded internal connection line GND2172 is connected via the smoothing capacitor C2161 and the bypass capacitor CP2162.

  The smoothing capacitor C2161 is a capacitor for smoothing the voltage waveform of the power supply, and the bypass capacitor CP2162 is a capacitor for removing noise of the voltage of the power supply.

For this reason, the power supply voltage supplied to the I ² CI / O expander 615 of the decoration control device 610 is smoothed by the smoothing capacitor C2161 and noise is removed by the bypass capacitor CP2162, and the I ² CI / O expander is removed. It is supplied to the panda 615.

  Similarly, the internal connection line Vcc2173 extending from the Vcc terminal of the downstream connectors 612A and 612B and the internal connection line GND2174 extending from the GND terminal are connected via the smoothing capacitor C2161 and the bypass capacitor CP2162. Thereby, the smoothed and denoised voltage is applied to the connection line Vcc connected to the decoration control device 610 downstream.

  The branch type decoration control device 610 has been described above. Next, the connection type decoration control device 610 will be described.

  In addition to the downstream connector 612A, the Zener diode ZD2143 connected to the connection line SDA, the Zener diode ZD2144 connected to the connection line SCL, the internal connection line Vcc2173, the internal connection line GND2174, the smoothing capacitor C2161 and the bypass capacitor CP2162 The configuration is referred to as a first downstream connector portion 2182.

  In addition to the downstream connector 612B, the Zener diode ZD2145 connected to the connection line SDA, and the Zener diode ZD2146 connected to the connection line SCL, the internal connection line Vcc2173, the internal connection line GND2174, the smoothing capacitor C2161 and the bypass capacitor CP2162 The configuration is a second downstream connector portion 2183.

  When the decoration control device 610 is of a connected type, only one downstream connector is provided in the substrate, so the downstream connector 612A is present but the downstream connector 612B is not present.

  Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 do not branch at the branches 2103 and 2104, and the second connection line SDA2131 and the second connection line SCL2132 do not exist, which is different from the decoration control device 610 of the branch type. It becomes composition.

  Further, the connection type decoration control device 610 is also different from the branch type decoration control device 610 in that there is no electronic component that constitutes the second downstream connector portion 2183. The other configuration is the same as that of the branch type decoration control device 610.

  Next, the termination type decoration control device 610 will be described.

In the case where the decoration control device 610 is a terminal type, since the downstream connector is not provided in the substrate, both of the downstream connectors 612A and 612B are not present.

Therefore, the branch-type decoration control device 610 is connected to the I ² CI / O expander 615 in that the internal connection line SDA2111 and the internal connection line SCL2112 are not branched at the branches 2101, 2102, 2103, and 2104. Have different configurations.

  In addition, the termination-type decoration control device 610 is different from the branch-type decoration control device 610 in that there is no electronic component that constitutes the first downstream connector portion 2182 and the second downstream connector portion 2183. The other configuration is the same as that of the branch type decoration control device 610.

  Next, the relay substrate 600 will be described.

  Since the relay substrate 600 is configured to include only one downstream connector in the substrate as in the connection type decoration control device 610, the downstream connector 612A is present but the downstream connector 612B is not present.

  Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 do not branch at the branches 2103 and 2104, and the second connection line SDA2131 and the second connection line SCL2132 do not exist, so the same configuration as the connection type decoration control device 610 It becomes.

  However, the relay substrate 600 is different from the connection type decoration control device 610 in that the relay substrate 600 is provided with a pull-up resistor for pulling up the voltage of the connection line SDA and the connection line SCL.

  Specifically, as shown in FIG. 21, in the relay substrate 600, the voltages of the upstream connection line SDA connected to the first master IC 570a and the downstream connection line SDA connected to the decoration control device 610 are selected. A pull-up resistor R2151 for pull-up is connected to the first connection line SDA2121. Similarly, a pull-up resistor R2152 for pulling up the voltage of the upstream connection line SCL connected to the first master IC 570a and the downstream connection line SCL connected to the decoration control device 610 is a first connection line. Connected to SCL2122.

  More specifically, the first connection line SDA2121 branches at a branch 2109, and the branched first connection line SDA2121 is connected to the pull-up resistor R2151. Similarly, the first connection line SCL2122 branches at a branch 2110, and the branched first connection line SCL2122 is connected to the pull-up resistor R2152. Hereinafter, a pull-up resistor portion 2180 is obtained by combining a pull-up resistor R2151 for pulling up the voltage of the connection line SDA and a pull-up resistor R2152 for pulling up the voltage of the connection line SCL.

  Next, the simple relay board 1600 will be described.

The simple relay substrate 1600 includes a plurality of downstream connectors (downstream connectors 612A and 612B) in the substrate, as in the branch type decoration control device 610. However, simple relay substrate 1600 does not include a circuit corresponding to I ² CI / O expander unit 2181, and instead, a circuit corresponding to the aforementioned pull-up resistor unit 2180 provided on relay substrate 600 is provided. The configuration is different from that of the branch type decoration control device 610. The other configuration is the same as that of the branch type decoration control device 610.

In the present embodiment, the above-described configuration of the pull-up resistor unit 2180 is provided only on the relay substrate 600 and the simple relay substrate 1600, and is not provided on the decoration control device 610 or the effect control device 550. However, as long as the levels of the connection line SDA and the connection line SCL can be generated correctly, they may be provided in the decoration control device 610 or the presentation control device 550. That is, the pull-up resistors R2151 and 2152 may be provided at locations where the voltage Vcc can be supplied to the terminals of the drains of the transistors driving the connection lines SDA and SCL.

  For example, if the pull-up resistors R2151 and 2152 are provided in the first master IC 570a, the pull-up resistor unit 2180 does not have to be provided in the relay substrate 600, the simple relay substrate 1600, or the decoration control device 610.

  FIG. 22 is an explanatory diagram of a slave address 2200 included in data output from the effect control device 550 according to the first embodiment of this invention to the decoration control device 610.

  The slave address 2200 is composed of a fixed address portion 2201 consisting of upper 3 bits and a variable address portion 2202 consisting of lower 5 bits.

The fixed address portion 2201 has a value of “110” set in advance, and can not be changed by the I ² CI / O expander 615.

The variable address unit 2202 can be set by the I ² CI / O expander 615. The variable address unit 2202 has a 4-bit I ² CI / O expander address 2203 corresponding to the pattern set to the terminals A0 to A3 of the I ² CI / O expander 615 to be controlled, and the data. It is constituted by 1-bit R / W identification data 2204 indicating whether it is a read request (“1”) or a write request (“0”).

  Since the effect control data output from the effect control device 550 to the decoration control device 610 is a write request, “0” is normally registered in the R / W identification data 2204.

FIG. 23 is an explanatory diagram of an I ² CI / O expander address table 2300 according to the first embodiment of this invention.

The I ² CI / O expander address table 2300 is a table managed by the first master IC 570 a. The I ² CI / O expander address table 2300 shows the correspondence between the slave address 2301 and the I ² CI / O expander address 2302.

The slave address 2301 stores a slave address of the decoration control device 610 designated as a target of transmission and reception by the effect control device 550. As described above with reference to FIG. 20, the slave address is configured by combining the high-order 3-bit fixed address portion, 4-bit I ² CI / O expander address, and 1-bit R / W identification data. .

In the I ² CI / O expander address 2302, as described above with reference to FIGS. 19 and 20, the 4-bit I ² CI / O expander address corresponding to each slave address is registered.

However, among the I ² CI / O expander addresses, the address “1000” and the address “1011” (shaded entries in FIG. 23) are for identifying the respective I ² CI / O expanders 615 to each other. It can not be used as a unique address.

The address “1000” is used as a power-on default value of the address (all call address) specified when outputting a common command to all the decoration control devices 610. The address "1011" is the first master IC 570a by software.
Is a common address used when unconditionally resetting all the decoration control devices 610 connected to.

As described above, since 14 addresses can be set in the I ² CI / O expander 615 of the decoration control device 610, the effect control device 550 controls the 14 I ² CI / O expander 615. be able to. Moreover, since each decoration control device 610 is provided with PORT0 to PORT15, it is possible to control 16 (16 types of) LEDs. Therefore, the effect control device 550 can control 224 LEDs (in other words, 224 types).

FIG. 24 is a diagram for describing a work register assigned to the output setting register 635 provided in the I ² CI / O expander 615 according to the first embodiment of this invention.

A work register (device register) and a control register (control register) are assigned to the output setting register 635 of the I ² CI / O expander 615.

The work register is information for setting the I ² CI / O expander 615 in advance, or a rendering device (decor device 620, for example, connected to the I ² CI / O expander 615). It stores information for specifying the output mode of the LED).

  The control register also stores information that defines the procedure for writing data to the work register. The work register is configured to distribute and store a plurality of pieces of information in different storage areas, and a different register number is assigned to each storage area.

The register number “00h” and the register number “01h” correspond to a mode register for initializing the I ² CI / O expander 615. The register name "MODE1" is assigned to the storage area of the register number "00h". Further, the register name "MODE2" is assigned to the storage area of the register number "01h". When values are written to the storage areas of register numbers “00h” and “01h”, initialization of the I ² CI / O expander 615 is performed based on the written values.

Note that bit 3 (OCH) of the “MODE 2” register is a parameter that defines the timing at which the effect control data stored in the output setting register 635 of the I ² CI / O expander 615 is actually reflected on the effect device . In the first embodiment of the present invention, as described in FIG. 18, “0” is set, and the presentation control data stored in the output setting register 635 is output when the stop condition is received. , It is set to actually control the output state of the rendering device. Further, in the fourth embodiment, the value of bit 3 (OCH) of the register of “MODE 2” is set to “1”, and the effect stored in the output setting register 635 when the reply signal (ACK) is output. An embodiment will be described which is set to output control data and to actually control the output state of the rendering device.

In the register numbers “02h” to “11h” (register names “PWM0” to “PWM15”), parameters to be controlled such as LEDs included in the decorative device 620 are set. When a value is written to any of the storage areas of register numbers “02h” to “11h”, of the 16 LEDs constituting the light emitting device (decorative device 620) connected to I ² CI / O expander 615 The brightness of the LED corresponding to the register number into which the value is written is adjusted based on the written value. For example, when a value is written to the storage area of the register number “02h”, the luminance of the LED 0 connected to the port 0 shown in FIG. 19 is adjusted.

Note that, as described above, the I ² CI / O expander 615 can also control movable objects such as motors and solenoids. When a solenoid is connected to the I ² CI / O expander 615, the solenoid is energized to operate the register number corresponding to the port to which the solenoid is connected, or is not operated without energization. A value indicating what to do is written. When the motor is connected to the I ² CI / O expander 615, a value indicating the target rotational position of the motor is written in the register number corresponding to the port to which the motor is connected.

  In the register number "12h" (register name "GRPPWM") and the register number "13h" (register name "GRPFREQ"), parameters for specifying the operation pattern of the entire control object and the like are set. When values are written to the storage areas of the register numbers “12h” and “13h”, the blinking pattern of the entire LED (16 LEDs) is set based on the written values. Specifically, a duty cycle which is the on / off ratio of the entire LED is set to the register number "12h", and a blinking cycle of the entire LED is set to the register number "13h".

  The output states of the LEDs controlled by the respective ports are set in the register numbers “14h” (register name “LEDOUT0”) to “17h” (register name “LEDOUT3”). In each register, it is possible to set four LED output states.

  When a value is written to the storage area of the register number "14h", the output states of LED0 to LED3 are set based on the written value. Similarly, the output states of the LED4 to LED7 are stored in the storage area of the register number "15h", the output states of the LED8 to LED11 are stored in the storage area of the register number "16h", and the LED12 to LED15 are stored in the storage area of the register number "17h". The output state of is set.

  Subaddresses are set to register numbers “18h” to “1Ah” (register names “SUBADR1” to “SUBADR3”). When values are written in the storage areas of register numbers “18h” to “1Ah”, first to third subaddresses are set based on the written values.

  An all-call address for outputting a command to all the decoration control devices 610 is set in a register number "1Bh" (register name "ALLCALLADR"). The all-call address is used, for example, when the initialization process is performed by all the decoration control devices 610 when the power is turned on.

  FIG. 25 is an explanatory diagram of the start condition and the stop condition in which the master IC according to the first embodiment of this invention outputs data via the connection line SDA and the connection line SCL.

  The connection line SCL has a signal level of HIGH when data is not transmitted. When outputting data to the decoration control device 610, the master IC changes the signal level of the connection line SCL from LOW to HIGH, and causes the decoration control device 610 to act as a strobe signal for capturing data of the connection line SDA.

  The signal level of the connection line SDA is HIGH when data is not transmitted, and data is output from the connection line SDA in accordance with the clock signal of the connection line SCL.

  The master IC outputs a signal serving as a start condition indicating that data output starts by changing the signal level of connection line SDA from HIGH to LOW while maintaining the signal level of connection line SCL high. .

The I ² CI / O expander 615 of the decoration control device 610 recognizes that output of data is started when a signal as a start condition is input from the connection line SDA and the connection line SCL.

  The master IC changes the signal level of the connection line SDA from low to high while maintaining the signal level of the connection line SCL high, and outputs a signal serving as a stop condition indicating that the output of data is completed. .

The I ² CI / O expander 615 of the decoration control device 610 recognizes that the output of the data ends when the signal serving as the stop condition is input. In the first embodiment of the present invention, as described above, when the decoration control device 610 receives a signal that is a stop condition, control of the rendering device (decoration device 620) controlled by the decoration control device 610 is started. .

  FIG. 26 is a timing chart in which the decoration control device 610 to which the data output from the master IC according to the first embodiment of this invention is input outputs a response signal.

  The decoration control device 610 counts the number of changes in the signal level of the connection line SCL after the start condition is satisfied, and takes in data input from the connection line SDA in accordance with the clock signal of the connection line SCL.

  Then, the decoration control device 610 outputs a response signal to the master IC via the connection line SDA immediately before the start condition is satisfied and immediately before the number of changes in the signal level of the connection line SCL reaches nine. In other words, the decoration control device 610 outputs a response signal via the connection line SDA when the signal level of the connection line SCL changes from HIGH to LOW after taking in the data of the 8th bit from the connection line SDA. Do.

  As shown in FIG. 26, a response signal (ACK response signal) indicating that data reception was successful is indicated by the LOW level, and a response signal (NACK response signal) indicating that data reception failed. In the figure, corresponding to no ACK output) is indicated by the HIGH level.

  In addition, when the signal level of the connection line SCL changes eight times after the start condition is satisfied, the master IC waits for the input of the response signal from the decoration control device 610 by releasing the connection line SDA. Then, the master IC changes the signal level of the connection line SCL while releasing the connection line SDA, and takes in the response signal from the decoration control device 610.

  FIG. 27 is a timing chart of signal levels of the connection line SDA and the connection line SCL when the master IC according to the first embodiment of this invention outputs effect control data.

  First, when starting to output data, the master IC changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL high, thereby indicating a start condition. , And notify the decoration control device 610 to start outputting data.

  Next, the master IC outputs the slave address of the decoration control device 610 to be controlled, which consists of 7 bits in total. Further, the master IC outputs information indicating whether it is a write request which is a read request to the eighth bit.

Then, when the signal level of the connection line SCL goes high for the ninth time, the master IC
Since the response signal is input from the decoration control device 610, the signal level of the connection line SDA changes to LOW if it is an ACK response signal, and the signal level of the connection line SDA changes to HIGH if it is a NACK response signal. .

  Next, after outputting the address data, the master IC outputs data with the number of bits which is a multiple of eight. Furthermore, after the eighth bit of data is output, the ninth bit of data is output while waiting for an ACK response signal to be input. After that, when the bit data corresponding to the multiple of 8 is output, after confirming that the ACK response signal is input, the (multiple of 8 + 1) bit is output and all the data are output. Repeat until.

  When the master IC outputs a bit that is a multiple of eight of the data and then does not receive an ACK response signal even after a predetermined time has elapsed, it assumes that data transmission has failed and starts again. Send the condition. Then, the address data is output again through the connection line SDA, and the data is output from the first bit again while confirming the ACK reply signal.

  Further, after outputting the data of the last bit of the data, the master IC waits for the input of an ACK response signal, and outputs a signal indicating a stop condition.

  In FIG. 27, data of 24 bits in total (8 bits of slave address, 16 bits of data) is output after the signal indicating the start condition is output and before the signal indicating the stop condition is output. Depending on the size of data to be transmitted, 24 bits or more may be used, or 24 bits or less.

FIG. 28 shows the master IC and the I ² CI / O expander when the master IC according to the first embodiment of this invention specifies the slave's individual address and sets presentation control data in the decoration control device 610. FIG. 10 is a diagram for explaining the format of data transmitted and received between 615 and 615.

The first 8-bit data 2801 to be output includes the address “A0 to A6” of the decoration control device 610 targeted for data transmission and 1 bit indicating whether the data is a read request or a write request. R / W identification data is included. Of the addresses “A0 to A6”, “A4 to A6” is a fixed address part having a value “110”, and “A0 to A3” is set to terminals A0 to A3 of the I ² CI / O expander 615 Corresponds to an individual address (see FIG. 19). Data 2801 is data corresponding to “ADDRESS” and “R / W” in FIG.

The next output 8-bit data 2802 includes setting data to the control register assigned to the output setting register 635 (see FIG. 18) of the I ² CI / O expander 615. Data 2802 is data corresponding to “DATA” transmitted first in FIG.

  Here, the control register will be described. The control register consists of 8 bits, and the upper 3 bits “AI0 to AI2” are automatic write parameters that specify the method of writing to or reading from the work register of the output setting register 635. The lower 5 bits “D0 to D4” are It is a register address specifying an access start position (a start position to start writing or a start position to start reading) in the register.

The automatic writing parameter is accessed by the master IC including access to only the area of the access start position designated by the register address (prohibit auto-increment) or an area adjacent to the area of the access start position to be designated (auto-increment) Is permitted. Specifically, any value of “000”, “100”, “101”, “110”, and “111” can be set.

  When the value of “000” is set to the automatic writing parameter, auto-increment is inhibited, only the area of the access start position designated by the register address is accessed, and the area other than the start position is not accessed. For example, if the register address is "10100", only the storage area whose register number is "14h" is accessed, and other storage areas are not accessed. That is, it is used when only the value of the storage area of a specific register address is changed. In the case where the values of the storage areas of a plurality of register addresses are continuously changed, designation of the address can be omitted by permitting auto-increment as described below.

  When the value of "100" is set in the automatic write parameter, auto-increment is permitted, and after accessing the area of the access start position specified by the register address, the area is moved in the direction of increasing the register number and accessed in order repeat. Then, after accessing the last storage area where the register number is "1 Bh", access the storage area where the register number is "00 h", and access again while moving the area in the direction of increasing the register number again repeat. For example, if the register address is "10100", after accessing the storage area where the register number is "14h", the register number is "15h" → "16h" → · · · · "1Bh" → "00h" → An area where “01h” → ···· (ie, all areas) is repeatedly accessed.

  When setting the value of "101" to the automatic writing parameter, the register number is accessed after accessing the area of the access start position designated by the register address, as in the case of setting the value of "100" to the automatic writing parameter. Repeat the access sequentially while moving the area in the direction of increasing. However, once the storage area having the register number “11h” is accessed, the storage area having the register number “02h” is accessed, and thereafter, the section having the register numbers “02h” to “11h” The recording area (area related to the brightness adjustment of the LED) is repeatedly accessed. For example, if the register address is "10100", after accessing the storage area where the register number is "14h", the register number is "15h" → "16h" → · · · · "1Bh" → "00h" → The areas where "01h" → · · · are accessed in order. Then, after accessing the storage area where the register number is “11h”, the area where the register number becomes “02h” → “03h” →... → “11h” → “02h” → “03h” →. , Repeat access.

  Setting the value of "110" to the automatic writing parameter causes the register number to be accessed after accessing the area of the access start position designated by the register address, as in the case of setting the value of "100" to the automatic writing parameter. Repeat the access sequentially while moving the area in the direction of increasing. However, once the storage area having the register number "13h" is accessed, the storage area having the register number "12h" is accessed, and thereafter, the section having the register numbers "12h" to "13h" The recording area (area related to the blinking cycle of the LED) is repeatedly accessed. For example, if the register address is "10100", after accessing the storage area where the register number is "14h", the register number is "15h" → "16h" → · · · · "1Bh" → "00h" → The areas where "01h" → · · · are accessed in order. Then, after accessing the storage area where the register number is “13h”, the area where the register number is “12h” → “13h” → “12h” → “13h” →... Is repeatedly accessed.

When setting the value of "111" to the automatic writing parameter, the register number is accessed after accessing the area of the access start position designated by the register address, as in the case of setting the value of "100" to the automatic writing parameter. Repeat the access sequentially while moving the area in the direction of increasing. However, once the storage area having the register number "13h" is accessed, the storage area having the register number "02h" is accessed, and thereafter, the section having the register numbers "02h" to "13h" The recording area (area related to the brightness of the LED and the blinking cycle) is repeatedly accessed. For example, if the register address is "10100", after accessing the storage area where the register number is "14h", the register number is "15h" → "16h" → · · · · "1Bh" → "00h" → The areas where "01h" → · · · are accessed in order. Then, after accessing the storage area in which the register number is "13h", the area in which the register number is "02h" → "03h" → · · · · "13h → 02h" → "03h" → · · · , Repeat access.

  Here, returning to the explanation of FIG. 28, setting data 2803 of the work register is output following setting data 2802 of the control register. The setting data 2803 is data corresponding to “DATA” transmitted secondly or later in FIG.

  When the automatic writing parameter is “000”, setting data 2803 is 8-bit data for updating one storage area designated by the register address. When the automatic writing parameter is set to a value other than "000", this setting data 2803 is a multiple of 8 necessary to repeatedly update a plurality of areas starting from the storage area designated by the register address. It will be bit data.

FIG. 29 shows the case where the master IC according to the first embodiment of the present invention specifies the individual address of the slave and sets the effect control data in the decoration control device 610, the master IC and the I ² CI / O expander It is a figure which applied a concrete numerical value to presentation control data transmitted and received between 615 and 615. FIG. 29 shows effect control data in which auto-increment is inhibited and only one specific storage area of the work register is updated. Specifically, the PORT 0 terminal of the I ² CI / O expander 615 The case of updating the light emission state of the LED connected to the PORT 3 terminal will be described.

First, “1101100” indicating the slave address of the I ² CI / O expander 615 of the decoration control device 610 of the transmission destination is assigned to the 8-bit data 2901 output first.

The next output 8-bit data 2902 is set in the control register of the output setting register 635 of the I ² CI / O expander 615 assigned to set the automatic writing parameter and the output data of the LED. Value is included.

Here, since the light emission state of the LED connected to the PORT0 terminal to the PORT3 terminal of the I ² CI / O expander 615 is set, LEDOUT0 (address = 10100) is designated as the register address.

  Note that "000" is designated as the automatic writing parameter in order to inhibit auto-increment.

Next, the output 8-bit data 2903 includes data for setting the light emission mode of the decoration device 620 controlled by the decoration control device 610 of the transmission destination. Specifically, data to be set in the LEDOUT0 register is assigned. As a result, the light emission state (light on, light off, blink, etc.) of the LED connected to the PORT 0 terminal to the PORT 3 terminal of the I ² CI / O expander 615 is designated, and the LED emits light in the designated state.

In this ^way, the light emission state of the LED PORT0 terminal ~PORT3 terminal I 2 CI / O expander 615 is ^controlled, the other PORT terminal I 2 CI / O expander 615 (PORT4~PORT15) also By specifying the value of control register data 2902 and setting output data 2903, individual control is possible. Even if a motor or solenoid is connected to the PORT terminal, the same control is performed.

  FIG. 30 is a diagram for explaining the order of transmitting effect control data of the master IC according to the first embodiment of this invention. In FIG. 30, when auto-increment is permitted and all storage areas of the work register are updated, the order of transmitting each data included in the effect control data is defined.

  First, the master IC transmits 8-bit data (data having the same format as data 2801 in FIG. 28) capable of specifying the individual address of the decoration control device 610 to be controlled.

Next, the master IC transmits data (data in the same format as data 2802 in FIG. 28) set in the control register of the output setting register 635 of the I ² CI / O expander 615 to be controlled. In FIG. 30, in order to allow auto-increment to update all the storage areas of the work register, "100" is specified for the automatic write parameter, and a register address for specifying the start position of write or read is specified. "00h" to be the head area of the work register is specified.

Therefore, in the I ² CI / O expander 615 of the decoration control device 610 to be controlled after receiving the control register setting value, the storage area (mode register 1) of the register number “00h” is updated first. It will be

Next, after transmitting the control register set value, the master IC transmits a value (8 bits in total) to be written to the mode register 1. When receiving the write value, the I ² CI / O expander 615 updates the value of the mode register 1, increments the register number, and prepares to update the next “01h” storage area (mode register 2). do.

Further, the master IC transmits a value (total 8 bits) to be written to mode register 2 and thereafter transmits setting values in order to the registers of the remaining storage areas having register numbers “02h” to “1Bh”. Do. The I ² CI / O expander 615 updates the value of the corresponding register each time the write value is received, increments the register number, and repeats the preparation for updating the next storage area, thereby the work register The values of all the registers from "00h" to "1Bh" assigned to are updated.

When the I ² CI / O expander 615 updates the last “1 Bh” storage area of the work register, it changes the register number to “00 h” and waits for the mode register 1 to be updated.

31, when the master IC of the first embodiment of the present invention initializes the ^I 2 CI / O expander 615, the initialization instruction transmitted from the master IC to the ^I 2 CI / O expander 615 It is a figure explaining the format of data.

  When the CPU 551 of the effect control device 550 instructs the master IC to initialize the decoration control device 610, the master IC transmits initialization instruction data to all the decoration control devices 610 connected thereunder. .

In the 8-bit data 3101 output first, the fixed address “110” shown in FIG.
And a reset address "1011" (see FIG. 23) which is a common address. Note that this data 3101 corresponds to "ADDRESS" in FIG. 27, and the "R / W" bit is set to "0" indicating writing.

  A first predetermined value “10100101” is set to the 8-bit data 3102 to be output next, and a second predetermined value “01011010” is set to the 8-bit data 3103 to be output next. Data 3102 corresponds to "DATA" transmitted first in FIG. 27, and data 3103 corresponds to "DATA" transmitted second in FIG.

All the I ² CI / O expanders 615 connected to the master IC initialize themselves upon receiving initialization instruction data including the reset address, the first predetermined value, and the second predetermined value.

The reason for outputting both the first predetermined value and the second predetermined value after the output of the reset address is due to the influence of noise or the like although the master IC does not transmit the reset address "1011". The reason is that the I ² CI / O expander 615 erroneously fetches the reset address “1011” to prevent the initialization from being performed at an incorrect timing.

Also, the reset address is an address common to all (in other words, a plurality of) I ² CI / O expanders 615 unlike the individual addresses. Therefore, only transmit once initialization instruction data including the reset address, since all will be initialized by selecting I ² CI / O expander 615 (s), I 2 ^CI / O Aix As compared with the method of individually selecting the pandas 615 and instructing initialization, initialization can be instructed at high speed.

  In FIG. 31, although the first predetermined value and the second predetermined value are different values, they may be the same value. Alternatively, one of the first predetermined value and the second predetermined value may be transmitted once.

  FIG. 32 is a diagram for explaining the abnormality determination table 3200 of the first master IC 570a according to the first embodiment of this invention.

The abnormality determination table 3200 is stored in the RAM 553 of the effect control device 550. The abnormality determination table 3200 is provided to monitor the connection state between the first master IC 570a of the effect control device 550 and the I ² CI / O expander 615 connected to the first master IC 570a. The abnormality determination table 3200 stores information corresponding to each I ² CI / O expander 615 according to the connection state.

  The abnormality determination table 3200 includes an I / O expander address 3201, a slave address 3202, an error counter 3203, a comparison value 3204, and an error flag 3205.

The I / O expander address 3201 corresponds to the address (see FIG. 19) set at the terminals A0 to A3 of the I ² CI / O expander 615 connected to the first master IC 570a.

The slave address registered in the I ² CI / O expander address table 2300 shown in FIG. 23 is registered in the slave address 3202.

The error counter 3203 transmits presentation control data from the first master IC 570a to the I ² CI / O expander 615, and increments when the ACK can not be received twice consecutively from the I ² CI / O expander 615. Be done.

In the comparison value 3204, a value to be compared with the value of the error counter 3203 is registered in order to determine whether or not the I ² CI / O expander 615 has a failure. The value of the comparison value 3204 may be set according to the type of the rendering device to be controlled.

In the error flag 3205, an error flag indicating whether or not an abnormality has occurred in the connection state of the entry with the I ² CI / O expander 615 is registered.

The method of determining whether or not a failure occurs in the I ² CI / O expander 615 will be specifically described. When the value of the error counter 3203 reaches a predetermined value set to the comparison value 3204, an error occurs. The flag 3205 is set to “ON”, and the occurrence of a fault in the I ² CI / O expander 615 corresponding to the entry is registered.

  In the first embodiment of the present invention, as described later, the output process (see FIG. 37) of the effect control data is performed in synchronization with the VDP interrupt (about 33.3 ms cycle). .

As described above, if the ACK from the I ² CI / O expander 615 can not be received for the ^second transmission of presentation control data from the first master IC 570 a to the I ² CI / O expander 615, an error occurs. The counter 3003 is incremented.

Therefore, when an abnormality has occurred, the execution cycle of data output processing is 33.3 ms, and the comparison value 3004 is "300". Therefore, the I ² CI / O expander is 33.3 ms × 300 10 10 s. Detect that an abnormality related to 615 has occurred.

  FIG. 33 is a diagram for explaining the abnormality determination table 3300 of the second master IC 570b according to the first embodiment of this invention.

The abnormality determination table 3300 of the second master IC 570b is stored in the RAM 553 of the effect control device 550, similarly to the abnormality determination table 3200 of the first master IC 570a. The abnormality determination table 3300 is provided to monitor the connection state between the second master IC 570 b of the effect control device 550 and the I ² CI / O expander 615 connected to the second master IC 570 b. The abnormality determination table 3300 stores information corresponding to each I ² CI / O expander 615 according to the connection state. The configuration of the abnormality determination table 3300 is the same as the configuration of the abnormality determination table 3200 of the first master IC 570a.

  In the first embodiment of the present invention, since there is no decoration control device 610 connected to both the first master IC 570a and the second master IC 570b, the I / O expander address of each decoration control device 610 to be controlled is Is set for each master IC. Therefore, in FIG. 32 and FIG. 33, I / O expander addresses of the same value are set. In addition, since only one address can be set to the I / O expander address, when a plurality of master ICs control one decoration control device 610, it is necessary to set a common address.

  The master IC of the first embodiment of the present invention is provided with a plurality of registers used to configure the operation of the device and to transmit and receive serial data. The command register (REG) 581 shown in FIGS. 11 and 12 is one of such registers, and instructs the connected decoration control device 610 to output a start condition or a stop condition.

  The effect control device 550 transmits an effect instruction to the decoration control device (slave) 610 via the master IC, and executes various effect processing. FIG. 34 shows a procedure for initializing each slave, and FIG. 35 shows an outline of a procedure for transmitting effect control data to each slave.

  FIG. 34 is transmitted and received between the CPU 551 and a master IC (first master IC 570a or second master IC 570b) when initializing (resetting) each decoration control device (slave) according to the first embodiment of this invention It is a figure explaining information.

  When the slave initialization start process is started, the CPU 551 of the effect control device 550 sets “1” in a bit instructing execution of the start condition (STA) and the stop condition (STO) of the command REG 581 (3401).

  The master IC first outputs a stop condition and then outputs a start condition to each decoration control device (slave) 610 to be controlled according to the information (STO, STA) set in the command REG 581 (3411) . By outputting a stop condition, each slave is notified that data transmission has been completed, and then, by outputting a start condition, each slave is ready to receive input of a command.

  When the master IC outputs a start condition, it inputs an interrupt signal (INT) to the CPU 551 to generate an interrupt. The CPU 551 that has generated an interrupt starts transmission restart processing (1) of transmission instruction data (3402). In transmission restart processing (1) of transmission instruction data, a reset address is set in the output buffer 572. The reset address is a fixed address predetermined to reset each slave. At this time, “0” is set to STA and STO of the command REG 581.

  The master IC outputs predetermined data (reset command) to the reset address set in the output buffer 572 (3412). The reset command corresponds to the first predetermined value (data 3102) and the second predetermined value (data 3103) described in FIG.

  When the master IC outputs a reset address, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated an interrupt starts transmission restart processing (2) of transmission instruction data (3403). In transmission restart processing (2) of transmission instruction data, the value of the first half of the reset instruction is set in the output buffer 572. The first half value of the reset command corresponds to the first predetermined value (data 3102) described in FIG. At this time, “0” is set to STA and STO of the command REG 581. The master IC outputs the first half value of the reset command set in the output buffer 572 (3413).

  After that, when the master IC outputs the first half value of the reset command, it inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated an interrupt starts transmission restart processing (3) of transmission instruction data (3404), and sets the value of the latter half of the reset instruction in the output buffer 572. At this time, “0” is set to STA and STO of the command REG 581. The master IC outputs the second half value of the reset command set in the output buffer 572 (3414). The second half of the reset command corresponds to the second predetermined value (data 3103) described with reference to FIG.

Furthermore, when the master IC outputs the second half value of the reset command, it inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated an interrupt starts transmission restart processing (4) of transmission instruction data (3405), and the STA of the command REG 581 is “0”, S
Set “1” to TO and instruct the master IC to output the stop condition.

  The master IC outputs a stop condition to each slave according to the information set in the command REG 581 (3415).

  Each slave is initialized by the above processing. If the initialization fails (3406), the process is restarted from step 3402.

  FIG. 35 shows transmission and reception between the CPU 551 and a master IC (first master IC 570a or second master IC 570b) when transmitting effect control data to each decoration control device (slave) according to the first embodiment of this invention Is a diagram for explaining the information to be

  When effect control is performed, the CPU 551 of the effect control device 550 first sets “1” to a bit instructing execution of the start condition (STA) and the stop condition (STO) of the command REG 581 (3501).

  The master IC outputs the stop condition to each slave based on the values (“1”) set in the STA and the STO of the command REG 581, and then outputs the start condition (3511).

  Then, when the master IC outputs the start condition to each slave, since each slave is ready to receive the effect control data, the interrupt signal is input to the CPU 551 to generate an interrupt. The CPU 551 that has generated an interrupt sets presentation control data indicating the address of the slave to be controlled and the control content in the output buffer 572 (3502). At this time, “0” is set to STA and STO of the command REG 581.

  The master IC outputs the address and effect control data set in the output buffer 572 to each slave (3512). At this time, the slave corresponding to the output address executes the rendering process based on the received rendering control data.

  Then, when the master IC outputs the address and the effect control data to each slave, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 which has generated the interrupt sets “1” to the STA of the command REG 581 and “0” to the STO (3503). Thereafter, the master IC outputs a start condition again, that is, a so-called restart condition is output (3513).

  Subsequently, the CPU 551 and the master IC designate another address and perform the same processing (3504, 3514, 3505, 3515). When the output of the rendering control data for the last nth slave is completed by the CPU 551 (3506), and the master IC outputs the rendering control data to the corresponding slave (3516), the output of all the data is complete, so the stop Output the condition. Specifically, when the master IC finishes outputting the presentation control data to the final slave, an interrupt signal is input to cause the CPU 551 to generate an interrupt, and the CPU 551 that has generated the interrupt sets “0” to STA of the command REG581. "," STO is set to "1" (3507), and then the master IC outputs a stop condition (3517).

  In the first embodiment of the present invention, the stop condition is outputted to update the effect mode of the effect device, but in the fourth embodiment to be described later, the response signal ( ACK) An example configured to update the rendering mode of the rendering device when transmitting will be described.

  FIG. 36 is a diagram for explaining the steps of transmitting presentation control data from the presentation control device 550 according to the first embodiment of this invention to the master IC (the first master IC 570a or the second master IC 570b).

  When slave output data editing processing described later is executed, the CPU 551 of the effect control device 550 secures an output data preparation area in the RAM 553 and stores effect control data for each slave in the output data preparation area.

  In the output data preparation area, the area is further divided for each slave, and the address corresponding to each slave and the effect control data corresponding to the contents of the effect are stored. Specifically, the address corresponds to the data of transmission order 1 shown in FIG. 30, and the effect control data corresponds to the data of transmission orders 2 to 30 shown in FIG.

  Further, CPU 551 further secures the output data save area in RAM 553 so that the unsent effect control data is not overwritten, and saves the data stored in the output data preparation area by the slave output data save process in the output data save area. Let Thereafter, the evacuated data is set in the output buffer 572 of the master IC at a predetermined timing.

  The output data preparation area and the output data save area are secured in RAM 553 for each master IC, and in the first embodiment of the present invention, areas corresponding to first master IC 570a and second master IC 570b are secured respectively. .

  FIG. 37 is a flowchart showing a procedure of processing by the effect control device 550 according to the first embodiment of this invention. This process is a process executed by the CPU 551 of the effect control device 550.

  When the effect control device 550 is powered on, the effect control device 550 first executes the processing of steps 3701 to 3706. Then, every time a synchronization signal (for example, a synchronization signal of 33.3 ms second period) synchronized with the image update period is input from the VDP 556 to the CPU 551 as an interrupt signal, the effect control periodic process of step 3707 is repeatedly executed.

  First, the effect control device 550 executes an initialization process including the initialization of the RAM 553 of the effect control device 550 (3701). At this time, the initialization stage number for the first master IC 570a, which will be described later, and the initialization stage number for the second master IC 570b are both set to “0”.

  Then, the effect control device 550 inputs a reset pulse to the first master IC 570a and the second master IC 570b via the output I / F 558a and the NOR gate circuit 561, and initially initializes the first master IC 570a and the second master IC 570b. (3702).

Subsequently, the effect control device 550 outputs initialization instruction data from the first master IC 570a in order to initialize the I ² CI / O expander 615 of all the decoration control devices 610 connected to the first master IC 570a. First slave IC 570a side slave initialization start processing is executed (3703). Similarly, in order to initialize the I ² CI / O expanders 615 of all the decoration control devices 610 connected to the second master IC 570 b, the second master IC 570 b side outputting initialization instruction data from the second master IC 570 b The slave initialization start process is executed (3704). Details of the slave initialization start process will be described with reference to FIG.

  Furthermore, the effect control device 550 stands by until both of the initialization stage number for the first master IC 570 and the initialization stage number for the second master IC 570b become "0" (3705). The initialization stage number is a number indicating the progress of the initialization process for each of the first master IC 570a and the second master IC 570b, and is “0” immediately after the presentation control device 550 is activated immediately after the power is turned on. However, when the initialization process is started, “1” to “4” is incremented one by one step by step, and when the initialization process is completed, it is returned to “0” again. In the process of resuming transmission of initialization instruction data described with reference to FIG. 42, processes corresponding to the value of the set initialization stage number are sequentially executed.

  When initialization of all masters and slaves is completed, the presentation control device 550 permits reception of a synchronization signal (VDP interrupt) synchronized with the image update period from the VDP 556 and acceptance of a timer interrupt (3706).

  Thereafter, the effect control device 550 executes effect control periodic processing that is executed each time a VDP interruption occurs (3707). Details of the effect control periodic process will be described later with reference to FIG.

  FIG. 38 is a flowchart showing procedures of slave initialization start processing on the first master IC 570a side and slave initialization start processing on the second master IC 570b according to the first embodiment of this invention.

  The slave initialization start process on the first master IC 570a side is executed in the process of step 3703 of FIG. 37 and the process of step 3923 of the effect control periodic process (FIG. 39). Also, the slave initialization start process on the second master IC 570b side is similarly executed by the processes of steps 3704 and 3927.

  In the initialization start process on the first master IC 570a side, first, the CPU 551 of the effect control device 550 prohibits a master interrupt and a timeout interrupt (3801). Then, the first master IC 570a is selected as a master to be initialized (3802).

  Further, in the slave initialization start process on the second master IC 570b side, the CPU 551 prohibits the master interrupt and the timeout interrupt as in the first master IC 570a side slave initialization start process (3811). Then, the second master IC 570b is selected as a master to be initialized (3812).

  In the subsequent processing, processing common to the selected master is executed with respect to the first master IC 570a side slave initialization start processing and the second master IC 570b side slave initialization start processing.

  The CPU 551 sets "1" to the initialization stage number of the selected master (3803). Further, the monitoring timer for the selected master is set (3804), and monitoring of time-out is started (3805).

  The CPU 551 sets “1” for STA, “1” for STO, “0” for SI, and “0” for MODE for the command REG 581 of the selected master (3806).

As described above, STA is a bit for instructing output of the start condition, and STO is a bit for instructing output of the stop condition. When "1" is set to each bit, the master IC outputs a corresponding signal. In the process of step 3806, signals of both the start condition and the stop condition are output.

  SI is a bit for reporting the occurrence of the above-mentioned master interrupt, and when “1” is set, occurrence of an interrupt is requested from the master IC to the CPU 551 and this bit is “0”. The master IC which has generated the interrupt is in a state of waiting for processing until it is changed to. When the CPU 551 sets “0” to this bit, the interrupt occurring in the CPU 551 is released, and the master IC waiting for processing resumes the processing to be performed next. In the process of step 3806, since "0" is set, the occurrence of the interrupt is cancelled, and the master IC waiting for the process resumes the operation.

  MODE is a bit for designating a mode for transmitting data, and “buffer mode” is designated when “1” is set, and “byte mode” is designated when “0” is set. Be done. In the process of step 3806, since "0" is set, data is exchanged in the byte mode.

  Thereafter, the CPU 551 permits the master interrupt and the timeout interrupt (3807), and returns to the caller.

  FIG. 39 is a flowchart showing the procedure of effect control periodic processing according to the first embodiment of this invention.

The effect control periodic process is a process executed in step 3707 of FIG. 37, and the effect control data to be transmitted from each master to each slave (I ² CI / O expander 615) each time a VDP interrupt occurs. It is a process for editing and transmitting the effect control data.

  First, the CPU 551 of the effect control device 550 outputs data serving as an instruction to display an image on the VDP 556 in order to display the image on the display device 53 (3901). Further, in order to output a sound corresponding to the game state from the speaker 30, sound control data is output to the sound LSI 557. The sound LSI 557 causes the speaker 30 to output a sound based on the input sound control data (3902).

  Further, as described in FIG. 36, the CPU 551 executes slave output data save processing for saving the effect control data stored on the RAM 553 so as not to be overwritten (3903). The output data saved in the save area is set in the master IC at a predetermined timing, as described above.

  Subsequently, the CPU 551 prohibits the master interrupt and the timeout interrupt (3904). Next, the update stage number corresponding to the first master IC 570a is set to "0" (3905). Further, the monitoring timer of the first master IC 570a is set (3906), and the monitoring process of timeout is started (3907). The update stage number is a number indicating the stage at which the rendering mode of the rendering device has been updated by the rendering control data, and is set for each master IC. The update stage number is stored in the RAM 553 of the effect control device 550.

  Furthermore, the CPU 551 sets “1” for STA, “1” for STO, “0” for SI, and “1” for MODE for the command REG 581 of the first master IC 570 a (3908). In the process of step 3908, since "1" is set to MODE, data is transmitted and received in the buffer mode.

Similarly, for the second master IC 570b, the CPU 551 sets the update stage number of the second master IC 570b to "0" (3909). Furthermore, set the monitoring timer (
3910), start timeout monitoring processing (3911). Further, for the command REG 581 of the second master IC 570b, “1” is set to STA, “1” to STO, “0” to SI, and “1” to MODE (3912).

  The CPU 551 selects the top slave (decorative control device 610) of each master (3913). In each master IC, the order of slaves transmitting presentation control data is set in advance. In the process of step 3910, the leading slave in the order is set, and in the process of resuming transmission of effect control data described later, effect control data is sequentially transmitted to each slave connected to the first master IC 570a. Then, the output data to each selected slave is prepared (3914).

  Further, the CPU 551 sets the retry counters of all the master ICs to 0 (3915). The retry counter is a counter that is incremented at the time of transmission failure when transmitting effect control data to each master. If the retry counter becomes larger than a predetermined value, it can be determined that some kind of failure has occurred. Thereafter, the master interrupt and the timeout interrupt are permitted (3916).

  Subsequently, the CPU 551 edits data to be output next to the VDP 556 (3917), and further edits speaker related data to be output to the sound LSI 557 (3918).

  Furthermore, the effect control device 550 executes slave output data editing processing for editing the effect control data to be transmitted to the decoration control device 610 that controls the light emitter (3919). In the slave output data editing process, as described in FIG. 36, effect control data of each slave is generated and stored in the output data preparation area secured on the RAM 553.

  Next, the effect control device 550 refers to the abnormality determination table 3200 shown in FIG. 32, and executes an error determination process regarding the light emission control slave connected to the first master IC 570a (3920).

  In the error determination process, the effect control device 550 determines whether all the error flags 3205 of the entry corresponding to the light emission control slave in the abnormality determination table 3200 are “ON”, that is, an error occurs in all the light emission control slaves. It is determined whether the In other words, it is determined whether there is at least one or more light emission control slaves for which the error flag 3205 is "OFF". If it is determined by this error determination processing that errors have occurred in all the light emission control slaves, the conditions for resetting all the light emission control slaves connected to the first master IC 570a and the first master IC 570a are satisfied. It is assumed.

  Based on the result of the error determination process of step 3920, the effect control device 550 determines whether the reset condition is satisfied (3921). As described above, when the error flags 3205 of all the light emission control slaves are "ON" at the time of the error determination process of step 3920, it is determined that the reset condition is satisfied.

If it is determined that the reset condition is satisfied (result of 3921 is "Y"), the effect control device 550 initializes the first master IC 570a (3922), and all I connected to the first master IC 570a. ² CI / O expander 615 (decorative controller 610) simultaneously executes a first master IC side slave initialization start processing for outputting an initialization instruction data to the (3923).

As described above, when it is determined that the reset condition is satisfied, the processing in step 3717 simultaneously instructs initialization to all the I ² CI / O expanders 615 connected to the first master IC 570 a. Do. That is, since all the I ² CI / O expanders 615 are to be selected and initialized at the same time, it is faster than the method of individually selecting the I ² CI / O expanders 615 to instruct initialization. The I ² CI / O expander 615 can be quickly returned to a normal state. At this time, the CPU 551 writes the initialization instruction information to the reset REG 573 via the bus 563 to softly reset the first master IC 570a.

  If it is determined that the reset condition is satisfied in the process of step 3921, there is a possibility that an abnormality has occurred in the first master IC 570a, so that the first master IC 570a is also initialized in the process of step 3722. There is.

  Since the first master IC 570a functions as signal level control means for controlling the signal levels of the connection lines SDA and SCL in accordance with an instruction from the CPU 551, all light emission control devices have an abnormality related to data transmission. In this case, it is also conceivable that an abnormality has occurred in the first master IC 570a itself.

  Therefore, when an abnormality related to data transmission occurs in all the decoration control devices 610, the first master IC 570a is initialized by the CPU 551 (arithmetic processing means) just in case. As a result, even when an abnormality occurs in the first master IC 570a, the first master IC 570a can be reliably controlled.

  Furthermore, the effect control device 550 similarly executes an error determination process for the second master IC 570b (3924), and determines whether a reset condition is satisfied (3925). Then, when the reset condition is satisfied, the second master IC 570b is reset (3926), and the second master IC side slave initialization start process is executed to initialize the slave connected to the second master IC 570b. (3927). Thereafter, the process returns to the process shown in FIG. 37, and waits until the synchronization signal is input from the VDP 556 to the CPU 551.

As described above, in the processes shown in FIGS. 37 to 39, in synchronization with the cycle of updating the image of the display device 53, the I of the decoration control device 610 is transmitted from the first master IC 570a and the second master IC 570b. ² Send presentation control data to the CI / O expander 615. Then, since the I ² CI / O expander 615 controls the decoration device 620 based on the received effect control data, the effect on the display device 53 and the effect on the decoration device 620 are harmonized, giving the player a sense of discomfort. Because there is no, you can enhance the interest.

In addition, each time the decoration control device 610 receives the effect control data transmitted from the first master IC 570a and the second master IC 570b in synchronization with the cycle of updating the image of the display device 53, the I ² CI / O The expander 615 updates the value of the work register (see FIG. 24). Therefore, since the value of the work register is updated to the latest state every time, even if the value of the work register is destroyed due to noise or the like, it is possible to return to the normal value.

  In addition, since the error determination processing is performed in step 3920 and step 3924 in synchronization with the cycle of updating the image of the display device 53, the frequency of determining an error can be appropriately set. That is, if the execution frequency of the error determination process is too high, the processing load of the CPU 551 of the effect control device 550 increases, and conversely, if the frequency of execution of the error determination process is too low, occurrence of abnormality can be detected at appropriate timing. It disappears. By performing the error determination in synchronization with the cycle of updating the image of the display device 53, it is possible to detect an error at an appropriate timing, and it is possible to appropriately cope with the occurrence of a defect in each process.

  FIG. 40 is a flow chart showing a procedure of processing upon generation of a transmission interruption interrupt and generation of a timeout interrupt according to the first master IC 570a of the first embodiment of this invention.

  The transmission interruption interrupt is a so-called master interruption, and processing is executed according to the state at the time of interruption. The timeout interrupt is an interrupt generated when the monitoring timer set in the monitoring timer circuit 562 times out, and is for monitoring that the transmission process by the first master IC 570a is not completed within a predetermined time. It is. When a timeout interrupt occurs, the first master IC 570a is initialized.

First, when a master interrupt from the first master IC 570a occurs, the CPU 551 stops updating the monitoring timer of the monitoring timer circuit 562 and ends monitoring of the timeout related to the first master IC 570a (4001). Further, it is checked whether the status code of the first master IC 570a corresponds to "Recovery" (4002). The status code is a value indicating the state of the master IC, and is set in the status register (REG) 582. In the process of step 4002, referring to transmission processing continuation determination table 4400 described later with reference to FIG. 44, when the set status code is "70h" or "78h", it corresponds to "recovery". It is judged. If the status code corresponds to "recovery" is occupied by a slave ^(I 2 CI / O expander 615) where the connecting line SDA or connection lines SCL are connected to the first master IC570a or first master IC570a, release It can not be done.

  The CPU 551 determines whether the status code of the first master IC 570a corresponds to "recovery" (4003). Then, if it does not correspond (result of 4003 is "N"), the initialization stage number and the update stage number of the first master IC 570a are acquired (4004).

  The CPU 551 determines whether the initialization step number of the master IC to be initialized is “0” (4005). The case where the initialization step number is "0" indicates that the initialization process is not in progress. That is, when the initialization step number is other than "0", it indicates that the initialization process is being executed.

  If the initialization step number of the master IC to be initialized is not “0” (the result of 4005 is “N”), the CPU 551 is in the process of initializing as described above, so The transmission restart process is executed (4006). Details of transmission restart processing of initialization instruction data will be described later with reference to FIG.

  On the other hand, when the initialization step number of the master IC to be initialized is “0” (the result of 4005 is “Y”), the CPU 551 has already completed the initialization processing, and transmits effect control data. Since it is on the way, transmission resumption processing of effect control data is executed (4007). Details of transmission resumption processing of effect control data will be described later with reference to FIG.

  When the CPU 551 determines that the status code of the first master IC 570a corresponds to "restoration" at the branch of step 4003 (the result of 4003 is "Y"), the first master IC 570a is soft reset ( 4011) Next, in order to initialize the decoration control device 610 connected to the first master IC 570a, the first master side slave initialization start processing is executed (4011). The first master-side slave initialization start process is the same process as the process described above with reference to FIG.

  FIG. 41 is a flow chart showing a procedure of processing upon generation of a transmission interruption interrupt and generation of a timeout interrupt of the second master IC 570b according to the first embodiment of this invention.

  The processing at the time of the transmission interruption interruption occurrence and the time-out interruption occurrence on the second master IC 570b side is similar to the processing at the first master IC 570a shown in FIG. 40, and if the first master IC 570a is replaced with the second master IC 570b Description is omitted because it is good.

  FIG. 42 is a flowchart showing the procedure of the transmission restart process of initialization instruction data according to the first embodiment of this invention.

  The CPU 551 first determines whether to continue the transmission process of the initialization instruction data based on the status code (4201), and branches the process according to the determination result (4202). As described above, the status code is a value indicating the state of the master IC, and is set in the status register (REG) 582. In the processing of step 4201, transmission processing of initialization instruction data is continued with reference to transmission processing continuation determination table 4400 described later with reference to FIG. 44 from the combination of the set status code and the current initialization step number. It is determined whether to do. The relationship between the initialization stage number and the status code will be described in detail with reference to FIG.

  The initialization step number is set to one of “1” to “4” according to the processing step when the master IC is being initialized, and the initialization of the master IC is When complete, it is set to "0". However, when the initialization of the master IC is completed and the initialization step number becomes "0", the transmission restart process of the initialization instruction data is not called (the branch of step S4005 in the process of the calling source in FIG. 40). Thus, the process of resuming transmission of effect control data is executed), so here, the explanation will be made on the assumption that the initialization step numbers are "1" to "4".

  If the determination result by the combination of the initialization step number and the status code is not "continue" (result of 4202 is "N"), the CPU 551 is not in a normal state (for example, data transmission failed) Therefore, the value “1” indicating the start of initialization is set as the initialization stage number (4203). Further, the monitoring timer is set and monitoring of time out is started (4204).

  Finally, the CPU 551 outputs “1” to STA, “1” to STO, “1” to SI, “0” to MODE, and “0” to MODE so that the stop condition and start condition are output. The setting is made (4205), and the processing returns to the calling source.

  On the other hand, when the determination result by the combination of the initialization step number and the status code is "continue" (the result of 4202 is "Y"), the CPU 551 normally executes the initialization process. And branch the process based on the initialization stage number (4206).

  When the initialization step number is “1”, the CPU 551 sets a reset address in the output buffer 572 of the master IC to be processed (4207).

  When "1" is set in the initialization step number, it means that the start condition is output from the master IC. Referring to the transmission processing continuation determination table 4400 in FIG. 44, the status code is set to “08h” or “10h” indicating that the start condition or restart condition has been transmitted. Therefore, when the initialization stage number is set to "1" and the status code is set to "08h" or "10h", the processing of step 4207 and subsequent steps is executed.

The CPU 551 increments the initialization stage number (4208), sets a monitoring timer, and starts monitoring for timeout (4209). Finally, in order to continue the processing, “0” is set to each of STA, STO, SI and MODE of the command REG 581 of the master IC to be processed (4210), and the processing returns to the calling source.

  If the initialization step number is “2”, the CPU 551 sets the first half of the value indicating the reset command in the output buffer 572 of the master IC to be processed (4211).

  When "2" is set in the initialization step number, it means that a reset address is set in the output buffer 572 of the master IC. Referring to transmission processing continuation determination table 4400 in FIG. 44, the status code is an ACK indicating that the slave address (here, the reset address) has already been transmitted and that the signal has been normally received from each slave. “18h” is set to indicate that a response has been made. However, the status code is set to "20h" when a NACK indicating that the signal can not be received normally from each slave is replied. Therefore, when “2” is set in the initialization step number and “18h” is set in the status code, the processes after step 4211 are executed.

  When the value is set in the output buffer 572, the CPU 551 executes the processing of steps 4208 to 4210 as in the case where the initialization step number is “1”.

  If the initialization step number is “3”, the CPU 551 sets the latter half of the value indicating the reset command in the output buffer 572 of the master IC to be processed (4212).

  When "3" is set in the initialization step number, it means that the value of the first half of the reset command is set in the output buffer 572 of the master IC. Referring to the transmission processing continuation determination table 4400 in FIG. 44, the status code is an ACK indicating that the data set in the output buffer 572 has been transmitted and that a signal has been normally received from each slave. “28h” is set to indicate the event. However, the status code is set to “30 h” when a NACK indicating that the signal can not be received normally from each slave is acknowledged. Therefore, when the initialization stage number is set to "3" and the status code is set to "28h", the processing after step 4212 is executed.

  When the value is set in the output buffer 572, the CPU 551 executes the processing of steps 4208 to 4210 as in the case where the initialization step number is “1”.

  When "4" is set in the initialization step number, it means that the value of the latter half of the reset command is set in the output buffer 572 of the master IC. Referring to transmission processing continuation determination table 4400 in FIG. 44, “28 h” or “30 h” is set as the status code and “28 h” as the status code as in the case where the initialization step number is “3”. In this case, the processing after step 4212 is performed.

  If the initialization step number is "4", the CPU 551 turns off the error flags of all the decoration control devices 610 connected to the master IC to be processed, since the processing necessary for the initialization processing is completed. (4213) Further, the error counter is set to 0 and initialized (4214). Then, the initialization stage number is set to “0” indicating that the initialization process is not in progress. Finally, in order to complete the initialization process and output a stop condition from the master IC to be processed to all the decoration control devices 610 connected to the master IC, STO of the command REG581 of the master IC to be processed is performed. Each of “1”, STA, SI and MODE is set to “0” (4216), and the process is returned to the caller.

  FIG. 43 is a flowchart showing a procedure of transmission resumption processing of effect control data according to the first embodiment of this invention.

  The CPU 551 first determines the process to be executed based on the status code (4301), and determines whether the process is "retransmission" (4302). In the processing of step 4301, processing to be executed is determined with reference to the transmission processing continuation determination table 4400 (FIG. 44) based on the combination of the value set in the status code and the update step number.

  The update stage number is a number for controlling the timing of transmitting the effect control data with respect to each of the first master IC 570a and the second master IC 570b. Specifically, when the effect control periodic process (step 3707 in FIG. 37, FIG. 39) is executed, the update stage number is set to “0”. Further, as described later, when rendering control data is set in the output buffer 572, the update stage number is set to “1”.

  The status code is a value indicating the state of the master IC, as described above, and is set in the status register (REG) 582. The relationship between the update stage number and the status code will be described in detail with reference to FIG.

  If the CPU 551 determines that the process is not “retransmission” based on the status code (the result of 4302 is “N”), it further determines whether the value of the update stage number is “0”. (4303). At this time, referring to FIG. 44, the processing that is not "retransmission" includes "continue" or "restoration", but when the processing is "restoration" when the transmission interruption interrupt occurs, it is shown in Figs. As described above, the initialization process is performed without executing the transmission control process of the effect control data. Therefore, when the process is not "retransmission", the process is always "continue".

  Then, when the value of the update step number is “0” (the result of 4303 is “Y”), the CPU 551 sets the data prepared on the RAM 553 in the output buffer 572 (4304). In this case (the value of the update stage number is “0” and the process is “continue”), the status code is “08h” or “10h”, which corresponds to the state after the start condition is output.

  Furthermore, the CPU 551 sets the value of the update stage number to “1” (4305), sets the monitoring timer, and starts monitoring for timeout (4306). Finally, the STA, STO, and SI of the command REG 581 of the master IC to be processed are set to “0”, and MODE is set to “1” to transmit the data set in the output buffer 572 in the buffer mode. The setting is made (4307), and the process returns to the calling source process.

  On the other hand, when the value of the update step number is “1” (the result of 4303 is “N”), the CPU 551 sets the error flag corresponding to the selected slave (decorative control device 610) to “off”. (4308) Further, the error counter is initialized (4309). When the value of the update stage number is “1”, “28h” is set in the status code, which indicates that the data transmission has been completed normally, if the processing is performed normally.

  Thereafter, the CPU 551 determines whether or not the transmission restart processing has been completed for all slaves (4310). Then, when the processing is completed for all slaves (the result of "4310" is "Y"), the stop condition is output, and the STO of the command REG 581 is made to designate the mode for transmitting data as "buffer mode". Then, “1” is set to MODE and “0” is set to STA and SI (4311), and processing returns to the caller.

  If the processing has not been completed for all slaves (the result of 4310 is “N”), the CPU 551 sets the retry counter to 0 (4312), and selects the next slave to be processed (4313). ). Then, the output data to the selected slave is prepared (4314), the update stage number is set to "0" (4315), the monitoring timer is set, and the monitoring of time-out is started (4316).

  Finally, the CPU 551 outputs a start condition and sets STA and MODE of the command REG 581 to “1” and sets STO and SI to “0” so as to designate the mode for transmitting data as “buffer mode” (4317 ), Return to the caller process.

  When the CPU 551 determines that the process is retransmission based on the status code (the result of 4302 is “Y”), the CPU 551 increments the value of the retry counter (4318). Then, it is judged whether the value of the retry counter has reached the designated value (4319). The value designated at this time is set in the abnormality determination table 3200 or the abnormality determination table 3300 shown in FIG. 32 or 33, and corresponds to the comparison value 3204 corresponding to the currently selected slave.

  If the value of the retry counter has not reached the designated value (result of 4322 is "N"), the CPU 551 selects the slave again while it is currently selected (4320), and prepares data to be output to the selected slave. (4314), the processing after step 4315 is executed.

  On the other hand, when the value of the retry counter reaches the designated value (the result of 4322 is “Y”), the CPU 551 sets the error flag 3205 of the selected slave to “ON”, and the processing after step 4310 Run.

  FIG. 44 is a diagram showing an example of a transmission processing continuation determination table 4400 for determining the continuation of the data transmission restart processing according to the first embodiment of this invention.

  As described above, the transmission process continuation determination table 4400 stores information for determining the continuation of the data transmission restart process. Data transmission restart processing includes transmission restart processing of initialization instruction data (FIG. 42) and transmission restart processing of effect control data (FIG. 43), and transmission processing continuation determination table 4400 includes processing for each case. Continuation judgment is registered.

  The transmission processing continuation determination table 4400 includes a status code 4401, a determination of continuation of the initialization instruction data transmission restart processing 4402, a determination of continuation of the rendering control data transmission restart processing 4403, and a state 4404.

  The status code 4401 is a value indicating the state of the master IC as described above.

  A state 4404 is a state of the master IC corresponding to the status code 4401. For example, if the status code is "08H", it indicates that the transmission of the start condition has been completed. Further, when the status code is "10H", it indicates that the re-transmission of the start condition, that is, the transmission of the restart condition is completed.

  Further, in the first embodiment of the present invention, when connection line SDA or connection line SCL is occupied for some reason, and can not be released, “70H” or “78H” is set in status code 4401. Be done.

Subsequently, the continuation judgment of the initialization instruction data transmission restart processing corresponding to the status code 440
The continuation judgment 4403 of 2 and the production control data transmission resumption processing will be described.

  In the initialization instruction data transmission restart process, the process is executed for each stage corresponding to the initialization stage number, and the continuation judgment 4402 of the initialization instruction data transmission restart process is defined for each initialization stage number. Specifically, as shown in the figure, "continue", "resume" or "recovery" is defined corresponding to the combination of the value of the initialization step number and the value of the status code.

  If the value of the continuation determination 4402 is “continuation”, it indicates that the initialization instruction data transmission restart processing is normally processed. Specifically, the value of the continuation determination 4402 is "continue" when the output of the start condition is successful when the initialization phase number is 1 or when the address transmission is successful when the initialization phase number is 2. become. That is, when the processing executed in the initialization instruction data transmission resumption processing matches the status code set in the status register (REG) 582, the value of the continuation determination 4402 becomes "continue".

  On the other hand, when the value of the continuation determination 4402 is "resume", it indicates that the initialization instruction data transmission restart process is not properly processed, and it is necessary to restart the initialization instruction data transmission restart process. It is shown that. That is, when the processing executed in the initialization instruction data transmission restart processing does not match the status code set in the status register (REG) 582, the value of the continuation determination 4402 becomes "resume", for example, the data This state occurs when transmission fails.

  Furthermore, when the value of the continuation determination 4402 is "restoration", it indicates that the connection line SDA or the connection line SCL is occupied and can not be released. In this case, it is necessary to initialize the master IC corresponding to the occurrence of the transmission interruption interrupt and the slave connected to the master IC.

  In the effect control data transmission restart process, the process is executed based on the setting value of the update stage number, and the continuation judgment 4403 of the effect control data transmission restart process is defined for each setting value of the update stage number. Specifically, as shown in the figure, "continuation", "retransmission" or "restoration" is defined corresponding to the combination of the value of the update stage number and the value of the status code.

  The update phase number is set to "1" at the timing when the data is first transmitted after the start condition is output, and is set to "0" when the data output preparation for one slave is completed. That is, when the initial setting is completed, the update step number is set to "1", and thereafter, data is continuously transmitted. The value of “continuation judgment 4403” becomes “continuation” if the status code is set to “08H” or “10H” after transmission of the start condition (the update step number is “0”) and after transmission of data ( This is the case where the status code "28H" indicating the success of data transmission is set in the update step number "1".

  On the other hand, if connection line SDA or connection line SCL is occupied for some reason and can not be released, data can not be transmitted / received, so initialize the master IC and the slave connected to the master IC. To restore the occupied state by. Specifically, the status code 4401 is "70H" or "78H".

  In other cases, that is, when the status code and the setting value of the update step number do not match when the data can be transmitted and received, “resend” is set, and processing for resending the effect control data is performed. To be executed.

FIG. 45 is a flowchart showing a procedure of data transmission processing by the master IC according to the first embodiment of this invention. This process is a common process of the first master IC 570a and the second master IC 570b, and the CPU 551 controls the command register 581 (FIGS. 11 and 12).
When “0” is set in the SI bit of “see)”, the master IC which has been waiting due to the occurrence of the interrupt process starts the process.

  First, the controller 574 of the master IC determines whether the output of the start condition is requested, that is, whether the STA of the command REG 581 is set to “1” (4501).

  The controller 574 executes start condition output processing (4502) when the output of the start condition is requested (result of 4501 is “Y”). The start condition output processing executes processing necessary to output the start condition according to the signal levels of the connection line SCL and the connection line SDA. Details of the start condition output process will be described later with reference to FIG.

  When the execution of the start condition output process is completed, the controller 574 sets the value of STCD in the status code (4503). STCD is a variable for substituting a status code to be set, and a predetermined value is set in start condition output processing, data transmission processing to a slave described later, and stop condition output processing. When the status code is set to a value, the transmission interruption interrupt is generated by setting “1” to SI of the command REG581.

  Next, when the output of the start condition is not requested (the result of 4501 is “N”), the controller 574 determines whether the output of the stop condition is requested, that is, “1” in STO of the command REG581. It is determined whether “is set (4504).

  When the output of the stop condition is not requested (result of 4504 is “N”), the controller 574 executes data transmission processing to the slave (4505). Then, the value of STCD set in the data transmission process to the slave is set in the status code (4503). Thereafter, the transmission interruption interrupt is generated by setting “1” to SI of the command REG 581.

  When the output of the stop condition is requested (result of 4504 is “Y”), the controller 574 executes stop condition output processing (4506). The stop condition output process executes the process necessary to execute the stop condition according to the signal levels of the connection line SCL and the connection line SDA. The details of the stop condition output process will be described later with reference to FIG. Thereafter, the value of STCD set in the data transmission process to the slave is set in the status code (4507), and this process is ended (a transmission interruption interrupt is not generated).

  FIG. 46 is a flowchart showing the procedure of the start condition output process according to the first embodiment of this invention.

  The start condition is output by changing the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH. In the start condition output process, the process according to the signal level of each connection line at the start of the process is executed.

  When the controller 574 starts the start condition output process, it first sets "08H" in the status code variable (STCD). "08H" indicates that the output of the start condition is completed.

  The controller 574 determines whether the output of the stop condition is requested, that is, whether the value of STO of the command REG 581 is set to “1” (4602).

  The controller 574 sets the signal level of the connection line SCL to LOW when the output of the stop condition is required and the signal level of the connection line SCL and the signal level of the connection line SDA are both HIGH (4603). Further, the signal level of the connection line SDA is set to LOW (4604), and SCL release monitoring processing is executed (4605). Details of the SCL release monitoring process will be described later with reference to FIG.

  The controller 574 releases the connection line SDA by turning off the transistor 578a (FIG. 11 or 12) (4606). At this time, if all the other ICs (I / O expander 615 etc.) connected to the connection line SDA release the connection line SDA, the signal level of the connection line SDA is changed to HIGH.

  The controller 574 determines whether or not the signal level of the connection line SDA is HIGH (4607). If the signal level of the connection line SDA is HIGH (the result of 4607 is “Y”), the connection line SDA can be released, so at this point both the signal level of the connection line SCL and the signal level of the connection line SDA are HIGH. It is set.

  Then, the controller 574 sets the signal level of the connection line SDA to LOW by setting the transistor 578a (FIG. 11 or 12) to ON (4608). By this processing, the signal level of the connection line SDA is changed from HIGH to LOW while the signal level of the connection line SCL is maintained at HIGH, so that the start condition is satisfied.

  The controller 574 subsequently sets the signal level of the connection line SCL to LOW by setting the transistor 578b to ON (4609). Further, the value of FBF is set to on (4610). The FBF is a flag indicating that the start condition has just been established, and for example, when transmitting data after the start condition is established, if the FBF is on, it is the first transmitted data, so the slave address I will judge. Then, by setting the FBF to OFF after receiving the address, each slave can recognize that the received data is effect control data.

  On the other hand, when the signal level of the connection line SDA is not HIGH (the result of 4607 is “N”), the controller 574 determines whether the signal level of the connection line SDA has become HIGH until a predetermined time elapses. It is judged (4611). When the predetermined time has elapsed (the result of 4611 is "Y"), it is determined that the connection line SDA is in the occupied state, and the process of releasing the connection line SDA after step 4612 is executed. Specifically, the signal level of the connection line SCL is changed at least nine times without turning on the transistor 578a (with the connection line SDA released) by not applying an operable voltage to the transistor 578a by the driver 576a Let

  The controller 574 first sets 0 to the value of the variable LP indicating the number of times of signal input to the connection line SCL (4612). Further, the signal level of the connection line SCL is set to LOW by turning on the transistor 578a (4613). At this time, the signal level of the connection line SCL changes from HIGH to LOW. Furthermore, the number of changes in the signal level of the connection line SCL is counted by adding 1 to LP (4614).

  Subsequently, the controller 574 executes an SCL release monitoring process described later with reference to FIG. 47 (4615). Then, it is judged whether the value of LP has become 9, ie, whether the number of times of change of the signal level of the connection line SCL has reached nine times (4616). If the value of LP has not reached 9 (result of 4616 is “N”), the processing from steps 4613 to 4615 is executed again.

The I ² CI / O expander 615, which has been brought into the read mode (details will be described later) by the processing of steps 4612 to 4616, outputs data to the connection line SDA in accordance with the change in the signal level of the connection line While the signal level of the connection line SCL changes at least nine times, a timing for confirming an acknowledge (ACK) signal from the master IC is generated. At this time, since the connection line SDA is released, the signal level becomes HIGH, and the I ² CI / O expander 615 in the read mode determines that the acknowledge signal has not been received. It will release the SDA.

In this manner, since the connection line SDA is forcibly released from the I ² CI / O expander 615 in the read mode, the signal level of the connection line SDA is maintained at HIGH.

  When the number of times of change of the signal level of the connection line SCL reaches nine times (result of 4616 is "Y"), the controller 574 determines whether or not the output of the stop condition is requested (4617).

  When the output of the stop condition is requested (result of 4617 is “Y”), the controller 574 sets the signal level of the connection line SCL to LOW (4618). Further, the signal level of the connection line SDA is set to LOW by setting the transistor 578a to ON (4619). Thereafter, the SCL release monitoring process is executed (4620), and subsequently, the SCL release monitoring process is executed (4621). Thereafter, the processing of steps 4608 to 4610 is executed, and the processing returns to the calling source.

  Also, when the controller 574 is requested to output the stop condition at the time of the branch of step 4602 and the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH, Execute the process Furthermore, at the point of time of the branch of step 4602, when the output of the stop condition is requested, and the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW, the processing from step 4606 is executed. .

  The controller 574 sets the transistor 578 a to be off when the output of the stop condition is required and the signal level of the connection line SCL and the signal level of the connection line SDA are both LOW at the time of the branch of step 4602. Thus, the connection line SDA is released (4622). Further, it is judged whether or not the signal level of the connection line SDA is HIGH (4623).

  When the signal level of the connection line SDA is not HIGH (the result of 4623 is “N”), the controller 574 determines whether the signal level of the connection line SDA has become HIGH until a predetermined time elapses. (4625). When a predetermined time has elapsed (the result of 4625 is "Y"), it is determined that connection line SDA is in the occupied state, SCL release monitoring processing is executed (4626), and connection line SDA after step 4612 is released. Execute the process

On the other hand, when the signal level of the connection line SDA is HIGH (the result of 4623 is “Y”), the controller 574 further determines whether a stop condition is required (4624). When the stop condition is requested (the result of 4624 is “Y”), the processing from step 4604 is executed.

  When the stop condition is not requested (result of 4624 is “N”), the controller 574 executes the SCL release monitoring process (4627), and indicates that the start condition re-output (restart condition) is completed. "10H" to be shown is set to STCD (4628). Thereafter, the processing of step 4608 and subsequent steps is executed.

  Also, the controller 574 reaches 9 changes in the signal level of the connection line SCL (the result of 4616 is “Y”), and when the output of the stop condition is not requested (the result of 4617 is “N”), it is determined whether or not the signal level of the connection line SDA is HIGH (4629).

  If the signal level of the connection line SDA is not HIGH (the result of 4629 is “N”), the controller 574 determines whether the signal level of the connection line SDA has become HIGH until a predetermined time elapses. (4630). Then, when a predetermined time has passed (the result of 4630 is "Y"), it is determined that the connection line SDA is in the occupied state, and the status code is set to "70H" (4631) to generate a transmission interruption interrupt .

  When the controller 574 does not require the output of the stop condition at the time of the branch of step 4602 and the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW, the connection line SDA The signal level of is set to LOW (4632), and the processing after step 4622 is executed.

  If the controller 574 does not require the output of the stop condition at the time of the branch of step 4602 and the signal level of the connection line SCL and the signal level of the connection line SDA are both LOW, the processing after step 4622 is performed. Run.

  When the controller 574 does not require the output of the stop condition at the time of the branch of step 4602, and the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH, Execute the process of

  When the controller 574 does not require the output of the stop condition at the time of the branch of step 4602 and the signal level of the connection line SCL and the signal level of the connection line SDA are both HIGH, the processing after step 4608 is performed. Run.

  FIG. 47 is a flowchart showing the procedure of the SCL release monitoring process according to the first embodiment of this invention.

  When the SCL release monitoring process is started, the controller 574 releases the connection line SCL (4701) by turning off the transistor 578b (FIG. 11 or 12). At this time, if all the other ICs (I / O expander 615 and the like) connected to the connection line SCL release the connection line SCL, the signal level of the connection line SCL is changed to HIGH. Subsequently, the signal level of the connection line SCL is changed to HIGH, and it is determined whether the connection line SCL is released (4702).

When the signal level of the connection line SCL is HIGH (the result of 4702 is “Y”), the controller 574 returns to the process of the caller because the process is successful. On the other hand, if the signal level of the connection line SCL is not HIGH (the result of 4702 is "N"), it is determined whether the signal level of the connection line SCL has become HIGH until a predetermined time elapses. (4703).

  The controller 574 has a status code “78H” indicating that the connection line SCL can not be released if the signal level of the connection line SCL does not become HIGH after a predetermined time (the result of 4703 is “Y”). Set to 4704 to generate a transmission interruption interrupt.

  FIG. 48 is a flowchart showing the procedure of the SDA release monitoring process according to the first embodiment of this invention.

  The controller 574 releases the connection line SDA (4801) by turning off the transistor 578a (FIG. 11 or 12) when the SDA release monitoring process is started. At this time, if all the other ICs (I / O expander 615 etc.) connected to the connection line SDA release the connection line SDA, the signal level of the connection line SDA is changed to HIGH.

  Then, the controller 574 determines whether the signal level of the connection line SDA is HIGH (4802). If the signal level of the connection line SDA is HIGH (the result of 4802 is “Y”), since the connection line SDA has been released, the process returns to the calling source process.

  On the other hand, when the signal level of the connection line SDA is not HIGH (the result of 4802 is “N”), the controller 574 determines whether the signal level of the connection line SDA is HIGH until a predetermined time elapses. It is determined whether or not (4802).

  The controller 574 performs SCL release monitoring processing (FIG. 47) of releasing the connection line SCL if the signal level of the connection line SDA does not become HIGH even after a predetermined time has elapsed (result of 4803 is “Y”). Execute and release the connection line SCL (4804). Thereafter, “70H” indicating that connection line SDA can not be released is set in the status code (4805), and a transmission interruption interrupt is generated.

FIG. 49 is a flowchart showing a procedure of data transmission processing to the I ² CI / O expander 615 on the slave side according to the first embodiment of this invention.

  The controller 574 first initializes a variable CTR, which stores the number of times of data transmission, to 0 (4901). Subsequently, the signal level of the connection line SCL is set to LOW by setting the transistor 578 b (FIG. 11 or 12) to ON (4902). Then, by executing the SDA release monitoring process (4903), the signal level of the connection line SDA is set to be changed to HIGH. At this time, all the other ICs (I / O expander 615 and the like) connected to the connection line SDA release the connection line SDA.

  The controller 574 determines whether the value of the variable CTR is 8 or not, that is, whether or not the number of times of data transmission has reached 8 (4904). If the number of times of data transmission has not reached eight (the result of 4904 is “N”), data is output to the slave via the connection line SDA, and 1 is added to CTR (4905). Subsequently, SCL release monitoring processing is executed (4906), and further data is output by executing processing of step 4902 and thereafter.

On the other hand, when the number of times of data transmission reaches eight (the result of 4904 is “Y”), the controller 574 outputs a response signal from the I ² CI / O expander 615 on the slave side via the connection line SDA. (4907).

The controller 574 takes in the output response signal from the connection line SDA (4908), and executes SCL release monitoring processing (4909). Furthermore, it is determined whether the content of the response signal fetched in the process of step 4908 is "ACK" (4910).

  The controller 574 sets the signal level of the connection line SCL to LOW by setting the transistor 578 b to ON when the content of the response signal from the slave is “ACK” (result of 4910 is “Y”) ( 4911) The slave releases the connection line SDA (4912). Furthermore, it is determined whether the current data transmission mode is the buffer mode (4913).

  When the current data transmission mode is the buffer mode (result of 4913 is “Y”), the controller 574 determines whether transmission of the last byte is completed (4914). When transmission of the last byte is not completed and data is to be transmitted (result of 4914 is "N"), the value of FBF is set to OFF, and 0 is set to the variable CTR indicating the number of transmissions of data. (4915). As described above, the FBF is a flag indicating that the start condition has just been established, and the flag indicating that the transmission of the slave's address has been completed by setting it off after the first data transmission. It can be handled.

  Thereafter, the controller 574 determines whether or not the signal level of the connection line SDA is HIGH (4916). If the signal level of the connection line SDA is not HIGH (the result of 4916 is “N”), the process waits for a predetermined time (4917). If the signal level of the connection line SDA is not HIGH even after the predetermined time has elapsed (the result of 4917 is "Y"), 70H is set in the status code (4918), and a transmission interruption interrupt is generated. On the other hand, when the signal level of the connection line SDA is HIGH (the result of 4916 is “Y”), the processing of step 4902 and subsequent steps is executed to transmit the next data.

  If the current data transmission mode is not the buffer mode, that is, if the current data transmission mode is not the buffer mode (ie, the result of 4913 is “N”), or the transmission of the last byte is completed (the result of 4914 is “Y”). “), It is determined whether or not the FBF is set to ON (4919). If FBF is set to ON (result of 4919 is “Y”), FBF is set to OFF, and status code “18H” indicating that address transmission is successful is set to STCD (status code) (4920). On the other hand, when the FBF is not set to ON (the result of 4919 is “N”), the status code “28H” indicating that the data transmission is successful is set in the STCD (4921).

  In addition, when the content of the response signal from the slave is "NACK" indicating that the content of the response signal is not "ACK", that is, the controller 574 indicates that the data could not be received (the result of 4910 is “N”), the signal level of the connection line SCL is set to LOW by setting the transistor 578 b to ON (4922).

  Further, the controller 574 determines whether or not the FBF is set to on (4923). If the FBF is set to ON (the result of 4923 is “Y”), the status code 20H indicating that the transmission of the address has failed is set to STCD (4924). On the other hand, when the FBF is not set to ON (the result of 4923 is "N"), the status code 30H indicating that the data transmission has failed is set to STCD (4925). When the above process is completed, the process returns to the caller process.

  FIG. 50 is a flowchart showing the procedure of the stop condition output process according to the first embodiment of this invention.

The stop condition is output by changing the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH. In the stop condition output process, the process is executed according to the signal level of each connection line at the start of the process.

  When the controller 574 starts the stop condition output process, it branches the process according to the signal levels of the connection line SCL and the connection line SDA (5001).

  When both the signal level of the connection line SCL and the signal level of the connection line SDA are HIGH, the signal level of the connection line SCL is set to LOW by setting the transistor 578b (FIG. 11 or 12) to ON. Set (5002). After the process of step 5002 is completed, or when the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH, the transistor 578a (FIG. 11 or 12) is turned on. Set the signal level of the connection line SDA to LOW (5003).

  The controller 574 executes the SCL release monitoring process for releasing the connection line SCL after the process of step 5003 is completed or when the signal level of the connection line SCL and the signal level of the connection line SDA are both LOW. To do (5004).

  The SCL release monitoring process is a process for setting the signal level of the connection line SCL that is at the LOW level to HIGH, thereby enabling data transmission / reception. Details of the SCL release monitoring process are as described in FIG. When the SCL release monitoring process ends normally, the signal level of the connection line SCL is set to HIGH. Further, if the signal level of the connection line SCL can not be set to HIGH and the connection line SCL can not be released, a transmission interruption interrupt is generated.

  After the processing in step 5004 is completed, or when the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW, the controller 574 monitors SDA release for releasing the connection line SDA. Execute the process (5005).

  The SDA release monitoring process is a process of changing the signal level of the connection line SDA from LOW to HIGH, and is occupied when the connection line SDA is occupied for some reason and the signal level remains LOW. A process of releasing connection line SDA is included. The details of the SDA release monitoring process are as described in FIG. When the SCL release monitoring process ends normally, the signal level of connection line SDA is changed from LOW to HIGH. At this time, the signal level of connection line SCL is maintained at HIGH, so the stop condition is satisfied. Do. When the connection line SDA can not be released, a transmission interruption interrupt is generated.

51 to 53 are flowcharts showing the procedure of processing in the slave side I ² CI / O expander 615 according to the first embodiment of this invention.

FIG. 51 is a flowchart showing the procedure of processing in the slave side I ² CI / O expander 615 according to the first embodiment of this invention.

The slave side I ² CI / O expander 615 executes various controls by the bus controller 634 as described with reference to FIG.

First, when the reset signal is generated by the reset signal generation circuit 639 (see FIG. 18, the same applies hereinafter), the bus controller 634 executes initialization processing of itself (I ² CI / O expander 615) (5101). At this time, the transistor 630 is turned off by the driver 632 and the connection line SDA is released. Also, by the driver 637, ports 0 to 1
All of the transistors 638A to 638P connected to 5 are turned off. Also, the output setting register 635 is set to a predetermined initial state. Then, the signal levels of connection line SCL and connection line SDA are taken. Then, the process stands by until the signal levels of the connection line SCL and the connection line SDA are both HIGH 5103 (5102).

  When the connection line SCL and the connection line SDA change to the state 5103 (the result of 5102 is “Y”), the bus controller 634 waits until the signal level of one of the connection line SCL and the connection line SDA changes ( 5104).

  When the signal level of the connection line SDA changes to LOW from the state 5103 (the result of 5104 is “SDA」 ”), the bus controller 634 sets the variable CN to 0, sets the state number to 1, and Clear the preparation area for temporarily storing (5105). The variable CN is a counter indicating the number of times data has been received. The state number is set according to the signal transmitted from the master, and corresponds to, for example, the processing (write processing, read processing, etc.) requested of the slave. When the signal level of connection line SDA changes to LOW from state 5103 in which the signal levels of connection line SCL and connection line SDA are both HIGH, this corresponds to the start condition being output from the master IC, and the state number A value of 1 indicates that a start condition has been output.

  At this time, the signal level of the connection line SCL is HIGH, and the signal level of the connection line SDA is LOW, which is a state 5106. The bus controller 634 stands by until the signal level of the connection line SCL or the connection line SDA changes (5107).

  When the signal level of the connection line SCL changes to LOW from the state 5106 (the result of 5107 is “SCL」 ”), the bus controller 634 receives data whether the variable CN has become 8 or not, that is, 8 times It is judged whether or not it has been made (5108). If the value of the variable CN is not 8 (the result of 5108 is “N”), it is in the state 5109 where the signal levels of the connection line SCL and the connection line SDA are both LOW at this stage. Thereafter, the process waits until the signal level of the connection line SCL or connection line SDA changes (5110).

  When the signal level of connection line SDA changes to HIGH (the result of 5110 is “SDA Δ”), bus controller 634 states that the signal level of connection line SCL is LOW and the signal level of connection line SDA is HIGH. The process transitions to 5111 and waits until the signal level of the connection line SCL or connection line SDA changes (5112).

  If the signal level of connection line SDA changes to LOW (the result of 5112 is “SDA」 ”), bus controller 634 transitions to state 5109 until the signal level of connection line SCL or connection line SDA changes. Wait (5110).

  On the other hand, when the signal level of the connection line SCL changes to HIGH (the result of 5112 is “SCL Δ”), the bus controller 634 determines whether the state number is 1 or 2, that is, after the start condition output. It is determined whether or not the requested process is a write request (5115).

  When the state number is 1 or 2 (the result of 5115 is “Y”), the bus controller 634 adds 1 to the value of the variable CN, and takes in the data stored in the reception buffer (5116). If the state number is not 1 or 2 (result of 5115 is “N”), or when the process of step 5116 is completed, the state of the connection line SCL and the connection line SDA both become the state 5103 where both signal levels are HIGH. It waits until the signal level of the connection line SDA changes (5104).

  When the signal level of the connection line SCL changes to LOW (the result of 5104 is “SCLSDA”), the bus controller 634 causes the variable CN to be changed when the signal levels of the connection line SCL and the connection line SDA are HIGH. It is determined whether 8 has been reached, that is, whether data has been received 8 times (5117). When the value of the variable CN is not 8 (result of 5117 is “N”), at this stage, the signal level of the connection line SCL becomes LOW and the signal level of the connection line SDA becomes HIGH. And execute the processing of step 5112 and subsequent steps. On the other hand, if the value of the variable CN is 8 (the result of 5117 is “Y”), the processing of step 5201 and after shown in FIG. 52 is executed.

  When the signal level of the connection line SDA changes to HIGH when the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW when the signal level of the connection line SCL is HIGH (the result of 5107 is “SDA Δ)), It is determined whether the status number is 2, ie, whether the requested process is a read request (5118). Note that the change in the signal level of the connection line SDA to HIGH from the state 5106 in which the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW corresponds to the output of the stop condition.

  If the state number is 2 (the result of 5118 is “Y”), the bus controller 634 checks. The data stored in the preparation area is stored in the setting register (5119). If the state number is not 2 (result of 5118 is “N”), or if the process of step 5119 ends, 0 is set to the state number (5120). At this time, since it is in the state 5103 in which the signal levels of the connection line SCL and the connection line SDA are both HIGH, the process waits until the signal level of the connection line SCL or the connection line SDA changes (5104). .

FIG. 52 is a flowchart showing the procedure of the address recognition process and the like in the slave side I ² CI / O expander 615 according to the first embodiment of this invention.

Note that the I ² CI / O expander 615 used in the present embodiment can be used whether or not the read mode can be generated. Therefore, the flowchart will be described on the assumption that any type of I ² CI / O expander 615 is provided.

  Here, the read mode will be described.

In the present embodiment, each time transmitting data of a predetermined unit of bytes from the master IC to the ^I 2 CI / O expander ^615, the configuration for receiving a response signal 1 bit from I 2 CI / O expander 615 to the master IC The master IC sends presentation control data to the I ² CI / O expander 615.

By the way, depending on the gaming machine, it may be considered convenient to be able to transmit data of a predetermined unit byte from the I ² CI / O expander 615 to the master IC. For example, in this case, the I ² CI / O expander 615 detects a detection state of various sensors involved in a game and develops a gaming machine having a specification to be transmitted to the master IC.

^I 2 CI / O expander 615 used in such a gaming machine, in response to a request from the master ^IC, to generate a "read mode" within the I 2 CI / O expander 615, SCL signal from the master IC in correspondence with the ^change, transmitted per transmitting data of a predetermined unit of bytes from the I 2 CI / O expander 615 to the master IC, a response signal 1 bit to the ^I 2 CI / O expander 615 from the master IC It is preferable to make it the following structure.

Specifically, of the address data transmitted from the master IC to the I ² CI / O expander 615 on the slave side, the read mode is generated when the bit of the R / W identification data 2204 is “1”. It is defined in advance as a request (hereinafter referred to as a “read request”) for the purpose.

  When the signal level of the connection line SCL changes to LOW while the signal levels of the connection line SCL and the connection line SDA are HIGH (the result of 5104 in FIG. 51 is “SCL ▽”), the bus controller 634 sets the data. When reception is completed eight times, that is, reception of data is completed (the result of 5117 is “Y”), the connection line SDA is released on the master IC side (5201).

Subsequently, the bus controller 634 determines whether the state number is 1 or not, that is, immediately after the start condition is output (5202). If the status number is 1 (the result of 5202 is "Y"), it is checked whether the received address matches the address assigned to itself (I ² CI / O expander 615) ( 5203, 5204).

If the received address and the own address do not match (the result of 5204 is “N”), the state number is set to 0 (5217), and the processing after step 5213 is executed. Here, even if the received address corresponds to the above-mentioned “read request” and the I ² CI / O expander 615 which performs the processing can not generate the above-mentioned read mode, step 5204. The judgment result of is set to "N".

  On the other hand, if the received address and the own address match (the result of 5204 is “Y”), it is determined whether the requested process is a read request (5205). If the requested process is a read request (the result of 5205 is “Y”), the process after step 5301 in FIG. 53 is executed.

  On the other hand, when the requested processing is not a read request, that is, in the case of a write request (result of 5205 is “N”), the bus controller 634 sets 2 which is a corresponding state number (5206).

Thereafter, the bus controller 634 drives the driver 632 to turn on the transistor 630, thereby setting the signal level of the connection line SDA to LOW and starting occupation of the signal line. Further, the self-occupied WDT 641 is activated to start monitoring of the bus by the self-occupied WDT 641 (5207). When the bus controller 634 starts to occupy the bus, the self-occupied WDT 641 starts a timer, and resets itself (I ² CI / O expander 615) when a predetermined time passes. By this processing, even when the connection line SDA continues to be occupied, it is possible to release the occupation by reset when the time set in the self-occupied WDT 641 elapses. At this time, by resetting only itself, the influence on the other can be minimized.

  At this time, the signal levels of the connection line SCL and the connection line SDA are both in the state 5208 where the signal levels are LOW, and then the bus controller 634 waits until the signal level of the connection line SCL changes to HIGH (5209).

  When the signal level of the connection line SCL changes to HIGH (the result of 5209 is “SCL Δ”), the bus controller 634 enters a state 5210 where the signal level of the connection line SCL is HIGH and the signal level of the connection line SDA is LOW, Further, it waits until the signal level of the connection line SCL changes to LOW (5211).

  When the signal level of the connection line SCL changes to LOW (the result of 5209 is “SCL」 ”), the bus controller 634 releases the connection line SDA by turning off the transistor 630 by driving the driver 632 and the self-occupied WDT 641. To stop the monitoring of the bus by the self-occupied WDT 641 (5212). Then, the value of the variable CN is set to 0, and the reception buffer is cleared (5213). At this time, the signal level of the connection line SCL is LOW, the signal level of the connection line SDA is HIGH, and the state 5111 of FIG. 51 is obtained.

  If the state number is not 1 in the process of step 5202 (the result of 5202 is “N”), the bus controller 634 determines the success or failure of reception (5214, 2515). If the reception is successful (the result of 5215 is "Y"), the data of the reception buffer is stored in the preparation area (5216), and the processing after step 5207 is executed.

  On the other hand, when the data reception fails (the result of 5215 is “N”), the bus controller 634 sets the state number to 0 (5217), and executes the processing of step 5213 and subsequent steps.

FIG. 53 is a flow chart showing a procedure of data read processing in the slave side I ² CI / O expander 615 according to the first embodiment of this invention.

  If the process requested from the master IC is a read request (the result of 5205 in FIG. 52 is “N”), the bus controller 634 sets the state number to 3 corresponding to the read process (5301).

  Thereafter, the bus controller 634 drives the driver 632 to turn on the transistor 630, thereby setting the signal level of the connection line SDA to LOW and starting occupation of the signal line. Furthermore, the self-occupied WDT 641 is activated to start monitoring the bus by the self-occupied WDT 641 (5302). At this time, the signal levels of the connection line SCL and the connection line SDA are both LOW, and the bus controller 634 waits until the signal level of the connection line SCL changes to HIGH (5304).

  When the signal level of the connection line SCL changes to HIGH (the result of 5304 is “SCL Δ”), the bus controller 634 enters state 5305 and waits for the signal level of the connection line SCL to change to LOW (5306). .

  When the signal level of the connection line SCL changes to LOW (the result of 5306 is “SCL」 ”), the bus controller 634 releases the connection line SDA by driving the driver 632 to turn off the transistor 630, and the self-occupied WDT 641. To stop the monitoring of the bus by the self-occupied WDT 641 (5307).

  Further, the bus controller 634 sets the value of the variable CN to 0 (5308), and outputs data to the connection line SDA (5309). At this time, in the case of outputting a low level signal to the connection line SDA, the self-occupied WDT 641 is operated to start monitoring of the bus by the self-occupied WDT 641. When outputting a signal of HIGH level to the connection line SDA, the self-occupied WDT 641 is not operated (5310). This is because the bus is not occupied when the signal level of the connection line SDA is HIGH.

At this time, the bus controller 634 waits until the signal level of the connection line SCL is LOW (5311) and the signal level of the connection line SCL changes to HIGH (5312).
). When the signal level of the connection line SCL changes to HIGH (the result of 5312 is "Y"), 1 is added to the value of the variable CN (5313). Then, the signal level of the connection line SCL is in the state 5314 where the signal level is HIGH, and the process waits until the signal level of the connection line SCL changes to LOW (5315). When the signal level of the connection line SCL changes to LOW (the result of 5315 is “SCL」 ”), when monitoring the bus by the self-occupied WDT 641, stop the self-occupied WDT 641 and monitor the bus by the self-occupied WDT 641. It ends (5316).

  The bus controller 634 determines whether the value of the variable CN has reached 8 or not, that is, whether all data for eight times have been output to the connection line SDA (5317). If the output of all the data has not been completed (the result of 5317 is "N"), the next data is output to the connection line SDA (5318), and the processing after step 5310 is executed.

  On the other hand, when the value of variable CN reaches 8 and transmission of all data is completed (result of 5317 is “Y”), the bus controller 634 drives the driver 632 to turn off the transistor 630 and thereby the connection line. Release the SDA (5319). However, since the process of step 5319 is necessary only when the bus controller 634 sets the connection line SDA to the low level, when the bus controller 634 sets the connection line SDA to the high level, , You do not need to run.

  At this time, since the signal level of the connection line SCL is LOW and the signal level of the connection line SDA is HIGH (5320), the process waits until the signal level of the connection line SCL is HIGH (5321).

At this time, 8-bit units of data have already been transmitted from the I ² CI / O expander 615 to the master IC 570 a (see FIG. 11 and the same with the master IC 570 b in FIG. 12). When the next data is to be received, an ACK response signal is transmitted from the master IC 570 a (570 b) to the I ² CI / O expander 615.

  Then, when the signal level of the connection line SCL becomes HIGH (the result of 5321 is “SCL Δ”), the bus controller 634 takes in the signal level (response signal) of the connection line SDA (5322). Then, it is determined whether or not the fetched response signal is ACK (LOW level), that is, whether or not the master IC is in a state of receiving the next data (5323).

  At this time, if the fetched response signal is ACK (result of 5323 is “Y”), the signal level of the connection line SCL is HIGH, and the signal level of the connection line SDA is LOW (5324), The bus controller 634 stands by until the signal level of the connection line SCL changes to LOW (5325). When the signal level of the connection line SCL changes to LOW (the result of 5325 is “SCL」 ”), the value of the variable CN is set to 0 (5326), and the processing after step 5318 is performed to output the next data. Run.

  On the other hand, if the fetched response signal is NACK (the result of 5323 is “N”), the bus controller 634 sets the variable CN to 0, the state number to 0, and clears the reception buffer ( 5327). At this time, the signal levels of the connection line SCL and the connection line SDA are both HIGH, corresponding to the state 5103 of FIG. 51, and the process of step 5104 of FIG. 51 is executed.

Next, in the first embodiment of the present invention, the timing at which data is exchanged between the CPU 551 of the effect control device 550 and the first master IC 570a and the second master IC 570b will be described.

  FIG. 54 is a timing chart showing a state in which processing by the first master IC 570a and the second master IC 570b is executed in parallel by an instruction from the CPU 551 of the effect control device 550 at the time of VDP interruption according to the first embodiment of this invention It is a chart.

  In the first embodiment of the present invention, when the VDP interrupt occurs at the timing of updating the image displayed on the display device 53, the CPU 551 of the effect control device 550 outputs the effect control data to each master IC. Start. Each master IC, upon receiving the effect control data from the CPU 551, executes processing such as transmitting the received effect control data to each slave independently of the other master ICs. Then, when the output of the rendering control data to all the slaves is completed, each master IC outputs a stop condition, and updates the rendering mode of the rendering device (decorative device 620) controlled by each slave.

  Thus, the processing by the first master IC 570a and the second master IC 570b is executed in parallel, and further, by synchronizing the VDP interruption and the update timing of the rendering mode of each rendering device, the rendering harmonized with the image display It is possible to do

  More specifically, when the VDP interrupt occurs, the CPU 551 of the effect control device 550 executes effect control periodic processing (step 3707 in FIG. 37, FIG. 39) and outputs a start condition to each master IC. .

  Then, the CPU 551 edits output data to each device controlled by the effect control device 550. Specifically, VDP output data editing for producing effects on the display device 53 (step 3917 in FIG. 39), speaker related data editing for outputting sound from the speaker 30 (step 3918 in FIG. 39), and as a rendering device Editing of the effect control data to be output to the decoration control device 610 for controlling the LEDs (step 3919 in FIG. 39), and data editing for controlling the driving body such as the motor. If a master interrupt to the CPU 551 occurs by each master IC during the execution of these editing processes, the presentation control data edited by the transmission restart process (FIG. 43) of the presentation control data is output to the output buffer 572 of each master IC. Will be written. Then, effect control data is output to each slave by the data transmission process by the master shown in FIG.

  Also, during the idle period (period * in FIG. 54) from the end of data output to the last slave to the generation of the next VDP interrupt, the CPU 551 performs slave output data editing processing, that is, downlink data Is editing.

  Finally, when the presentation control data is transmitted to all the slaves to be transmitted, the master IC outputs a stop condition to the slave by the transmission restart processing of the presentation control data (step S4311 in FIG. 43). The effect control data received by each slave is reflected in the effect mode of each effect device.

  Thereafter, the CPU 551 waits until the next VDP interrupt occurs. Then, when the next VDP interrupt occurs, the above-mentioned effect control periodic process (step 3707 in FIG. 37, FIG. 39) is executed to output a start condition to each master IC, and the same process is repeated thereafter.

  Next, a configuration example of the grouped rendering device (decorative device 620) will be described.

FIG. 55 is a diagram showing an example of connection between the I ² CI / O expander 615 of the decoration control device 610 and the decoration device 620 according to the first embodiment of the present invention, and eight sets of LEDs are used. it is a diagram showing a configuration for controlling the I ² CI / O expander 615.

  The decoration device 620 is composed of LEDs as an example, and emitting light of various colors by controlling three colors of red (R), green (G) and blue (B) as one set To be possible. For example, when all the red, green and blue LEDs are colored, they can emit white light.

And, in the first embodiment of the present invention, one I ² CI / O expander 615 can control LEDs corresponding to 16 ports (PORT 0 to 15), so three colors It is possible to connect up to 5 sets of LED's.

However, it may be considered that LEDs (rendering devices) are connected to more than 16 ports in order to perform effects that further enhance interest. In FIG. 55, a configuration in which five sets or more (eight sets) of LEDs are connected across two I ² CI / O expanders 615 and controlled will be described.

As described above, since the I ² CI / O expander 615 is provided with 16 ports (PORT 0 to 15), it is possible to connect up to 5 sets of three-color LEDs. However, if rendering is performed as a group of eight sets of LEDs, at least two I ² CI / O expanders 615 are required.

Thus, in the configuration shown in FIG. 55, one I ² CI / O expander 615 controls each set of red and green LEDs, and the other I ² CI / O expander 615 (615b) controls each set Is configured to control the blue LED. Then, these two I ² CI / O expanders 615 are controlled as the same group, and as described later with reference to FIG. 56A, the stop control outputted from the effect control device 550 is accepted and the effect control is simultaneously executed. As a result, it is possible to perform the rendering by the LEDs controlled by the plurality of I ² CI / O expanders 615 without a sense of discomfort.

  FIG. 56A is a diagram showing a timing at which the decoration control device 610 according to the first embodiment of the present invention receives data and controls the rendering device, in the case where the received data is reflected when the stop condition is output. FIG.

In the figure, first, a start condition is output from the effect control device 550, and then, the effect control data is sequentially output from the effect control device 550 to the plurality of I ² CI / O expanders 615, and finally, the effect control device A state where the stop condition is output from 550 is shown. For convenience of explanation, it is assumed that five I ² CI / O expanders 615 of the decoration control device 610 are provided, and they are respectively the first I ² CI / O expander to the fifth I ² CI / O expander.

Here, what is "data 1" in the figure indicates effect control data transmitted from the effect control device 550 to the first I ² CI / O expander, and hereinafter, "data 2" to "data 5" are 12 shows effect control data transmitted from the effect control device 550 to each of the ^{second I 2} CI / O expander to the fifth I ² CI / O expander.

In addition, in the figure, the one indicated by “rendering device (1)” indicates an LED or the like connected to the I / O port of the first I ² CI / O expander, and hereinafter “rendering device (2)” "-" effect device (5) "is the first ^2I 2 CI / O expander, second and ^5I 2 CI / O expander of I / O
Each corresponds to an LED or the like connected to the port.

Incidentally, the effect control device 550, when transmitting the performance control data to the ^1I 2 CI / O expander, second ^5I 2 CI / O expander Each ^of timing for switching the selection of the I 2 CI / O expander Then, the presentation control device 550 outputs the start condition (functioning as a restart condition) to the I ² CI / O expander. However, after the presentation control device 550 first outputs the start condition, the period from the transmission of presentation control data to all of the first I ² CI / O expander to the fifth I ² CI / O expander (in the diagram During the period indicated by T), the stop condition is not output, and after this period T has elapsed, the stop condition is output.

In the first embodiment of the present invention, since the effect control data is serially transmitted from the connection line SDA, a time difference occurs in the timing at which the effect control data arrives for each I ² CI / O expander. Each I ² CI / O expander temporarily secures the presentation control data received in a buffer (not shown) built in the bus controller 634 (FIG. 18) when receiving presentation control data from the presentation control device 550. It is only

Here, it is assumed that each I ² CI / O expander performs processing such that the light emission mode of the LED is changed simultaneously with the reception of the effect control data. Since a time difference occurs in the change of the light emission mode of the LED, there is a possibility that an effect with a sense of discomfort may be performed.

For example, when red (R), green (G) and blue (B) LEDs are connected across a plurality of I ² CI / O expanders as shown in FIG. 55 described above, The LED may emit light in a color that misleads the player.

  Specifically, the reliability notification device 15 (FIG. 2) described above is set so that the expectation of becoming a big hit differs depending on the color to be emitted, and the big hit is determined if the reliability notification device 15 is red. It shall be the specification. Then, it is assumed that the notification operation of causing the reliability notification device 15 to emit light in purple that does not become the determination of the big hit is performed.

When such notification operation is performed, control is performed such that the red LED and the blue LED in the light emitter provided in the reliability notification device 15 are simultaneously lit to cause the light emitter to emit light in purple, The player wins a jackpot if there is a moment when only the red LED lights up due to the time difference when the LEDs connected across a plurality of I ² CI / O expanders emit light as shown in FIG. 55 described above Misunderstanding that there is a risk of trouble between the game arcade and the player.

Therefore, in the first embodiment of the present invention, when the stop condition is received from the effect control device 550, the effect control data in the buffer is overwritten in the output setting register 635, and the storage content of the output setting register 635 is stored. The output controller 636 reflects the data in the driver 637 to change the light emission mode of the LED connected to the I ² CI / O expander.

Therefore, as shown in FIG. 56A, at the time of the stop condition output, it is possible to simultaneously reflect the effect control data received by each I ² CI / O expander on the output mode of each effect device, and effect without discomfort It becomes possible.

In the first embodiment of the present invention, at the time of reception of the stop condition, the timing for reflecting the effect control data received by the I ² CI / O expander in the output mode of each effect device is exemplified as the update command signal. However, other update command signals may be used. An update command signal that can be represented by a signal change of the connection lines SDA and SCL even if it is transmitted during the transmission of presentation control data, without being limited to the one transmitted at the end of presentation control data like a stop condition. If it is, it is applicable.

  FIG. 56B is a diagram illustrating timing when the decoration control device 610 according to the first embodiment of the present invention receives data and controls the light emitting device.

  FIG. 56B illustrates a light emission (control) mode in which two light emitting devices provided in the game board 10 are alternately lit. As described above, the game board 10 is provided with the center case 51, and the center case 51 is provided with the accessory 47 and the decoration lamp 48 (see FIG. 2). Here, a device provided in the accessory 47 is described as a light emitting device (1), and a device provided in the decoration lamp 48 is described as a light emitting device (2). The light emission mode of the light emitting device is set based on the gaming state.

  To describe the gaming state specifically, the number of start memories is 0 until time t1, and a demonstration screen is displayed on the image display device 53. At this time, the light emitting device (1) and the light emitting device (2) are alternately lit at a light emitting interval 16f. Note that 1f corresponds to the screen update cycle, and in the light emission interval 16f, the light emitting device (1) and the light emitting device (2) are alternately lit each time the screen is updated 16 times.

Here, light emission control data (rendering control data) is transmitted from the effect control device 550 to the I ² CI / O expander 615 that controls the light emitting device (1) at a time interval of 1 f. The light emission control data in this case is either light emission control data to turn on the light emitting device (1) or light emission control data to turn off the light emitting device (1), and effects are alternately switched at time intervals of 16f. The control unit 550 updates the light emission control data.

Specifically, among the work registers assigned to the output setting register 635 of the I ² CI / O expander 615 in FIG. 24, the register numbers “14h” (register name “LEDOUT0”) to “17h” (register names) The light emission control data is updated by switching the ON state of the bit corresponding to the light emitting device (1) to ON and OFF among “LEDOUT3”. The same process is performed for the light emitting device (2).

  In addition, from time t1 to time t2, the game ball is in the starting winning opening, and the special figure variation display game is being executed. Therefore, the special view variation display game is executed on the special view display of the common view / special view display 35, and in the image display device 53, a plurality of identification information is variably displayed corresponding to the special view variation display game. . While the special figure variation display game is being executed, the light emitting device (1) and the light emitting device (2) are alternately lit at a light emitting interval 8f. Here, the light emission control data is updated by the effect control device 550 each time the time 8 f elapses.

  In the period from time t2 to time t3, the special figure variation display game is ended, and the identification information is stopped and displayed. At this time, only the light emitting device (1) is on.

  Further, the result of the special view variation display game being executed at this time is a big hit, and it shifts to the special game state from time t3, and the image display device 53 outputs a big hit display. At this time, the light emitting device (1) and the light emitting device (2) are alternately lit at a light emitting interval 4f. Here, the emission control data is updated by the effect control device 550 each time the time 4 f elapses.

Thus, the light emission control data for turning on any light emitting device (for example, the light emitting device (1) and the light emitting device (2)) visible from the player side, and the light emission control data for turning off the light emitting device By transmitting while switching, the target light emitting device can be blinked. Then, if the light emission control data is not correctly transmitted, the light emitting device does not blink and the light emission control data is constantly turned on or off, so that the light emission control data is visually recovered and recovered from the abnormality. It can be confirmed.

  Furthermore, in order to be able to perform this confirmation anytime, in addition to transmitting while switching between the light emission control data for turning on the light emitting device and the light emission control data for turning off, the variable display game is executed Even during a period in which the light emission control data is turned on, the light emission control data to be turned off is transmitted while switching the light emission control data.

  Note that it is also possible to configure the time interval at which the light emission control data can be updated to be variable depending on whether the variable display game is in progress or not. For example, although the light emission control data can be updated at a time interval of 4f when the variable display game is not being executed, the light emission control data is updated at a time interval of 8f when the variable display game is being executed. You may reduce the processing burden as you do.

  With such a configuration, the light emission control is performed in such a direction that the processing load of the effect control device 550 (including the processing load of the CPU 551) is largely changed between the execution of the variable display game and the non-execution. The burden of data update processing can be distributed.

In FIG. 57, in the first embodiment of the present invention, a state occurs in which the I ² CI / O expander 615 starting to occupy the connection line SDA is waiting for the falling of the connection line SCL, and a certain time period has elapsed. after the lapse, to reset the I ² CI / O expander 615 occupies the connection line SDA self, is a diagram for explaining a procedure to attempt to release the bus.

When a start condition is output from the master IC, the master IC starts outputting data to the I ² CI / O expander 615 on the slave side, and the STA of the master IC is set to ON. Thereafter, the master IC sequentially transmits 8-bit data from B7 to B0 to the I ² CI / O expander 615 while sequentially changing the signal level of the connection line SCL. At this time, the I ² CI / O expander 615 on the slave side sequentially takes in data in response to the change in the signal level of the connection line SCL.

  Then, when eight bits (one byte) of data, that is, one data, are transmitted, the connection line SDA is released on the master IC side (step 5201 in FIG. 52). When the connection line SDA is released, the signal level is set to HIGH. Then, it waits until a reply signal (ACK, NACK) is transmitted from the slave side.

The slave side I ² CI / O expander 615 outputs a response signal (ACK) by changing the signal level of the connection line SDA to LOW. After that, the I ² CI / O expander 615 on the slave side is connected to the connection line SDA for a period until the master IC changes the signal level of the connection line SCL from LOW to HIGH and then from HIGH to LOW. (Corresponding to steps 5207 to 5212 in FIG. 52).

Referring to FIG. 57, when the 7th bit of data is transmitted on the master IC side, the slave side recognizes that the signal level of the connection line SCL has changed due to noise etc., and the I ² CI / O ex of the slave side The panda 615 recognizes that the eighth bit of data has been transmitted. Therefore, the slave sets the signal level to LOW to output the response signal (ACK), and occupies the connection line SDA. In the first embodiment of the present invention, at the same time, the monitoring of the occupation of the connection line SDA by the slave is started by the self-occupied WDT 641.

At this time, the master IC can not transmit data (B0) until it is changed to HIGH because the connection line SDA is occupied by the I ² CI / O expander 615 on the slave side and the signal level is LOW. It has become. Furthermore, since the slave side I ² CI / O expander 615 waits until the signal level of the connection line SCL falls, it waits for the signal levels to change with each other, and the entire processing stops Resulting in.

Therefore, in the first embodiment of the present invention, as described above, the time during which the I ² CI / O expander 615 on the slave side occupies the connection line SDA is monitored by the self-occupied WDT 641. When a predetermined time has elapsed since the start of occupation, the connection line SDA is forcibly released by resetting the slave side I ² CI / O expander 615 itself.

  Then, since the last data can not be output even if the connection line SDA is released, the CPU 551 resets the master IC. Thereafter, the stop condition and the start condition are output, and the process is restarted.

In FIG. 58, in the first embodiment of the present invention, the state in which the connection line SDA is occupied for some reason occurs, and the I ² CI / O expander 615 which detects the occupation of the connection line SDA is self. It is a figure explaining the procedure which resets and tries to release a bus.

Although FIG. 57 describes the case where I ² CI / O expander 615 occupying connection line SDA releases connection line SDA by resetting itself, FIG. 58 monitors the entire bus, Describes the procedure for forcibly releasing the bus when the bus is not released because another slave (such as another I ² CI / O expander 615 connected to the connection line SDA) occupies the connection line SDA. Do.

  The monitoring by the bus monitoring WDT 640 is started when the signal level of the connection line SDA becomes low level, and ends when the signal level of the connection line SDA becomes high level. That is, when the time during which the signal level of the connection line SDA is continuously LOW becomes constant, the bus monitoring WDT 640 outputs a command for outputting a reset signal to the reset signal generation circuit 639.

As described with reference to FIG. 57, when the bus is occupied by ^I 2 CI / O expander 615 on the slave side, the input and output of signals between the master IC and the slave side of the ^I 2 CI / O expander 615 Stops, and the signal level of the connection line SDA does not change (it is in a standby state until the signal level changes). Therefore, when the signal level of the connection line SDA does not change for a predetermined time, all the I ² CI / O expanders 615 connected to the connection line SDA reset themselves at each determination. Release the bus.

Referring to FIG. 58, after data B1 is output from the master IC, the bus is occupied by another slave. In the case of FIG. 58, since the slave is not occupied by the self slave, it is not possible to identify the slave that is actually occupied. Therefore, each of the slaves (I ² CI / O expander 615) connected to connection line SDA releases the bus by resetting itself (precisely, I connected to connection line SDA ^{2 Of the} CI / O expander 615, only one having the function of resetting itself performs reset processing).

  Thereafter, the CPU 551 resets the master IC, and after the stop IC and the start condition are output from the master IC, the processing is restarted.

Figure 59 is a first in embodiment when the bus is occupied by I ² CI / O expander 615 of the slave side, the slave side of the I ² CI / O expander in response to a command from the master IC of the present invention 615 is a figure explaining the procedure which releases a bus | bath.

If the number of signal level changes on the connection line SCL differs between the master side and the slave side due to noise, etc., as described above, the connection line SDA is occupied by the I ² CI / O expander 615 on the slave side, and the bus is released. It will not be done.

Therefore, if the master IC can not transmit data while the bus is occupied, the CPU 551 resets the master IC. Then, an attempt is made to output the stop condition and the start condition to each slave (the I ² CI / O expander 615 connected to the master IC).

At this time, in the slave side I ² CI / O expander 615, first, the stop condition output processing shown in FIG. 50 is executed. At this time, since the signal levels of the connection line SCL and the connection line SDA are both LOW, SCL release processing is executed (5004 in FIG. 50, FIG. 47). Since it is the connection line SDA that is occupied, the SCL release process is normally performed, and the signal level of the connection line SCL is set to HIGH.

Subsequently, the process of step 5005 of FIG. 50 is performed, and the SDA release monitoring process (FIG. 48) is performed. The SDA release monitoring process tries to change the signal level of the connection line SDA to HIGH in the processing of step 4802 but can not be made HIGH because it is occupied by the slave I ² CI / O expander 615. Therefore, in the process of step 4805, “70H” (“recovery”) is set in the status code, and then a transmission interruption interrupt is generated.

  When a transmission interruption interrupt occurs, as shown in FIGS. 40 and 41, the CPU 551 performs soft reset on the master IC (4011 in FIG. 40, 4111 in FIG. 41).

Thereafter, the master IC changes the signal level of the connection line SCL at least nine times. By doing this, the I ² CI / O expander 615 on the slave side detects a change in signal level of the connection line SCL from HIGH to LOW while the signal level of the connection line SCL changes at least nine times. Then, the connection line SDA is released (corresponding to getting out of the loop of steps 5208 to 5211 in FIG. 52), and a reply signal (ACK) is transmitted to the master IC.

Next, after confirming that the connection line SDA is released, the master IC outputs a stop condition to the slave side I ² CI / O expander 615, then outputs a start condition, and transmits data again. I do.

In FIG. 60, in the first embodiment of the present invention, when a read mode is generated in the slave side I ² CI / O expander 615 due to an erroneous command from the master IC and the bus is occupied, I ² CI / O expander 615 on the slave side by a command from the master IC is a diagram for explaining a procedure to release the bus.

In the present embodiment, with respect to I ² CI / O expander 615 of the slave side from the master IC, although not intended to send a command to generate a read mode, due to the influence of noise or the like, I ² The description will be made on the assumption that the CI / O expander 615 makes a judgment on its own and transitions to the read mode.

Even if the I ² CI / O expander 615 is in the read mode, the monitoring timer circuit 562 causes the CPU 551 to time out as in the case of the write request if a predetermined time or more passes while the bus is occupied. An interrupt occurs (see FIGS. 10 and 41). At this time, as described in FIG. 58, the CPU 551 first initializes the master IC by executing a soft reset. Then, an attempt is made to output the stop condition and the start condition to each slave (the I ² CI / O expander 615 connected to the master IC).

When the start condition output is executed and the signal level of the connection line SCL is changed at least nine times, the I ² CI / O expander 615 outputs data to the connection line SDA according to the change of the signal level of the connection line SCL. However, while the change of the signal level of the connection line SCL is performed nine times, the timing of confirming the reply signal (ACK) from the master IC occurs. At this time, since the connection line SDA is kept open on the master IC side, the I ² CI / O expander 615 on the slave side takes a signal level of the connection line SDA, and NACK of NACK becomes HIGH level. It recognizes that the response signal has been received, determines that the data transmission is to be stopped thereafter, and releases the connection line SDA.

  According to the first embodiment of the present invention, each master IC (signal level control means) included in the effect control device 550 (group general control means) transmits data to the decoration control device 610 (group unit control means) Then, since a response signal is transmitted from the decoration control device 610 to the effect control device 550, it is possible to confirm whether or not data transmission has been performed, and malfunction can be prevented.

  Further, according to the first embodiment of the present invention, the effect control device 550 transmits data to the decoration control device 610 via one data line (connection line SDA), and the effect control from the decoration control device 610 Since the reply signal is also transmitted to the device 550 through the same data line, the wiring between the substrates can be reduced.

Furthermore, according to the first embodiment of the present invention, one data line is connected from the effect control device 550 (master IC, group general control means) to the decoration control device 610 (I ² CI / O expander 615, The data line may be occupied by the decoration control device 610 and may not be used because it is commonly used for data transmission to the group unit control means) and transmission of a response signal from the decoration control device 610 to the presentation control device 550. However, since the process of initializing the decoration control device 610 is performed by the initialization means and the occupation state of the data line can be released, the communication can be prevented from being stopped.

  Furthermore, according to the first embodiment of the present invention, the decoration control device 610 occupying the data line determines the occurrence of the communication stop state and initializes itself by the other decoration. The data lines can be released without affecting the processing of the controller 610.

  Further, according to the first embodiment of the present invention, when the occupancy condition of the data line is detected, all of the decoration control devices 610 connected to the data line ensure themselves by initializing themselves. Data lines can be released.

  According to the first embodiment of the present invention, the effect control device 550 can transmit a command to release the data line. Furthermore, since the timing of output start and output end of the response signal is instructed from the effect control device 550, the process of the decoration control device 610 is simplified. Then, after the start of the output of the response signal, when a failure occurs such that the output end command does not arrive, the failure is canceled by the exclusive release command means, and the communication can be restored to the normal state.

  Furthermore, according to the first embodiment of the present invention, even if the number of decoration control devices 610 connectable to one master IC has an upper limit, the effect control device 550 includes a plurality of master ICs. More decoration controls 610 can be used.

  Further, in the first embodiment of the present invention, the first master IC 570a (first signal level control means) controls the rendering device provided on the game board 10, and the second master IC 570b (second signal level). The control means is configured to control the rendering device provided on the front frame 3. As described above, when the front frame 3 and the game board 10 are developed by forming the presentation device provided in the game board 10 and the presentation device provided in the front frame 3 in different groups, the decoration control device Since the upper limit number of 610 may be limited to each group to be developed and taken into consideration, it is possible to improve development efficiency by, for example, developing equipment in parallel for each configuration.

Furthermore, according to the first embodiment of the present invention, the plurality of decoration control devices 610 (I ² CI / O expander 615) selected by the CPU 551 and connected to the selected master IC are selected as Since initialization is collectively performed, it is possible to perform high-speed initialization processing as compared with a method of selecting and initializing the decoration control devices 610 one by one.

  At this time, control can be performed such that only the decoration control device 610 connected to the selected master IC is initialized and the decoration control device 610 connected to the other master IC not selected is not initialized.

  Therefore, among all the decoration control devices 610 provided in the game machine, only the decoration control device 610 belonging to the minimum necessary range can be initialized, so the decoration control device 610 is initialized and the presentation device is performed. The frequency of interruption of the operation can be reduced.

  Further, according to the first embodiment of the present invention, since it is configured to perform hard reset when all the master ICs are to be reset, the case where each master IC is soft reset one by one and In comparison, initialization can be performed at high speed.

  On the other hand, when trying to reset some of the master ICs, in order to execute initialization by soft reset via the data bus, such a complex that individual initialization signal input terminals of all the master ICs are separately input. It is sufficient to have one port without the need for a circuit. That is, it becomes possible to perform the reset of all the master ICs that is always executed each time at startup at high speed, and the reset of only a part of the master ICs that is executed only in the emergency can be implemented by a simplified circuit. Therefore, it is effective particularly in the case of a configuration in which the number of master ICs is large.

  Further, according to the first embodiment of the present invention, the processing by the master IC operates in parallel, so high-speed processing becomes possible. Furthermore, since the control is performed so as to update the effect mode of the effect device in synchronization with the timing of screen update, it is possible to produce the light emission harmonized with the screen display.

  Furthermore, according to the first embodiment of the present invention, the timing for reflecting the taken-in data as the output mode of the rendering device is determined by the signal level change of the timing signal line and the data line (reception of the stop condition). This eliminates the need for a signal like the conventional LAT signal. Therefore, the wiring for transmitting the LAT signal becomes unnecessary, and the wiring can be further simplified.

  Further, according to the first embodiment of the present invention, it is possible to transmit individual effect control data to the plurality of decoration control devices 610 using the same signal line, and it is further possible to control It is possible to simultaneously update the effect modes of the effect devices.

Second Embodiment
In the first embodiment of the present invention described above, after power-on, the bus monitoring WDT 640 and the self-occupied WDT 641 are configured to operate unconditionally.

  However, since bus monitoring WDT 640 and self-occupied WDT 641 are optional functions for resetting decoration control device 610 based on the signal level of connection line SDA, whether to use this function or not can be selected by any method. Is preferred.

  In particular, immediately after power-on, the signal level of connection line SDA is unstable, so the function of resetting decoration control device 610 while monitoring the signal level of connection line SDA operates immediately after power-on. In such a case, an unexpected reset process may occur to cause a malfunction. Therefore, it is preferable that the bus monitoring WDT 640 and the self-occupied WDT 641 be invalidated immediately after power on.

  Therefore, a second embodiment will be described in which monitoring by the watchdog timer is enabled or disabled as necessary. In the second embodiment of the present invention, control is performed so that monitoring by the watchdog timer is not performed until reset processing is completed after power on of the gaming machine or immediately after initialization. Hereinafter, the details of the second embodiment of the present invention will be described with reference to FIGS. 61 to 64.

  In the following description of the embodiment, the same reference numerals are assigned to configurations and processes common to the first embodiment, and the description will be omitted.

FIG. 61 is a block diagram showing the configuration of the I ² CI / O expander 615 according to the second embodiment of this invention.

The I ² CI / O expander 615 according to the second embodiment of the present invention is illustrated in that the functions of the bus monitoring WDT 640 and the self-occupied WDT 641 are enabled or disabled according to the set values in the output setting register 635. The configuration is different from the I ² CI / O expander 615 according to the first embodiment shown in FIG.

As described above, a work register (device register) and a control register (control register) are allocated to the output setting register 635 of the I ² CI / O expander 615.

  In the second embodiment of the present invention, output setting register 635, bus monitoring WDT 640, and self-occupied WDT 641 are connected, and based on the value set in the work register of output setting register 635, the watchdog timer Control ON / OFF.

  When controlling the watchdog timer ON / OFF, first, an all-call address (ALLCALL address, second common address, see FIG. 23) capable of outputting a common command to all the decoration control devices 610 is selected. Set as the destination. Then, by setting a predetermined value in a bit that controls ON / OFF of the watchdog timer, ON / OFF of the watchdog timer of all the decoration control devices 610 is simultaneously set.

At this time, by switching the availability of the all-call address, it is possible to designate whether or not to allow setting of ON / OFF of the watchdog timer to all the decoration control devices 610 simultaneously. Note that “0” or “1” is set in bit 0 of the mode register 1 as to whether the all-call address can be used. Also, watchdog timer ON /
OFF sets bit 0 of mode register 2 to "0" or "1". Details of the all-call address and the availability setting of the watchdog timer will be described later.

As described above, the mode register 1 and the mode register 2 are mode registers for performing the initial setting of the I ² CI / O expander 615, and are provided as a part of the work register of the output setting register 635 (see FIG. See Figure 24). The mode register 1 corresponds to the register number "00h", and the mode register 2 corresponds to the register number "01h". When values are written to the mode register 1 and the mode register 2, that is, the storage areas of register numbers “00h” and “01h”, initialization of the I ² CI / O expander 615 is performed based on the written values. It will be. The details of mode register 1 and mode register 2 will be described below with reference to FIG.

  FIG. 62 is a diagram showing an example of the mode register 1 and the mode register 2 according to the second embodiment of this invention. 62 (A) shows the configuration of mode register 1, and FIG. 62 (B) shows the configuration of mode register 2. Mode register 1 and mode register 2 each have 8 bits.

  Each bit of the mode register 1 includes ALLCALL, SUB3, SUB2, SUB1, SLEEP, AI0, AI1, and AI2 in order from bit 0.

  ALLCALL is a parameter indicating availability of the all-call address, and can be used when “1” is set, and can not be used when “0” is set. Note that “1” (usable) is set as the initial value, and the all-call address is usable immediately after initialization (reset).

  SUB3, SUB2 and SUB1 are parameters indicating whether or not the sub address can be set. SLEEP is a parameter for which whether or not to be in the power saving mode is set. AI0, AI1, and AI2 are parameters for specifying the address auto-increment, and the details are as described in FIG.

  Each bit of the mode register 1 includes “WDT PERIOD” (2 bits), “WDT ENABLE”, “OCH”, and “DMBLNK” sequentially from bit 0. Bits 6 and 7 are unused.

  WDT PERIOD indicates a parameter corresponding to watchdog timer monitoring time, and is expressed by 2 bits. For example, the monitoring time is 5 ms when it is set to “00”, and 35 ms when it is set to “11”.

  WDT ENABLE is a parameter to control ON / OFF of the watchdog timer, and can be used (ON) when “1” is set, and not available (OFF) when “0” is set. ). Since the initial value is set to "0", the watchdog timer is set not to operate immediately after the initialization. Therefore, the master IC enables the watchdog timer as needed.

The OCH is a parameter that defines the timing at which the effect control data stored in the output setting register 635 of the I ² CI / O expander 615 is actually reflected on the effect device, as described in FIG. Specifically, the effect control data can be set to be output when the stop condition or the ACK is received. When the value of OCH is set to “0”, the effect control data is actually reflected on the effect device in the stop condition.

DMBLNK is a parameter for adjusting the blinking and brightness of the LED connected to the I ² CI / O expander 615.

  FIG. 63 is a flowchart showing the procedure of the transmission restart process of initialization instruction data according to the second embodiment of this invention. The same processes as those in the procedure of the first embodiment of the present invention shown in FIG. 42 are assigned the same reference numerals, and different processes will be described.

  In the first embodiment of the present invention, the initialization stage number is set to a value from 0 to 4, but in the second embodiment of the present invention, the initialization stage number is a value from 0 to 10. Is set. Therefore, in the second embodiment of the present invention, the combination of the initialization step number and the output buffer setting value as shown in FIG. 64 is defined in advance, and the output buffer setting value is set based on the initialization step number. Are set in the output buffer 572.

  Specifically, the CPU 551 first determines whether the initialization stage number matches the status code (6301), and determines whether the initialization stage number matches the status code (6302). If the initialization step number and the status code do not match (the result of 6302 is “N”), the processing of step 4203 and thereafter is executed. The processing after step 4203 is the same as the processing described in FIG.

  The determination of the matching between the initialization step number and the status code is the same as the transmission processing continuation determination table 4400 shown in FIG. 44 in the first embodiment of the present invention, but the second embodiment of the present invention In the case of (1), since the initialization stage numbers are 1 (0) to 10, the correspondence relationship is different.

  Hereinafter, the first embodiment of the present invention and the initialization step numbers of the second embodiment of the present invention will be specifically described in association with each other.

  If the initialization step number is 1 in the second embodiment of the present invention, it indicates that the initialization processing is performed immediately after the start of the execution of the initialization processing, and it is consistent with the same judgment criteria as the first embodiment of the present invention. Determine the sex.

  The case where the initialization step numbers are 2, 5 and 8 in the second embodiment of the present invention corresponds to the case where the initialization step number is 2 in the first embodiment of the present invention. If the initialization step number is 2, 5 or 8, since the address was transmitted in the immediately preceding process (see FIG. 64), it is judged to be consistent when it indicates that the transmission of the address was successful. .

  In the case where the initialization step numbers are 3, 4, 6, 7, 9, 10 in the second embodiment of the present invention, the initialization step numbers are 3, 4 in the first embodiment of the present invention. It corresponds to the case of. If the initialization step number is 3, 4, 6, 7, 9, 10, the data has been transmitted in the immediately preceding process (see FIG. 64), which indicates that the data transmission is successful. It is determined that

  If the initialization step number matches the status code (result of 6302 is “Y”), the CPU 551 determines whether the initialization step number is 10 (6303). If the initialization step number is 10 (the result of 6303 is “Y”), it indicates that the initialization processing has been completed, so the end processing of step 4213 and subsequent steps is executed. The processing after step 4213 corresponds to the case where the initialization step number is 4 in the first embodiment of the present invention, and is similar to the processing described in FIG. When the initialization step number is 10 in the second embodiment of the present invention, the final step of the initialization processing is the same as the initialization step number of 4 in the first embodiment of the present invention. Is shown.

  When the initialization step number is not 10, that is, when the initialization step number is 1 to 9 (the result of 6303 is “Y”), the CPU 551 outputs a value corresponding to the initialization step number. It is set to 572 (6304). The initialization stage number and the value corresponding to the initialization stage number are previously defined, and an example is shown in FIG. Subsequently, the CPU 551 executes the processing of step 4208 and subsequent steps. The processing after step 4208 is the same as the processing described in FIG.

  FIG. 64 is a diagram showing the correspondence between the initialization step number and the output buffer setting value set in the output buffer 572 according to the second embodiment of this invention.

  When the initialization step number is 1, “D6h” is set in the output buffer 572 as the output buffer setting value. “D6h” indicates a reset address. The reset address is also a common address (a first common address different from the all-call address) capable of outputting a common command to all the decoration control devices 610.

  Furthermore, when the initialization stage number is 2, “A5h” is set in the output buffer 572 when the initialization stage number is 3, and “5 Ah” is set. "A5h" indicates the first half of the reset command (initialization designation data), and "5Ah" indicates the second half of the reset designation (initialization designation data). The case where the initialization stage number is 1 to 3 is the same as that of the first embodiment of the present invention described above.

When the initialization step number is 4, “D0h” is set in the output buffer 572. “D0h” indicates an all call address. That is, the value set in the output buffer 572 next (when the initialization step number is 5) is transmitted to all the decoration control devices 610 (I ² CI / O expander 615). Each decoration control device 610 (I ² CI / O expander 615) is reset by a process (first initialization means) based on the command transmitted in the case of the initialization stage numbers 1 to 3. Immediately after the reset, since the value of bit 0 of the mode register 1 is set to 1, the all-call address of the I ² CI / O expander 615 is valid.

  When the initialization step number is 5, “01h” is set in the output buffer 572. “01h” indicates that the control register is inhibited from auto-increment and the mode register 2 is designated.

  When the initialization step number is 6, “04h” corresponding to the initialization means activation command is set in the output buffer 572. “04h” is a set value of the mode register 2 and indicates that the watchdog timer monitoring time (5 ms in FIG. 64), the watchdog timer can be used, and the output is reflected by the stop condition. Specifically, "00000100" (= "04h") is set by setting "00" in WDT PERIOD, "1" in WDT ENABLE, and "0" in OCH. As described above, the processing in the case where the initialization step number is 6 is performed by the initialization means (second initialization means) for detecting that the bus is occupied by monitoring the state of the bus and for initialization. It functions as an enabling means of a certain watchdog timer.

  When the initialization step number is 7, "D0h" corresponding to the all call address is set again in the output buffer 572.

When the initialization step number is 8, “00h” is set in the output buffer 572. “00h” indicates that the control register is inhibited from auto-increment and the mode register 1 is designated.

  When the initialization step number is 9, “00h” corresponding to the common address invalidation instruction is set in the output buffer 572. “00h” sets the mode register 1 to invalidate the all call address. The process executed when the initialization step number is 9 functions as a common address invalidation means for invalidating the all-call address.

  As described above, in the second embodiment of the present invention, when the initialization stage number is 6, monitoring by the watchdog timer is enabled. After that, when the initialization phase number becomes 9, the use of the all-call address is prohibited so that the watchdog timer is not invalidated by noise or the like.

  Furthermore, after the use of the all-call address is prohibited, a command for periodically enabling the watchdog timer for each decoration control device 610 to ensure that the watchdog timer continues to be valid. (A command corresponding to the above-mentioned initialization means activation command) may be output individually. By doing this, even if the watchdog timer of some decoration control device 610 is invalidated due to the influence of noise or the like, it is possible to minimize the influence and operate the gaming machine stably.

Further, in the second embodiment of the present invention, reset processing (reset processing by the first initialization means) is executed when the game machine is powered on, and each decoration control device 610 (I ² CI / O expander 615 ) Has been initialized. If data transmission fails in the middle of the reset process, the process may be re-executed from the reset process without retransmitting the data. With this configuration, the initialization process can be performed reliably.

  It should be noted that it is only by the bus monitoring WDT 640 and the reset process by the self-occupied WDT 641 (the reset process by the second initialization means) that whether or not the activation is enabled by the initialization means activation command from the presentation control device 550 is there.

On the other hand, detection of power on to the I ² CI / O expander 615 (detected by voltage rise of Vcc in FIG. 61) and detection of external reset signal to the I ² CI / O expander 615 (FIG. 61) The reset process (reset process by the first initialization unit) executed by transmission of the initialization instruction data to the I ² CI / O expander 615 is detected from the effect control device 550). It is not possible to set whether to activate or not by the command of.

  The common address that can be invalidated by the common address invalidation instruction from the effect control device 550 is only the all-call address (second common address).

  On the other hand, the reset address (first common address) is always valid and can not be invalidated by a command from the effect control device 550.

  FIG. 65 is a view for explaining the structure of data to be transmitted to each slave according to the second embodiment of the present invention, showing a case where individual addresses are designated to set parameters. In the figure, "S" indicates a start condition, "P" indicates a stop condition, and "ACK" indicates an ACK signal.

In the second embodiment of the present invention, data is transmitted to all slaves from the first slave to the final slave in one image update cycle. Then, in the transmission data, the transmission address of each slave at the beginning, the control register storing information defining the procedure for writing data to the work register, the control data of various rendering devices (register number "00h" to register number "1Bh" Is included. The details of the transmission data are as described in FIG.

  Mode register 1 set values and mode register 2 set values are set in the control data of the register number “00h” and the register number “01h”. In the mode register 1 setting value, the all call address is set to be valid or invalid. In the mode register 2 set value, it is set whether or not the set value of the watchdog timer and the transmission data output as a stop condition are to be reflected on various rendering devices.

  Therefore, valid or invalid of the all-call address and the parameters of the watchdog timer are periodically set for each image update period.

  Alternatively, individual addresses may be designated for each slave as shown in FIG. 65 to enable or disable the all-call address and to set parameters of the watchdog timer, but as shown in FIG. These parameters may be set by specifying a call address.

  FIG. 66 is a diagram for explaining the structure of data to be transmitted to the slaves according to the second embodiment of this invention, and showing a case where parameters are set by specifying an all-call address.

  In the transmission data shown in FIG. 66, before transmitting data to each slave, the all-call address is specified, and the mode register 2 set value is collectively set. Specifically, auto-increment is inhibited for the mode register 2 and the monitoring time is set to 5 ms.

  Therefore, the parameters of the watchdog timer are set periodically at each image update period. In addition, since all call addresses are specified at the beginning of transmission data to set the watchdog timer parameters, a reset is generated in a specific slave due to the influence of noise etc., and the parameters of the slave return to the initial state. Also, the next time data is sent, it is possible to reset the parameters of the slave early.

  FIG. 67 is a diagram for explaining timings of transmitting and receiving data between the master IC and the slave in the second embodiment of the present invention.

  As described above, in the second embodiment of the present invention, presentation control data is transmitted from the master IC within the image update period, that is, within the VDP interrupt generation interval (second time value), and the slave responds A signal (ACK) is returned.

  The transmission data is transmitted corresponding to the pulse width output to the connection line SCL. Specifically, as shown in FIG. 67, a pulse for eight clocks for data transmission and a pulse for one clock for ACK response are output from the output of the start condition to the output of the corresponding stop condition. Ru.

  Further, the generation interval of the VDP interrupt includes a data transmission period and a pause (waiting) period from the end of the data transmission period to the generation of the next VDP interrupt. The data transmission period is a period from when the start condition is output to when the stop condition is output.

  At this time, the monitoring period (set by the mode 2 register) of the watchdog timer is set to a period longer than the pulse width output to the connection line SCL and shorter than the generation interval of the VDP interrupt.

  If the monitoring period of the watchdog timer is shorter than the pulse width output to the connection line SCL, the slave may be reset although the data is normally processed. In addition, if the monitoring period of the watchdog timer is set to a period shorter than the generation interval of the VDP interrupt, it is possible to quickly recover from the abnormality in time for the image update period, that is, the timing of the next data transmission. Become.

As described above, according to the second embodiment of the present invention, the watchdog timer can be enabled or disabled at any timing. Therefore, since it becomes possible to operate or stop the watchdog timer as needed, the versatility of the decoration control device 610 (I ² CI / O expander 615) can be improved.

Further, according to the second embodiment of the present invention, setting parameters are simultaneously transmitted to all the decoration control devices 610 (I ² CI / O expander 615) using the all-call address. , Enable and disable the watchdog timer at high speed.

Third Embodiment
In the first embodiment of the present invention, the control of the master IC controls the signal level of the connection line SCL to release the occupation of the connection line SDA, but this increases the load on the master IC. There is a risk of In the third embodiment of the present invention, by arranging timing signal line changing means for controlling the signal level of connection line SCL, the signal level of the signal level of connection line SCL is controlled without control of the master IC. Do.

  FIG. 68 is a block diagram showing a configuration of an effect control device 550 according to the third embodiment of this invention.

  The difference between the effect control device 550 of the third embodiment of the present invention and the effect control device 550 of the first embodiment of the present invention is the connection line SCL connected to the output I / F 558a and the relay substrate 600. The transistor 579 b is connected between the transistor 579 a and the output I / F 558 a and the connection line SCL connected to the simplified relay substrate 1600.

  Further, since the pull-up resistor R to which a predetermined voltage is applied is connected to the connection line SCL, when the transistor 579a or 579b is turned on for a certain period of time, the signal level of the corresponding connection line SCL is forced. Since it becomes LOW, if the signal level of the previous connection line SCL is HIGH, a pulse is output on the connection line SCL. As described above, in the third embodiment of the present invention, the dummy pulse can be output to the connection line SCL regardless of the output state of the master IC.

  Note that the CPU 551, the transistor 579a, and the transistor 579b are disposed over the same substrate, and a signal line connecting the CPU 551 and each transistor is not broken. Therefore, the transistor 579a and the transistor 579b are unexpected. It is possible to prevent operation at timing.

  FIG. 69 is a flow chart showing a procedure of processing upon generation of a transmission interruption interrupt and generation of a timeout interrupt of the first master IC 570a according to the third embodiment of this invention.

  The difference with the first embodiment of the present invention is that, when the status code is "recovery", after the first master IC 570a is soft reset (6901), the transistor 579a outputs a dummy pulse (6902). Thereafter, the first master side slave initialization start process is executed (4012).

  When a transmission interruption interrupt or a time-out interrupt occurs on the second master IC 570b side, processing of replacing the portion of the first master in the processing of this flowchart with the second master is performed. At this time, in the process corresponding to step 6902, the transistor 579b is driven to output a dummy pulse.

  As described above, when the connection line SDA is not released due to the influence of noise or the like, after resetting the master IC, the connection pulse SCL is output by outputting a dummy pulse to the connection line SCL. To release. A more detailed procedure will be described below.

FIG. 70 is a view for explaining the procedure for releasing the bus when the bus is occupied by the slave side I ² CI / O expander 615 in the third embodiment of the present invention.

As described above, when the number of changes in the signal level of the connection line SCL differs between the master side and the slave side due to noise or the like, the connection line SDA is occupied by the I ² CI / O expander 615 on the slave side and the bus is released. It will not be done.

  Therefore, if the master IC can not transmit data while the bus is occupied, the CPU 551 resets the master IC. Thereafter, the dummy pulse is output to eliminate the difference in the number of changes in the signal level of the connection line SCL, thereby releasing the occupation of the connection line SDA.

  Specifically, “70H” (“recovery”) is set in the status code by occupancy of the connection line SDA (4805 in FIG. 48), and then a transmission interruption interrupt occurs. When a transmission interruption interrupt occurs, as shown in FIG. 69, the CPU 551 performs soft reset on the master IC (6901 in FIG. 69), and then outputs a dummy pulse (69023 in FIG. 69). At this time, the dummy pulse may be output until occupation of the connection line SDA is released, or may be changed at least nine times.

Thus, the I ² CI / O expander 615 on the slave side changes the signal level of the connection line SCL by the output of the dummy pulse, and changes the signal level of the connection line SCL from HIGH to LOW. Is released, the connection line SDA is released, and a reply signal (ACK) is returned to the master IC. Thereafter, the master IC outputs a start condition and resumes data transmission.

  As described above, after soft resetting of the master IC, ACK is received to confirm release of the connection line SDA, and then each slave is initialized. Therefore, occurrence of trouble is suppressed and reliable communication control is performed. Can.

  Further, according to the third embodiment of the present invention, the occupation of the connection line SDA can be released without increasing the load on the master IC.

  Furthermore, according to the third embodiment of the present invention, since the signal level of the connection line SCL is set to HIGH if the master IC is not operating, the signal for releasing the occupation is always set by the corresponding transistor. It becomes possible to output.

  Further, according to the third embodiment of the present invention, since the CPU for controlling the effect and the transistor for outputting the dummy pulse are arranged on the same substrate, the transistor can not be controlled due to a contact failure or the like. This can prevent unexpected timing when the transistor is placed on another substrate.

Fourth Embodiment
In the first embodiment of the present invention, the decoration control device 610 (I ² CI / O expander 615) updates the light emission state of the connected LED at the timing when the stop condition is received from the first master IC 570a. doing. On the other hand, in the fourth embodiment of the present invention, the light emission state of the connected LED is switched at timings other than the reception timing of the stop condition from the first master IC 570a. By doing this, it becomes unnecessary to control the signal level for outputting the stop condition, so it is possible to shorten the data transmission time.

  In the fourth embodiment of the present invention, the decoration control device 610 updates the light emission state of the connected LED at the timing when the reply signal (ACK) is sent back to the master IC. In order to update the aspect of the rendering device at the timing when ACK is returned, of the data transmitted from the master IC to each slave, the bit of OCH (see FIG. 62B) included in the set value of the mode 2 register It is necessary to set "1".

  FIG. 71 is a view showing a connection example of the decoration control device 610 and the decoration device 620 according to the fourth embodiment of the present invention, wherein one decoration control device 610 is provided with five sets of LEDs. Is a diagram showing a configuration controlled by By the lighting state of the LED for five sets, each color of red, green and blue is mixed, and many colors are expressed.

  Also in the fourth embodiment, the above-described reliability notification device 15 (FIG. 2) will be described as an example of the decoration device 620. In other words, it is assumed that the jackpot is determined if the reliability notification device 15 lights up in red.

  According to the configuration shown in FIG. 71, the light emission state of the five sets of LEDs connected to the decoration control device 610 is simultaneously updated, so that unexpected coloration does not occur. That is, even if the light emission mode of the LED is not received at the timing when the stop condition is received, it is possible to simultaneously update the light emission states of the LEDs of each set at the timing when the ACK is returned.

  FIG. 72 shows transmission and reception between the CPU 551 and a master IC (first master IC 570a or second master IC 570b) when transmitting effect control data to each decoration control device (slave) according to the fourth embodiment of this invention Is a diagram for explaining the information to be In addition, about the procedure in common with FIG. 35 corresponding in the 1st Embodiment of this invention, a common code | symbol is allocated and description is abbreviate | omitted.

  When effect control is performed, the CPU 551 of the effect control device 550 first sets “1” to a bit instructing output of the start condition (STA) of the command REG 581 (7201). At this time, unlike the first embodiment of the present invention, “0” is set to the bit instructing the output of the stop condition (STO) to instruct not to output the stop condition.

  The master IC outputs a start condition to each slave based on the values set in STA and STO of the command REG 581 (7211). The start condition output at this time is the restart condition in the fourth embodiment of the present invention.

  Then, since the master IC is ready to receive presentation control data in each slave, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 which has generated an interrupt sets the first effect control data (data of byte unit transmitted first among the data of FIG. 30) in the output buffer 572 (7202). At this time, “0” is set to STA and STO of the command REG 581.

  The master IC outputs the effect control data (the address of the slave is stored) set in the output buffer 572 to the slave corresponding to the address (3512). At this time, the slave corresponding to the output address executes the rendering process based on the received rendering control data.

  Then, the slave receiving the effect control data returns an ACK. At this time, the slave that has sent back the ACK updates the light emission mode of the effect device (LED) to be controlled at this timing.

  Then, the master IC having received the ACK inputs an interrupt signal to the CPU 551 to generate an interrupt. Even when the master IC receives a NACK, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 which has generated an interrupt sets the next effect control data (data of the byte unit transmitted second in FIG. 30) of the slave to be controlled in the output buffer 572 and sets STA and STO of the command REG581. Sets "0" (7202). As a result, next effect control data is transmitted from the master IC to the slave (3512).

  Thereafter, the master IC inputs an interrupt signal to the CPU 551 every time it receives an ACK or NACK to generate an interrupt, and the CPU 551 which has generated an interrupt causes the output buffer 572 to control the next effect of the slave to be controlled. Data (data in units of bytes to be transmitted in the third and subsequent bytes in FIG. 30) is set, and the processing of setting “0” to STA and STO of the command REG 581 is repeated. This process is repeated until all the effect control data is transmitted.

  At the timing after all the effect control data have been transmitted, the CPU 551 which has generated an interrupt sets “1” for STA of the command REG 581 and “0” for STO (7203). Thereafter, the master IC outputs a start condition again, that is, a so-called restart condition is output (3513).

  Subsequently, the CPU 551 and the master IC sequentially designate the addresses of slaves to be controlled second and subsequent, and perform the same processing (7204, 3514, 7205, 3515). The output of the effect control data for the last nth slave is completed by the CPU 551 (7206), and when the master IC outputs the effect control data to the corresponding slave (3516), the output of all the data is completed.

  Thereafter, the CPU 551 maintains the signal level of the connection line SCL at the LOW level (7217). Specifically, when the master IC completes output of presentation control data to the final slave, an interrupt signal is input to cause the CPU 551 to generate an interrupt, and the CPU 551 that has generated the interrupt sets “1” to SI of the command REG581. Leave the signal as it is set, and keep the signal level of the connection line SCL LOW.

As described above, in the fourth embodiment of the present invention, the effect mode (light emission mode) of the effect device (light emitter) is updated at the timing when the slave returns an ACK. Therefore, the master IC transmits effect control data to the next slave without waiting for reception of the ACK transmitted from the slave. Therefore, since it becomes possible to transmit presentation control data continuously, it becomes possible to shorten the total required time required for transmission of presentation control data.

  Hereinafter, the procedure for transmitting the effect control data will be specifically described with reference to the flowcharts of FIGS. 73 and 74.

  FIG. 73 is a flowchart showing the procedure of effect control periodic processing according to the fourth embodiment of this invention. In the fourth embodiment, since the effect control periodic processing of the first embodiment of the present invention shown in FIG. 39 is replaced with the processing of FIG. 73, the processing common to FIG. 39 is common. The code is assigned and the description is omitted.

  In the first embodiment of the present invention, as described above, the master IC transmits the next effect control data after receiving the ACK, that is, after confirming that the data has been transmitted normally. The Therefore, when not receiving ACK but receiving NACK indicating that data could not be properly received, the data was retransmitted.

  On the other hand, in the fourth embodiment of the present invention, instead of transmitting data in the buffer mode as in the first embodiment, presentation control data is transmitted for each register in the byte mode. And regardless of whether production control data were able to be transmitted normally, production control data is transmitted continuously and processing for resending production control data is not performed.

  Referring to FIG. 73, the processes of steps 3901 to 3907 and steps 3909 to 3911 are the same as in the first embodiment. Then, in the first embodiment, in order to transmit effect control data in the buffer mode, “1” is set to the MODE bit of the command register 581 in the processing of steps 3908 and 3912. On the other hand, in the fourth embodiment, since effect control data is transmitted in the byte mode, “0” is set to the MODE bit of the command register 581 by the processing of steps 7301 and 7302 instead of steps 3908 and 3912. Set

  Therefore, in the fourth embodiment, one update step number is added each time one byte of effect control data (corresponding to 30 pieces of data illustrated in FIG. 30) to be transmitted to the slave is transmitted. Therefore, after the update stage number is initialized to 0 and the start condition is output, the update stage number is performed until values set in all the registers are output, that is, until one slave's worth of presentation control data is transmitted. Is to be updated. In the case of transmitting 30 pieces of data illustrated in FIG. 30, the maximum value of the update stage number is 29.

  In addition, although the transmission processing continuation determination table for determining continuation of the transmission resumption processing of data of the first embodiment shown in FIG. 44 is used in common also in the fourth embodiment, effect control “Update step number = 1” in the determination 4403 for continuation of data transmission restart processing is replaced with “update step number ≧ 1”.

  Furthermore, in the fourth embodiment, since the effect control data is not retransmitted, there is no need to perform processing on a retry counter that manages the number of retransmissions. Therefore, the process of step 3915 of initializing the retry counter is not performed.

  Furthermore, processing common to the first embodiment is executed from step 3913, step 3914, and slave output data editing processing from step 3916 to step 3919, and error processing after step 3920 is not executed in the fourth embodiment. It is supposed to be.

In the first embodiment of the present invention, when the update step number is 0, this is a state immediately after the start condition (or restart condition) is output, and when the update step number is 1, the data is It indicates that it is in the state of being sent.

  The above is the procedure of the effect control periodic process of the fourth embodiment of this invention. Subsequently, each procedure of transmission resumption processing of effect control data according to the fourth embodiment of this invention will be described.

  FIG. 74 is a flow chart showing a procedure of transmission resumption processing of effect control data according to the fourth embodiment of this invention. In the fourth embodiment, the transmission restart process of the effect control data of the first embodiment of the present invention shown in FIG. 43 is replaced with the process of FIG.

  The CPU 551 first determines the value of the update stage number (7401). Then, it is determined whether the update stage number is the maximum value (7402). When the update step number is the maximum value, as described above, the values set in all the registers are transmitted, and transmission of data in slave units is completed.

  If the update stage number is not the maximum value (the result of 7402 is “N”), the CPU 551 executes a process of transmitting the unsent data since the unsent effect control data remains. Specifically, 1 is added to the update stage number (7403), and data corresponding to the added update stage number is extracted from the prepared output data (7404), and the extracted data is output to the output buffer 572. Set (7405).

  Furthermore, the CPU 551 sets a monitoring timer and starts monitoring for timeout (7406). Finally, the STA, STO, and SI of the command REG 581 of the master IC to be processed are set to “0”, and MODE is set to “0” to transmit the data set in the output buffer 572 in byte mode. It sets (7407) and returns to the processing of the calling source.

  On the other hand, when the update step number reaches the maximum value (the result of 7402 is “Y”), the CPU 551 completes the transmission of the rendering control data for one slave, and thus transmits the rendering control data for all the slaves. It is judged whether it is completed (7408). If transmission of effect control data has not been completed for all slaves (the result of 7408 is “N”), the next slave is selected (7410), and the update stage number is set to 0 (7411).

  Then, the CPU 551 sets a monitoring timer and starts monitoring for timeout (7412). Finally, the STA of the command REG 581 of the master IC to be processed is set to "1" to output the restart condition, and the STO and SI are set to "0". Further, in order to transmit the data set in the output buffer 572 in the byte mode, the MODE is set to "0" (7413), and the process is returned to the caller.

  When the transmission of the rendering control data for all the slaves is completed (the result of 7408 is “Y”), the CPU 551 is left in a state where the SI is set to “1”, that is, in a state where an interrupt is generated. (7414) Return to the process of the caller. At this time, the signal level of the connection line SCL is set to LOW, and this signal level is maintained.

  In this manner, after the effect control data is transmitted to all the slaves, the interrupt is generated, and the signal level of the connection line SCL is set to LOW to maintain the state of the connection line SCL. As compared with the case where the signal level is set to HIGH, data transmission can be resumed immediately, and high-speed communication can be performed.

Furthermore, by keeping the signal level of the connection line SCL LOW while the interrupt is generated, each slave is erroneous even if the level of the data signal line changes due to noise etc. in the state where the interrupt is generated. Communication can be performed because it is not recognized that the start condition is output.

  FIG. 75 is a diagram for explaining the structure of data to be transmitted to each slave according to the fourth embodiment of this invention.

  In the fourth embodiment of the present invention, as in the other embodiments, data is transmitted to all slaves from the first slave to the final slave in one image update cycle. Then, until the next image update cycle starts, that is, until the next VDP interrupt occurs, the pause time is reached. The configuration of transmission data is the same as in the other embodiments.

  Further, the fourth embodiment is different from the other embodiments in that the stop condition is not output after the effect control data of all the slaves are output. However, when initialization instruction data is transmitted to the slave for initialization, as in the first embodiment, the stop condition is output after transmission of the initialization instruction data is completed (step in FIG. 42). 4216).

  FIG. 76 is a diagram for explaining timings of transmitting and receiving data between the master IC and the slave in the fourth embodiment of the present invention.

  As described above, in the fourth embodiment of the present invention, presentation control data is transmitted from the master IC to all slaves within an image update period, that is, an occurrence interval of a VDP interrupt. At this time, a reply signal (ACK) is returned from the slave to the master IC, but in the fourth embodiment of the present invention, the master IC ignores the returned ACK.

  As described above, the master IC does not output the stop condition even after the effect control data has been transmitted to all the slaves.

  In addition, after the rendering control data has been transmitted to all the slaves, the signal level of the connecting line SCL is set to LOW, and when transmitting the next rendering control data, the signal level of the connecting line SCL is set. A start condition is output by setting the signal level to HIGH and further setting the signal level of the connection line SDA to LOW.

  Conventionally, since the signal level of the connection line SCL is set to HIGH after the output of the stop condition which is the transmission completion command, the slave recognizes that the signal level of the connection line SDA is set to LOW due to noise or the like. On the side, there is a possibility that the start condition which is the transmission start command may be erroneously recognized as being output. On the other hand, such erroneous recognition is realized by setting the signal level of the connection line SCL to LOW after outputting the rendering control data to all the slaves as in the fourth embodiment of the present invention. It is possible to prevent the communication and to perform more accurate communication.

  FIG. 77 describes the case where the received data is reflected in the light emission state of the LED when the decoration control device 610 receives the data and outputs the ACK to the master IC in the fourth embodiment of the present invention. It is a figure to do.

  As shown in FIG. 77, at the time of ACK output, each slave reflects the effect control data in the output mode of the effect device, thereby controlling the timing for transmitting the effect control data, thereby specifying the specific effect device. It becomes possible to control with

  As described above, in the fourth embodiment of the present invention, in order to transmit effect control data continuously, it is not necessary to have a waiting time until receiving an ACK, and it is necessary to perform error processing. The overhead can be reduced.

  In particular, as shown in FIG. 71, this is particularly effective when rendering can be performed in units of one slave instead of a plurality of slaves. When a plurality of master ICs are provided, the entire effect control process is performed by updating the effect mode of the effect device with a stop condition for each master IC or updating the effect mode of the effect device with an ACK transmission timing. It is possible to reduce the load on

In the fourth embodiment of the present invention, the transistor 630 (FIG. 18) for causing all slaves (I ² CI / O expanders) connected to the master IC to output a response signal to the connection line SDA. However, this transistor 630 is not necessarily required. If unidirectional communication is assumed as in the fourth embodiment, it is also possible to use a custom-made slave IC which is not provided with this transistor.

However, since the general-purpose IC on the slave side generally used in I ² C communication is normally provided with this transistor, there is a network in which a custom-made product and a general-purpose product are mixed. Preferably it can be configured.

  The gaming machine according to the fourth embodiment of the present invention has a configuration in which confirmation of the response signal is not performed on the master IC side, so a slave IC having a function of outputting a response signal to the master IC via connection line SDA. Even if each of the general-purpose slave ICs (for example, a general-purpose slave IC) and a slave IC (for example, a custom-made slave IC) not having the function of outputting a response signal to the master IC through the connection line SDA is connected to the master IC It is possible to operate without.

  Although a pachinko machine that generates a special gaming state corresponding to the result of the variable display game is disclosed as an embodiment, the present invention is not limited to the variable display game, but a special game corresponding to the results of other auxiliary games. Naturally, it may be a gaming machine that generates a state.

  For example, the entrance of a specific winning device is opened (the movable member of the specific winning device is activated and the inlet is opened) when the predetermined condition is met, and the gaming ball taken into the winning device is provided inside the winning device. A game in which lottery is performed in which prize area (having a specific prize area and a general prize area) may be used as the auxiliary game. In this case, the special gaming state is generated by the game ball taken into the inside of the winning device winning in the specific winning area.

  Also, as an embodiment, a pachinko machine that generates a special gaming state corresponding to the result of the special view variable display game is disclosed, but it corresponds to the result of the common view change display game (or Naturally, it is intended that the present invention is applicable even to a pachinko machine that generates a special game state) (due to the result of the display game). For example, even if it is a pachinko machine that generates a special gaming state when the entrance of a specific winning device is opened according to the result of the common view variation display game and the gaming ball taken into the winning device reaches a specific winning region. The invention is applicable.

  Moreover, although the structure by which the game control apparatus and the presentation control apparatus were isolate | separated is disclosed as embodiment, the game control apparatus and the presentation control apparatus are united and one control apparatus is comprised, and Naturally, it is naturally intended that the game control device itself may be configured as a group general control means.

Furthermore, all the embodiments disclosed in the present specification can be applied to other gaming machines such as pachislot machines.

  The embodiment disclosed this time is illustrative in all points and not restrictive. Further, the scope of the present invention is shown not by the above description of the invention but by the scope of claims, and is intended to include all modifications within the scope of meaning and contents equivalent to the scope of claims.

  Moreover, the following are mentioned as a typical thing of the viewpoint of this invention except having described in the claim.

  (1) game control means for controlling the game in an integrated manner, and effect control means capable of controlling, for each system, a plurality of effect devices for effecting a game in response to an instruction from the game control means In the gaming machine, each group of the rendering devices is divided into a plurality of groups, group unit control means for controlling the rendering devices belonging to the divided groups is provided for each group, and A timing control signal line for transmitting a timing signal from the group control unit to the group control unit; and a group control unit. And a data signal line for transmitting and receiving data in the down direction and the up direction with the group unit control means. Data transmission is enabled between the loop general control means and the group unit control means, and the group general control means sets the signal level of the data signal line to the signal level corresponding to the downward data. The first transmission means for sequentially transmitting the downlink data to the group unit control means by repeatedly changing the signal level of the timing signal line, and the first transmission means for transmitting the downlink data. Occupancy determination means for determining whether or not the data signal line is in an occupied state, and regulation for restricting transmission of downlink data by the first transmission means when it is determined that the data signal line is in an occupied state And the group unit control means is configured to transmit uplink data via the data signal line to which the first transmission means has transmitted downlink data. And a second transmission means for outputting the data to the group general control means, wherein the first transmission means is connected to an arithmetic processing means for performing arithmetic processing relating to control of the rendering device, and to the group unit control means. And signal level control means for controlling each signal level of the data signal line and the timing signal line between the group unit control means and the group unit control means based on a command from the arithmetic processing means. The general control means further comprises timing signal line changing means for changing the signal level of the timing signal line regardless of the signal level of the timing signal line output by the signal level control means. .

  (2) The timing signal line is set to a low level by at least one of the signal level control means and the timing signal line changing means, and the second transmission means transmits the data signal line when transmitting uplink data. Data signal line occupancy means for occupying and setting to a low level, occupancy continuing means for continuing occupancy of the data signal line when the signal level of the timing signal line is maintained at high level, and the data signal line is occupied And the exclusive release means for releasing the occupation of the data signal line when the signal level of the timing signal line changes to the low level, and the timing signal line change means sets the data signal line to the low level. When it is detected that it is occupied, the signal level of the timing signal line is changed from high level to low level. By Rukoto, gaming machine according to (1) to release the occupation of the data signal lines.

  (3) The timing signal line changing means is disposed on the same substrate as the signal level control means, and the arithmetic processing means controls the timing signal line changing means. (2) The gaming machine described.

(4) When the variable display game is executed by the establishment of the predetermined condition and the variable display game results in a specific result mode, a special game state advantageous to the player is generated, and A light emitter controlled to have different light emission modes according to the game state is provided as a part, and the group general control means updates the light emission control data for controlling the light emission mode of the light emitter according to the game state A light emission mode control data updating means is provided, the first transmission means periodically transmits the light emission control data updated by the light emission mode control data update means, and the group unit control means is the first transmission means A light emission mode for updating the light emission mode of the light emitter in correspondence with the light emission control data acquired by the light emission control data acquired by the light emission control data acquired by the light emission control data transmitted by the light emission control data The light emission mode control data updating means switches between light emission control data for turning on the light emitter and light emission control data for turning off the light emitter through the period in which the variable display game is being executed. As described above, the first update means for updating the light emission control data, the light emission control data for turning on the light emitter and the light emission control data for turning off the light emitter through a period in which the variable display game is not executed The gaming machine according to (3), further comprising: a second updating unit that updates the light emission control data so as to switch.

  (5) The group unit control means outputs a reply signal to the group general control means through the data signal line which has transmitted the data when the take-in means takes in data. The group general control means transmits initialization instruction data for initializing the group unit control means after releasing the occupation of the data signal line by the timing signal line change means, and transmits the initialization instruction data. The system further comprises initialization confirmation means for confirming that the group unit control means has been initialized by receiving data from the response signal output means as the data is taken in by the acquisition means. The gaming machine according to (4), which is characterized by

  According to the invention of (1), by outputting a signal to the timing signal line using the timing signal line changing means, the occupied state of the data signal line can be released quickly.

  According to the invention of (2), when the signal level control means releases the timing signal line, the timing signal line changing means can transmit the signal of exclusive release to the group unit control means at any time.

  According to the invention of (3), it is possible to prevent the timing signal line changing means from operating at an unexpected timing.

  According to the invention of (4), it is possible to confirm an internal state such as occurrence of communication abnormality or recovery from abnormality depending on the light emission state of the rendering device, whether the variable display game is being executed or stopped. it can.

  According to the invention of (5), the next control can be performed after confirming that the state of the data signal line is normal by performing initialization after confirming reception of the response signal. It is possible to suppress the recurrence.

  As described above, the present invention is applicable to a game machine in which the effect control device controls the effect device via a plurality of decoration control devices.

1 Game machine 2 Main unit frame (outer frame)
3 front frame (game slot)
9a, 9b Decorative member 10 Game board 12 Auxiliary gaming machine unit 13 1st movable lighting 13a Lighting drive 1st motor (MOT)
14 Second movable lighting 14a Lighting drive second motor (MOT)
15 Reliability notification device 29 Error notification LED
Reference Signs List 30 speaker 45 side lamp 51 center case 53 display device 58 movable effect device 63 first effect unit 64 second effect unit 70 first effect member 71 role-driving first motor (MOT)
80 second effect member 81 product drive second motor (MOT)
500 game control device 550 effect control device 570a 1st master IC
570b Second Master IC
581 Command register (REG)
582 Status register (REG)
583 Own Address Setting Register (REG)
600 relay board 603 free terminal monitor 610 decoration control device 615 I ² CI / O expander 620 decoration device 625 decoration device substrate 640 bus monitoring watchdog timer (WDT)
641 Self-occupied Watchdog Timer (WDT)
1600 Simple relay board 3200, 3300 Error judgment table

Claims (1)

A plurality of effect devices are divided into a plurality of groups, and group unit control means for controlling the effect devices belonging to the divided groups are provided in each group.
A group general control means for comprehensively controlling each of the group unit control means;
A connector including a data signal line, a timing signal line, and a power supply line for supplying a power supply voltage to the group unit control means between the group general control means and the group unit control means Connection enables data transmission from the group general control means to the group unit control means,
The group unit control means
First initialization means for initializing the group unit control means by inputting an initialization signal to an initialization signal input terminal provided separately from the data signal line, and reconnection of the harness When power supply to the group unit control means is started from the power supply line constituting the harness, the group unit control means itself is initialized based on the voltage rise due to the power supply, and the second initialization means is provided.
The group general control means
Arithmetic processing means for performing arithmetic processing related to control of the rendering device;
Signal level control means connected to the group unit control means for controlling each signal level of the data signal line and the timing signal line with the group unit control means based on a command from the arithmetic processing means When,
Is configured to include
The signal level control means
Third initialization means for initializing itself when power supply to the signal level control means is started, and initialization capable of transmitting an initialization signal between the arithmetic processing means and the signal level control means And a fourth initialization means for enabling initialization of the signal level control means by the arithmetic processing means by providing a signal line,
A game machine characterized in that an effect control means capable of controlling an effect relating to a game based on a command from the game control means for controlling the game in an integrated manner is configured as the group general control means.