JP6504601B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  Patent Document 1 discloses a semiconductor device including a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a copper wiring formed on the insulating film.

JP, 2010-171386, A

  One object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of a crack in an insulating film located below a wiring while suppressing an increase in wiring resistance.

  When disposing copper wiring on an insulating film, a barrier metal film may be interposed between them. When heat is applied to the semiconductor device during or after the manufacturing process, thermal expansion of the wiring, the barrier metal film, and the insulating film occurs. The wiring and the barrier metal film usually have a thermal expansion coefficient higher than that of the insulating film, and generate a stress in the direction along the surface of the insulating film by the thermal expansion. In addition to the stress due to its own thermal expansion, the barrier metal film also transmits the stress from the wiring to the insulating film. When the barrier metal film has a lower rigidity than that of the wiring, the barrier metal film is deformed by the stress from the wiring, and transmits the stress of the wiring to the insulating film located below. Due to this stress, stress is concentrated at the periphery of the wiring, and a crack may occur in the insulating film located therebelow. The occurrence of such a crack may be avoided by thinning the wiring, but in this case, there is a contradiction that the resistance value of the wiring increases.

Therefore, the semiconductor device of the present invention is formed on a semiconductor substrate, an insulating film formed on the semiconductor substrate and having a thermal expansion coefficient lower than that of a wiring and a barrier metal film described later, and the insulating film. The barrier metal film includes a wiring mainly composed of copper, and a barrier metal film interposed between the insulating film and the wiring, and the barrier metal film has a laminated structure in which a plurality of metal films are laminated, the insulation A first metal film formed on the film and a second metal film formed on the first metal film, wherein the first metal film has a lower rigidity than copper and a lower thermal expansion than copper And the second metal film has a higher rigidity than copper and a lower coefficient of thermal expansion than copper.
According to the configuration of the present invention, the barrier metal film (second metal film) having a rigidity higher than that of copper is interposed between the insulating film and the wiring whose main component is copper. Therefore, even if the wiring generates a stress in a direction along the surface of the insulating film by thermal expansion, the barrier metal film (second metal film) is not easily deformed by the stress. Thus, the transfer of stress from the wiring to the insulating film can be suppressed by the barrier metal film (second metal film) . As a result, generation of a crack in the insulating film can be suppressed. Further, while the occurrence of a crack can be suppressed by the barrier metal film (second metal film) , the wiring can be thickened, so that the increase in resistance of the wiring can be suppressed or the resistance can be reduced. .

In the semiconductor device, the barrier metal film (second metal film) preferably has a thermal expansion coefficient lower than that of copper. According to this configuration, the amount of deformation of the barrier metal film (second metal film) due to thermal expansion can be made smaller than the amount of deformation due to thermal expansion of the wiring. As a result, since the stress applied from the barrier metal film to the insulating film is small, generation of a crack in the insulating film can be effectively suppressed.
In the semiconductor device, the barrier metal film (second metal film) may have a rigidity of 50 Gpa or more and 180 Gpa or less. In the semiconductor device, the barrier metal film (second metal film) may have a thermal expansion coefficient of less than 8.6 μm / m · K. In the semiconductor device, the barrier metal film (second metal film) may contain one or more metal species selected from the group including tantalum, tungsten, molybdenum, chromium and ruthenium.

In the semiconductor device, the barrier metal film (second metal film) may have a rigidity of 100 Gpa or more and 180 Gpa or less, and may have a thermal expansion coefficient of less than 5 μm / m · K. In the semiconductor device, the barrier metal film (second metal film) may include one or more metal species selected from the group including tungsten, molybdenum and chromium. In the semiconductor device, the insulating film may include a nitride film or an oxide film . Prior Symbol semiconductor device, the barrier metal film (second metal film) may have a smaller thickness than the wiring.

The semiconductor device may further include a multilayer wiring structure formed on the semiconductor substrate and having a plurality of wiring layers stacked via an interlayer insulating film. In this case, the insulating film may be formed on the multilayer wiring structure so as to cover the multilayer wiring structure, and the wiring may be formed on the insulating film as a top layer wiring.
In the case where the side surface of the uppermost layer wiring is not supported by a protective film or the like, the insulating film is particularly likely to be cracked due to the thermal expansion of the wiring. In such a case, by interposing a barrier metal film having high rigidity between the wiring and the insulating film, it is possible to prevent the occurrence of a crack while suppressing an increase in the wiring resistance value.

  The semiconductor device may further include a bonding wire electrically connected to the wiring. For example, when the bonding wire is connected to the wiring, the semiconductor substrate or the like may be heated to a temperature of 200 ° C. or more (for example, about 260 ° C.). The applied heat is transferred to the wiring directly or through the semiconductor substrate or the like to cause its thermal expansion. At this time, since the barrier metal film relieves the stress from the wiring, the generation of the crack of the insulating film can be suppressed.

  The semiconductor device includes: an insulating film on wiring formed on the insulating film so as to cover the wiring; and a rewiring formed on the insulating film on wiring so as to be electrically connected to the wiring. May be further included. The above configuration may further include a bonding wire electrically connected to the rewiring. For example, when the bonding wire is connected to the rewiring, the semiconductor substrate or the like may be heated to a temperature of 200 ° C. or more (for example, about 260 ° C.). The applied heat is transferred to the wiring through the semiconductor substrate, the rewiring, and the like. At this time, since the barrier metal film relieves the stress from the wiring, the generation of the crack of the insulating film can be suppressed.

  The semiconductor device may further include a connection electrode electrically connected to the wiring, and a wiring substrate having a bonding surface in which the semiconductor substrate is flip-chip bonded via the connection electrode. For example, when connecting a connection electrode to a wiring substrate, the semiconductor substrate may be heated to a temperature of 200 ° C. or more (for example, about 260 ° C.). The applied heat is transferred to the wiring through the semiconductor substrate, the connection electrode and the like. At this time, since the barrier metal film relieves the stress from the wiring, the generation of the crack of the insulating film can be suppressed.

  The semiconductor device may further include a land disposed on the surface opposite to the bonding surface of the wiring substrate and electrically connected to the wiring through a via electrode. For example, a semiconductor device is mounted on a mounting substrate via solder in contact with lands. During this mounting, the semiconductor device is heated to melt the solder. As a result, although the wiring is also heated, the barrier metal film relieves the stress from the wiring, so that the generation of the crack of the insulating film can be suppressed.

  The semiconductor device may further include a connection electrode electrically connected to the wiring, and a sealing resin covering the front surface, the back surface, and the side surface of the semiconductor substrate so as to expose the connection electrode. . For example, the connection electrode may be formed as an external terminal to achieve an electrical connection with the outside. In this case, the semiconductor device may be mounted on the mounting substrate via the solder in contact with the connection electrode. During this mounting, the semiconductor device is heated to melt the solder. As a result, although the wiring is also heated, the barrier metal film relieves the stress from the wiring, so that the generation of the crack of the insulating film can be suppressed.

FIG. 1 is a bottom view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view showing the internal structure of the semiconductor device of FIG. FIG. 3 is a cross-sectional view taken along line III-III in FIG. FIG. 4 is an enlarged cross-sectional view of a portion surrounded by a broken line circle IV in FIG. FIG. 5 is a cross-sectional view showing an example of the barrier metal film. FIG. 6A is a view for explaining a part of the manufacturing process of the wiring of FIG. 4; FIG. 6B is a view showing the next process of FIG. 6A. FIG. 6C is a view showing the next process of FIG. 6B. FIG. 6D is a view showing the next process of FIG. 6C. FIG. 6E is a view showing the next process of FIG. 6D. FIG. 6F is a view showing the next process of FIG. 6E. FIG. 7 is an enlarged cross-sectional view showing a portion of the semiconductor device according to the second embodiment of the present invention in which the wiring is formed. FIG. 8 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. FIG. 9 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention. FIG. 10 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention. FIG. 11 is an enlarged cross-sectional view showing a portion where a wiring of the semiconductor device according to the sixth embodiment of the present invention is formed. FIG. 12A is a view for explaining a part of the manufacturing process of the wiring of FIG. 11; FIG. 12B is a view showing the next process of FIG. 12A. FIG. 12C is a view showing the next process of FIG. 12B. FIG. 12D is a view showing the next process of FIG. 12C. FIG. 12E is a view showing the next process of FIG. 12D. FIG. 12F is a view showing the next process of FIG. 12E. FIG. 12G is a view showing the next process of FIG. 12F. FIG. 13 is a cross-sectional view showing a modification of the wiring.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.
First Embodiment
FIG. 1 is a bottom view showing a semiconductor device 1 according to a first embodiment of the present invention. FIG. 2 is a plan view showing an internal structure of the semiconductor device 1 of FIG. FIG. 3 is a cross-sectional view taken along line III-III in FIG. FIG. 4 is an enlarged cross-sectional view of a portion surrounded by a broken line circle IV in FIG.

The semiconductor device 1 is a semiconductor device to which a quad flat non-leaded package (QFN) is applied. The semiconductor device 1 includes a semiconductor chip 2, a die pad 3, leads 4, bonding wires 5, and a resin package 6 for sealing them. The outer shape of the resin package 6 (semiconductor device 1) is a flat rectangular parallelepiped shape.
A plurality of pads 7 are disposed on the surface of the semiconductor chip 2. Each pad 7 is formed, for example, on the peripheral portion of the semiconductor chip 2. Each pad 7 is electrically connected to, for example, a semiconductor element. A back metal 8 made of a metal layer such as gold (Au), nickel (Ni), silver (Ag) or the like is formed on the back surface of the semiconductor chip 2.

  The die pad 3 and the leads 4 are formed by punching a thin metal plate (for example, a thin copper plate). A plated layer 9 made of silver is formed on the surfaces of the die pad 3 and the leads 4. The die pad 3 has a square shape in a plan view, and the semiconductor chip 2 is disposed at the central portion thereof. At the periphery of the back surface of the die pad 3, a depression having a substantially quarter-elliptical cross-section is formed over the entire circumference by crushing from the back surface side. The sealing resin which constitutes the resin package 6 is intruding into the recess.

  Thus, the peripheral edge portion of the die pad 3 is sandwiched from above and below by the sealing resin (resin package 6), and the dropout of the die pad 3 from the resin package 6 is prevented (retained). The back surface of the die pad 3 is exposed from the back surface of the resin package 6 except for a portion which is recessed in a cross-sectional substantially quarter-elliptical shape. A plated layer 10 made of solder is formed on a portion of the back surface of the die pad 3 exposed from the resin package 6.

  The leads 4 are provided in the same number (for example, nine) at positions facing the side surfaces of the die pad 3. At each position opposed to the side surface of the die pad 3, the leads 4 extend in the direction orthogonal to the opposite side surface, and are arranged at equal intervals in the direction parallel to the side surface. At the end of the rear surface of the lead 4 on the die pad 3 side, a depression having a substantially quarter-elliptical cross section is formed by crushing from the rear surface. The sealing resin that constitutes the resin package 6 has entered into the recess.

  As a result, the end portion of the lead 4 on the die pad 3 side is sandwiched by the sealing resin (resin package 6) from above and below, and the falling of the lead 4 from the resin package 6 is prevented (retained). The back surface of the lead 4 is exposed from the back surface of the resin package 6 except for a portion which is recessed in a cross-sectional substantially quarter-elliptical shape. The side surface of the lead 4 opposite to the die pad 3 is exposed from the side surface of the resin package 6. A plated layer 10 made of solder is formed on a portion of the back surface of the lead 4 exposed from the resin package 6.

  In the present embodiment, the semiconductor chip 2 is bonded to the surface (plating layer 9) of the die pad 3 via the bonding material 11 with the surface on which the pad 7 is disposed facing upward. . The bonding material 11 is, for example, a solder paste. If the electrical connection between the semiconductor chip 2 and the die pad 3 is unnecessary, the back metal 8 is omitted, and the back surface of the semiconductor chip 2 is attached to the surface of the die pad 3 through a bonding material made of insulating paste or the like. It may be joined. In this case, the plating layer 9 on the surface of the die pad 3 may be omitted.

The bonding wire 5 has one end joined to the pad 7 of the semiconductor chip 2 and the other end joined to the surface of the lead 4. Bonding wire 5 includes, for example, a copper wire or a gold wire.
Referring to FIG. 4, semiconductor chip 2 includes a semiconductor substrate 12, a multilayer wiring structure 13, a passivation film 14 as an example of the insulating film of the present invention, and a wiring 15. The semiconductor substrate 12 is made of, for example, a silicon substrate having an element forming surface 16 on which semiconductor elements (diodes, transistors, resistors, capacitors, etc.) are formed.

The multilayer wiring structure 13 has a plurality of wiring layers stacked in order from the element formation surface 16 of the semiconductor substrate 12 via an interlayer insulating film. In the present embodiment, the multilayer wiring structure 13 includes a first metal layer 18 stacked on the element formation surface 16 of the semiconductor substrate 12 via the first interlayer insulating film 17 and a first metal layer 18 via the second interlayer insulating film 19. A second metal layer 20 stacked on the metal layer 18 and a third interlayer insulating film 21 covering the second metal layer 20 are included. The first interlayer insulating film 17, the second interlayer insulating film 19 and the third interlayer insulating film 21 contain an insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN), for example. The first metal layer 18 and the second metal layer 20 contain aluminum.

  An upper surface barrier film 22 and a lower surface barrier film 23 are formed on the upper and lower surfaces of the first metal layer 18 to prevent diffusion of impurities into the first interlayer insulating film 17 and the second interlayer insulating film 19, respectively. Similarly, an upper surface barrier film 22 and a lower surface barrier film 23 are formed on the upper and lower surfaces of the second metal layer 20, respectively, for preventing the diffusion of impurities to the second interlayer insulating film 19 and the third interlayer insulating film 21. . The upper barrier film 22 formed on the upper surfaces of the first metal layer 18 and the second metal layer 20 may contain, for example, titanium nitride. On the other hand, lower surface barrier film 23 formed on each lower surface of first metal layer 18 and second metal layer 20 is formed by, for example, sequentially laminating titanium nitride and titanium from lower surfaces of first metal layer 18 and second metal layer 20. It may have a two-layer structure.

  The passivation film 14 is formed on the multilayer wiring structure 13 so as to cover the multilayer wiring structure 13. More specifically, the passivation film 14 is formed on the third interlayer insulating film 21. The passivation film 14 may be, for example, silicon oxide, BPSG (boron phosphorus silicon glass) or silicon nitride. The passivation film 14 may have a laminated structure in which silicon nitride and silicon oxide are laminated in order from the surface of the third interlayer insulating film 21.

  A first via 24 a penetrating the second interlayer insulating film 19 is connected to the upper surface of the first metal layer 18. The first via 24 a penetrates the second interlayer insulating film 19 and is connected to the lower surface of the second metal layer 20. The first via 24a contains tungsten. For example, a first barrier film 25 a containing titanium nitride is interposed between the first via 24 a and the second interlayer insulating film 19.

  On the other hand, a second via 24 b penetrating the third interlayer insulating film 21 and the passivation film 14 is connected to the upper surface of the second metal layer 20. The second via 24 b is exposed from the surface of the passivation film 14. The second via 24 b is formed flush with the surface of the passivation film 14. The second via 24b contains tungsten. A second barrier film 25 b containing, for example, titanium nitride is interposed between the second via 24 b and the third interlayer insulating film 21 and the passivation film 14.

  Referring to the enlarged view of FIG. 2 and FIG. 4, a plurality of interconnections 15 are formed on passivation film 14 at intervals. Each wire 15 is arranged to cover the second via 24 b exposed from the surface of the passivation film 14. Each wire 15 integrally includes a connection portion 40 electrically connected to the bonding wire 5 and a lead portion 41 selectively drawn from the connection portion 40. In the present embodiment, the connection portion 40 is formed in a substantially rectangular shape in plan view as a part of the above-described pad 7 (see FIG. 3). The lead portions 41 adjacent to each other in each of the wires 15 may be formed to run parallel to each other at a predetermined distance.

Each interconnection 15 has a flat upper surface 27 along the surface of passivation film 14. The width W of each wire 15 is, for example, 7 μm or more and 20 μm or less. The thickness T of each wire 15 is, for example, not less than 7 μm and not more than 20 μm. In the range of these numerical values, the aspect ratio R ₁₅ (= thickness T / width W) of each wire 15 may be 0 <R ₁₅ ≦ 1. The inter-wire distance L of the plurality of wires 15 may be, for example, 20 μm or less.

The wiring 15 may contain a metal whose main component is copper. The metal containing copper as a main component refers to a metal whose mass ratio (mass%) of copper is the highest with respect to other components (hereinafter the same). For example, when the wiring 15 is made of an aluminum-copper (Al-Cu) alloy, an aluminum-silicon-copper (Al-Si-Cu) alloy, etc., the mass ratio R _Cu of _copper is the mass ratio R _{Al of aluminum} or silicon Higher than mass ratio R _Si (R _Cu > R _Al, R _Cu > R _Si ). Although metals containing copper as the main component may contain trace amounts of impurities, high purity copper with a purity of 99.9999% (6N) or higher, high purity copper with a purity of 99.99% (4N) or higher, etc. included.

  A barrier metal film 26 and a copper seed film (not shown) are disposed between each wire 15 and the passivation film 14. The barrier metal film 26 is formed on the passivation film 14, and the copper seed film (not shown) is formed on the barrier metal film 26. In the present embodiment, the copper seed film (not shown) is integrated with each wire 15. The barrier metal film 26 is formed such that its both end portions are located inside the side surface 28 of the wiring 15 in a cross sectional view. That is, the width of the barrier metal film 26 is smaller than the width W of the wiring 15. The barrier metal film 26 has a thickness smaller than that of the wiring 15. The thickness of barrier metal film 26 may be, for example, not less than 0.1 μm and not more than 0.3 μm. Each wire 15 is electrically connected to the second via 24 b via the copper seed film (not shown) and the barrier metal film 26.

  On the surface of each wire 15, a laminated film of a Ni (nickel) film 29, a Pd (palladium) film 30, and an Au (gold) film 31 is formed. The Ni film 29 is formed along the upper surface 27 and the side surface 28 of each wire 15 such that the one surface and the other surface cover the wires 15. In the present embodiment, the portion of the Ni film 29 formed on the upper surface 27 of each wire 15 is formed thicker than the other portions. The Ni film 29 may have a uniform thickness. The thickness of the Ni film 29 may be, for example, 2 μm or more and 4 μm or less.

  The Pd film 30 covers the entire area of the Ni film 29 with a uniform thickness (for example, 0.1 μm or more and 0.5 μm or less). Au film 31 covers the entire area of Pd film 30 with a uniform thickness (for example, 0 μm or more and 0.05 μm or less) thinner than, for example, Pd film 30. The laminated film of the Ni film 29, the Pd film 30 and the Au film 31 functions as a protective film for protecting the wiring 15. The bonding wire 5 is connected to the Au film 31. That is, in the present embodiment, the pad 7 is formed by the connection portion 40 of each wire 15, the Ni film 29, the Pd film 30, and the Au film 31.

  Here, as a reference example, a semiconductor device including a barrier metal film 26 having a lower rigidity than copper will be considered with reference to Table 1 below. Table 1 shows each material of the wiring 15, the barrier metal film 26, and the passivation film 14 of the semiconductor device according to the reference example. In the following, the case where the wiring 15 is made of high purity copper having a purity of 99.9999% (6N) or higher, high purity copper having a purity of 99.99% (4N) or higher (hereinafter simply referred to as "copper") is described. An example will be described.

  The semiconductor device according to the reference example includes a barrier metal film 26 made of titanium, which has a lower rigidity than copper, between the passivation film 14 made of an oxide film or a nitride film and the wiring 15 made of copper. When heat is applied to the semiconductor device during or after the manufacturing process, thermal expansion of the wiring 15, the barrier metal film 26, and the passivation film 14 occurs. The interconnection 15 and the barrier metal film 26 have a thermal expansion coefficient higher than that of the passivation film 14, and generate a stress in the direction along the surface of the passivation film 14 due to the thermal expansion.

  The barrier metal film 26 also transmits the stress from the interconnection 15 to the passivation film 14 in addition to the stress due to its own thermal expansion. When the barrier metal film 26 has a rigidity lower than that of the wiring 15, the barrier metal film 26 receives stress from the wiring 15 to be deformed, and transmits the stress of the wiring 15 to the passivation film 14 located therebelow. Due to this stress, stress is concentrated at the periphery of the wiring 15, and there is a possibility that a crack (crack) may occur in the passivation film 14 located therebelow. The occurrence of such a crack may be avoided by thinning the wiring 15. However, in this case, there is a contradiction that the resistance value of the wiring 15 is increased.

  From the above, generation of cracks in the passivation film 14 can be achieved by adopting, for the barrier metal film 26, a metal material having a rigidity higher than that of copper (48 GPa) instead of or in addition to titanium. It is thought that it can control. Further, it is considered that the increase in the resistance value of the wiring 15 can be suppressed or the resistance can be reduced by thickening the wiring 15.

  Also, by making the thermal expansion coefficient of the barrier metal film 26 less than the thermal expansion coefficient of copper (16.5 μm / m · K), more preferably the thermal expansion coefficient of titanium (8.6 μm / m · K), It is considered that the occurrence of cracks can be effectively suppressed. In other words, it is considered that generation of cracks in the passivation film 14 can be effectively suppressed by bringing the thermal expansion coefficient of the barrier metal film 26 close to the thermal expansion coefficient of the passivation film 14. In these cases, from the viewpoint of suppressing the increase in resistance value, it is desirable that a metal material smaller than the electrical resistivity (= 420 nΩ · m) of titanium be employed as the metal material of the barrier metal film 26. An example of the metal material of the barrier metal film 26 which satisfies the above conditions is shown in Table 2 below.

  As shown in Table 2, the barrier metal film 26 is one or more metals selected from the group including tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr) and ruthenium (Ru). May contain seeds. According to these metal species, a barrier metal film having a thermal expansion coefficient of 4 μm / m · K to 7 μm / m · K, a rigidity of 50 Gpa to 180 Gpa, and an electric resistivity of 50 nΩ · m to 150 nΩ · m 26 can be obtained.

  That is, according to these metal species, a barrier metal film having a thermal expansion coefficient smaller than that of copper (16.5 μm / m · K) and that of titanium (8.6 μm / m · K) 26 can be realized. Further, according to these metal species, it is possible to realize the barrier metal film 26 having a rigidity larger than that of copper (48 Gpa) or titanium (44 Gpa). Furthermore, according to these metal species, a barrier metal film 26 having an electrical resistivity smaller than that of titanium (420 nΩ · m) can be realized.

  Referring to Table 2, at least one of the conditions of thermal expansion coefficient of 4 μm / m · K to 5 μm / m · K, rigidity of 100 Gpa to 180 Gpa, and electric resistivity of 50 nΩ · m to 100 nΩ · m A barrier metal film 26 may be formed. When all of these conditions are satisfied, the barrier metal film 26 can include at least one of tungsten and molybdenum.

  For example, the barrier metal film 26 may have a thermal expansion coefficient of 4 μm / m · K to 5 μm / m · K and a rigidity of 100 Gpa to 180 Gpa. In this case, the barrier metal film 26 can include one or more metal species selected from the group including tungsten, molybdenum and chromium. The barrier metal film 26 may have a thermal expansion coefficient of 4 μm / m · K to 5 μm / m · K and an electric resistivity of 50 nΩ · m to 100 nΩ · m. In this case, the barrier metal film 26 can include at least one of tungsten and molybdenum. The barrier metal film 26 may have a rigidity of 100 Gpa or more and 180 Gpa or less and an electric resistivity of 50 nΩ · m or more and 100 nΩ · m or less. In this case, the barrier metal film 26 can include one or more metal species selected from the group including tungsten, molybdenum and ruthenium.

  Referring to FIG. 4, when a metal material having a rigidity higher than that of copper is employed for barrier metal film 26 instead of titanium, passivation film 14 may include an oxide film or a nitride film. In this case, the barrier metal film 26 can include one or more metal species selected from the group including tantalum, molybdenum, chromium and ruthenium. With these metal species, the barrier metal film 26 can be formed on the passivation film 14 while maintaining good adhesion to the passivation film 14. Further, since the barrier metal film 26 has an electrical resistivity smaller than that of titanium, the resistance of the semiconductor device 1 can be reduced.

On the other hand, when a metal material having a rigidity higher than that of copper in addition to titanium is adopted for the barrier metal film 26, the structure is as shown in FIG. FIG. 5 is a cross-sectional view showing an example of the barrier metal film 26. As shown in FIG. In FIG. 5, only the configuration of the wiring 15, the barrier metal film 26, and the periphery thereof are illustrated.
As shown in FIG. 5, a barrier metal film 26 having a laminated structure in which a plurality of metal films are laminated is interposed between the wiring 15 and the passivation film 14. The barrier metal film 26 includes a first metal film 26 a formed on the passivation film 14 and a second metal film 26 b formed on the first metal film 26 a. The first metal film 26 a is a titanium film, and is electrically connected to the second via 24 b. The thickness of the first metal film 26a may be, for example, 0.1 μm or more and 0.3 μm or less. On the other hand, the second metal film 26b is a metal film containing one or more metal species selected from the group including tantalum, tungsten, molybdenum, chromium and ruthenium. The thickness of the second metal film 26b may be, for example, 0.1 μm or more and 0.3 μm or less.

  In this configuration, the passivation film 14 may be a nitride film, and the second metal film 26 b may be a tungsten film. If the passivation film 14 is a nitride film, the first metal film 26a (titanium film) can be formed on the passivation film 14 while maintaining good adhesion. Further, the second metal film 26b (tungsten film) can be formed on the first metal film 26a (titanium film) while maintaining good adhesion.

  As described above, according to the present embodiment, the barrier metal film 26 having a rigidity higher than that of copper is interposed between the wiring 15 mainly composed of copper and the passivation film 14. Therefore, even if the wiring 15 generates a stress in a direction along the surface of the passivation film 14 due to thermal expansion, the barrier metal film 26 is not easily deformed by the stress. Thereby, the barrier metal film 26 can suppress transmission of stress from the wiring 15 to the passivation film 14. In addition, since the barrier metal film 26 has a thermal expansion coefficient lower than that of copper, the amount of deformation of the barrier metal film 26 due to thermal expansion can be smaller than the amount of deformation of the wiring 15 due to thermal expansion. Thereby, the stress applied from the barrier metal film 26 to the passivation film 14 can be reduced. As a result, generation of cracks in the passivation film 14 can be effectively suppressed. Further, while the occurrence of cracks can be suppressed by the barrier metal film 26, the wiring 15 can be thickened, so that the increase in the resistance value of the wiring 15 can be suppressed or the resistance can be reduced.

  Further, in the present embodiment, the bonding wire 5 is connected to the wiring 15. For example, when bonding wire 5 is connected to interconnection 15, semiconductor substrate 12 or the like may be heated to a temperature of 200 ° C. or more (for example, about 260 ° C.). The applied heat is transferred to the interconnection 15 directly or through the semiconductor substrate 12 or the like to cause its thermal expansion. At this time, since the barrier metal film 26 relieves the stress from the wiring 15, the generation of the crack of the passivation film 14 can be suppressed.

6A to 6F are diagrams for describing a part of the manufacturing process of the wiring 15 of FIG. In the following description, reference is made to FIG. 4 as needed. In the following, the case where the wiring 15 is made of high purity copper will be described as an example.
First, prior to the formation of the interconnections 15, a multilayer interconnection structure 13 (see FIG. 4) is formed on the semiconductor substrate 12. Next, a passivation film 14 is formed on the multilayer wiring structure 13. Next, a second via 24b (see FIG. 4) penetrating the passivation film 14 is formed. Next, as shown in FIG. 6A, the barrier metal film 26 and the copper seed film 32 are formed in this order on the surface of the passivation film 14 by sputtering, for example.

  Next, as shown in FIG. 6B, a resist film 33 having an opening 34 selectively is formed on the copper seed film 32 in the region where each interconnection 15 is to be formed. Next, copper is plated and grown from the surface of the copper seed film 32 exposed from the opening 34 by electrolytic plating. Copper is grown (embedded) to the middle of the opening 34. In this process, the plated and grown copper is integrated with the copper seed film 32. Thus, the wiring 15 is formed.

Next, as shown in FIG. 6C, Ni is grown from the upper surface 27 of the wiring 15 by electroless plating using the opening 34 of the resist film 33. Thereby, a part of the Ni film 29 is formed. Thereafter, as shown in FIG. 6D, the resist film 33 is removed.
Next, as shown in FIG. 6E, copper seed film 32 and barrier metal film 26 are selectively removed by wet etching, for example. In this step, the end of the barrier metal film 26 is etched (over-etched) inside the side surface 28 of the wiring 15 so that the end of the barrier metal film 26 is positioned inside the side surface 28 of the wiring 15 Is formed. Thus, a step is formed between the end of the barrier metal film 26 and the side surface 28. In this step, the side surface 28 of the wiring 15 may be etched together with the copper seed film 32 so that the side surface 28 of the wiring 15 is positioned inside the end of the Ni film 29.

Next, as shown in FIG. 6F, Ni, Pd and Au are plated and grown in this order from the side surface 28 of the wiring 15 and the Ni film 29 by electroless plating. Thereby, a laminated film of the Ni film 29, the Pd film 30, and the Au film 31 is formed. Thereafter, the temperature of the semiconductor substrate 12 is set to 200 ° C. or higher (for example, 260 ° C.), and the bonding wire 5 (see FIG. 4) is connected to the wiring 15 (Au film 31).
Second Embodiment
FIG. 7 is an enlarged cross-sectional view showing a portion where the wiring 15 of the semiconductor device 61 according to the second embodiment of the present invention is formed. FIG. 7 corresponds to the enlarged view of the portion enclosed by the broken line circle IV in FIG. 3 described above. In FIG. 7, the parts corresponding to the respective parts shown in FIG.

  The semiconductor device 61 is electrically connected to the first resin film 62 as an example of the insulating-on-wiring film of the present invention formed on the passivation film 14 so as to cover the wiring 15 and to be electrically connected to the wiring 15. And the rewiring 63 formed on the resin film 62. The first resin film 62 contains, for example, a polyimide resin. The first resin film 62 has a pad opening 65 for exposing a part of the wiring 15 as an electrode pad 64. Rewirings 63 are drawn on the first resin film 62.

  The rewiring 63 is formed to enter the pad opening 65 from the surface of the first resin film 62. The rewiring 63 is electrically connected to the electrode pad 64 in the pad opening 65. In the present embodiment, the rewiring 63 has a two-layer structure including a UBM (under bump metal) film 66 and a wiring film 67 formed on the UBM film 66. The UBM film 66 has one surface and the other surface formed along the surface of the first resin film 62 and the surface of the electrode pad 64. The UBM film 66 may have a two-layer structure including a titanium film and a copper film formed on the titanium film. The wiring film 67 is formed along the UBM film 66 so as to enter the concave space formed by the UBM film 66 entering the pad opening 65. The wiring film 67 may contain a metal whose main component is copper. A second resin film 68 is formed on the rewiring 63 so as to cover the rewiring 63.

  The second resin film 68 has a rewiring pad opening 70 which exposes a part of the rewiring 63 as a rewiring pad 69. An electrode post 71 is formed on the redistribution pad 69. The electrode post 71 corresponds to the pad 7 (see FIG. 2). The electrode post 71 is formed to enter the redistribution pad opening 70 from the surface of the second resin film 68. The electrode post 71 is electrically connected to the redistribution pad 69 in the redistribution pad opening 70. In the present embodiment, the electrode post 71 has a two-layer structure including the UBM film 72 and the wiring film 73 formed on the UBM film 72.

  The UBM film 72 has one surface and the other surface formed along the surface of the second resin film 68 and the surface of the redistribution pad 69. The UBM film 72 may have a two-layer structure including a titanium film and a copper film formed on the titanium film. The wiring film 73 is formed along the UBM film 72 so as to enter the concave space formed by the UBM film 72 entering the pad opening 65. The wiring film 73 may contain a metal whose main component is copper. The bonding wire 5 is connected to the electrode post 71.

  As described above, according to the present embodiment, the bonding wire 5 is electrically connected to the rewiring 63 through the electrode post 71. For example, when bonding wire 5 is connected to electrode post 71, semiconductor substrate 12 or the like may be heated to a temperature of 200 ° C. or higher (for example, about 260 ° C.). The applied heat is transmitted to the wiring 15 through the semiconductor substrate 12, the electrode post 71, the rewiring 63, and the like. At this time, since the barrier metal film 26 relieves the stress from the wiring 15, generation of a crack in the passivation film 14 can be suppressed (see also FIG. 4, FIG. 5 and the like).

In the present embodiment, the crack in the first resin film 62 is formed by forming the UBM film 66 of the rewiring 63 with one or more metal species selected from the group containing tantalum, tungsten, molybdenum, chromium and ruthenium. May be suppressed. Further, by forming the UBM film 72 of the electrode post 71 with one or more metal species selected from the group containing tantalum, tungsten, molybdenum, chromium and ruthenium, generation of cracks in the second resin film 68 can be achieved. You may make it suppress.
Third Embodiment
FIG. 8 is a cross-sectional view showing a semiconductor device 81 according to a third embodiment of the present invention. In FIG. 8, parts corresponding to the parts shown in FIG. 2 etc. described above are assigned the same reference numerals and explanation thereof is omitted.

  In semiconductor device 81, connection electrodes 82 respectively connected to a plurality of pads 7 (wirings 15) formed on the surface of semiconductor chip 2 and semiconductor chip 2 (semiconductor substrate 12) are flip chip bonded via connection electrodes 82. And the wiring substrate 83 having the bonded surface 83a. The connection electrode 82 may be a block or columnar conductor or may be solder. A plurality of lands 84 and solder balls 85 electrically connected to the respective lands 84 are formed on the back surface 83 b of the wiring substrate 83 opposite to the bonding surface 83 a. The lands 84 and the solder balls 85 are electrically connected to the corresponding connection electrodes 82 and the pads 7 (wirings 15) through via electrodes 86 formed on the wiring substrate 83. A sealing resin 88 is formed in a gap 87 between the semiconductor chip 2 and the wiring substrate 83 so as to fill the gap 87.

  As described above, according to the present embodiment, the semiconductor chip 2 is connected to the wiring substrate 83 via the connection electrode 82. For example, when the connection electrode 82 is connected to the wiring substrate 83, the semiconductor chip 2 (semiconductor substrate 12) or the like may be heated to a temperature of 200 ° C. or more (for example, about 260 ° C.). The applied heat is transmitted to the wiring 15 through the semiconductor substrate 12, the connection electrode 82 and the like. At this time, since the barrier metal film 26 relieves the stress from the wiring 15, it is possible to suppress the crack of the passivation film 14 (see also FIG. 4 and FIG. 5 etc.).

Further, according to the present embodiment, the semiconductor device 81 is mounted on a mounting substrate (not shown) via the solder balls 85 in contact with the lands 84. At the time of this mounting, the semiconductor device 81 is heated to melt the solder balls 85. As a result, although the wiring 15 is also heated, the barrier metal film 26 relieves the stress from the wiring 15, so that the crack of the passivation film 14 can be suppressed (see also FIG. 4 and FIG. 5 etc.).
Fourth Embodiment
FIG. 9 is a cross-sectional view showing a semiconductor device 91 according to a fourth embodiment of the present invention. In FIG. 9, the parts corresponding to the parts shown in FIG.

The semiconductor device 91 includes the connection electrodes 92 respectively connected to the plurality of pads 7 (wirings 15) formed on the surface of the semiconductor chip 2 and the semiconductor chip 2 (semiconductor substrate 12) so as to expose the connection electrodes 92. It includes an element forming surface 16, and a sealing resin 93 covering the back surface and the side surface. The sealing resin 93 doubles as the resin package 6.
As described above, according to the present embodiment, the connection electrode 92 is formed as an external terminal for achieving electrical connection with the outside. In this case, the semiconductor device 91 is mounted on a mounting substrate (not shown) via the solder in contact with the connection electrode 92. At the time of this mounting, the semiconductor device 91 is heated to melt the solder. As a result, although the wiring 15 is also heated, the barrier metal film 26 relieves the stress from the wiring 15, so that the crack of the passivation film 14 can be suppressed (see also FIG. 4 and FIG. 5 etc.).

Further, rewiring 63 as shown in FIG. 7 may be formed on connection electrode 92, for example. In this case, the semiconductor device 91 is mounted on a mounting substrate (not shown) via the solder in contact with the electrode pad 64 (see FIG. 7). During this mounting, the solder is melted by heating. The heat at the time of mounting is transmitted to the wiring 15 through, for example, the rewiring 63 or the like. Even in such a case, the barrier metal film 26 relieves the concentration of stress from the wiring 15. Thereby, the crack of the passivation film 14 resulting from the heating at the time of mounting can be suppressed (see also FIG. 4 and FIG. 5 etc.).
Fifth Embodiment
FIG. 10 is a cross-sectional view showing a semiconductor device 101 according to a fifth embodiment of the present invention. In FIG. 10, parts corresponding to the parts shown in FIG. 2 etc. described above are assigned the same reference numerals and descriptions thereof will be omitted.

  As shown in FIG. 10, the semiconductor device 101 is a semiconductor device to which a small outline package (SOP) having a lead 4 drawn out of a resin package 6 (sealing resin) is applied. Similar to the semiconductor device 1 described above, the semiconductor chip 2 is disposed on the die pad 3. Although the lower surface of the die pad 3 is not exposed from the resin package 6 in this embodiment, the lower surface of the die pad 3 may be formed to be exposed from the resin package 6.

  The lead 4 includes an inner lead portion 4 a sealed in the resin package 6 and an outer lead portion 4 b integrally formed with the inner lead portion 4 a and drawn out of the resin package 6. The inner lead portion 4 a is electrically connected to the pad 7 (wiring 15) of the corresponding semiconductor chip 2 through the bonding wire 5 in the resin package 6. The outer lead portion 4 b is formed to extend toward the lower surface of the resin package 6. The outer lead portion 4 b is a mounting terminal connected to the mounting substrate.

As described above, also by the configuration of the present embodiment, the same effects as the effects described in the first embodiment can be obtained. In the present embodiment, the semiconductor device 101 to which the SOP is applied has been described. However, as long as the semiconductor device 101 has the leads 4 drawn out of the resin package 6 (sealing resin), the semiconductor device 101 may be of a type other than SOP. That is, the semiconductor device 101 includes small outline J-leaded (SOJ), ceramic flat package (CFP), small outline transistor (SOT), quad flat package (QFP), dual flat package (DFP), and plastic leaded chip carrier (PLCC). , Dual Inline Package (DIP), Single Inline Package (SIP), or the like.
Sixth Embodiment
FIG. 11 is an enlarged cross-sectional view showing a portion where the wiring 15 of the semiconductor device 111 according to the sixth embodiment of the present invention is formed. FIG. 11 corresponds to the enlarged view of the part surrounded by the broken line circle IV in FIG. 3 described above. In FIG. 11, the parts corresponding to the parts shown in FIG. 4 etc. are given the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 11, in the present embodiment, the metal film 112 is formed on the wiring 15. The metal film 112 includes a laminated film made of a plurality of metal films. In the present embodiment, the metal film 112 includes a laminated film of a Ni (nickel) film 113 and a Pd (palladium) film 114. The width of the metal film 112 is larger than the width W of the wiring 15. In other words, the width W of the wiring 15 is smaller than the width of the metal film 112.

  More specifically, the Ni film 113 of the metal film 112 has a flat surface, and is formed on the wiring 15 so that both end portions are positioned outside the side surface 28 of the wiring 15 in a cross sectional view. There is. The Ni film 113 has a thickness smaller than the thickness of the wiring 15. The Ni film 113 may be formed to have a uniform thickness. The thickness of the Ni film 113 may be, for example, 2 μm or more and 4 μm or less.

  On the other hand, the Pd film 114 of the metal film 112 has a flat surface, and is formed on the Ni film 113 so that both end portions are located outside the side surface 28 of the wiring 15 in a cross sectional view. The Pd film 114 is formed on the Ni film 113 in alignment with the Ni film 113. That is, the end of the Pd film 114 is formed to be flush with the end of the Ni film 113. The Pd film 114 has a thickness smaller than that of the Ni film 113. The Pd film 114 may be formed to have a uniform thickness. The thickness of the Pd film 114 may be, for example, 0.1 μm or more and 0.5 μm or less.

The bonding wire 5 is connected to the metal film 112 (Pd film 114). That is, in the present embodiment, the pad 7 is formed by the connection portion 40 of each wire 15 and the metal film 112 (Ni film 113 and Pd film 114).
As described above, also by the configuration of the present embodiment, the same effects as the effects described in the first embodiment can be obtained.

12A to 12G are diagrams for describing a part of the manufacturing process of the wiring 15 of FIG. In the following description, reference is made to FIG. 11 as needed. In the following, the case where the wiring 15 is made of high purity copper will be described as an example.
First, as shown in FIG. 12A, prior to the formation of the interconnections 15, a multilayer interconnection structure 13 (see FIG. 11) is formed on the semiconductor substrate 12. Next, a passivation film 14 is formed on the multilayer wiring structure 13. Next, the second via 24 b penetrating the passivation film 14 is formed.

Next, as shown in FIG. 12B, barrier metal film 26 and copper seed film 32 are formed in this order on the surface of passivation film 14 by sputtering, for example. Next, as shown in FIG. 12C, a resist film 33 having an opening 34 selectively is formed on the copper seed film 32 in the region where each interconnection 15 is to be formed.
Next, as shown in FIG. 12D, copper is plated and grown from the surface of the copper seed film 32 exposed from the opening 34 by electrolytic plating. Copper is grown (embedded) to the middle of the opening 34. In this process, the plated and grown copper is integrated with the copper seed film 32. Thus, the wiring 15 is formed.

  Next, as shown in FIG. 12E, Ni is grown from the upper surface 27 of the wiring 15 by electroless plating using the opening 34 of the resist film 33. Thereby, the Ni film 113 is formed. Next, Pd is grown on the Ni film 113 by electroless plating using the openings 34 of the resist film 33. In this process, a Pd film having a thickness smaller than that of the Ni film 113 is formed. Thereby, the metal film 112 including the Ni film 113 and the Pd film 114 is formed. Thereafter, as shown in FIG. 12F, the resist film 33 is removed.

  Next, as shown in FIG. 12G, copper seed film 32 and barrier metal film 26 are selectively removed by wet etching, for example. In this step, the side surface 28 of the wiring 15 is etched together with the copper seed film 32 so that the side surface 28 of the wiring 15 is located inside the end of the metal film 112. Thus, a step is formed between the side surface 28 of the wiring 15 and the end of the metal film 112. Further, in this step, the end of the barrier metal film 26 is etched (over-etched) inside the side surface 28 of the wiring 15, and both ends of the barrier metal film 26 are positioned inside the side surface 28 of the wiring 15. It is formed to Thus, a step is formed between the end of the barrier metal film 26 and the side surface 28.

Thereafter, the bonding wire 5 (see FIG. 11) is connected to the Pd film 114 by setting the temperature of the semiconductor substrate 12 to 200 ° C. or higher (for example, 260 ° C.).
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, in each of the embodiments described above, the barrier metal film 26 is one or more selected from the group including tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr) and ruthenium (Ru). An example including the metal species of However, these metal species have a higher rigidity than that of copper (titanium), a lower coefficient of thermal expansion than that of copper (titanium), and a lower electrical resistivity than that of titanium. And the like, and is not intended to limit the material of the barrier metal film 26. Therefore, the barrier metal film 26 can contain various metal materials as long as the above conditions are satisfied. For example, the metal material satisfying the above conditions may be one or more metal species selected from the group comprising tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr) and ruthenium (Ru). The alloy may be included.

Further, in the first embodiment described above, the example in which the laminated film of the Ni film 29, the Pd film 30, and the Au film 31 covering the wiring 15 is formed has been described. However, as shown in FIG. 13, the bonding wire 5 may be directly connected to the wiring 15 without forming the laminated film of the Ni film 29, the Pd film 30 and the Au film 31.
Further, in the above-described sixth embodiment, the example in which the metal film 112 including the laminated film of the Ni film 113 and the Pd film 114 is formed has been described. In this configuration, the metal film 112 may include an Au (gold) film formed on the Pd film 114. Furthermore, the metal film 112 may be a metal film containing one or more metal species selected from the group including Ni, Pd and Au.

  In the first, second, fifth, and sixth embodiments described above, the example in which the semiconductor devices 1, 61, 101, and 111 include the bonding wire 5 has been described. However, in place of or in addition to bonding wire 5, semiconductor devices 1, 61, 101, 111 may include a connecting member such as a conductor plate having a relatively large current passing area.

  In addition, various design changes can be made within the scope of matters described in the claims.

Reference Signs List 1 semiconductor device 5 bonding wire 12 semiconductor substrate 13 multilayer wiring structure 14 passivation film 15 wiring 26 barrier metal film 61 semiconductor device 62 first resin film 63 rewiring 81 semiconductor device 82 connection electrode 83 wiring substrate 83a bonding surface 83b back surface 84 land 86 Via electrode 88 sealing resin 91 semiconductor device 92 connection electrode 93 sealing resin 101 semiconductor device 111 semiconductor device

Claims (16)

A semiconductor substrate,
An insulating film formed on the semiconductor substrate and having a thermal expansion coefficient lower than that of a wiring and a barrier metal film described later ;
A copper-based wiring formed on the insulating film;
A barrier metal film interposed between the insulating film and the wiring ;
The barrier metal film has a laminated structure in which a plurality of metal films are laminated, and a first metal film formed on the insulating film and a second metal film formed on the first metal film Including
The first metal film has a lower rigidity than copper and a lower coefficient of thermal expansion than copper,
The semiconductor device, wherein the second metal film has a higher rigidity than copper and a lower coefficient of thermal expansion than copper . The semiconductor device according to claim 1 , wherein the second metal film has a rigidity of 50 Gpa or more and 180 Gpa or less. The second metal layer has a thermal expansion coefficient of less than 8.6 [mu] m / m · K, a semiconductor device according to claim 1 or 2. The semiconductor device according to any one of claims 1 to 3 , wherein the second metal film contains one or more metal species selected from the group including tantalum, tungsten, molybdenum, chromium and ruthenium. The semiconductor device according to any one of claims 1 to 3 , wherein the second metal film has a rigidity of 100 Gpa or more and 180 Gpa or less and a thermal expansion coefficient of less than 5 μm / m · K. . The semiconductor device according to any one of claims 1 to 3 , wherein the second metal film contains one or more metal species selected from the group including tungsten, molybdenum and chromium. The insulating film comprises a nitride film or an oxide film, a semiconductor device according to any one of claims 1-6. The semiconductor device according to any one of claims 1 to 7 , wherein the barrier metal film has a thickness smaller than that of the wiring. The semiconductor device further includes a multilayer wiring structure formed on the semiconductor substrate and having a plurality of wiring layers stacked via an interlayer insulating film,
The insulating film is formed on the multilayer wiring structure so as to cover the multilayer wiring structure,
The semiconductor device according to any one of claims 1 to 8 , wherein the wiring is formed on the insulating film as a top layer wiring. The semiconductor device according to any one of claims 1 to 9 , further comprising a bonding wire electrically connected to the wire. The semiconductor device according to claim 10 , wherein the bonding wire comprises a copper wire or a gold wire. An insulating film on wiring formed on the insulating film so as to cover the wiring;
The semiconductor device according to any one of claims 1 to 9 , further comprising a rewiring formed on the insulating film on the wiring so as to be electrically connected to the wiring. The semiconductor device according to claim 12 , further comprising a bonding wire electrically connected to the rewiring. A connection electrode electrically connected to the wire;
The semiconductor device according to any one of claims 1 to 9 , further comprising: a wiring substrate having a junction surface in which the semiconductor substrate is flip chip bonded via the connection electrode. The semiconductor device according to claim 14 , further comprising a land disposed on the surface opposite to the bonding surface of the wiring substrate and electrically connected to the wiring through a via electrode. A connection electrode electrically connected to the wire;
The semiconductor device according to any one of claims 1 to 9 , further comprising: a sealing resin that covers the front surface, the back surface, and the side surface of the semiconductor substrate so as to expose the connection electrode.

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