JP6505804B2 - Thin film transistor - Google Patents

Description

  The present invention relates to a thin film transistor (TFT) having an oxide semiconductor layer as a channel layer.

  A field effect transistor (FET) is widely used as a unit electronic element of a semiconductor memory integrated circuit, a high frequency signal amplification element, an element for driving a liquid crystal, and the like. Thin film transistors (TFTs) are a type of field effect transistor. With the remarkable development of image display devices in recent years, this TFT is widely used as a switching element in various image display devices. Various image display devices include a liquid crystal image display (LCD), an organic electroluminescence image display, and the like.

LCDs, which are representative of displays, occupy the mainstream in the small-sized panel field and the large-sized image display panel field for TVs. On the other hand, since the organic EL image display device is superior to the LCD in terms of high definition, future development is expected.
With the improvement of moving picture resolution and the spread of three-dimensional displays, LCDs have been increased in frame rate. High frame rate driving is effective for improving moving picture resolution, and further speeding up of the frame rate is required. A large screen, high definition, and high frame rate driving are the keywords as a perspective of the image display device, and the performance required for this realization is required of the TFT. For example, with an increase in pixel capacity due to an increase in screen size, an increase in the number of scanning lines due to high definition, and an increase in frame rate, TFTs are required to have high field effect mobility (hereinafter sometimes referred to as mobility). ing.

The mobility of the a-Si: H (hydrogenated amorphous silicon) TFT used in the conventional LCD is about 2 cm ² / Vs at the maximum. However, the large screen, high definition, and high frame rate driving required for a video display can not be coped with this degree of mobility.

  In addition, since the organic EL is a current drive element and an increase in the current value of the drive TFT is required to improve the brightness of the screen, a high mobility TFT is essential for the organic EL image display device. In addition to the high mobility, the TFT used for driving the organic EL image display device is also required to have reliability against current stress. At present, low temperature poly-Si (LTPS) is mentioned as a candidate for a TFT material satisfying both mobility and reliability. However, there is a problem that the screen size that can be realized is limited by the relationship of the used beam length at the time of laser crystallization, and the in-plane nonuniformity of the TFT characteristics caused by the inter-shot variation of laser light.

  Attention is focused on TFTs using oxide semiconductors instead of a-Si: H TFTs or LTPS. For example, a TFT using an oxide semiconductor such as zinc oxide (ZnO) or indium gallium zinc oxide (IGZO) in an active layer (semiconductor layer) exhibits excellent properties in mobility and the like, and its improvement development is advanced There is.

  An oxide semiconductor is formed of a highly ionic bond, and is characterized in that the difference in electron mobility is small whether it is crystalline or amorphous. That is, it is characterized in that relatively high electron mobility can be realized even in an amorphous state. In addition, even when crystallized, it is possible to manufacture a TFT which is not easily affected by the grain boundary barrier and which is suitable for a large area which requires in-plane uniformity. Furthermore, since it has an in-gap state derived from oxygen deficiency near the valence band, holes are less likely to be free carriers than electrons, and it is reported that the off current during TFT operation can be reduced to about 10-15A. There is. In addition, because of the wide band gap semiconductor compared to silicon-based TFTs, they have superiority in the light stability of the visible light region. Furthermore, since an amorphous film can be formed at room temperature by using a sputtering method or the like, researches on forming an oxide semiconductor film transistor on a resin substrate such as PET are also conducted.

  As a TFT technology using an oxide semiconductor, for example, Patent Document 1 discloses a TFT using indium tin oxide (ITO) or the like as a channel layer as an oxide conductive material having a high carrier concentration. In this document, the film thickness of the channel layer which is an extremely thin film (6 to 10 nm) is made uniform, and the surface of the gate insulating film is planarized to improve interface characteristics and reduce leakage current and improve the subthreshold coefficient. I am trying.

In Patent Document 2, an oxide semiconductor film having a carrier concentration of about 1 × 10 ¹⁸ cm ⁻³ is manufactured by sputtering an oxide sintered body in which gallium is solid-solved in indium oxide.

  Further, in Patent Document 3, in the bottom gate type TFT, the on-off ratio is increased by increasing the oxygen density of the surface layer of the oxide semiconductor as compared to the gate insulating film side by performing oxygen-containing plasma irradiation. There is.

  Patent Document 4 discloses an oxide TFT having a two-layered active layer composed of indium zinc oxide (or ITO) and GIZO, and it is supposed that high mobility and a preferable threshold voltage can be obtained. Specifically, a two-layer active layer TFT is prepared in which GIZO with a low carrier concentration of 60 nm is provided on an indium zinc oxide (or ITO) layer with a high carrier concentration of 5 nm.

  Patent Document 5 discloses an oxide TFT having two channel layers of In-Ga-Zn-O having different composition ratios as an active layer and a resistive layer, and has high mobility and high on-off ratio. It is supposed to be obtained.

JP 2007-250987 A WO 2010/032422 JP, 2010-258196, A Unexamined-Japanese-Patent No. 2010-21555 JP, 2009-212497, A

The techniques of the above patent documents have the following problems.
In Patent Document 1, since the film thickness of the channel layer is as thin as 10 nm or less, the channel layer may be formed in an island shape, and a portion in which a semiconductor layer is not formed is likely to be generated in the channel layer.

  In Patent Document 2, regions with different resistances are not provided in the oxide semiconductor layer, and there is room for improvement in the subthreshold coefficient.

  In Patent Document 3, the on-off ratio is improved by providing a high oxygen densification region in the semiconductor layer by oxygen plasma treatment, but high mobility is not obtained.

  In patent document 4, since the channel layer of 2 layer structure is required, there existed a problem in productivity or manufacturing cost compared with the case where a channel layer is produced with a single material.

  There is room for improvement in the mobility obtained in Patent Document 5, and when producing a channel layer having a two-layer structure, two types of targets and / or two oxygen introduction amounts are required at the time of producing the channel layer. become. This is problematic in terms of productivity and manufacturing cost as compared with the case where the channel layer is made of a single material.

  An object of the present invention is to provide a thin film transistor having a high on-off ratio while having high mobility in view of the above problems. Another object of the present invention is to provide a thin film transistor which can be manufactured efficiently.

According to the first embodiment of the present invention, it has a source electrode and a drain electrode, a gate electrode, a gate insulating film, a protective insulating film, and a channel layer, and the channel layer is protected with the gate insulating film. A thin film transistor is provided, which is located between insulating films and has a region with a low spreading resistance value and a region with a wide spreading resistance value.
According to Embodiment 2 of the present invention, it has a source electrode and a drain electrode, a gate electrode, a gate insulating film, an insulating substrate, and a channel layer, and the channel layer is isolated from the gate insulating film. A thin film transistor is provided, which is located between a conductive substrate and has a region of low spreading resistance and a region of high spreading resistance.
Further, according to another aspect of the present invention, there is provided a step of forming a channel layer on a gate insulating film, a step of forming the protective insulating film in contact with the channel layer, and
And heat-treating at 150 to 500 ° C. after the formation of the protective insulating film.
Further, according to another aspect of the present invention, there is provided a process of forming a channel layer on an insulating substrate, hydrogen plasma treatment, reverse sputtering in a rare gas atmosphere, electron beam irradiation, and the like to the channel layer. Providing a process for producing a thin film transistor, comprising the step of performing one or more treatments selected from ultraviolet radiation.

  The present invention can provide a thin film transistor having a high on-off ratio while having high mobility. In addition, a thin film transistor that can be efficiently manufactured with a single oxide semiconductor material can be provided.

It is a schematic sectional drawing which shows the example of the bottom gate type thin-film transistor of Embodiment 1 of this invention. It is a SSRM image of the thin-film transistor produced in Example 1. FIG. 6 is an SSRM spectrum of the thin film transistor produced in Example 1. FIG. It is a SSRM image of the thin-film transistor produced by the comparative example 6. FIG. It is a SSRM spectrum of the thin-film transistor produced by the comparative example 6. FIG. It is a transfer curve of the thin-film transistor produced by Example 1 and Comparative Example 6. It is a measurement result of the mobility of the thin-film transistor produced by Example 1 and Comparative Example 6. It is the result of measuring the relationship of Hall mobility and carrier concentration at the time of annealing-processing, after forming an oxygen permeable insulating film into a film in an oxide semiconductor film. It is the result of measuring the relationship between annealing time, Hall mobility, and carrier concentration in the case of annealing treatment only in the state of an oxide semiconductor film. It is a transfer curve of the thin-film transistor produced in parallel, performing the process similar to FIG. 8 or 9. FIG. It is a figure regarding the annealing time dependence of TFT characteristic at the time of thickening a protective insulation layer (oxygen permeable insulation film). It is a schematic sectional drawing which shows the example of the top gate positive stagger thin film transistor which is Embodiment 2 of this invention. FIG. 2 is a schematic cross-sectional view of a bottom gate (reverse staggered) thin film transistor manufactured in Example 1; It is a figure which shows the result of having measured the thin film transistor manufactured in Example 1 by XPS. It is a figure which shows the result of having measured the thin film transistor manufactured in Example 1 by XPS. FIG. 2 is a schematic cross-sectional view of a double gate thin film transistor manufactured in a reference example 1; FIG. 5 is a diagram showing performance characteristics of a double gate thin film transistor manufactured by forming a channel layer in the same manner as FIG. 4; FIG. 3 is a view showing performance characteristics of a double gate thin film transistor manufactured by forming a channel layer in the same manner as FIG. 2; FIG. 7 is a schematic cross-sectional view of an etch stopper bottom gate inverted staggered thin film transistor manufactured in Reference Example 2; It is a figure which shows the relationship between the annealing time and a transfer curve of the thin-film transistor which made thickness of a protective insulating film 0 nm. It is a figure which shows the relationship of the annealing time and a transfer curve of the thin-film transistor which set thickness of the protective insulating film to 5 nm. It is a figure which shows the relationship between the annealing time and a transfer curve of the thin-film transistor which set thickness of the protective insulating film to 10 nm. It is a figure which shows the relationship between the annealing time and a transfer curve of the thin-film transistor which set the thickness of the protective insulating film to 20 nm. It is a figure which shows the relationship of the annealing time and a transfer curve of the thin-film transistor which set thickness of the protective insulating film to 50 nm. It is a figure which shows the relationship of the annealing time and mobility of the thin-film transistor which set thickness of the protective insulating film to 0 nm. It is a figure which shows the relationship of the annealing time and mobility of the thin-film transistor which made thickness of a protective insulating film 5 nm. It is a figure which shows the relationship between the annealing time and mobility of the thin-film transistor which set thickness of the protective insulating film to 10 nm. It is a figure which shows the annealing time and the relationship of mobility of the thin-film transistor which set the thickness of the protective insulating film to 20 nm. It is a figure which shows the annealing time and the relationship of mobility of the thin-film transistor which set thickness of the protective insulating film to 50 nm.

  Hereinafter, embodiments of the present invention will be described in detail. However, this invention is not limited to the following embodiment, The form and detail can be changed variously.

Embodiment 1
The thin film transistor according to this embodiment includes a source electrode and a drain electrode, a gate electrode, a gate insulating film, a protective insulating film, and a channel layer. The channel layer is located between the gate insulating film and the protective insulating film, and has a region with a low spread resistance value and a region with a high spread resistance value. When the channel layer has a region having a low spreading resistance value and a region having a wide spreading resistance value, a thin film transistor having high field effect mobility and high on-off ratio can be obtained.

FIG. 1 is a schematic cross-sectional view showing an example of a bottom gate inverted staggered thin film transistor according to an embodiment of the present invention.
In the thin film transistor 1, a gate electrode 20, a source electrode 50 and a drain electrode 60 are formed on a substrate 10. The gate insulating film 30 is formed in contact with the gate electrode 20. A source electrode 50 and a drain electrode 60 are formed on the gate insulating film 30, and a channel layer 40 is formed between the source electrode 50 and the drain electrode 60. The channel layer 40 is in contact with the gate insulating film 30. A protective insulating film layer 70 is formed to cover the source electrode 50, the drain electrode 60, and the channel layer 40. The channel layer 40 is between the gate insulating film 30 and the protective insulating film layer 70 and in contact with these layers.

  Here, the channel layer is a region of the semiconductor facing the gate electrode and in contact with the gate insulating film, which is a region sandwiched between the source electrode and the drain electrode, and has a semiconductor film thickness. More specifically, the range of the region is defined by the film thickness of the semiconductor film, the channel length (the distance between the source electrode and the drain electrode), and the channel width (the width of the source electrode and the drain electrode).

Further, there is a region (low resistance region) 42 with low spreading resistance of the channel layer 40 on the gate insulating film side of the channel layer 40, and a region (high resistance region) with high spreading resistance on the side facing the gate insulating film. There are 44).
The low spreading resistance region 42 is a band-like region having a thickness of 10 nm or more in the vicinity of the gate insulating film 30, preferably inward from the surface of the channel layer 40 on the gate insulating film 30 side.
The region 44 with high spreading resistance is a band-like region having a thickness of 10 nm or more in the vicinity of the protective insulating film 70, preferably from the surface of the channel layer 40 on the protective insulating film 70 side.

  In the present application, the magnitude of the spreading resistance is obtained from a scanning spread resistance microscope (SSRM) measurement after cutting out a cross section including the channel layer. The SSRM measurement (SSRM spectrum) in the Y-axis (vertical) direction of the cross section is preferably scanned so as to sequentially cross the gate electrode 20, the gate insulating film 30, the channel layer 40 and the protective insulating film 70. It is further preferred to scan as. In addition, a two-dimensional SSRM image can be acquired by sequentially expanding the SSRM measurement in the Y-axis direction of the cross section in the X-axis (horizontal) direction. In addition, the film thickness of the gate insulating film 30, the channel layer 40, and the protective insulating film 70 are measured from a cross-sectional TEM image including the channel layer using a transmission electron microscope (TEM), and the spread is obtained by comparing with the SSRM image. The positional relationship between the high resistance area and the low expansion resistance area can be determined. From the measurement principle, the spread resistance changes its absolute value largely depending on the material of the probe, the shape of the sample, the surface condition of the measurement, etc.

  The low spreading resistance region can be determined from the SSRM spectrum shape of the channel portion and the threshold resistance of the SSRM image. First, the region and region edge where the spreading resistance is lower than the SSRM spectrum shape are determined. When focusing on the SSRM spectrum of an arbitrary channel portion, if the local minimum is one spectrum, the spectrum width is defined as a region having a wide spread resistance. However, if there is a shoulder or plateau where the change in spread resistance is within one digit over a region of 10 nm or more in the spectrum, the residual square sum should be minimized using a Gaussian function with the minimum value as the reference peak. Fitting is performed as follows (the high resistance region including the shoulder and the plateau is excluded from the fitting range), and the region width is defined after peak separation. Incidentally, the shoulder or plateau is limited to one having a spread resistance value which is one digit or more higher than the spread resistance minimum value. Here, the spectrum width is a distance between two points having a maximum resistance value which has a peak and a resistance value lower by two digits or more compared to the average spreading resistance value of the gate insulating film, and the two points are the end of the region. . The average spreading resistance value of the gate insulating film is defined as the maximum distributed resistance value of the portion corresponding to the gate insulating film of the SSRM image.

In the case of an SSRM spectrum including two or more local minimums, peak separation is performed using each local minimum as a reference peak and using a Gaussian function such that the residual sum of squares is minimized. The spectrum having the peak with the lowest resistance value is taken as a low-resistance region, and the region width and region edge are defined as described above. However, if the ratio of peak resistance values of adjacent spectra is within one digit or if the peak width is less than 10 nm after peak separation, it is not considered as a peak separation target.
Next, each SSRM spectrum is expanded in the cross-sectional X-axis direction, and in the SSRM image, a low spreading resistance region is defined in the plane. Acquire the resistance value of the low-resistance region end (gate insulating film side) in a representative SSRM spectrum (preferably at least 5 randomly obtained SSRM spectra, more preferably 10 or more, still more preferably 20 or more), The region within the threshold resistance value is plotted in the SSRM image with the minimum and maximum resistance values in that resistance range as the threshold resistance. At this time, although the plots are arranged along the interface between the gate insulating film and the channel layer, it is possible to widen the threshold resistance value so that the plots are continuously arranged at both ends in the X axis direction of the SSRM image (however, Expandable within one digit of both threshold resistors). After adjusting the threshold range so that the plots are continuously arranged in the X axis direction of the SSRM image by 50% or more, a perpendicular line is drawn from the gate metal-gate insulating film interface and the distance at which the plot first intersects the gate insulating film width Do. When the gate insulating film width is expanded in the X-axis direction, the peak value of the histogram is defined as the average gate insulating film width. Here, in obtaining the histogram, data of 50% or more of the number of pixels constituting the X axis of the SSRM image is used as a population, and each insulating film width is allocated to a range divided into equally spaced sections, and the central value of the sections Let's represent that section with Further, the number of interval ranges at equal intervals is twenty. That is, the gate insulating film thickness obtained by TEM is divided into 20 parts. If the average gate insulating film width is comparable (± 10%) to the gate insulating film thickness (TEM image) as compared with the TEM image, it can be said that the region having a low spreading resistance is in contact with the gate insulating film. Further, the same processing can be performed on the end of the low resistance region (the protective insulating film side), and the width of the low resistance region can be defined.

  The region of high spreading resistance is determined corresponding to the region of low spreading resistance in the channel layer described above. For example, if the channel film thickness is measured to be 50 nm from the cross-sectional TEM, and the region having a low spreading resistance is measured to be 50 nm, the region having a high spreading resistance does not exist. For example, if the channel film thickness is measured to be 50 nm from the cross-sectional TEM, the area with low spreading resistance is measured to be 30 nm, and the second lowest spreading resistance area is not observed from the SSRM spectrum, the remaining 20 nm area is broadened. It becomes an area with high resistance. At this time, the region where the spreading resistance is high may be biased to the protective layer side, or the region where the spreading resistance is low by 10 nm may be present on the protective layer side and the gate insulating film side. However, when the film thickness is less than 10 nm, it is difficult to identify due to the influence of measurement error, so it can not be recognized as a region with high spreading resistance. For example, if the channel film thickness is measured to be 50 nm from the cross-sectional TEM, the area with low spreading resistance is measured to be 30 nm, and if the second lowest spreading resistance area is observed to be 20 nm from the SSRM spectrum, the area with high spreading resistance is It is the second lowest spreading resistance area. For example, if the channel film thickness is measured to be 50 nm from the cross-sectional TEM, the area with low spreading resistance is measured to be 30 nm, and if the second lowest spreading resistance area is observed to be 10 nm from the SSRM spectrum, the area with high spreading resistance is It becomes the remaining 10 nm region. However, at this time, it can be defined as a region having high spreading resistance when it has a thickness of 10 nm or more.

  The region with low spreading resistance is preferably in contact with the gate insulating film and has a thickness of 10 nm or more. On the other hand, it is desirable that a region having a high spreading resistance be present, and in particular, a region having a resistance value equal to that of the insulating film be present over 10 nm or more of the protective insulating film interface. Here, “equivalent” means that the ratio (R / R0) of the resistance value (R) in the region where the spreading resistance value is high to the average resistance value (R0) of the gate insulating film is 0.1 <R / R0 <1. means. When the channel layer is formed only in a region having a wide spread resistance, it is difficult to simultaneously achieve high on-off ratio and mobility. In addition, when the region having a low spreading resistance is not in contact with the gate insulating film, the main gate electric field is applied to the region having a high resistance value in the channel layer, and therefore, an increase in mobility can not be expected. In addition, since a region having a high spreading resistance equivalent to the insulating film is in contact with the protective insulating film side, electron injection and the like to the protective insulating film are alleviated, so that excellent characteristics in terms of reliability can be expected. .

Examples of SSRM images are shown in FIGS. 2 and 4, and examples of SSRM spectra are shown in FIGS.
2 and 3 show the measurement results of the thin film transistor manufactured in Example 1 described later. FIG.4 and FIG.5 is a measurement result of the thin-film transistor produced by the comparative example 6 mentioned later.
In the SSRM images of FIGS. 2 and 4, it can be seen that the metal of the gate electrode (gate metal), the gate insulating film, the oxide semiconductor layer (channel layer), and the protective insulating film are stacked in this order from the bottom. The shading of the color of the SSRM image represents the magnitude of the spreading resistance. The darker the color, the higher the spreading resistance. It can be seen that although the layer configurations and thicknesses of Example 1 and Comparative Example 6 are the same, the shades of color of the channel layer and the periphery thereof are different. This is because, in the channel layer of the first embodiment, there are areas of high spreading resistance and low areas of the spreading resistance, so the thickness of the light-colored portion is thin. On the other hand, in the channel layer of Comparative Example 6, only the region having a low spreading resistance is present, so the thickness of the light-colored portion is large.

  It is confirmed from the TEM photograph of the cross section that the thin film transistor to be measured has an oxide semiconductor layer of 50 nm ± 5 nm and a gate insulating layer of 90 nm ± 5 nm. From the SSRM spectrum of FIG. 5, oxidation is performed at a position of 90 nm (indicated by a broken line between C and D in the drawing) from the gate metal layer-gate insulating film interface (represented by a broken line between D and E in the drawing). It can be seen that the object semiconductor layer-gate insulating film interface (the end of the region where the spreading resistance is low) is located. On the other hand, according to the SSRM spectrum in FIG. 3, the oxide semiconductor layer-gate insulating film interface (region end with low spreading resistance) is located at a position of 81 nm (represented by a broken line between C and D in the figure). I understand that

  In addition, a region lower in resistance than an insulating film located in an oxide semiconductor region (a region located in a range of 85 to 140 nm from the gate metal-gate insulating film interface as an oxide semiconductor region in mutual comparison with TEM) Is 23 nm in FIG. 3 (area C in the figure) and 50 nm in FIG. 5 (area C in the figure). From both SSRM spectra and TEM images, it can be seen that the gate insulating film side interface in the region where the spreading resistance is low is in contact with the gate insulating film (region C in the figure), and both SSRMs in the oxide semiconductor layer Since the extremum can be regarded as a single spectrum from the spectrum, the spread resistance high region in FIG. 5 does not exist in the oxide semiconductor layer, while the spread resistance high region in FIG. 3 is in the oxide semiconductor layer. 27 nm (area B in the figure) is present on the side.

Further, in FIG. 3, a region (region C in FIG. 3) having a spread and low resistance is in contact with the gate insulating film (region D in FIG. 3), and extends to the protective insulating film (region A in FIG. The high area (area B in the figure) is in contact.
As described above, even if the SSRM spectrum is expanded to the SSRM image, it can be seen that the region with high spreading resistance does not exist in FIG. 5, and only the region with low spreading resistance is formed. On the other hand, FIG. 3 shows that the region having a spread resistance and low resistance is in contact with the gate insulating film, and the region having a spread resistance and high resistance is in contact with the protective insulating film side.

The transfer curves of the thin film transistors produced in Example 1 and Comparative Example 6 are shown in FIG. 6, and the measurement results of mobility are shown in FIG.
From this result, it is understood that the thin film transistor having the structure of this embodiment has high mobility and the on-off ratio is improved.

  In the present embodiment, the thickness of the channel layer is usually 20 to 200 nm, preferably 30 to 100 nm, more preferably 40 to 80 nm, and still more preferably 45 to 70 nm. If the film thickness of the channel layer is 20 nm or more, the film thickness when forming a film on a large area becomes uniform, and the characteristics of the produced TFT become uniform in the plane, which is preferable. On the other hand, if the film thickness is 200 nm or less, it is preferable because the film formation time is suitable for industrial production.

The channel layer preferably comprises an oxide semiconductor of substantially single composition.
Here, substantially single means that there is only one sputtering target or solution used in producing the channel layer. In addition, except for the metal element forming the insulating film and the electrode in contact with the channel layer, the composition ratio of the metal element contained in the channel layer is equal to or greater than 80% in the film thickness direction, further 85% or more Preferably, 90% or more is the same. Here, the composition ratio of the metal element in the film thickness direction can be identified by depth resolution XPS or SIMS. However, since the component ratio of the metal element contained in the channel layer in the vicinity of the insulating film interface is difficult to identify, in this region, the spectral intensity of the metal element of interest is from the bulk direction of the channel layer to the insulating film direction The component ratio is considered to be the same if it is smoothly attenuated toward the end.

  The material forming the channel layer applicable to the present invention may be a crystalline material or an amorphous material. In addition, an amorphous portion may be present in the channel layer formed of a crystalline layer, or a crystalline portion may be present in the channel layer formed of an amorphous layer. The crystal is regarded as a crystal if the periodic structure can be confirmed by TEM observation as the judgment of whether it is a crystal or not.

As a typical example of a crystal-based material, for example, indium oxide, Ga-doped indium oxide, Al-doped indium oxide, Ga and Al-doped indium oxide, Zn-doped indium oxide, or Sn-doped indium oxide Can be mentioned. In addition, the third element is at least one metal element selected from Sn, Ga, Hf, Zr, Ti, Al, Mg, Ge, Sm, Nd, and La, which contains In, Zn, and a third element. There is a certain material.
The material for forming the channel layer is selected from indium oxide, Ga-doped indium oxide, Al-doped indium oxide, Ga and Al-doped indium oxide, Zn-doped indium oxide and Sn-doped indium oxide It is preferable because a thin film transistor having a high on-off ratio can be obtained while having a high mobility.

As a representative example of the amorphous material, for example, Sn-In-Zn oxide, In-Zn-Ga-Mg oxide, In oxide, In-Sn oxide, In-Ga oxide, In-Zn oxide, Zn-Ga oxide, Sn-In-Zn oxide, In-Sn-Zn-Al oxide, In-Sn-Zn-Mg oxide, In-Ga-Zn-Al oxide, and the like. The composition ratio of the constituent metal atoms does not necessarily have to be 1. In addition, although Zn and Sn may not easily form an amorphous state by itself, the inclusion of In facilitates the formation of an amorphous phase. For example, in the case of an In—Zn-based material, it is preferable that the proportion of the number of atoms excluding oxygen be such that In is contained at about 20 atomic% or more. In the case of the Sn-In system, the composition may be such that the proportion of the number of atoms excluding oxygen is about 80 atomic% or more of In. In the case of the Sn-In-Zn system, the atomic number ratio excluding oxygen may be a composition in which In is contained at about 15 atomic% or more.
In addition, the third element is at least one metal element selected from Sn, Ga, Hf, Zr, Ti, Al, Mg, Ge, Sm, Nd, and La, which contains In, Zn, and a third element. There is a certain material.
Although it has a feature that it is easy to form an amorphous layer, a crystalline layer appears by annealing treatment or laser irradiation at high temperature.

The material for forming the gate insulating film is not particularly limited, and any commonly used material can be selected. As a material of the gate insulating film, for example _{SiO 2, SiNx, SiONx, Al} 2 O 3, Ta 2 O 5, TiO 2, MgO, ZrO 2, CeO 2, K 2 O, Li 2 O, Na 2 O, Rb _{2 O,} may be used _{Sc 2 O 3, Y 2 O} 3, Hf 2 O 3, CaHfO 3, PbTiO 3, BaTa 2 O 6, SrTiO 3, compounds such as AlN. Among these, preferred are SiO ₂ , SiNx, Al ₂ O ₃ , Y ₂ O ₃ , HfO ₃ and CaHfO ₃ , and more preferred are SiO ₂ , SiNx, Y ₂ O ₃ , HfO ₃ and CaHfO ₃ . . The number of oxygen in the above oxide may not necessarily coincide with the stoichiometric ratio (for example, it may be SiO ₂ or SiO x).

There is no restriction | limiting in particular in the material which forms each electrode of a drain electrode, a source electrode, and a gate electrode, The material generally used can be selected arbitrarily. For example, transparent electrodes of ITO, indium zinc oxide, ZnO, SnO ₂ etc., metal electrodes of Al, Ag, Cu, Cr, Ni, Mo, Au, Ti, W, Ta etc., or metal electrodes of alloys containing these. Can be used. In addition, each of the drain electrode, the source electrode, and the gate electrode may have a multilayer structure in which two or more different conductive layers are stacked. In particular, since a source / drain electrode is strongly required to have a low resistance wiring, a good conductor such as Al or Cu may be sandwiched by a metal having excellent adhesion such as Ti or Mo.

In the present embodiment, as shown in the examples, a material that doubles as the substrate and the gate electrode may be used, but the substrate and the electrode may be different materials. In this case, an insulating substrate is preferred. As such a substrate, for example, a glass substrate represented by a non-alkali glass substrate produced by a fusion method or a float method such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass, ceramic substrate, etc. And a plastic substrate having heat resistance that can withstand the processing temperature of the present manufacturing process. In addition, a substrate provided with an insulating film on the surface of a metal substrate such as stainless alloy may be applied. When the substrate is a mother glass, the size of the substrate is the first generation (320 mm × 400 mm), the second generation (400 mm × 500 mm), the third generation (550 mm × 650 mm), the fourth generation (680 mm × 880 mm, or 730 mm) × 920 mm), 5th generation (1000 mm × 1200 mm or 1100 mm × 1250 mm), 6th generation 1500 mm × 1800 mm, 7th generation (1900 mm × 2200 mm), 8th generation (2160 mm × 2460 mm), 9th generation (2400 mm × 2800 mm) 2450 mm × 3050 mm), the tenth generation (2950 mm × 3400 mm), and the like can be used. Alternatively, an insulating film may be formed on the substrate as a base film. As the base film, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film is formed as a single layer or a stack using a CVD method, a sputtering method, or the like.
Furthermore, the silicon substrate with a thermal oxide film can be regarded as a substrate with a gate insulating film and a gate electrode, in which the gate insulating film is a thermal oxide film and the gate electrode is silicon.

In the transfer characteristics of the thin film transistor, the main conduction path of carriers is in the vicinity of the gate insulating film interface; thus, the mobility and the on-off ratio are largely affected by the state of the oxide semiconductor region in that portion. In the present embodiment, since the region having a low spreading resistance is formed in the vicinity of the gate insulating film, the maximum current value obtained when the on operation is performed becomes large. Also, the fact that the spreading resistance value is low indicates that the product of mobility and carrier concentration is high, and Wager et. al. "Transparent Electronics" Springer, New York, p. 129 describes that oxide semiconductors with high carrier concentration generally have high mobility, and the mobility of thin film transistors derived from this transfer characteristic is also described. It is expected to be higher. The mobility of the thin film transistor of the present invention is preferably 40 cm ² / Vs or more, more preferably 80 cm ² / Vs or more.

On the other hand, in the thin film transistor of this embodiment, the conductivity on the protective insulating film side (back channel side) is lower than that in the vicinity of the gate insulating film because the spreading resistance is relatively high. Therefore, when the gate electrode is applied to the negative side, the conduction on the back channel side where electrons are easily accumulated is suppressed, and a transistor with low off current can be obtained.
For these reasons, the thin film transistor of this embodiment has high mobility and high on-off ratio. The on-off ratio of the thin film transistor of this embodiment is preferably 1 × 10 ⁶ or more, more preferably 1 × 10 ⁷ or more, and still more preferably 1 × 10 ⁸ or more.

  Next, the subthreshold coefficient (S value) is a coefficient that correlates with the rising degree of the on state from the off state of the transfer characteristic, and means that the lower the value, the steeper the rising. In addition, when the gate voltage is swept from the negative side to the positive side, the induced electrons near the surface of the insulating layer utilize the localized acceptor-like level in the band gap or the interface state of the oxide semiconductor-insulating film surface. It is known that by contributing to conduction, the rising of the transfer curve becomes dull and a good subthreshold coefficient can not be obtained.

  If a highly conductive layer is formed in contact with (or in the vicinity of) the surface of the gate insulating film, such levels are occupied more quickly, so that a good subthreshold coefficient can be obtained. Further, as described above, since the current value in the off region is also reduced, it can be considered that the subthreshold coefficient is advantageously acted accordingly.

  It is generally known that carriers present in an oxide semiconductor are derived from oxygen deficiency. The high spread resistance value on the back channel side (the side not in contact with the gate insulating film) of the oxide semiconductor layer means that the oxygen deficiency on the back channel side is small.

  Here, the stability of the thin film transistor performance against bias stress and light irradiation is interpreted to have a correlation with the amount of oxygen deficiency present on the gate insulating film (front channel) side or the back channel side, so the spread resistance on the back channel side By forming the region having a high value, a thin film transistor having high reliability which is excellent in bias stress resistance and light stability can be obtained. Also, the region where the spreading resistance value on the back channel side is high is equivalent to the insulating film or a resistance value according to the insulating film, that is, the region where the spreading resistance value is high is the difference between the spreading resistance value of the insulating film and the resistance If so, it is possible to obtain a thin film transistor having high reliability which is further excellent in bias stress resistance and light stability.

  Since an oxide semiconductor layer having a low spreading resistance region generally has a high carrier concentration, it has an effect of reducing a potential barrier existing in crystal grains or between crystal grains, as described in J. Appl. Phys. , Vol. 94, p 7768 (2003). For this reason, it is possible to reduce variations in the in-plane characteristics caused by the barrier, and it is possible to produce a thin film having in-plane uniformity from the viewpoint of the TFT characteristics. Furthermore, the use of an amorphous semiconductor for the semiconductor layer is effective in reducing variations.

  In addition, since the channel layer of the present embodiment has substantially the same composition, a film having a spread resistance to the film thickness can be produced from a single sputtering target or solution, which is excellent in productivity and cost. ing.

  The thin film transistor of the present embodiment can be disposed on a substrate and used as a thin film transistor substrate, and can also be used in an image display device.

The channel layer of the thin film transistor of the present embodiment can be manufactured by a method including the following steps (1) to (3).
(1) Step of depositing an oxide semiconductor layer by sputtering a single metal oxide target in a rare gas atmosphere containing water or hydrogen (2) at least a rare gas atom, an oxygen molecule, and a hydrogen molecule Step of sputtering a single metal oxide target in a gas atmosphere containing oxygen to form an oxide semiconductor layer (3) a single metal oxide target is a rare gas atom, a rare gas atom And sputtering the oxide semiconductor layer in a gas atmosphere containing oxygen molecules, and reducing the deposited layer.

As the reduction treatment in the step (3), vacuum annealing, hydrogen plasma treatment, ultraviolet irradiation, and water vapor annealing are preferable. Particularly preferred is water vapor annealing. The steam annealing is preferably performed under conditions of a pressure of 1 to 3 MPa and a temperature of 150 ° C. to 500 ° C. This treatment can increase the carrier concentration of the thin film, so that a channel layer having a carrier concentration higher than that of the oxide semiconductor film even if the carrier concentration immediately after the oxide semiconductor film is less than 1 × 10 ¹⁸ / cm ³ can be obtained. Can.

By using the film forming method of the step (1), hydrogen ions and hydrogen radicals are generated in plasma, so that a reduction action occurs and the carrier concentration of the obtained semiconductor thin film becomes high. In addition, since it is possible to suppress oxygen ions colliding with the substrate at high speed from within the target during film formation, a semiconductor thin film of good quality can be formed, and the carrier concentration after heating is 10 ¹⁵ to 10 ²² / cm ³ depending on the annealing time. The region of 1 × 10 ^{18 to} 5 × 10 ²¹ / cm ³ can be stably produced.

The partial pressure ratio of water molecules to noble gas atoms is represented by [H ₂ O] / ([H ₂ O] + [dilute gas atoms]). [H ₂ O] is the partial pressure of water molecules in the gas atmosphere, and [rare gas atom] is the partial pressure of rare gas atoms in the gas atmosphere. The partial pressure ratio is preferably 0.1 to 10%, more preferably 0.5 to 7.0%, still more preferably 1.0 to 5.0%, particularly preferably 1.0 to 3.0%. . When the content of water molecules is less than 0.1% in partial pressure ratio to the rare gas atom, the generation suppressing effect of hydrogen ions and hydrogen radicals in plasma can not be obtained, and the carrier concentration in the film before heating is lowered. As a result, there is a possibility that a channel layer containing a desired carrier concentration can not be obtained after heat treatment after film formation of the protective layer. On the other hand, when the content of water molecules is more than 10% in partial pressure ratio to the rare gas atoms, water escapes from the thin film at the time of heat treatment, so that the film density of the oxide semiconductor film decreases and Mobility may be reduced. The rare gas atom is not particularly limited, but is preferably an argon atom. Further, in addition to the rare gas and the water, oxygen and nitrogen may be contained in the range which does not affect the TFT element.

  The channel layer may be formed by the step (2) instead of the step (1). In the step (2), the gas atmosphere during sputtering preferably contains a hydrogen atom at a molar ratio of 2 times or more with respect to the oxygen atom. By doing so, the same effect as that in which water is introduced into the gaseous atmosphere can be obtained.

  The channel layer may be formed by step (3) instead of the above step (1) or (2). When the reduction process is not performed on the channel layer according to the steps (1) to (3), the reduction process can be performed through the process of forming the oxygen-permeable insulating film in contact with the channel layer by CVD or sputtering. For example, in the case of forming an oxygen-permeable insulating film by sputtering, by adjusting the output and the sputtering pressure, implantation of the insulating film into the channel layer occurs to generate oxygen vacancies. As a result, the carrier concentration in the channel layer is increased to cause reduction. In the case of forming an oxygen-permeable insulating film by CVD, it is possible to reduce the channel layer by adjusting the substrate temperature and the introduction ratio by using an introduced gas containing hydrogen.

  Subsequent to the process of (1), (2) or (3), the heat treatment after the formation of the protective insulating film spreads in the channel layer to be in contact with the gate insulating film and spreads the low resistance region in contact with the protective insulating film It is possible to adjust the high resistance region.

Specifically, the thin film transistor of the present embodiment can be manufactured, for example, as follows.
First, a metal film to be a gate electrode is formed on an insulating substrate, and the metal film is patterned to form a gate electrode, and then a gate insulating film covering the gate electrode is formed on the insulating substrate. .

Next, an oxide semiconductor film to be a channel layer is formed over the gate insulating film.
In forming the oxide semiconductor film, it is preferable to sputter a target formed of a metal oxide in a rare gas atmosphere containing water or hydrogen. The thin film formed by this operation is characterized in that the bond with oxygen is suppressed and the carrier concentration is high.

Next, the oxide semiconductor film is patterned into a desired shape to form a channel layer.
Next, a source / drain film is formed over the channel layer, and the source / drain film is patterned to form a source / drain electrode (one is a source electrode and the other is a drain electrode).

Next, a protective insulating film is formed so as to cover the source / drain electrodes and to cover the channel layer at the distance between the source / drain electrodes. Here, as a protective insulating film, an insulating film having oxygen permeability (hereinafter, may be abbreviated as an oxygen permeable insulating film) which is in contact with the channel layer is preferable.
As the oxygen permeable insulating film, for example, SiO ₂ , SiON, Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , MgO, ZrO ₂ , CeO ₂ , K ₂ O, Li ₂ O, Na ₂ O, Rb ₂ O Films such as, Sc ₂ O ₃ , Y ₂ O ₃ , Hf ₂ O ₃ , CaHfO ₃ , PbTiO ₃ , BaTa ₂ O ₆ , SrTiO ₃ can be used. Among these, preferred are SiO ₂ , SiON, Al ₂ O ₃ , Y ₂ O ₃ , Hf ₂ O ₃ and CaHfO ₃ , and more preferred are SiO ₂ and Al ₂ O ₃ . The oxygen numbers of these oxides do not necessarily have to match the stoichiometric ratio (for example, they may be SiO ₂ or SiO x). The oxygen permeable insulating film is formed by plasma CVD or sputtering. Preferably, the film is formed by sputtering in a rare gas atmosphere containing oxygen.

  The oxygen-permeable insulating film can be formed before the formation of the source / drain film, as exemplified by the etch stop type.

  Next, heat treatment is performed on the channel layer as necessary. The environment for heat treatment is preferably in the atmosphere, in oxygen, in an oxygen-added nitrogen gas atmosphere, or in an oxygen-added rare gas atmosphere. Further, the heat treatment apparatus is not particularly limited, but a lamp annealer (LA; lamp annealer), a rapid thermal annealer (RTA; rapid thermal annealer), or a laser annealer can be used. By performing this operation, oxygen is supplied from the back channel side to the channel layer through the oxygen permeable insulating film, so that the spreading resistance value is sequentially increased in the film thickness direction from the gate insulating film side.

It is not desirable to go through a process for reducing the carrier concentration in the oxide semiconductor film or the channel layer during the steps from the formation of the oxide semiconductor film to the formation of the oxygen-permeable insulating film. For example, oxygen is rapidly taken into the channel layer by performing atmospheric annealing before forming the oxygen-permeable insulating film, and the carrier concentration of the channel layer is uniformly reduced, so that the high carrier concentration in the vicinity of the gate insulating film interface It is difficult to have a region of
Even when the above process is performed, the channel layer is formed by performing an operation such as reduction annealing in a hydrogen addition inert gas or annealing in a high pressure steam atmosphere before forming an oxygen permeable insulating film. The overall carrier concentration is increased, and a desired channel layer can be obtained by heat treatment after the formation of the oxygen-permeable insulating film. In addition, after heat treatment after the formation of the oxygen-permeable insulating film, an oxygen-permeable insulating film such as SiNx or AlN may be formed.

Regarding the importance of the protective insulating film, after an oxygen-permeable insulating film (SiO ₂ film: 100 nm thick) is formed on an oxide semiconductor film (InGaO: In / In + Ga = 0.072: 50 nm thick),
The results of measuring the relationship between annealing time and Hall mobility and carrier concentration when annealing is performed at 300 ° C. in an air atmosphere and when annealing is performed only in the oxide semiconductor film are shown.
FIG. 8 shows the results of measurement of the relationship between Hall mobility and carrier concentration in the case where an oxygen-permeable insulating film is formed on an oxide semiconductor film and then annealing treatment is performed.
FIG. 9 shows the results of measurement of the relationship between annealing time, Hall mobility, and carrier concentration in the case where annealing is performed only in the oxide semiconductor film.

In FIG. 8, due to the presence of the oxygen permeable insulating film, the carrier concentration gradually changes as the annealing time becomes longer. On the other hand, in FIG. 9, the carrier concentration rapidly decreases and then becomes constant. In the case of FIG. 8, depending on the annealing time, it is observed that the Hall mobility becomes extremely high due to the treatment.
From the above results, it can be understood that the protective insulating layer is important in the present embodiment.

FIG. 10 shows a transfer curve of a thin film transistor fabricated in parallel by performing the same process as that of FIG. 8 or 9, and the annealing process is one hour. In FIG. 10, A is a transfer curve of the thin film transistor manufactured in the case of FIG. 8, that is, in the step of annealing after forming the oxygen-permeable insulating film on the oxide semiconductor film. B is a transfer curve of the thin film transistor manufactured in the case of FIG. 9, that is, the step of annealing in the state of only the oxide semiconductor film. The mobility of the thin film transistor indicated by the line A in FIG. 10 is 126.1 cm ² V ⁻¹ s ⁻¹ , and the mobility of the thin film transistor indicated by the line B is 39.5 cm ² V ⁻¹ s ⁻¹ . It can be seen from FIG. 10 that the measurement results of FIGS. 8 and 9 are also reproduced in the thin film transistor.

  FIG. 11 is a diagram relating to the annealing time dependency of the TFT characteristics when the protective insulating layer (oxygen permeable insulating film) is thickened to 300 nm. It can be seen that the one hour annealing does not match the characteristics of FIG. This indicates that the appropriate annealing time varies depending on the thickness and the nature of the insulating film.

When an oxygen-permeable insulating film is formed on an oxide semiconductor thin film, if the average carrier concentration in the channel is 10 ¹⁸ cm ⁻³ or more, the annealing time and temperature thereafter are adjusted, It has a high spreading resistance region on the protective insulating film side and a low spreading resistance region on the gate insulating film side, and has a mobility of 40 cm ² V ⁻¹ s ⁻¹ or higher, and an on-off ratio of 10 ⁶ It is possible to manufacture a TFT having the above-described good performance. By annealing, oxygen is supplied to the oxide semiconductor thin film through the oxygen permeable insulating film. A spreading resistance gradient occurs in the film thickness direction, the resistance on the protective insulating film side becomes higher, and the resistance on the gate insulating film side becomes lower than that on the protective insulating film side. If the annealing time is too short, the supply of oxygen in the film thickness direction is not sufficient, and although the mobility is high, a film can not be obtained with an on-off ratio. The same is true even if the annealing temperature is too low. Furthermore, when the supply of oxygen is excessively extended to the oxide semiconductor region in the vicinity of the gate insulating film interface because the annealing time is too long, the spreading resistance on the gate insulating film side becomes high, and it becomes difficult to obtain high mobility. The same is true even if the annealing temperature is too high. The appropriate annealing time and temperature vary depending on the semiconductor material to be selected, and also vary depending on the thickness and film quality of the semiconductor and the oxygen permeable insulating film. This is because the way of supplying oxygen from the oxygen permeable insulating film to the semiconductor layer is different. Furthermore, if appropriate conditions are selected, it is possible to obtain a TFT element in which the mobility does not decrease even when annealed for a long time.

Embodiment 2
The thin film transistor according to this embodiment includes a source electrode and a drain electrode, a gate electrode, a gate insulating film, a protective insulating film, an insulating substrate, and a channel layer. The channel layer is located between the gate insulating film and the insulating substrate, and has a region with a low spread resistance value and a region with a high spread resistance value. As in Embodiment 1, when the channel layer has a region with a low spreading resistance value and a region with a wide spreading resistance value, a thin film transistor having a high field-effect mobility and a high on-off ratio can be obtained.

FIG. 12 is a schematic cross-sectional view showing a top gate positive staggered thin film transistor according to an embodiment of the present invention.
In the thin film transistor 2, a source electrode 50 and a drain electrode 60 are formed on an insulating substrate (substrate) 10. A channel layer 40 is formed between the source electrode 50 and the drain electrode 60. A gate insulating film 30 is formed on the substrate 10, the source electrode 50, the drain electrode 60, and the channel layer 40. The channel layer 40 is in contact with the gate insulating film 30. A gate electrode 20 is formed in contact with the gate insulating film 30. The channel layer 40 is between the gate insulating film 30 and the substrate 10, the source electrode 50, and the drain electrode 60 and is in contact with these.

  In the present embodiment, the channel layer has a region 42 with low spreading resistance on the side of the gate insulating film 30, and the region 44 facing the gate insulating film 30 has a region 44 with high spreading resistance.

  The configuration of members such as the channel layer 40 is the same as that of the first embodiment.

The thin film transistor of the present embodiment can be manufactured, for example, as follows.
First, the source electrode and the drain electrode on the insulating substrate are formed.
Subsequently, an oxide semiconductor film to be a channel layer is formed over the insulating substrate and the source and drain electrodes. Here, the oxide semiconductor film is preferably 20 nm or more and substantially uniform. In the case of the top gate structure, it is preferable to sputter a target formed of a metal oxide as a film formation method of the oxide semiconductor film. With respect to the atmosphere at the time of film formation, in addition to water or a rare gas atmosphere containing hydrogen, a rare gas atmosphere containing oxygen can also be selected.

Here, the average carrier concentration of the channel layer is preferably adjusted to 5 × 10 ¹⁹ / cm ³ or less, more preferably 1 × 10 ¹⁸ / cm ³ or less, still more preferably 1 × 10 ¹⁷ / cm ³ or less . When the carrier concentration of the oxide semiconductor film layer after film formation is high, heat treatment is performed in the air, in oxygen, in an oxygen-added nitrogen gas atmosphere, in an oxygen-added rare gas atmosphere, or in an oxygen-added inert gas atmosphere. Is preferred. In addition, when the carrier concentration is not sufficiently reduced by the heat treatment, the average carrier concentration of the channel layer can be adjusted to a desired value by oxygen plasma treatment, N ₂ O plasma treatment, or ozone treatment.

Subsequently, the surface of the oxide semiconductor channel layer is induced on the surface of the channel layer on the substrate by inducing oxygen defects by hydrogen plasma treatment, reverse sputtering in a rare gas atmosphere, electron beam irradiation, or ultraviolet light irradiation. Perform an operation to increase the carrier concentration in the near region. Here, the average carrier concentration in this region is preferably 1 × 10 ^{18 to} 5 × 10 ²¹ / cm ³ , and more preferably 2 × 10 ^{18 to} 5 × 10 ²⁰ / cm ³ . The average carrier concentration of the channel layer is preferably 1 × 10 ^{16 to} 5 × 10 ¹⁹ / cm ³ , and preferably 1 × 10 ^{17 to} 5 × 10 ¹⁹ / cm ³ . For example, the average carrier concentration in the high carrier concentration region is in the range of 1 × 10 ^{18 to} 5 × 10 ²¹ / cm ³ , and the average carrier concentration of the channel layer is in the range of 1 × 10 ^{16 to} 5 × 10 ¹⁹ / cm ³ In the case of the thin film transistor in which the concentration of the former is higher, the field effect mobility of 40 (cm ² / V · s) or more and the on-off ratio of 10 ⁶ can be achieved. Also, for example, the average carrier concentration in the high carrier concentration region is in the range of 3 × 10 ^{18 to} 5 × 10 ²⁰ / cm ³ , and the average carrier concentration of the channel layer is 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . With a thin film transistor in the range, it is possible to achieve field effect mobility of 80 (cm ² / V · s) or more and an on-off ratio of 10 ⁸ .

  Subsequently, a gate insulating film which covers the channel layer, the source electrode, and the drain electrode over the substrate is formed. Further, a gate electrode is formed on the gate insulating film. The gate electrode is located on the channel layer.

Note that it is not preferable to go through a process of changing the carrier concentration in the oxide semiconductor film in the step of forming the gate insulating film. For example, when the gate insulating film is formed by plasma CVD process, hydrogen is diffused into the channel layer when the substrate temperature is high, and the carrier concentration in the channel layer is uniformly increased, and the desired average carrier concentration in the channel layer is obtained. It becomes difficult to get. In addition to the oxygen-permeable insulating film, an oxygen-permeable insulating film such as SiNx or AlN may be formed on the gate insulating film.
When an oxygen-permeable insulating film is selected as the gate insulating film, even if the carrier concentration changes in the step of forming the gate insulating film, if the carrier concentration on the gate insulating film side is high, heating after forming the gate insulating film The carrier concentration of the channel layer is sequentially decreased in the film thickness direction from the gate insulating film side by the treatment, and the average carrier concentration in the oxide semiconductor channel layer present in a region of 5 nm or less from the gate insulating film interface is 1 × 10 ¹⁸ / cm It can be adjusted to a range of ^{3 ~5 × 10 21 / cm 3} .

Example 1
(1) Production of Thin Film Transistor In this example, a bottom gate type (reverse stagger type) TFT shown in FIG. 13 was produced.
First, a channel layer (oxide semiconductor layer) 40 is formed by DC sputtering on a low resistance n-type crystalline silicon substrate (substrate and gate electrode) 20 on which a gate insulating film 30 made of thermal silicon oxide is formed. A 50 nm In-Ga-O oxide semiconductor was deposited. As a target, a polycrystalline sintered body having an InGaO composition (Ga / (In + Ga) = 0.072: atomic ratio) was used. The input DC power at the time of sputtering was 100 W. The atmosphere for film formation was a total pressure of 0.4 Pa, the gas flow ratio was Ar: H ₂ O = 99: 1, and the film formation rate was 8 nm / min. The substrate temperature was 25 ° C. In addition, since a shadow mask is used at the time of deposition, the channel layer is formed in a patterned state.

This substrate is set in a plasma CVD apparatus, the substrate is maintained at 200 ° C., 100 sccm of protection is introduced at a pressure of 110 Pa at a rate of 110 sccm of SiH ₄ at ₂ sccm, N ₂ O at 100 sccm, and N ₂ at 120 sccm. An insulating film 70 was stacked. Next, this substrate was set in a dry etching apparatus, and contact holes for gate electrodes and source / drain electrodes were formed. The contact hole position was adjusted so that the channel length L was 200 μm and the channel width W was 1000 μm. Then, this laminate was set in a sputtering apparatus, and after depositing Mo, it was patterned again by the photolithographic method to form source / drain electrodes 50, 60.
Subsequently, the TFT was manufactured by heating at 300 ° C. for 1 hour in the atmosphere.

(2) Evaluation of TFT With respect to the TFT obtained in (1) above, the TFT characteristics obtained from the transfer curve obtained in the atmosphere are threshold voltage V _th = −0.3 V, field effect mobility μ = 191 (cm ² / V · s), and the on-off ratio (On / Off) = 10 ⁷ . In addition, the Vth shift voltage was 0.2 V after applying a voltage of 20 V to the gate for 10000 seconds at 50 ° C.
The transfer curve was measured using a semiconductor parameter analyzer (Keithley Instrument Co., Ltd. product Keithley 4200).
The field effect mobility was determined from the transfer characteristic when 5 V was applied to the drain voltage. Specifically, a graph of the transfer characteristic Id-Vg was created, the transconductance (Gm) of each Vg was calculated, and the field effect mobility was derived from the equation of the linear region. Gm is represented by ∂ (Id) / ∂ (Vg), and Vg is applied up to -15 to 25 V, and the maximum mobility in that range is defined as the field effect mobility. The field effect mobility was evaluated by this method unless otherwise specified in the present invention. The above Id is the current between the source and drain electrodes, and Vg is the gate voltage when the voltage Vd is applied between the source and drain electrodes.
The threshold voltage was defined as Vg at Id = 10 ^-9 A from the graph of transfer characteristics. Moreover, the on-off ratio determined the ratio [On / Off] by making the value of Id of Vg = -10V into Off current value, and setting the value of Id of Vg = 20V into On current value.

(3) Evaluation of TFT Channel Layer A depth-resolved XPS measurement, a cross-sectional TEM measurement, and an SSRM measurement were performed on the TFT obtained in (1).

(3a) Depth-Resolved XPS Measurement The channel portion was subjected to depth direction analysis by X-ray photoelectron spectroscopy (hereinafter simply referred to as XPS). In this example, the XPS spectrum of In.3d5 / 2, Ga.2p3 / 2, Si.2p was measured while excavating the surface by sputtering using Ar ions at an acceleration voltage of 1 keV.

  Specifically, Quantum 2000 manufactured by ULVAC-PHI, Inc. was used for XPS analysis. As the X-ray source, monochromatized Al Kα rays were used. The pass energy was 29.35 eV.

The drilling was performed from the surface 70 a of the SiO ₂ layer 70 through the channel layer 40 to the gate insulating film side interface 40 a of the channel layer 40 under the condition that the sputtering rate of the SiO ₂ film is 1.7 nm / min. Then, XPS measurement was performed for points every 1.6 nm in the film thickness direction.

From the surface 70 a of the SiO ₂ layer 70 through the oxide semiconductor film 40, the atoms present at the gate insulating film side interface 40 a of the channel layer 40 are found to be oxygen, silicon, indium, gallium from XPS measurement The Although carbon was also observed from the surface 70a, it was excluded because it was adsorption of only the surface. Further, from FIG. 14 in which the ratio of constituent metal atoms is plotted in the film thickness direction, the ratio of silicon which is a constituent metal of the SiO ₂ layer 70 which is a protective layer and indium which is a main metal atom which constitutes the channel layer 40 is The film thickness reversed was defined as the protective layer side interface 40b. Further, the gate insulating film side interface 40a has a film thickness in which the ratio of silicon, which is a constituent metal of the SiO ₂ layer 30 which is a gate insulating film layer, and indium which is a main metal atom that constitutes the channel layer 40 is reversed. The atomic ratio is the peak ratio of the desired peak, for example, In.3d5 / 2, Ga.2p3 / 2, Si2p, O1s, divided by the sensitivity coefficient given by Perkin-Elmer, and the atomic ratio at the surface is determined. And When obtaining the area of the photoelectron peak, the obtained spectral data was subjected to 5-point smoothing by the Savitzky-Golay method to remove the satellite peak of the X-ray source, and then the background was removed by the Shirley method.

  In addition, the atomic ratio of indium and gallium, which are atoms forming the channel layer, was determined at each depth position. As shown in FIG. 14, a plateau was observed between the two interfaces 40a and 40b. Since the ratio of indium and gallium was smoothly attenuated from the channel toward the interface, the composition was regarded as single in the film thickness direction in the interface to plateau region. The indium ratio (In / (In + Ga)) in the plateau region is 0.951 to 0.940 (average value is 0.947), assuming that the plateau region of indium is a region 5 nm or more from the interface (FIG. 15). there were. The ratio of the maximum value to the minimum value to the average value was 1% or less, respectively, so that the composition was regarded as single in the film thickness direction also inside the channel layer. Similarly, the gallium ratio (Ga / (In + Ga)) in the plateau region is 0.060 to 0.047, and the average value is 0, assuming that the plateau region of gallium is a region 5 nm or more from the interface (FIG. 15). It was .053. Since the ratio of the maximum value to the average value and the minimum value was 15% or less, respectively, the composition was regarded as single in the film thickness direction also in the channel layer.

(3b) Cross-Sectional TEM Measurement When a cross section of the channel portion 40 was observed using a transmission electron microscope (TEM), it became clear that the gate insulating film was 90 nm and the oxide semiconductor thin film was 50 nm.

(3c) SSRM Measurement A cross section of the channel portion 40 was obtained by underwater mechanical polishing. Subsequently, the spreading resistance measurement was performed on the cross section by SSRM. The SSRM image shown in FIG. 2 and the SSRM spectrum shown in FIG. 3 were obtained. As described above, it can be seen that the region with low spreading resistance is present at a position of 23 nm from the gate insulating film side interface of the oxide semiconductor layer, and the remaining part is a region with high spreading resistance. Here, the interface between the oxide semiconductor and the gate insulating film obtained from the TEM image is 0 nm, and the thickness of the oxide semiconductor layer is 50 nm. Therefore, when the interface between the oxide semiconductor and the protective insulating film is 50 nm, a region with low spreading resistance Is located at 0 to 23 nm, and the region with high spreading resistance is located at 23 to 50 nm. Further, since the average resistance value of the region where the average gate insulating film resistance and the main spreading resistance are high is within one digit from the SSRM image, the region where the main spreading resistance is high can be regarded as having the same resistance value as the gate insulating film. .

The apparatus used and the measurement conditions are shown below.
-Observation device: Bruker AXS (formerly Veeco) Digital Instruments Division NanoScope IVa AFM Dimension 3100 Stage AFM system + SSRM option-SSRM scanning mode: Contact mode and spread resistance simultaneous measurement-SSRM probe (Tip): Diamond coated silicon cantilever- Sample processing: After preparing a cross section by mechanical polishing, each layer was short-circuited so that a bias voltage could be applied.
・ Measurement environment: Room temperature, in the air

The measurement results and the ratio of the resistance value (R) of the high spreading resistance region to the resistance of the gate insulating film (R0) to the forming material of the channel layer, the position of the high spreading resistance value region and the low spreading resistance value are shown in Table 1 Show.
The case where the ratio (R / R0) of the resistance value (R) of the region where the spreading resistance value is high to the resistance value (R0) of the gate insulating film is 0.1 <R / R0 <1 is ○, and otherwise Was marked x.
In the region of the channel layer, except for Example 12, the interface between the gate insulating film and the channel layer is 0 nm, and the interface between the channel layer and the protective insulating film is 50 nm.
In Example 12, the interface between the gate insulating film and the channel layer is 0 nm, and the interface between the channel layer and the glass substrate is 50 nm.
For the on-off ratio, "1.E + XX" means "1 × 10 ^XX ".

Example 2
As a target, a polycrystalline sintered body having an InGaZnO composition (In: Ga: Zn = 1: 1: 1 (atomic ratio)) was used. The input DC power at the time of sputtering was 100 W. The same process as in Example 1 was performed, except that the atmosphere during film formation was a total pressure of 0.4 Pa, and the gas flow ratio was Ar: O ₂ = 97: 3.
The characteristics obtained are shown in Table 1.

Example 3
As a target, a polycrystalline sintered body having an InGaZnO composition (In: Ga: Zn = 2: 2: 1 atomic ratio) was used. The input DC power at the time of sputtering was 100 W. The same processing as in Example 1 was performed except that the atmosphere during film formation was a total pressure of 0.4 Pa, and the gas flow ratio was Ar: O ₂ = 95: 5.
The characteristics obtained are shown in Table 1.

Example 4
As a target, a polycrystalline sintered body having an InGaZnO composition (In: Ga: Zn = 5: 3: 2 atomic ratio) was used. The input DC power at the time of sputtering was 100 W. The same processing as in Example 1 was performed except that the atmosphere during film formation was a total pressure of 0.4 Pa, and the gas flow ratio was Ar: O ₂ = 90: 10.
The characteristics obtained are shown in Table 1.

Example 5
As a target, a polycrystalline sintered body having an InGaZnO composition (In: Ga: Zn = 5: 1: 4 atomic ratio) was used. The input DC power at the time of sputtering was 100 W. The same processing as in Example 1 was performed except that the atmosphere during film formation was a total pressure of 0.4 Pa, and the gas flow ratio was Ar: O ₂ = 50: 50.
The characteristics obtained are shown in Table 1.

Example 6
As a target, a polycrystalline sintered body having an InGaZnO composition (In: Ga: Zn = 3: 1: 4 atomic ratio) was used. The input DC power at the time of sputtering was 100 W. The same processing as in Example 1 was performed except that the atmosphere during film formation was a total pressure of 0.4 Pa, and the gas flow ratio was Ar: O ₂ = 85: 15.
The characteristics obtained are shown in Table 1.

Example 7
As a target, a polycrystalline sintered body having an InGaZnO composition (In: Ga: Zn = 5: 2: 3 atomic ratio) was used. The input DC power at the time of sputtering was 100 W. The same processing as in Example 1 was performed except that the atmosphere during film formation was a total pressure of 0.4 Pa, and the gas flow ratio was Ar: O2 = 80: 20.
The characteristics obtained are shown in Table 1.

Example 8
As a target, a polycrystalline sintered body having an InSnZnO composition (In: Sn: Zn = 1: 1: 1 atomic ratio) was used. The input DC power at the time of sputtering was 100 W. The same processing as in Example 1 was performed except that the atmosphere during film formation was a total pressure of 0.4 Pa, and the gas flow ratio was Ar: O ₂ = 50: 50.
The characteristics obtained are shown in Table 1.

Example 9
As a target, a polycrystalline sintered body having an InSnZnO composition (In: Sn: Zn = 36.5: 15: 48.5 atomic ratio) was used. The input DC power at the time of sputtering was 100 W. The same processing as in Example 1 was performed except that the atmosphere during film formation was a total pressure of 0.4 Pa, and the gas flow ratio was Ar: O ₂ = 50: 50.
The characteristics obtained are shown in Table 1.

Example 10
As a target, a polycrystalline sintered body having an InSnZnO composition (In: Sn: Zn = 25: 15: 60 atomic ratio) was used. The input DC power at the time of sputtering was 100 W. The same processing as in Example 1 was performed except that the atmosphere during film formation was a total pressure of 0.4 Pa, and the gas flow ratio was Ar: O ₂ = 80: 20.
The characteristics obtained are shown in Table 1.

Example 11
In this example, a bottom gate (reverse staggered) TFT was manufactured by photolithography.
As in Example 1 (1), an oxide semiconductor layer of InGaO composition (Ga / (In + Ga) = 0.072: atomic ratio) is DC-blocked on low resistance n-type crystalline silicon on which a gate insulating film is formed. It formed by the sputtering method.

A resist is applied on the deposited In-Ga-O oxide semiconductor, prebaked at 80 ° C for 15 minutes, UV light with a light intensity of 300 mJ / cm ² is passed through a mask, and then 3 wt. After development was carried out with 100% tetramethylammonium hydroxide, and after washing with pure water, post-baking was carried out at 130 ° C. for 15 minutes to form a resist pattern in a desired channel shape. The In-Ga-O oxide semiconductor film was etched with a mixed acid of phosphoric acid, acetic acid and nitric acid to cut off the island of the semiconductor to form a channel layer.

Subsequently, a resist is applied thereon, prebaked at 80 ° C. for 15 minutes, UV light with a light intensity of 300 mJ / cm ² is irradiated through a mask, and then 3% by weight of tetramethyl ammonium hydroxide Then, development was performed, and after washing with pure water, post-baking was performed at 130 ° C. for 15 minutes to form a resist pattern of the source / drain electrode shape of a desired shape. Thereafter, a molybdenum layer was formed to a thickness of 300 nm on the entire surface, and the resist was peeled off with acetone to fabricate a lift-off device having a channel length of 10 μm and a channel width of 20 μm.

Further, an Al ₂ O ₃ film of 100 nm was deposited thereon as a protective insulating film by sputtering. The input RF power at the time of sputtering was 300 W. The atmosphere for film formation was a total pressure of 0.4 Pa, the gas flow ratio was Ar: O ₂ = 70: 30, the film formation rate was 2 nm / min, and the distance between the target and the substrate (T · S) was 7 cm. The substrate temperature was 25 ° C.
Subsequently, the TFT was manufactured by heating at 300 ° C. for 1 hour in the atmosphere.

The obtained TFT was evaluated in the same manner as in Example 1.
The composition of the oxide semiconductor layer (channel layer) is single in the film thickness direction, the oxide semiconductor layer is a crystalline layer having a continuous structure in the film thickness direction, and the crystalline layer is a bixbite type. It was confirmed to be an oxide showing a crystal structure. The other obtained results are shown in Table 1.

Example 12
In this example, a top gate type (positive stagger type) TFT having a structure shown in FIG. 12 was manufactured.
First, a metal mask was placed on the glass substrate 10, and molybdenum was deposited as source / drain electrodes 50, 60 so that a channel portion with a channel length L of 200 μm could be formed.

Subsequently, using a polycrystalline sintered body having an InGaO composition (Ga / (In + Ga) = 0.072: atomic ratio) as a target, a 50 nm-thick In—Ga— layer is formed as the oxide semiconductor layer 40 by DC sputtering. An O oxide semiconductor layer was deposited using a metal mask so as to cover a channel portion with a channel length L of 200 μm and a channel width W of 1000 μm. The input DC power at the time of sputtering was 100 W. The atmosphere for film formation was a total pressure of 0.4 Pa, the gas flow ratio was Ar: H ₂ O = 99: 1, and the film formation rate was 8 nm / min. The substrate temperature was 25 ° C.

  Here, heating was performed at 300 ° C. for one hour in the air to crystallize the oxide semiconductor layer and reduce carriers. Subsequently, hydrogen plasma treatment was performed on a region near the surface of the channel layer.

Subsequently, the gate insulating film 30 was formed to cover the channel layer 40, the source electrode 50, the drain electrode 60, and the oxide semiconductor film 40. The gate insulating film 30 is a SiO ₂ film was 100nm by sputtering. The input RF power at the time of sputtering was 300 W. The atmosphere for film formation was a total pressure of 0.4 Pa, the gas flow ratio was Ar: O ₂ = 70: 30, the film formation rate was 2 nm / min, and the distance between the target and the substrate (T · S) was 7 cm.

  Further, the gate electrode 20 of molybdenum was formed on the gate insulating film 30. The gate electrode 20 was formed by DC sputtering using a metal mask so as to be located on the channel layer 40.

The obtained TFT was evaluated in the same manner as in Example 1.
The composition of the oxide semiconductor layer 40 is single in the film thickness direction, the oxide semiconductor layer 40 is a crystalline layer having a continuous structure in the film thickness direction, and the crystalline layer has a bixbite crystal structure. It was confirmed to be an oxide showing The other obtained results are shown in Table 1.

Example 13
A non-alkali glass substrate of 4 inches in diameter was prepared, and Mo was deposited to a thickness of 50 nm by sputtering, and then patterned into a gate wiring shape by photolithography. Next, this substrate is set in a plasma CVD apparatus, the substrate is maintained at 350 ° C., SiH ₄ is introduced at ₂ sccm, N ₂ O at 100 sccm, and N ₂ at a pressure of 110 sccm at a pressure of 110 Pa. A 150 nm gate insulating film was obtained.
Next, the glass substrate with a gate insulating film is mounted on a sputtering apparatus, InGaO (Ga / (In + Ga) = 0.072: atomic ratio) is deposited under the same conditions as in Example 1, and a 50 nm channel layer (oxidized (Product semiconductor layer) was deposited. Next, it processed into the channel layer of the semiconductor region by the photolithographic method (channel length L: 20 micrometers, channel width W: 50 micrometers).
Set this substrate to a plasma CVD apparatus again, to hold the substrate to 170 ° C., the SiH ₄ 2 sccm, 100 sccm of _{N 2} O, was introduced at a pressure of 110Pa to _{N 2} at a rate of 120 sccm, a thickness of 50nm A protective insulating film (interlayer insulating film 1) was laminated.
Next, this substrate was set in a dry etching apparatus, and contact holes for gate electrodes and source / drain electrodes were formed. Then, this laminated body was set in a sputtering apparatus, and after depositing Mo, it was patterned again by a photolithographic method to form a source / drain electrode.
Subsequently, the substrate was annealed under the atmosphere at 300 ° C. for 8 hours.
Subsequently, the substrate is set again in the plasma CVD apparatus, the substrate is maintained at 250 ° C., SiH ₄ is introduced at a pressure of 110 sccm at a rate of ₂ sccm, N ₂ O at 100 sccm, and N ₂ at 120 sccm. An interlayer insulating film 2 of 300 nm was laminated. Then, contact holes for source, drain and gate electrodes were formed again by photolithography. Finally, the substrate was annealed in air at 350 ° C. for 1 hour to obtain a TFT.
The obtained TFT was evaluated in the same manner as in Example 1. The composition of the oxide semiconductor layer is single in the film thickness direction, the oxide semiconductor layer is a crystalline layer having a continuous structure in the film thickness direction, and the crystalline layer exhibits a bixbyite crystal structure. It was confirmed to be an oxide. The other obtained results are shown in Table 1.

Example 14
A non-alkali glass substrate of 4 inches in diameter was prepared, and Mo was deposited to a thickness of 50 nm by sputtering, and then patterned into a gate wiring shape by photolithography. Next, this substrate is set in a plasma CVD apparatus, the substrate is maintained at 350 ° C., SiH ₄ is introduced at ₂ sccm, N ₂ O at 100 sccm, and N ₂ at 120 sccm, at a pressure of 110 Pa and a thickness of 150 nm. The gate insulator of
Next, the glass substrate with a gate insulating film is mounted on a sputtering apparatus, InGaO (Ga / (In + Ga) = 0.072: atomic ratio) is deposited under the same conditions as in Example 1, and a 50 nm channel layer (oxidized (Product semiconductor layer) was deposited. Next, it processed into the channel layer of the semiconductor region by the photolithographic method (channel length L: 20 micrometers, channel width W: 50 micrometers).
Subsequently, the substrate was annealed under the atmosphere at 300 ° C. for 1 hour.
The substrate is set again in a plasma CVD apparatus, the substrate is kept at 200 ° C., SiH ₄ is introduced at ₄ sccm, N ₂ O at 100 sccm, and N ₂ at a pressure of 110 sccm at a pressure of 110 Pa. A protective insulating film (interlayer insulating film 1) was laminated. Next, this substrate was set in a dry etching apparatus, and contact holes for gate electrodes and source / drain electrodes were formed. Then, this laminated body was set in a sputtering apparatus, and after depositing Mo, it was patterned again by a photolithographic method to form a source / drain electrode.
Subsequently, the substrate was annealed under the atmosphere at 300 ° C. for 8 hours.
Subsequently, the substrate is set again in the plasma CVD apparatus, the substrate is maintained at 250 ° C., SiH ₄ is introduced at a pressure of 110 sccm at a rate of ₂ sccm, N ₂ O at 100 sccm, and N ₂ at 120 sccm. An interlayer insulating film 2 of 300 nm was laminated. Then, contact holes for source, drain and gate electrodes were formed again by photolithography. Finally, the substrate was annealed in air at 350 ° C. for 1 hour to obtain a TFT.
The obtained TFT was evaluated in the same manner as in Example 1. The composition of the oxide semiconductor layer is single in the film thickness direction, the oxide semiconductor layer is a crystalline layer having a continuous structure in the film thickness direction, and the crystalline layer exhibits a bixbyite crystal structure. It was confirmed to be an oxide. The other obtained results are shown in Table 1.

Example 15
A non-alkali glass substrate of 4 inches in diameter was prepared, and Mo was deposited to a thickness of 50 nm by sputtering, and then patterned into a gate wiring shape by photolithography. Next, this substrate is set in a plasma CVD apparatus, the substrate is maintained at 350 ° C., SiH ₄ is introduced at ₂ sccm, N ₂ O at 100 sccm, and N ₂ at 120 sccm, at a pressure of 110 Pa and a thickness of 150 nm. The gate insulator of
Next, the glass substrate with a gate insulating film is mounted on a sputtering apparatus, and a film forming atmosphere of InGaO (Ga / (In + Ga) = 0.072: atomic ratio) is formed under a total pressure of 0.4 Pa and a gas flow ratio of Ar: O. A channel layer oxide semiconductor layer of 30 nm was formed under the same conditions as in Example 1 except that ₂ = 50: 50. Next, it processed into the channel layer of the semiconductor region by the photolithographic method (channel length L: 20 micrometers, channel width W: 50 micrometers).
Subsequently, the substrate was annealed under vacuum at 300 ° C. for 1 hour.
Set this substrate to a plasma CVD apparatus again, to hold the substrate to 170 ° C., the SiH ₄ 2 sccm, 100 sccm of _{N 2} O, was introduced at a pressure of 110Pa to _{N 2} at a rate of 120 sccm, a thickness of 50nm A protective insulating film (interlayer insulating film 1) was laminated. Next, this substrate was set in a dry etching apparatus, and contact holes for gate electrodes and source / drain electrodes were formed. Then, this laminated body was set in a sputtering apparatus, and after depositing Mo, it was patterned again by a photolithographic method to form a source / drain electrode.
Subsequently, the substrate was annealed under the atmosphere at 300 ° C. for 4 hours.
Subsequently, the substrate is set again in the plasma CVD apparatus, the substrate is maintained at 250 ° C., SiH ₄ is introduced at a pressure of 110 sccm at a rate of ₂ sccm, N ₂ O at 100 sccm, and N ₂ at 120 sccm. An interlayer insulating film 2 of 300 nm was laminated. Then, contact holes for source, drain and gate electrodes were formed again by photolithography. Finally, the substrate was annealed in air at 350 ° C. for 1 hour to obtain a TFT.
The obtained TFT was evaluated in the same manner as in Example 1. The composition of the oxide semiconductor layer is single in the film thickness direction, the oxide semiconductor layer is a crystalline layer having a continuous structure in the film thickness direction, and the crystalline layer exhibits a bixbyite crystal structure. It was confirmed to be an oxide. The other obtained results are shown in Table 1.

Comparative Example 1
In Example 1, the same as in Example 1, except that annealing (at 300 ° C. for 1 hour) was performed in a hydrogen atmosphere immediately before forming the protective layer 70 to increase the carrier concentration in the oxide semiconductor layer 40. Manufactured and evaluated.

  The composition of the oxide semiconductor layer is single in the film thickness direction, the oxide semiconductor layer is a crystalline layer having a continuous structure in the film thickness direction, and the crystalline layer exhibits a bixbyite crystal structure. It was confirmed to be an oxide. The other obtained results are shown in Table 1.

Comparative example 2
A TFT was manufactured and evaluated in the same manner as in Example 1 except that the gate insulating film was formed by CVD in Example 1, and the substrate temperature during CVD was increased to 450 ° C.
Since the substrate temperature at the time of CVD was set to a relatively high temperature, the carrier concentration in the oxide semiconductor layer increased.

  The composition of the oxide semiconductor layer is single in the film thickness direction, the oxide semiconductor layer is a crystalline layer having a continuous structure in the film thickness direction, and the crystalline layer exhibits a bixbyite crystal structure. It was confirmed to be an oxide. The other obtained results are shown in Table 1.

Comparative example 3
In Example 13, the film thickness of the protective insulating film in contact with the channel layer was 3 nm. The others were manufactured and evaluated in the same manner as in Example 13.
The composition of the oxide semiconductor layer is single in the film thickness direction, the oxide semiconductor layer is a crystalline layer having a continuous structure in the film thickness direction, and the crystalline layer exhibits a bixbyite crystal structure. It was confirmed to be an oxide. The other obtained results are shown in Table 1.

Comparative example 4
In Example 13, the substrate temperature at the time of preparation of the protective insulating film in contact with the channel layer was 300 ° C. The others were manufactured and evaluated in the same manner as in Example 13.
The composition of the oxide semiconductor layer is single in the film thickness direction, the oxide semiconductor layer is a crystalline layer having a continuous structure in the film thickness direction, and the crystalline layer exhibits a bixbyite crystal structure. It was confirmed to be an oxide. The other obtained results are shown in Table 1.

Comparative example 5
In Example 15, the vacuum annealing process before the preparation in the protective insulating film in contact with the channel layer was not performed. The others were manufactured and evaluated in the same manner as in Example 15.
The composition of the oxide semiconductor layer is single in the film thickness direction, the oxide semiconductor layer is a crystalline layer having a continuous structure in the film thickness direction, and the crystalline layer exhibits a bixbyite crystal structure. It was confirmed to be an oxide. The other obtained results are shown in Table 1.

Comparative example 6
In Example 1, the same as in Example 1, except that annealing (at 300 ° C. for 1 hour) was performed in the atmosphere immediately before forming the protective layer 70 to increase the carrier concentration in the oxide semiconductor layer 40. Manufactured and evaluated.

  The composition of the oxide semiconductor layer is single in the film thickness direction, the oxide semiconductor layer is a crystalline layer having a continuous structure in the film thickness direction, and the crystalline layer exhibits a bixbyite crystal structure. It was confirmed to be an oxide. The other obtained results are shown in Table 1. In addition, it was confirmed that the crystallization is performed by the annealing process in the atmosphere immediately before the formation of the protective layer 70.

Reference Example 1
FIG. 16 is a schematic cross-sectional view of a double gate thin film transistor manufactured in Reference Example 1.
The thin film transistor has the same configuration as that of the first embodiment described above except that the top gate electrode 80 is provided on the protective insulating film 70 and the method of extracting the source and drain electrodes is different. It has two gate electrodes, a gate electrode (bottom gate) 20 and a top gate electrode 80.
FIG. 17 is a graph showing performance characteristics of a double gate thin film transistor manufactured by forming a channel layer in the same manner as FIG. FIG. 18 is a graph showing performance characteristics of a double gate thin film transistor manufactured by forming a channel layer in the same manner as FIG.

  In this thin film transistor, a top gate electrode is formed on a protective insulating film and applied. The structures of the transistors in FIGS. 17 and 18 are different from each other only in the state of the channel layer (the composition is the same), and the other conditions are the same. When applying a gate voltage to the bottom gate electrode, the top gate electrode is floated, and when applying a voltage to the top gate electrode, the bottom gate electrode is floated. Since the top gate and the bottom gate are asymmetrical in structure, characteristic comparison in FIG. 17 or in FIG. 18 is difficult. On the other hand, in FIG. 17 and FIG. 18, for example, when driving at the top gate is compared, in FIG. 18, the resistance value on the front channel (bottom gate side) side is low and the resistance on the back channel (top gate side) is high. While the on-off ratio is not obtained in the top gate operation, the on-off operation is obtained in FIG. 17 because there is only a region where the channel resistance is low. In addition, the maximum current value of the transfer characteristics during bottom gate operation in FIG. 18 is larger than that in FIG. 17 because it has a low resistance region on the front channel side and a high resistance region on the back channel side. I understand.

Reference Example 2
FIG. 19 is a schematic cross-sectional view of the etch stopper type bottom gate inverted stagger thin film transistor manufactured in the second embodiment.
This thin film transistor has the same configuration as that of the first embodiment described above except that an etching stopper 72 is formed on the channel layer 40 instead of the protective insulating film 70 and the method of taking out the source and drain electrodes is different.
In this thin film transistor, a gate metal film is formed, and the gate metal film is patterned to form the gate electrode 20, and then the gate insulating film 30 covering the gate electrode 20 is formed on the insulating substrate 10. Next, a target formed of a single metal oxide is sputtered under an expected atmosphere containing a rare gas atom and an oxygen molecule to form an oxide semiconductor layer. After that, a protective insulating film to be the etching stepper 72 is formed by CVD so as to cover the oxide semiconductor layer. At this time, in the case of forming an oxygen-permeable insulating film by CVD, it is possible to reduce the channel layer by using a gas containing hydrogen and adjusting the substrate temperature and the introduction ratio. For example, the oxide semiconductor layer can be reduced by increasing the flow ratio of N ₂ O to SiH ₄ in CVD (flowing SiH ₄ more than the reference value) or the substrate temperature in film formation. This is because H diffusion is promoted to the inside of the oxide semiconductor layer and reduction is promoted.
Here, since the reduction effect at the time of CVD differs depending on the device structure, it can not be determined generally. In the case where the oxide semiconductor layer is reduced by the CVD film formation step, it is not preferable to go through the step of annealing the oxide semiconductor layer before the CVD film formation step. This is because the density of the semiconductor film is increased by the annealing to prevent the diffusion of H.
Subsequently, the protective insulating film is etched as the etch stopper 72 to form an oxide semiconductor layer in a desired shape. Next, source / drain films are formed over the channel layer 40, and the source / drain films are patterned to form source / drain electrodes (one is the source electrode 50 and the other is the drain electrode 60).
Furthermore, heat treatment is performed on the channel layer 40. The environment for heat treatment is preferably in the atmosphere, in oxygen, in an oxygen-added nitrogen gas atmosphere, or in an oxygen-added rare gas atmosphere. Since oxygen is supplied from the back channel side into the channel layer through the oxygen permeable insulating film, the spreading resistance value is sequentially increased in the film thickness direction from the gate insulating film side.

In the thin film transistor described above, the mobility characteristic of the obtained element is different by adjusting the thickness of the protective insulating film (etching stopper) formed by CVD and the annealing time. In this example, thin film transistors having a channel layer thickness of 50 nm and a protective insulating film (SiO ₂ ) thickness of 0 nm (not formed), 5 nm, 10 nm, 20 nm, and 50 nm are produced. The influence of the annealing time on the performance was investigated. The annealing temperature was 300.degree.
FIGS. 20-24 show the relationship between the annealing time and the transfer curve for thin film transistors in which the thickness of the protective insulating film is 0 nm (not formed), 5 nm, 10 nm, 20 nm and 50 nm, respectively. 25 to 29 show the relationship between the annealing time and the mobility for thin film transistors in which the thickness of the protective insulating film is 0 nm (not formed), 5 nm, 10 nm, 20 nm, and 50 nm, respectively.
From this result, it is understood that by appropriately selecting the thickness of the protective insulating film and the annealing conditions, a thin film transistor with extremely high mobility can be obtained.
By adjusting the heat treatment after forming the protective insulating film (oxygen-permeable insulating film), a channel layer having desired mobility characteristics can be obtained. Further, after performing the heat treatment after the formation of the oxygen-permeable insulating film, the oxygen-permeable insulating film may be further adjusted, or an oxygen-permeable insulating film such as SiNx or AlN may be formed.

While several embodiments and / or examples of the present invention have been described above in detail, those skilled in the art will appreciate that the exemplary embodiments and / or examples are substantially without departing from the novel teachings and advantages of the present invention. It is easy to make many modifications to the embodiment. Accordingly, many of these variations are included within the scope of the present invention.
The contents of the Japanese application specification on which the Paris priority of the present application is based are entirely incorporated herein.

Claims (20)

A source electrode and a drain electrode, a gate electrode, a gate insulating film, a protective insulating film, and a channel layer,
The channel layer has a substantially single composition, a lifting one crystalline layer a continuous structure in the thickness direction,
The channel layer is located between the gate insulating film and the protective insulating film, has a region with a low spreading resistance value and a region with a wide spreading resistance value, and spreads on the gate insulating film side of the channel layer Thin film transistor with low area. A source electrode and a drain electrode, a gate electrode, a gate insulating film, an insulating substrate, and a channel layer,
The channel layer has a substantially single composition, a lifting one crystalline layer a continuous structure in the thickness direction,
The channel layer is located between the gate insulating film and the insulating substrate, has a region with a low spreading resistance value and a region with a wide spreading resistance value, and spreads on the gate insulating film side of the channel layer Thin film transistor with low area. A source electrode and a drain electrode, a gate electrode, a gate insulating film, a protective insulating film, and a channel layer,
The channel layer has a substantially single composition, a continuous structure in the film thickness direction, and includes an amorphous portion,
The channel layer is located between the gate insulating film and the protective insulating film, has a region with a low spreading resistance value and a region with a wide spreading resistance value, and spreads on the gate insulating film side of the channel layer There is a low area,
Field-effect mobility 40 cm ² A thin film transistor which is not less than / Vs. A source electrode and a drain electrode, a gate electrode, a gate insulating film, an insulating substrate, and a channel layer,
The channel layer has a substantially single composition, a continuous structure in the film thickness direction, and includes an amorphous portion,
The channel layer is located between the gate insulating film and the insulating substrate, has a region with a low spreading resistance value and a region with a wide spreading resistance value, and spreads on the gate insulating film side of the channel layer There is a low area,
Field-effect mobility 40 cm ² A thin film transistor which is not less than / Vs. The thin film transistor according to claim 1 , wherein the field effect mobility is 40 cm ² / Vs or more. Field effect mobility 50 cm ² The thin film transistor according to any one of claims 1 to 5, which is at least / Vs. 70 cm field effect mobility ² The thin film transistor according to any one of claims 1 to 6, which is at least / Vs. The thin film transistor according to any one of claims 1 to 7 , which has an on-off ratio of 1 × 10 ⁶ or more. The threshold voltage is -0.1V or more and 1.0V or less, The thin-film transistor in any one of Claims 1-8. The thin film transistor according to any one of claims 1 to 9 , wherein the region having a low spreading resistance value has a thickness of 10 nm or more in the direction from the interface with the gate insulating film to the inside of the channel layer. The thin film transistor according to claim 1 or 3 , wherein a region having a wide resistance value is provided on the side of the protective insulating film of the channel layer. The region with a high spreading resistance value, having a surface from above 10nm in the direction of the inside of the channel layer thickness of the protective insulating film, a thin film transistor according to claim 1 or 3. Region with a high spreading resistance of the channel layer thin film transistor according to claim 1 or 3 having the protective insulating film and the same spreading resistance. 5. The thin film transistor according to claim 2, wherein a region having a spread resistance value is provided on the insulating substrate side of the channel layer. The region with a high spreading resistance value, having the insulating surface from above 10nm inward direction of the channel layer thickness of the substrate, a thin film transistor according to claim 2 or 4. Region with a high spreading resistance of the channel layer thin film transistor according to claim 2 or 4 having the insulating substrate and the same spreading resistance. The thin film transistor according to any one of claims 3 to 13 , wherein the channel layer contains a crystalline material having a continuous structure in the film thickness direction. A display device using the thin film transistor according to any one of claims 1 to 17 . A method of manufacturing a thin film transistor according to claim 1 or 3 , wherein
Forming a channel layer on the gate insulating film;
Forming the protective insulating film in contact with the channel layer;
And (f) heating at 150 to 500 ° C. after the formation of the protective insulating film. It is a manufacturing method of the thin-film transistor of Claim 2 or 4 , Comprising:
Forming a channel layer on the insulating substrate;
And d) performing, on the channel layer, one or more processes selected from hydrogen plasma treatment, reverse sputtering in a rare gas atmosphere, electron beam irradiation, and ultraviolet ray irradiation.