JP6509681B2 - Power converter and vehicle - Google Patents

Description

  Embodiments of the present invention relate to a power converter and a vehicle.

  The inverter circuit includes, for example, a DC line connected to a DC power supply, and a pair of switching elements connected in series between the high potential side and the low potential side of the DC line. The pair of switching elements are electrically connected to an AC load.

  The energy loss in the inverter circuit is mainly divided into two: conduction loss and switching loss. The conduction loss occurs when current flows through switching elements provided on upper and lower arms of each phase of the inverter circuit. The switching loss in the inverter circuit is, for example, a heat generation loss, and is generated as a product of voltage and current in a period in which the voltage and current are changing, when the current and voltage change at the time of switching of the switching element. Loss. Therefore, in the inverter circuit, as the switching speed is higher, the heat generation loss generated in the switching element is reduced.

  In addition, a large voltage (surge voltage) may be generated instantaneously in the DC line in synchronization with the timing of switching the switching elements of the inverter circuit. The faster the switching speed of the switching element, the larger the amount of change in current flowing through the switching element when switching, and the larger the surge voltage.

  Conventionally, for example, in an inverter circuit employing a power semiconductor switching element (IGBT, MOSFET, etc.) that controls current by gate charge amount, switching speed is changed by switching the magnitude of gate charge current only in a small current region. There has been proposed a method of switching the gate resistance of the switching element according to the method and the size of the load to extend the life of the switching element.

  Further, as described above, since the surge voltage increases as the switching speed of the switching element increases, a method of changing the switching speed by switching the magnitude of the gate charging current according to the voltage of the DC power supply is also proposed. ing.

Unexamined-Japanese-Patent No. 5-328746 JP 2002-125362 A JP 2001-346376 A

  In the configuration of the inverter having the means for switching the gate charging current as described above, normal operation can not be performed if an abnormality occurs in a transistor or a resistor provided in a path for transmitting a gate drive signal to the switching element. , Had to stop the operation of the inverter circuit. However, when an abnormality occurs, it has been desired to be able to continue the operation of the inverter circuit and its mounted device even if the performance is lower than that of the normal operation.

  An embodiment of the present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a power conversion device and a vehicle capable of continuing operation when an abnormality occurs in a control circuit. .

A power conversion device according to an embodiment includes: an inverter circuit including a plurality of switching elements; a first gate driving circuit that supplies a gate driving signal to the switching elements via a first resistance; and a second lower than the first resistance. A second gate drive circuit for supplying a gate drive signal to the switching element through a resistor, an output command from the outside, a voltage between DC lines connected between a DC load and the inverter circuit, and the inverter circuit Receives the value of the current of the AC line connected between the switch and the AC load, generates and outputs a PWM signal for switching the switching element so as to realize the value of the output command, and between the DC lines Speed switching for selecting any one of the first gate drive circuit and the second gate drive circuit based on the value of the voltage of the AC line and the current of the AC line. A control unit for generating and outputting a signal based on said voltage or the gate voltage of the switching elements at both ends of the switching element, the said selected based on the speed switching signal first gate driving circuit or the second gate Gate signal processing for switching the output destination of the PWM signal from the gate drive circuit selected based on the speed switching signal to the other gate drive circuit when detecting the presence or absence of abnormality of the drive circuit and detecting that there is abnormality And a circuit.

FIG. 1 is a view for explaining one configuration example of the power conversion device and the vehicle of the first embodiment. FIG. 2 is a diagram schematically showing a configuration example of the first gate drive circuit and the second gate drive circuit shown in FIG. FIG. 3 is a diagram schematically showing another configuration example of the first gate drive circuit and the second gate drive circuit shown in FIG. FIG. 4 is a flowchart for explaining an example of the operation of the control unit and the gate signal processing circuit shown in FIGS. 1 to 3. FIG. 5 is a view for explaining one configuration example of the power conversion device and the vehicle of the second embodiment. FIG. 6 is a flowchart for explaining an example of the operation of the control unit and the gate signal processing circuit in the power conversion device and the vehicle of the second embodiment.

Hereinafter, a power conversion device and a vehicle according to an embodiment will be described with reference to the drawings.
FIG. 1 is a view for explaining one configuration example of the power conversion device and the vehicle of the first embodiment.

The vehicle of the first embodiment includes a power conversion device, a DC power supply BT, an electric motor M which is an AC load, and wheels WL and WL to which rotational power of the electric motor M is transmitted via an axle.
The power conversion device according to the first embodiment includes an inverter circuit INV, a control circuit CTRL, a current detection unit 20, a smoothing capacitor C, and a discharge resistor R.

  The DC power supply (DC load) BT includes, for example, a storage battery such as a lithium ion battery or a nickel hydrogen battery. The DC power output from the DC power supply BT is supplied to the inverter circuit INV. Further, the DC power supply BT charges an AC load connected via the inverter circuit INV, for example, electric energy generated by the motor M.

  The inverter circuit INV is a three-phase inverter that converts DC power supplied from the DC power supply BT into three-phase AC power. The inverter circuit INV includes a plurality of switching elements Su, Sx, Sv, Sy, Sw, and Sz. The inverter circuit INV supplies a three-phase alternating current to the motor M by opening and closing a plurality of switching elements Su, Sx, Sv, Sy, Sw, Sz in accordance with a gate drive signal from a control circuit CTRL described later.

  Inverter circuit INV is connected between DC power supply BT and motor M, and has a pair of switching elements connected in series between DC lines LINK (H) and LINK (L) supplying current from DC power supply BT. And a plurality of switch circuits. The U-phase switch circuit includes switching elements Su and Sx, the V-phase switch circuit includes switching elements Sv and Sy, and the W-phase switch circuit includes switching elements Sw and Sz. The switch circuits of each phase are connected in parallel with each other. In each phase, a pair of switching elements are connected in series and connected to the motor M between the pair of switching elements. For example, in the U-phase, the pair of switching elements Su and Sx are connected in series, and the series connection point of the pair of switching elements Su and Sx is connected to the motor M. The switching elements Su, Sx, Sv, Sy, Sw, and Sz are, for example, IGBTs (Insulated Gate Bipolar Transistors), FETs (Field-Effect Transistors), GTOs (gate turn-off thyristors), transistors, etc. It is a semiconductor switch that can be electrically controlled to open and close.

  The smoothing capacitor C and the discharge resistor R are connected between the high potential side DC line LINK (H) and the low potential side DC line LINK (L), and between the DC power supply BT and the inverter circuit INV. The plurality of switching elements Su, Sx, Sv, Sy, Sw, Sz, and a DC power supply BT are connected in parallel. The smoothing capacitor C suppresses the fluctuation of the voltage of the DC lines LINK (H) and LINK (L) by the operation of the inverter circuit INV. The capacitance stored in the smoothing capacitor C is discharged by the current flowing to the discharge resistor R.

  The inverter circuit INV and the DC power supply BT are connected or disconnected by a blocking means (not shown). The blocking means is provided for each of the DC lines LINK (H) and LINK (L). The blocking means is, for example, a means for opening and closing the DC lines LINK (H) and LINK (L) according to a control signal from the host controller, and is, for example, an electromagnetic contactor. An alternating current line is connected between the inverter circuit INV and the alternating current load, and the inverter circuit INV and the alternating current load can mutually supply alternating current via the alternating current line.

  The electric motor (AC load) M generates torque by the current supplied from the inverter circuit INV. A load device is connected to the output shaft of the motor M, and the generated torque is transmitted. In addition, the motor M converts kinetic energy of the load device into electric power and performs regenerative operation. The electric power generated by the regenerative operation of the motor M is converted into DC power by the inverter circuit INV, and the DC power supply BT is charged. In the present embodiment, an axle is connected to an output shaft of the motor M, and a torque generated is transmitted to the wheel WL via the axle. Further, the electric motor M converts the kinetic energy of the wheel WL transmitted via the axle into electric power and performs regenerative operation.

  The current detection unit 20 includes current detectors 22, 24, 26. The current detector 22 detects the current flowing in the U-phase AC line. The current detector 24 detects the current flowing in the V-phase AC line. The current detector 26 detects the current flowing in the W-phase AC line.

The control circuit CTRL includes a voltage detection unit 10, a control unit 12, a gate signal processing circuit 14, a first gate drive circuit 16, and a second gate drive circuit 18.
The voltage detection unit 10 detects a voltage between the DC lines LINK (H) and LINK (L) and supplies the voltage to the control unit 12.

  The control unit 12 includes, for example, an arithmetic unit such as a CPU (central processing unit) and a memory. Control unit 12 supplies motor M with an output command (not shown) input from the outside, a power supply voltage of DC power supply BT (voltage between DC lines LINK (H), LINK (L)), and an AC line. Switching elements Su, Sx, Sv, and Sy so as to realize an output command value from the outside based on the current (phase current) of each phase to be output and the carrier wave stored in advance in the memory (not shown). , Sw, and Sz are calculated and output. The PWM signal is generated, for example, for each of the switching elements Su, Sx, Sv, Sy, Sw, and Sz.

  The controller 12 outputs the speed switching signal of the switch circuit of each phase. The speed switching signal may be a signal common to the U-phase, V-phase, and W-phase switch circuits, or may be a signal generated for each phase. The speed switching signal is a signal for selecting one of a first gate drive circuit 16 and a second gate drive circuit 18 described later as a gate drive circuit. The control unit 12 selects the switching elements Su, Sx, Sv, Sy, for example, according to the voltage value between the DC lines LINK (H) and LINK (L) and the current value (phase current) to be output to the motor M. A speed switching signal is generated which changes the switching speed by switching the magnitude of the gate charging current of Sw and Sz.

  The gate signal processing circuit 14 receives, from the control unit 12, a PWM signal for controlling the operation of the switching elements Su, Sx, Sv, Sy, Sw, and Sz, and a speed switching signal. Further, the gate signal processing circuit 14 selects one of the first gate drive circuit 16 and the second gate drive circuit 18 according to the speed switching signal, and outputs a PWM signal.

  When the gate signal processing circuit 14 detects an abnormality in the first gate drive circuit 16 or the second gate drive circuit 18 based on the voltages at both ends of the switching elements Su, Sx, Sv, Sy, Sw, Sz, the speed switching is performed. The output destination of the PWM signal is switched from the gate drive circuit selected based on the signal to the other gate drive circuit. For example, when an abnormality is detected in the first gate drive circuit 16 or the second gate drive circuit 18, the gate signal processing circuit 14 sets the speed switching signal to a different value. That is, when an abnormality is detected in the first gate drive circuit 16 while the first gate drive circuit 16 is selected based on the speed switching signal, the gate signal processing circuit 14 performs PWM to the second gate drive circuit 18. It switches so that a signal is output (for example, let a speed switching signal be a value which selects the 2nd gate drive circuit 18). When an abnormality is detected in the second gate drive circuit 18 when the second gate drive circuit 18 is selected based on the speed switching signal, the gate signal processing circuit 14 outputs a PWM signal to the first gate drive circuit 16. The output is switched (for example, the speed switching signal is set to a value for selecting the first gate drive circuit 16).

  In addition, the gate signal processing circuit 14 detects a fault such as a transistor or a resistor provided in a path for transmitting a gate signal to the switching elements Su, Sx, Sv, Sy, Sw, Sz based on the speed switching signal. The selected gate drive circuit is switched to the other gate drive circuit (for example, the speed switch signal has a different value).

  The first gate drive circuit 16 and the second gate drive circuit 18 apply gate drive signals to the switching elements Su, Sx, Sv, Sy, Sw, and Sz in accordance with the PWM signal received from the gate signal processing circuit 14.

  FIG. 2 is a diagram schematically showing a configuration example of the first gate drive circuit and the second gate drive circuit shown in FIG. Here, a circuit for driving one of the switching elements Su, Sx, Sv, Sy, Sw, and Sz is shown, and the other circuits are omitted. The first gate drive circuit 16 and the second gate drive circuit 18 shown in FIG. 2 are provided in front of respective gates of the switching elements Su, Sx, Sv, Sy, Sw and Sz.

  The voltage Vce across the switching elements Su, Sx, Sv, Sy, Sw, and Sz is input to the gate signal processing circuit 14. The gate signal processing circuit 14 monitors the voltage Vce across the switching elements Su, Sx, Sv, Sy, Sw, and Sz, and detects an abnormality in the circuit if it does not match the state of the gate drive signal. That is, in the normal state, the voltage Vce is low when the gate drive signal is high (on), and the voltage Vce is high when the gate drive is low (off).

  For example, in the gate signal processing circuit 14, when the gate drive signal is at low level and the voltage Vce is lower than a predetermined value (first threshold), when the gate drive signal is at high level, the voltage Vce is at a predetermined value ( A circuit abnormality is detected when at least one of the second threshold value and the second threshold value). Also, for example, when the gate drive signal is high, the gate signal processing circuit 14 includes the voltage Vce within a predetermined range when the voltage Vce is not included in the predetermined range and when the gate drive signal is low. An abnormality may be detected in the circuit when at least one of the above and the other.

The first gate drive circuit 16 includes transistors S1 and S2 and resistors R1, R2 and R3.
The emitter of the transistor S1 and the emitter of the transistor S2 are connected via resistors R1 and R3. The gates of the transistor S1 and the transistor S2 are electrically connected to one of the output terminals of the PWM signal of the gate signal processing circuit 14. The collector of the transistor S1 is connected to the high level voltage, and the collector of the transistor S2 is connected to the low level voltage. The resistor R2 is connected in series between the resistors R1 and R3 and between the gates of the switching elements Su, Sx, Sv, Sy, Sw and Sz.

  The transistor S1 and the transistor S2 have opposite polarities. A common PWM signal is applied to the gates of the transistors S1 and S2. Therefore, the transistor S2 becomes nonconductive at the timing when the transistor S1 becomes conductive, and the transistor S1 becomes nonconductive at the timing when the transistor S2 becomes conductive.

  For example, when a speed switching signal to make a low switching speed is input to the gate signal processing circuit 14, the first gate drive circuit 16 operates, and the switching elements Su, Sx, Sv, Sy, etc. from the first gate drive circuit 16 operate. A gate drive signal that switches Sw and Sz at low speed is output. When the transistor S1 conducts according to the PWM signal, a high level gate drive signal is applied to the gates of the switching elements Su, Sx, Sv, Sy, Sw and Sz by the first gate drive circuit 16, and the transistor S2 conducts. During this time, a low level gate drive signal is applied to the gates of the switching elements Su, Sx, Sv, Sy, Sw and Sz by the first gate drive circuit 16.

  The second gate drive circuit 18 includes transistors S3 and S4 and resistors R4, R5 and R6. The resistors R1, R2, R3 of the first gate drive circuit 16 and the resistors R4, R5, R6 of the second gate drive circuit 18 have different resistance values, and the other configurations are the first gate drive circuit 16 and It is similar. The gates of the transistor S3 and the transistor S4 are electrically connected to the other of the PWM signal output terminals of the gate signal processing circuit 14. The collector of the transistor S3 is connected to the high level voltage, and the collector of the transistor S4 is connected to the low level voltage.

  For example, when a speed switching signal for high-speed switching is input to the gate signal processing circuit 14, the second gate drive circuit 18 operates, and from the second gate drive circuit 18, the switching elements Su, Sx, Sv, Sy, A gate drive signal that switches Sw and Sz at high speed is output. When the transistor S3 conducts according to the PWM signal, the second gate drive circuit 18 applies a high level gate drive signal to the gates of the switching elements Su, Sx, Sv, Sy, Sw, Sz, and the transistor S4 When conducting, the second gate drive circuit 18 applies a low level gate drive signal to the gates of the switching elements Su, Sx, Sv, Sy, Sw and Sz.

  The resistors R1, R2 and R3 of the first gate drive circuit 16 have gate resistances of the switching elements Su, Sx, Sv, Sy, Sw and Sz more than the resistors R4, R5 and R6 of the second gate drive circuit 18. It is set to be high. Therefore, when a drive signal is applied to the gates of the switching elements Su, Sx, Sv, Sy, Sw and Sz by the first gate drive circuit 16, the gate charging current is reduced and the switching speed is reduced. When a drive signal is applied to the gates of the switching elements Su, Sx, Sv, Sy, Sw, and Sz by the second gate drive circuit 18, the gate charging current is increased and the switching speed is increased.

  FIG. 3 is a diagram schematically showing another configuration example of the first gate drive circuit and the second gate drive circuit shown in FIG. Similar to the circuit shown in FIG. 2, the first gate drive circuit 16 and the second gate drive circuit 18 shown in FIG. 3 are provided in front of the respective gates of the switching elements Su, Sx, Sv, Sy, Sw and Sz. It is provided.

In this circuit, the configuration in which the gate signal processing circuit 14 detects an abnormality in the circuit is different from that in FIG.
The gate voltage of the switching elements Su, Sx, Sv, Sy, Sw, and Sz is input to the gate signal processing circuit 14. The gate signal processing circuit 14 monitors the gate voltage of the switching elements Su, Sx, Sv, Sy, Sw, and Sz, and detects an abnormality of the circuit if it does not match the state of the gate drive signal. That is, in a normal state, when the gate drive signal is high (on), the gate voltage is high (on), and when the gate drive is low (off), the gate voltage is low ( It is off.

For example, in the gate signal processing circuit 14, when the gate drive signal is high level and the gate voltage is lower than a predetermined value (third threshold), and when the gate drive signal is low level, the gate voltage is The circuit abnormality is detected when at least one of the fourth threshold value and the threshold value). Also, for example, when the gate drive signal is high, the gate signal processing circuit 14 includes the gate voltage within a predetermined range when the gate voltage is not included in the predetermined range, and when the gate drive signal is low. The circuit abnormality may be detected when at least one of the above and the other.
The gate signal processing circuit 14 monitors both the voltage Vce at both ends of the switching elements Su, Sx, Sv, Sy, Sw, and Sz and the gate voltage, and detects an abnormality based on both voltages. I do not care.

FIG. 4 is a flowchart for explaining an example of the operation of the control unit and the gate signal processing circuit shown in FIGS. 1 to 3.
The gate signal processing circuit 14 monitors the voltage Vce or gate voltage at both ends of the switching elements Su, Sx, Sv, Sy, Sw, Sz, and detects an abnormality in the circuit. (Step SA1)

  When the gate signal processing circuit 14 detects an abnormality in step SA1, the gate resistance of the switching elements Su, Sx, Sv, Sy, Sw, Sz is currently high based on the speed switching signal received from the control unit 12 Detects the status or low status. (Step SA2)

  When the gate resistance is low, the gate signal processing circuit 14 supplies a gate drive signal to the switching elements Su, Sx, Sv, Sy, Sw and Sz from the second gate drive circuit 18 to the first gate drive circuit. Switch to 16 to increase the gate resistance. (Step SA3)

  When the gate resistance is high, the gate signal processing circuit 14 supplies a gate drive signal to the switching elements Su, Sx, Sv, Sy, Sw, and Sz from the first gate drive circuit 16 to the second gate drive circuit. Switch to 18 to lower the gate resistance.

  At this time, the gate signal processing circuit 14 notifies the control unit 12 of a command for limiting the regeneration operation of the motor M or inhibiting the regeneration operation. Normally, when the vehicle decelerates (motor deceleration), energy returns to the inverter INV side, and the voltage between the DC lines LINK (H) and LINK (L) rises (regeneration operation). The regenerative operation is performed in a state where the gate resistance is fixed low, and if the DC voltage rises, switching to a state where the gate resistance is high can not be performed, so the switching elements Su, Sx, Sv, Sy, Sw, Sz are broken. There is a risk of Therefore, when the control unit 12 receives a command to limit the regenerative operation from the gate signal processing circuit 14, the control unit 12 generates a PWM signal so that the output torque of the motor M does not become negative. As described above, by limiting the regeneration operation or prohibiting the regeneration operation, it is possible to suppress the rise of the DC voltage and to avoid the destruction of the switching element. (Step SA4)

  In the present embodiment, for example, the control unit 12 sets a speed switching signal so as to attain a low switching speed (high gate resistance) when the open battery voltage Vmax or more in the remaining battery amount at the upper limit in normal use. Generate At this time, if the first gate drive circuit 16 having a high gate resistance breaks down, the regeneration operation may be limited as described above, and the regeneration amount is adjusted to prohibit the regeneration operation with the open voltage value Vmax as the upper limit. You may.

  Subsequently, the gate signal processing circuit 14 monitors the voltage Vce or the gate voltage at both ends of the switching elements Su, Sx, Sv, Sy, Sw, Sz, and detects an abnormality in the circuit. (Step SA5)

  When the abnormality is not detected in step SA5, the gate signal processing circuit 14 continues the operation of the inverter circuit INV by the speed switching signal switched in step SA3 or step SA4. Here, the gate signal processing circuit 14 continues the operation so as to output the PWM signal to the gate drive circuit after switching regardless of the speed switching signal transmitted from the control unit 12. The gate signal processing circuit 14 may continue the operation by fixing the value of the speed switching signal so that the gate driving circuit after switching is selected. At this time, the gate signal processing circuit 14 notifies the control unit 12 of an alarm that there is an abnormality in the circuit. The control unit 12 having received the alarm notifies, for example, the host control device (not shown) that there is an abnormality in the circuit. (Step SA6)

  When an abnormality is detected in step SA5, the gate signal processing circuit 14 notifies the control unit 12 of an instruction to stop the operation of the inverter circuit INV. When the control unit 12 receives a command to stop the operation of the inverter circuit INV, the control unit 12 opens all the switching elements Su, Sx, Sv, Sy, Sw, and Sz to stop the operation of the inverter circuit INV. (Step SA7)

As described above, in the power conversion device and the vehicle according to the present embodiment, when an abnormality occurs in a transistor, a resistor, or the like on a line that transmits a gate drive signal, the gate drive circuit that outputs the gate drive signal to the other By switching, it is possible to continue the operation without stopping the operation of the inverter circuit INV.
That is, according to the present embodiment, it is possible to provide the power conversion device and the vehicle capable of continuing the operation when an abnormality occurs in the control circuit.

Next, a power converter and a vehicle according to a second embodiment will be described with reference to the drawings.
FIG. 5 is a view for explaining one configuration example of the power conversion device and the vehicle of the second embodiment. The power conversion device of the present embodiment is different from the above-described first embodiment in that the power conversion device further includes a booster circuit BST.

  The booster BST is connected between the DC power supply BT and the inverter INV, and outputs a voltage value larger than the power supply voltage BT to the DC links LINK (H) and LINK (L). Since the booster BST can transmit energy bidirectionally, the energy regenerated by the inverter circuit INV can be charged to the DC power supply BT.

The booster circuit BST includes an input capacitor CIN, a booster reactor L, and switching elements SA and SB.
The switching elements SA and SB may be controlled to open and close electrically, for example, IGBTs (Insulated Gate Bipolar Transistors), FETs (Field-Effect Transistors), GTOs (gate turn-off thyristors), transistors, etc. Semiconductor switch.

  The switching element SA and the switching element SB are connected in series with each other. The switching element SA and the switching element SB are connected in parallel with the plurality of switching elements Su, Sx, Sv, Sy, Sw, Sz of the inverter INV. The connection line between the switching element SA and the switching element SB is electrically connected to the positive electrode of the DC power supply BT via the boost reactor L. The input capacitor CIN is connected in parallel to the DC power supply BT.

  The control circuit CTRL further includes a voltage detection unit 11 that detects a voltage across the input capacitor CIN, and a first gate drive circuit 16 and a second gate drive circuit 18 that output gate drive signals to the switching elements SA and SB. Have.

  Control unit 12 receives an externally input output command (not shown), a voltage between both ends of input capacitor CIN, a voltage between DC lines LINK (H) and LINK (L) of inverter circuit INV, and an AC line The PWM signal is calculated so as to achieve a desired output value based on the current (phase current) of each phase supplied to the motor M by this and the carrier wave stored in advance in the memory (not shown). Output. The PWM signal is generated for each of the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, and SB.

  The control unit 12 outputs a speed switching signal for the switch circuit of each phase. The speed switching signal may be a signal common to the U-phase, V-phase, and W-phase switch circuits, or may be a signal generated for each phase. For example, control unit 12 selects switching elements Su, Sx, Sv, Sy, Sw according to the voltage value between DC lines LINK (H), LINK (L) and the current value (phase current) output to motor M. , Sz, SA, SB by switching the magnitude of the gate charging current to generate a speed switching signal for changing the switching speed.

  In the power conversion device and the vehicle of the present embodiment, the gate signal processing circuit 14, the first gate drive circuit 16, and the second gate drive circuit 18 have the same configurations as those described with reference to FIGS.

FIG. 6 is a flowchart for explaining an example of the operation of the control unit and the gate signal processing circuit in the power conversion device and the vehicle of the second embodiment.
The gate signal processing circuit 14 monitors the voltage Vce or gate voltage at both ends of the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, and SB, and detects an abnormality of the circuit. (Step SB1)

When the gate signal processing circuit 14 detects an abnormality in step SB1, the gate signal processing circuit 14 detects the abnormality of the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, and SB based on the speed switching signal received from the control unit 12. It detects whether the gate resistance is high or low. (Step SB2)
When the gate resistance is in a low state, the gate signal processing circuit 14 supplies a gate drive signal to the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, and SB from the second gate drive circuit 18. It switches to the 1 gate drive circuit 16 and makes gate resistance high. (Step SB3)

  When the gate resistance is high, the gate signal processing circuit 14 is a circuit for supplying a gate drive signal to the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, and SB from the first gate drive circuit 16. It switches to the 2 gate drive circuit 18, and makes gate resistance low.

  Here, when the gate resistance is switched from a high gate resistance state to a low gate resistance state, the change in charging current of the gate becomes large, and the surge voltage generated in the DC lines LINK (H) and LINK (L) becomes large. At this time, if the main power supply voltage is increased, the voltage between the DC lines LINK (H) and LINK (L) exceeds the withstand voltage of the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, and SB, It causes trouble. Therefore, in the present embodiment, when switching from a state where the gate resistance is high to a state where the gate resistance is low, the gate signal processing circuit 14 stops the boosting operation of the boosting circuit BST or limits the voltage after boosting to switch the switching element Su. , Sx, Sv, Sy, Sw, Sz, SA, SB are avoided. (Step SB4)

Subsequently, the gate signal processing circuit 14 monitors the voltage Vce or the gate voltage at both ends of the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, and SB, and detects an abnormality of the circuit. (Step SB5)
When there is no abnormality at step SB5, the gate signal processing circuit 14 continues the operation of the inverter circuit INV by the speed switching signal switched at step SB3 or step SB4. Here, the gate signal processing circuit 14 continues the operation so as to output the PWM signal to the gate drive circuit after switching regardless of the speed switching signal transmitted from the control unit 12. The gate signal processing circuit 14 may continue the operation by fixing the value of the speed switching signal so that the gate driving circuit after switching is selected. At this time, the gate signal processing circuit 14 notifies the control unit 12 of an alarm that there is an abnormality in the circuit. The control unit 12 having received the alarm notifies, for example, the host control device (not shown) that there is an abnormality in the circuit. (Step SB6)

  The gate signal processing circuit 14 notifies the control unit 12 of an instruction to stop the operation of the inverter circuit INV when there is an abnormality in step SB5. When receiving the command to stop the operation of the inverter circuit INV, the control unit 12 opens all the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, and SB to stop the operation of the inverter circuit INV. (Step SB7)

As described above, in the power conversion device and the vehicle according to the present embodiment, when an abnormality occurs in a transistor, a resistor, or the like on a line that transmits a gate drive signal, the gate drive circuit that outputs the gate drive signal to the other By switching, it is possible to continue the operation without stopping the operation of the inverter circuit INV.
That is, according to the present embodiment, it is possible to provide the power conversion device and the vehicle capable of continuing the operation when an abnormality occurs in the control circuit.

Next, a power conversion device and a vehicle according to a third embodiment will be described with reference to the drawings.
The power conversion device and the vehicle according to the present embodiment are applicable to both the configuration including the booster and the configuration not including the booster, and are similar to the power conversion device and the vehicle according to the first and second embodiments described above. The configuration will be described with the same reference numerals. In the present embodiment, the control unit 12 integrates the output current of the inverter circuit INV detected by the current detection unit 20 for one cycle, and detects whether there is an abnormality or not by whether the value is zero or not. Not shown).

  If the gate drive signal output from the control circuit CTRL to the inverter circuit INV realizes an output command from the outside, a value obtained by integrating the output current of the inverter circuit INV for one cycle is zero. When the integrated value does not become zero, there is a possibility that there is an abnormality in the path until the output command value of the control circuit CTRL is received and the gate drive signal is output, or in the inverter circuit INV.

The abnormality detection means of the control unit 12 detects whether the gate resistance of the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, SB is high or low when it detects that there is an abnormality. Do.
When the gate resistance is in a low state, the abnormality detection unit of the control unit 12 generates a second gate drive circuit 18 for supplying a gate drive signal to the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, and SB. To the first gate drive circuit 16 to increase the gate resistance.

  When the gate resistance is high, the abnormality detection unit of the control unit 12 is a first gate drive circuit 16 for supplying a gate drive signal to the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, and SB. To the second gate drive circuit 18 to lower the gate resistance.

  Here, when switching from a state where the gate resistance is high to a state where the gate resistance is low, the abnormality detection means of the control unit 12 stops the boosting operation of the boosting circuit BST or limits the voltage after boosting to switch the switching elements Su and Sx. , Sv, Sy, Sw, Sz, SA, SB are avoided. Further, when switching from a state where the gate resistance is high to a state where the gate resistance is low, the control unit 12 generates a PWM signal so that the output torque of the motor M does not become negative. As described above, the regeneration operation is restricted or the regeneration operation is inhibited, the rise of the DC voltage is suppressed, and the destruction of the switching element is avoided.

Subsequently, the abnormality detection unit of the control unit 12 integrates the output current of the inverter circuit INV detected by the current detection unit 20 for one cycle, and detects whether there is an abnormality based on whether the integration result is zero. .
The abnormality detection means of the control unit 12 continues the operation of the inverter circuit INV with the current speed switching signal when the integration result is zero and there is no abnormality. Here, the abnormality detection unit of the control unit 12 fixes the value of the speed switching signal and continues the operation, and generates an alarm indicating that there is an abnormality in the circuit, for example, to the upper control device (not shown). Inform that there is.

  When the abnormality detection means of the control unit 12 detects that the integration result is not zero but there is an abnormality after switching the gate drive circuit, all the switching elements Su, Sx, Sv, Sy, Sw, Sz, SA, The SB is opened to stop the operation of the inverter circuit INV.

As described above, in the power conversion device and the vehicle according to the present embodiment, when an abnormality occurs in a transistor, a resistor, or the like on a line that transmits a gate drive signal, the gate drive circuit that outputs the gate drive signal to the other By switching, it is possible to continue the operation without stopping the operation of the inverter circuit INV.
That is, according to the present embodiment, it is possible to provide the power conversion device and the vehicle capable of continuing the operation when an abnormality occurs in the control circuit.
The configurations of the power conversion device of the first to third embodiments and the vehicle may be combined. Even in this case, the same effects as those of the first to third embodiments described above can be obtained.

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof. In the above embodiment, for example, when the gate signal processing circuit 14 switches the gate drive circuit to the other, the speed switching signal may have different values, and the value of the speed switching signal received from the control unit 12 is not changed. For example, the other gate drive circuit may be selected according to an abnormality flag or the like that rises when an abnormality is detected.

  DESCRIPTION OF SYMBOLS 10 ... Voltage detection part, 11 ... Voltage detection part, 12 ... Control part, 14 ... Gate signal processing circuit, 16 ... 1st gate drive circuit, 18 ... 2nd gate drive circuit, 20 ... Current detection part, 22, 24, 26 Current detector, R1 to R6 Resistor, S1 to S4 Transistor, INV: inverter circuit, M: motor, WL: wheel, CTRL: control circuit, Su, Sx, Sv, Sy, Sw, Sz, SA , SB: switching element, LINK (H), LINK (L): direct current line.

Claims (7)

An inverter circuit including a plurality of switching elements;
A first gate drive circuit for supplying a gate drive signal to the switching element via a first resistor;
A second gate drive circuit for supplying a gate drive signal to the switching element via a second resistor lower than the first resistor;
Receiving values of an output command from an external device, a voltage between DC lines connected between the DC load and the inverter circuit, and a current of an AC line connected between the inverter circuit and the AC load; The first gate drive circuit generates and outputs a PWM signal for switching the switching element so as to realize the value of the output command, and based on the value of the voltage between the DC lines and the current of the AC line. A control unit which generates and outputs a speed switching signal for selecting one of the second gate drive circuit and the second gate drive circuit;
The presence or absence of abnormality of the first gate drive circuit or the second gate drive circuit selected based on the speed switching signal is detected based on the voltage at both ends of the switching element or the gate voltage of the switching element. A gate signal processing circuit that switches the output destination of the PWM signal from the gate drive circuit selected based on the speed switching signal to the other gate drive circuit when it is detected that
The power converter characterized by being provided.   After switching the output destination of the PWM signal based on the detection that there is an abnormality in the gate signal processing circuit, no abnormality of the other gate drive circuit is detected, regardless of the speed switching signal. The power conversion device according to claim 1, wherein the output destination of the PWM signal is not switched.   After switching the output destination of the PWM signal based on detection of abnormality in the gate signal processing circuit, when an abnormality of the other gate drive circuit is detected, a command to stop the inverter circuit The power conversion device according to claim 1 or 2, wherein the power conversion device is output to the control unit.   The gate signal processing circuit determines that there is an abnormality in the first gate drive circuit or the second gate drive circuit, and a gate drive signal is supplied to the switching element by the first gate drive circuit. The power conversion device according to any one of claims 1 to 3, wherein the regenerative operation of the inverter circuit is limited. It further comprises a booster comprising a pair of switching elements connected between the DC lines,
The gate signal processing circuit determines that there is an abnormality in the first gate drive circuit or the second gate drive circuit, and a gate drive signal is supplied to the switching element by the first gate drive circuit. The power converter according to any one of claims 1 to 4, wherein the voltage boosted by the booster is limited. An inverter circuit including a plurality of switching elements;
A first gate drive circuit for supplying a gate drive signal to the switching element via a first resistor;
A second gate drive circuit for supplying a gate drive signal to the switching element via a second resistor lower than the first resistor;
Receiving values of an output command from an external device, a voltage between DC lines connected between the DC load and the inverter circuit, and a current of an AC line connected between the inverter circuit and the AC load; The first gate drive circuit generates and outputs a PWM signal for switching the switching element so as to realize the value of the output command, and based on the value of the voltage between the DC lines and the current of the AC line. A control unit for generating and outputting a speed switching signal for selecting any one of the second gate driving circuit and the second gate driving circuit, wherein the speed switching is performed when an integral value during one period of the current of the AC line is not zero. said control unit signals, a value for selecting different gate driving circuit and the selected gate drive circuit,
A gate signal processing circuit that outputs the PWM signal to any one of the first gate drive circuit and the second gate drive circuit based on the speed switching signal;
The power converter characterized by being provided. DC power supply as a DC load,
Motor as AC load,
A power converter according to any one of claims 1 to 6.
An axle for transmitting the power of the motor to the wheels;
A vehicle characterized by comprising.