JP6511976B2 - Electronic circuit - Google Patents

Description

  The present invention relates to electronic circuits, for example to electronic circuits comprising transistors.

  For example, in the communication field, a power amplifier or a low noise amplifier that amplifies a signal is used. In these amplifier circuits, a bias circuit and a matching circuit are provided at the control terminal of the transistor (for example, Patent Document 1). Thereby, the amplification circuit amplifies a signal in a desired amplification band.

JP-A-8-162859

  The amplification circuit suppresses signals in bands other than the amplification band. In particular, when the amplification band is a high frequency band, the amplification circuit suppresses signals of frequencies lower than that of the high frequency band. This improves the stability of the amplifier circuit in the low frequency band. In the amplification circuit, the bias voltage of the control terminal of the transistor may be adjusted from the outside to adjust the gain and the like. However, if the bias voltage at the control terminal is adjusted from the outside and stability is sought in a low frequency band, for example, a large capacitor will be used. This will increase the mounting area.

  This electronic circuit is made in view of the above-mentioned subject, and it aims at making a mounting area small.

  An electronic circuit according to an embodiment of the present invention includes a transistor having a control terminal connected to an input terminal, a first terminal connected to a reference potential, and a second terminal connected to an output terminal. A first filter circuit having a first capacitor whose other end is connected to the reference potential at a node between the control terminal and the input terminal; a first resistor whose one end is connected to the node; A second filter circuit having a second capacitor whose other end is connected to the reference potential at the other end of the first resistor, and which is connected in parallel with the first filter circuit between the node and the reference potential And a third filter circuit having a second resistor whose one end is connected to the node at the other end and the third terminal whose other end is connected to the reference potential at the other end. Do.

  According to this electronic circuit, the mounting area can be reduced.

FIG. 1 is a circuit diagram of an electronic circuit according to Comparative Example 1. FIG. 2 is a circuit diagram of the electronic circuit according to the first embodiment. FIG. 3 is a circuit diagram of an electronic circuit according to a second embodiment.

Description of an embodiment of the present invention
First, the contents of the embodiment of the present invention will be listed and described.
The present invention relates to a transistor having a control terminal connected to an input terminal, a first terminal connected to a reference potential, and a second terminal connected to an output terminal, and one end of the control terminal and the input terminal A first filter circuit having a first capacitor whose other end is connected to the reference potential, a first resistor whose one end is connected to the node, and one end of the other end of the first resistor A second capacitor circuit having an end connected to a reference potential, and a second filter circuit connected in parallel with the first filter circuit between the node and the reference potential, and one end connected to the node It is an electronic circuit comprising a third filter circuit having a second resistor whose end is connected to the bias terminal and a third resistor whose one end is connected to the node and the other end to the reference potential. A third filter having a second resistor and a third resistor suppresses the low frequency signal. Thus, it is not necessary to use a large capacitor between the bias terminal and the reference potential. Therefore, the mounting area can be reduced, and the band of the signal input to the bias terminal can be widened.

  The impedance of the first filter circuit in the high frequency band is lower than the impedance of the second filter circuit and the third filter circuit in the high frequency band, and the third filter in the low frequency band lower in frequency than the high frequency band. The impedance of the circuit is lower than the impedance of the first filter circuit and the second filter circuit in the low frequency band, and the second filter in the intermediate frequency band whose frequency is lower than the high frequency band and higher than the low frequency band The impedance of the circuit is preferably lower than the impedance of the first filter circuit and the third filter circuit in the intermediate frequency band. Thus, the first filter circuit functions as a matching circuit that matches the impedances of the input terminal and the control terminal in the high frequency band. The second filter circuit functions as a matching circuit that removes the intermediate frequency signal input to the input terminal to the reference potential. The third filter circuit functions as a matching circuit that removes the low frequency signal input to the input terminal to the reference potential. Therefore, the stability of the electronic circuit can be improved.

  It is preferable that the distributed constant line includes one end connected to the node and the other end commonly connected to one end of the first capacitor and one end of the first resistor. Thus, the impedance of the input terminal and the control terminal can be matched in the high frequency band by the first filter circuit and the distributed constant line.

  Preferably, the transistor is a FET, the first terminal is a source, the second terminal is a drain, and the control terminal is a gate. Thereby, the mounting area of the amplifier circuit having the FET can be reduced.

Comparative Example 1
An amplification circuit capable of externally adjusting the gate bias voltage of the FET will be described as Comparative Example 1. The gain of the amplification circuit can be controlled by adjusting the gate bias voltage. For example, in a high frequency amplification circuit that amplifies a signal of 20 GHz or more, such as a quasi-millimeter wave band or a millimeter wave band, stability in a band lower in frequency than a high frequency band which is an amplification band becomes a problem.

  FIG. 1 is a circuit diagram of an electronic circuit according to Comparative Example 1. As shown in FIG. 1, the electronic circuit 110 is an amplifier circuit having a FET 10. The source of the FET 10 is electrically connected to the ground through the distributed constant line Ls. The gate is electrically connected to the input terminal Tin. The drain is electrically connected to the output terminal Tout via the distributed constant line Ld. Distributed constant lines Ls and Ld are matching circuits of the source and the drain of the FET 10, respectively.

  A node N2 between the gate of the FET 10 and the input terminal Tin is electrically connected to the ground through a distributed constant line Lg and a capacitor Cg in series. A node N3 between the distributed constant line Lg and the capacitor Cg is electrically connected to the bias terminal Tvg via the resistors Rg and Ro. Capacitors Cg1, Cg2 and Cg3 are connected in parallel between the node between the resistors Rg and Ro and the ground, respectively. A capacitor C1 is connected in series between the input terminal Tin and the node N2. The capacitor C1 mainly functions as a DC cut capacitor.

  The electronic circuit 110 amplifies the high frequency signal input to the input terminal Tin and outputs the amplified signal from the output terminal Tout. A bias voltage Vg is applied to the bias terminal Tvg. Thereby, the gate bias voltage applied to the gate of the FET 10 can be controlled.

  The capacitor Cg passes the high frequency signal input to the input terminal Tin as indicated by the arrow 22. As a result, the distributed constant line Lg and the capacitor Cg function as a matching circuit for high frequency signals. Therefore, the amplification circuit can perform amplification operation stably in a high frequency band (for example, 50 GHz or more).

  The voltage Vg applied to the bias terminal Tvg is supplied as a gate bias voltage to the gate of the FET 10 through the resistors Ro and Rg. The capacitor Cg is open for signals of frequencies lower than the high frequency band (for example, less than 50 GHz). Therefore, capacitors Cg1 to Cg3 are provided. Cg1 to Cg3 pass signals of lower frequencies than the high frequency band as indicated by arrows 28. Thus, the low frequency signal input from the input terminal Tin can be removed to the ground. Thus, the amplifier circuit suppresses a frequency band lower than the high frequency band (for example, less than 50 GHz). Thereby, the amplifier circuit can operate stably in the low frequency band.

  However, in order for the capacitors Cg1 to Cg3 to function for signals close to DC (Direct Current) to, for example, 50 GHz, 10 pF, 100 pF and 0.1 μF are used as the capacitors Cg1 to Cg3, respectively. Such large capacitors are external.

In addition, the band of the gate bias voltage is limited by the time constant of the resistor Rg and the capacitor Cg or the source-gate capacitance Cgs of the FET 10. Furthermore, the bandwidth of the gate bias voltage is limited by the total capacitance _{C total} of the resistor Ro and a capacitor Cg1 Cg3. For example, the bandwidth of the effective gate bias voltage is f = Vg1 / (2π · Ro · C _total ) or less.

  Thus, in Comparative Example 1, a large capacitor is used. This increases the mounting area. In addition, the band of the gate bias voltage is limited by a large capacitor.

  FIG. 2 is a circuit diagram of the electronic circuit according to the first embodiment. As shown in FIG. 2, the electronic circuit 100 includes the FET 10 and the filter circuits 12, 14 and 16. A capacitor C1 is connected in series between the input terminal Tin and the node N2. The filter circuit 12 (first filter) has a capacitor Cg (first capacitor). One end of the capacitor Cg is connected to the node N2 via the distributed constant line Lg, and the other end is connected to the ground (reference potential). The filter circuit 14 (second filter circuit) has a resistor Rg (first resistor) and a capacitor Cgo (second capacitor). One end of the resistor Rg is connected to the node N2 through the distributed constant line Lg. One end of the capacitor Cgo is connected to the other end of the resistor Rg, and the other end is connected to the ground. One end of the distributed constant line Lg is connected to the node N2, and the other end is connected to the node N3. The filter circuit 16 (third filter circuit) has resistors Rb1 (second resistor) and Rb2 (third resistor). One end of the resistor Rb1 is connected to the node N1, and the other end is connected to the bias terminal Tvg. One end of the resistor Rb2 is connected to the node N1, and the other end is connected to the ground.

  The amplification band of the electronic circuit is a high frequency band. The low frequency band is a band lower in frequency than the high frequency band. The intermediate frequency band is a band lower in frequency than the high frequency band and higher in frequency than the low frequency band. Signals in the high frequency band, the intermediate frequency band and the low frequency band are respectively referred to as a high frequency signal, an intermediate frequency signal and a low frequency signal. The high frequency band is, for example, 50 GHz or more. The intermediate frequency band is, for example, 1 GHz or more and less than 50 GHz. The low frequency band is, for example, less than 1 GHz. The high frequency band, the intermediate frequency band and the low frequency band can be arbitrarily set in addition to the above example.

  The filter circuit 12 passes the high frequency signal among the signals input from the input terminal Tin to the ground as shown by the arrow 22. The filter circuit 14 passes the intermediate frequency signal of the signals input from the input terminal Tin to the ground as shown by the arrow 24. The filter circuit 16 passes the low frequency signal among the signals input from the input terminal Tin to the ground as shown by the arrow 26.

  First, it will be described that the filter circuit 16 functions as a bias circuit. When a voltage Vg is applied to the bias terminal Tvg, a current flows from the bias terminal Tvg to the ground as indicated by an arrow 20. A voltage divided by the resistors Rb1 and Rb2 is applied to the gate of the FET 10 as a gate bias voltage. As a result, even when the input terminal Tin is unloaded, the gate bias voltage can be suppressed from becoming high. Thus, the resistors Rb1 and Rb2 function as bleeder resistors. Although the resistors Rb1 and Rb2 can be set arbitrarily, it is preferable that the parallel resistance between the resistors R12 and Rb2 be small in order to be stable at low frequencies. For example, the resistances Rb1 and Rb2 are preferably several kΩ or less.

  Next, it will be described that the filter circuits 12, 14 and 16 function as matching circuits. In the following description, resistances of Rg, Rb1 and Rb2 are Rg, Rb1 and Rb2, respectively, and capacitances of the capacitors Cg and Cgo are Cg and Cgo. Let f be the frequency of the signal. At this time, the impedance Z12 of the filter circuit 12 is 1 / (2π · f · Cg). The impedance Z14 of the filter circuit 14 is Rg + 1 / (2π · f · Cgo). The impedance of the impedance Z16 of the filter circuit 16 is approximately Rb1 or Rb2.

  The filter circuit 12 and the distributed constant line Lg match the impedance seen from the node N2 to the gate of the FET 10 in the high frequency band and the impedance seen from the node N2 to the input terminal Tin. Thereby, desired amplification characteristics can be obtained in the high frequency band. The filter circuits 14 and 16 pass the intermediate frequency signal and the low frequency signal among the signals input to the input terminal Tin to the ground. This suppresses the instability of the amplification circuit in a band lower than the high frequency band (intermediate frequency band and low frequency band).

  In the high frequency band, the impedances of the filter circuits 12, 14 and 16 have a relationship of Z16 >> Z14> Z12. Thus, the impedance Z12 is mainly seen mainly for high frequency signals input from the input terminal Tin. Thus, the input impedance to the FET 10 can be matched to the high frequency signal by the distributed constant line Zg and the capacitor Cg.

  In the low frequency band, the impedance relationship is Z12, Z14 >> Z16. As a result, parallel resistances of the resistors Rb1 and Rb2 are mainly seen in the low frequency signal input from the input terminal Tin. The low frequency signal input to the input terminal Tin is removed by the parallel circuit of the resistors Rb1 and Rb2. Thus, the resistor Rb1 or Rb2 functions as a stabilization circuit for low frequency signals.

  In the intermediate frequency band, the impedance relationship is Z16 >> Z12> Z14. Thereby, the impedance Z14 is mainly seen in the intermediate frequency signal input from the input terminal Tin. Thus, the intermediate frequency signal input to the input terminal Tin is removed, and the amplifier circuit is stabilized. The resistance Rg is, for example, 10 to 100 Ω.

  According to the first embodiment, the filter circuit 16 has a function of a control circuit that removes a low frequency signal input from the input terminal Tin and a function of a bias circuit that applies a gate bias voltage to the gate. This can reduce the mounting area. Further, the filter circuit 16 removes low frequency signals using the resistors Rb1 and Rb2. Furthermore, in order to remove an intermediate frequency signal that can not be removed by the filter circuit 12, a filter circuit 14 is provided. Since the filter circuit 14 does not have to remove low frequency signals, the capacitor Cgo can be made smaller.

  As described above, a band lower in frequency than the high frequency band is divided into a low frequency band and an intermediate frequency band. The low frequency signal input from the input terminal Tin is removed by the filter circuit 16 which does not use a capacitor. The intermediate frequency signal which can not be removed by the filter circuit 16 is removed by the filter circuit 14 having the capacitor Cgo. As a result, the large capacitors Cg1 to Cg3 as in Comparative Example 1 become unnecessary. Therefore, the mounting area can be suppressed. Further, it is possible to suppress the limitation of the gate bias voltage band due to the large capacitors Cg1 to Cg3.

  In order for the filter circuits 12, 14 and 16 to function as described above, the impedance between the node N1 or N2 and the ground in the filter circuits 12, 14 and 16 preferably has the following relationship. The impedance Z12 of the filter circuit 12 in the high frequency band is lower than the impedances Z14 and Z16 of the filter circuits 14 and 16. The impedance Z16 of the filter circuit 16 in the low frequency band is lower than the impedances Z12 and Z14 of the filter circuits 12 and 14. The impedance Z14 of the filter circuit 14 in the intermediate frequency band is lower than the impedances Z12 and Z16 of the filter circuits 12 and 16.

  Furthermore, in order to make the filter circuit 12 function as a matching circuit in a high frequency band, it is preferable that a distributed constant line Lg be provided. The nodes N1 and N2 may be provided in common, or a line may be formed between the nodes N1 and N2.

  The second embodiment is a specific example of the first embodiment. FIG. 3 is a circuit diagram of an electronic circuit according to a second embodiment. As shown in FIG. 3, in the electronic circuit 102, the capacitor C1 and the distributed constant line L1 are connected in series between the input terminal Tin and the node N2. Distributed constant lines L2, L3 and a capacitor C3 are connected in series between the distributed constant line Ld and the output terminal Tout. A distributed constant line L4 and a capacitor C2 are connected in series between a node between the distributed constant line Ld and L2 and the ground. A drain bias terminal Tvd is connected to a node between the distributed constant line L4 and the capacitor C2. A distributed constant line L5 is connected as an open stub to a node between the distributed constant lines L2 and L3.

  The capacitors C1 to C3 mainly function as DC cut capacitors. The distributed constant line L1 functions as a gate matching circuit together with the distributed constant line Lg and the capacitor Cg. The distributed constant lines L2 to L5 function as a drain matching circuit together with the distributed constant line Ld. The distributed constant line L4 also functions as a choke for blocking high frequency signals.

Table 1 shows examples of the line length of the distributed constant line used in the second embodiment, the capacitance value of the capacitor, the resistance value of the resistor, the finger width of the transistor, and the number of fingers. The distributed constant line has a characteristic impedance of 50 Ω. The FTE 10 is a HEMT (High Electron Mobility Transistor) using AlGaAs and InGaAs. The gate length of the FET 10 is 0.1 μm. Six fingers with a gate width of 50 μm are used.

  According to the second embodiment, it is possible to provide a stable amplification circuit whose gate bias voltage can be controlled from the outside with an amplification band of 57 GHz to 66 GHz. The filter circuit 12 functions as an impedance matching circuit for high frequency signals of 57 GHz or more and 66 GHz or less. The filter circuit 14 removes an intermediate frequency signal of 1 GHz or more and less than 50 GHz input to the input terminal Tin. The filter circuit 16 removes low frequency signals of less than 1 GHz input to the input terminal Tin.

  In the first and second embodiments, the transistor is an FET, the source is a first terminal, the drain is a second terminal, and the gate is a control terminal. The transistor is a bipolar transistor, and the first terminal is an emitter. The terminal may be a collector and the control terminal may be a base.

  It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is indicated not by the meaning described above but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

10 FET
12-16 Filter Circuit 20-28 Arrow

Claims (3)

A transistor having a control terminal connected to the input terminal, a first terminal connected to the reference potential, and a second terminal connected to the output terminal;
A first filter circuit having a first capacitor having one end connected to the node between the control terminal and the input terminal and the other end connected to a reference potential;
A first resistor whose one end is connected to the node and a second capacitor whose one end is connected to the other end of the first resistor and the other end to a reference potential, and between the node and the reference potential A second filter circuit connected in parallel with the first filter circuit,
A third filter circuit having a second resistor having one end connected to the node and the other end connected to the bias terminal, and a third resistor having one end connected to the node and the other end connected to a reference potential;
Equipped with
The impedance of the first filter circuit in the high frequency band is lower than the impedance of the second filter circuit and the third filter circuit in the high frequency band,
The impedance of the third filter circuit in a low frequency band lower in frequency than the high frequency band is lower than the impedance of the first filter circuit and the second filter circuit in the low frequency band,
The impedance of the second filter circuit in an intermediate frequency band lower in frequency than the high frequency band and higher in frequency than the low frequency band is an electron lower than the impedance of the first filter circuit and the third filter circuit in the intermediate frequency band circuit. The electronic circuit according to claim 1 , further comprising a distributed constant line whose one end is connected to the node and whose other end is connected in common to one end of the first capacitor and one end of the first resistor. The transistor is a FET, said first terminal is a source, said second terminal is a drain, said control terminal electronic circuit according to claim 1 or 2, which is the gate.

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