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JP6519726B2 - Multilayer ceramic capacitor - Google Patents
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JP6519726B2 - Multilayer ceramic capacitor - Google Patents

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JP6519726B2
JP6519726B2 JP2014186314A JP2014186314A JP6519726B2 JP 6519726 B2 JP6519726 B2 JP 6519726B2 JP 2014186314 A JP2014186314 A JP 2014186314A JP 2014186314 A JP2014186314 A JP 2014186314A JP 6519726 B2 JP6519726 B2 JP 6519726B2
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剛之 矢尾
剛之 矢尾
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Description

本発明は、積層セラミックコンデンサに関し、複数の誘電体セラミック層と、誘電体セラミック層を介して積層された複数の内部電極とを有するセラミック積層体(コンデンサ本体)を具備する積層セラミックコンデンサに関する。   The present invention relates to a laminated ceramic capacitor, and more particularly to a laminated ceramic capacitor comprising a ceramic laminated body (capacitor main body) having a plurality of dielectric ceramic layers and a plurality of internal electrodes laminated via the dielectric ceramic layers.

近年、電子機器の小型・軽量化にともない、小型で、大容量を取得することが可能な積層セラミックコンデンサが広く用いられている。この積層セラミックコンデンサは、例えば、複数の誘電体層と、誘電体層間の複数の界面に配設された複数の内部電極とを有する積層体の外表面に、上記内部電極と導通するように外部電極が配設された構造を有するものが広く知られている。   2. Description of the Related Art In recent years, as the size and weight of electronic devices have decreased, multilayer ceramic capacitors that are small and capable of obtaining a large capacity are widely used. The multilayer ceramic capacitor is, for example, externally connected to an outer surface of a multilayer body having a plurality of dielectric layers and a plurality of internal electrodes disposed at a plurality of interfaces between the dielectric layers. Those having a structure in which an electrode is disposed are widely known.

そして、このような積層セラミックコンデンサとして、一般式ABO3(ただし、式中、Aは、Ba、Ca、SrおよびMgから選択される1種以上の元素であり、Bは、Ti、ZrおよびHfから選択される1種以上の元素であり、[A]/[B](モル比)が、0.990≦[A]/[B]<1.03である)で表されるペロブスカイト型結晶構造を有する化合物を含む主成分と、MgO等の第1副成分と、焼結助剤である第2副成分と、希土類Rの酸化物(ただし、RはY、Dy、Tb、GdおよびHoから選択される少なくとも一種)を含む第3副成分と、MnOを含む第4副成分と、Re(レニウム)の酸化物である第5副成分とを含み、前記主成分100モルに対し、各副成分の比率が、第1副成分:0.1〜3モル、第2副成分:0.1〜12モル、第3副成分:0.01〜10モル、第4副成分:0.05〜1.0モル、第5副成分:0.01〜1.0モルである誘電体磁器組成物を用いた誘電体層と、内部電極層とを有する積層セラミックコンデンサが提案されている。 And as such a multilayer ceramic capacitor, a general formula ABO 3 (wherein, A is one or more elements selected from Ba, Ca, Sr and Mg, and B is Ti, Zr and Hf Perovskite-type crystal represented by [A] / [B] (molar ratio) is 0.990 ≦ [A] / [B] <1.03) A main component containing a compound having a structure, a first subcomponent such as MgO, a second subcomponent which is a sintering aid, and an oxide of a rare earth R (where R is Y, Dy, Tb, Gd and Ho And a fourth subcomponent containing MnO, and a fifth subcomponent which is an oxide of Re (rhenium), and each of the main components is 100 mol The ratio of the minor component, the first minor component: 0.1 to 3 moles, the second minor component Dielectric: 0.1 to 12 mol, third subcomponent: 0.01 to 10 mol, fourth subcomponent: 0.05 to 1.0 mol, fifth subcomponent: 0.01 to 1.0 mol A multilayer ceramic capacitor having a dielectric layer using a body ceramic composition and an internal electrode layer has been proposed.

そして、この積層セラミックコンデンサの場合、誘電体層の薄層化が可能であり、製品の小型化を図ることができるとされている。   And, in the case of this laminated ceramic capacitor, it is said that thinning of the dielectric layer is possible, and the product can be miniaturized.

しかし、近年、積層セラミックコンデンサは種々の厳しい条件や環境の下で使用されるにようになっており、上記特許文献1の積層セラミックコンデンサにあっても、例えば、高温負荷信頼性などに関し、必ずしも十分な特性が確保されているとはいえず、さらに信頼性の高い積層セラミックコンデンサが求められるに至っている。   However, in recent years, multilayer ceramic capacitors have come to be used under various severe conditions and environments, and even with the multilayer ceramic capacitors of Patent Document 1, for example, high temperature load reliability etc. are not necessarily required. It can not be said that sufficient characteristics are secured, and a more reliable laminated ceramic capacitor has been required.

特開2008−254934号公報JP 2008-254934 A

本発明は、上記課題を解決するものであり、従来の積層セラミックコンデンサと比べて高温負荷信頼性の高い積層セラミックコンデンサを提供することを目的とする。   The present invention is intended to solve the above-mentioned problems, and it is an object of the present invention to provide a multilayer ceramic capacitor having high temperature load reliability as compared with a conventional multilayer ceramic capacitor.

上記課題を解決するため、本発明の積層セラミックコンデンサは、
複数の誘電体セラミック層と、前記誘電体セラミック層を介して積層された複数の内部電極とを備えるセラミック積層体と、前記内部電極と導通するように前記セラミック積層体に配設された外部電極とを備えた積層セラミックコンデンサであって、
前記誘電体セラミック層は、BaとTiとを含むペロブスカイト型化合物と、Caと、Mnと、Vとを含有し、
Ti=100モル%に対して、
Ca=0.44モル%以下であり、
V=0.1〜0.45モル%であり、
前記ペロブスカイト型化合物の結晶粒子の中央部にはCaが含まれておらず、
下記の式(1)により求められる、Caのモル量の、MnとVの合計モル量に対する割合が、10〜57%の範囲にあることを特徴としている。
Caのモル量の、MnとVの合計モル量に対する割合(%)={Caモル量/(Mnモル量+Vモル量)}×100 ……(1)
In order to solve the above problems, the multilayer ceramic capacitor of the present invention is
A ceramic laminate comprising a plurality of dielectric ceramic layers and a plurality of internal electrodes laminated via the dielectric ceramic layer, and an external electrode disposed on the ceramic laminate so as to be conductive to the internal electrodes A laminated ceramic capacitor comprising
The dielectric ceramic layer contains a perovskite type compound containing Ba and Ti, Ca, Mn and V.
For Ti = 100 mol%,
Ca = 0.44 mol% or less,
V = 0.1 to 0.45 mol%,
The central part of the crystal particle of the perovskite type compound does not contain Ca,
It is characterized in that the ratio of the molar amount of Ca to the total molar amount of Mn and V obtained by the following formula (1) is in the range of 10 to 57 %.
Ratio (%) of the molar amount of Ca to the total molar amount of Mn and V = {Ca molar amount / (Mn molar amount + V molar amount)} × 100 (1)

また、本発明の積層セラミックコンデンサにおいては、前記式(1)により求められる、前記Caのモル量の、MnとVの合計モル量に対する割合が、30〜57%であることが望ましい。 Further, in the laminated ceramic capacitor of the present invention, it is preferable that the ratio of the molar amount of Ca to the total molar amount of Mn and V, which is determined by the formula (1), be 30 to 57 %.

Caのモル量の、MnとVの合計モル量に対する割合を適正な割合(30〜57%)とすることにより、誘電体セラミック層の粒界やシェル部の絶縁性、信頼性が向上する。その結果、積層セラミックコンデンサの信頼性を向上させることが可能になる。 By setting the ratio of the molar amount of Ca to the total molar amount of Mn and V to an appropriate ratio (30 to 57 %), the insulation and reliability of the grain boundary and shell portion of the dielectric ceramic layer are improved. As a result, the reliability of the multilayer ceramic capacitor can be improved.

また、前記内部電極の平均厚みが、0.5μm以下であることが望ましい。   The average thickness of the internal electrode is preferably 0.5 μm or less.

内部電極層の厚みを0.5μm以下に設定することで、さらに高温負荷信頼性が向上する。   By setting the thickness of the internal electrode layer to 0.5 μm or less, the high temperature load reliability is further improved.

例えば、内部電極がNiから形成されている場合、内部電極の厚みが厚くなると、Niの誘電体セラミック層中への拡散が多くなり、Ca、Mn、Vを適切な割合で存在させることにより得られる上述の効果が阻害され、高温負荷信頼性が低下することになる。   For example, in the case where the internal electrode is formed of Ni, when the thickness of the internal electrode is increased, the diffusion of Ni into the dielectric ceramic layer is increased, which is obtained by causing Ca, Mn, and V to be present in an appropriate ratio. The above-described effects are hampered and the high temperature load reliability is reduced.

これに対し、内部電極層の厚みを0.5μm以下にすることにより、Ca、Mn、Vを適切な割合で存在させることによる、誘電体セラミック層の粒界やシェル部の絶縁性、信頼性を向上させるという効果を損なわないようにすることが可能になり、信頼性の高い積層セラミックコンデンサを提供することができるようになる。   On the other hand, by setting the thickness of the internal electrode layer to 0.5 μm or less, the presence of Ca, Mn, and V in an appropriate ratio causes the insulation and reliability of the grain boundary and shell portion of the dielectric ceramic layer. As a result, it is possible to maintain the effect of improving the reliability of the laminated ceramic capacitor and to provide a highly reliable multilayer ceramic capacitor.

本発明の積層セラミックコンデンサは、誘電体セラミック層が、BaとTiとを含むペロブスカイト型化合物と、Caと、Mnと、Vとを含有し、かつ、下記の式(1):
Caのモル量の、MnとVの合計モル量に対する割合(%)={Caモル量/(Mnモル量+Vモル量)}×100 ……(1)
で求められる、Caのモル量の、MnとVの合計モル量に対する割合が、10〜80%の範囲となるようにしているので、粒界やシェル部の絶縁性、信頼性を向上させることができる。
その結果、高温負荷信頼性の高い積層セラミックコンデンサを提供することができる。
In the multilayer ceramic capacitor of the present invention, the dielectric ceramic layer contains a perovskite type compound containing Ba and Ti, Ca, Mn, and V, and the following formula (1):
Ratio (%) of the molar amount of Ca to the total molar amount of Mn and V = {Ca molar amount / (Mn molar amount + V molar amount)} × 100 (1)
Since the ratio of the molar amount of Ca to the total molar amount of Mn and V, which is determined in the above, is in the range of 10 to 80%, the insulation and reliability of the grain boundary and the shell are improved. Can.
As a result, it is possible to provide a multilayer ceramic capacitor with high temperature load reliability.

なお、本発明により、高温負荷信頼性が向上するメカニズムは必ずしも明確ではないが、以下のように推測される。   Although the mechanism by which the high temperature load reliability is improved by the present invention is not necessarily clear, it is presumed as follows.

Mn、Vは絶縁抵抗を確保するために添加しているが、酸素空孔を増やす傾向があり、多すぎると信頼性が低下する。一方、Caは酸素空孔を減らす傾向がある。そこで、Ca/(Mn+V)値を制御する、例えば10%以上とすることで、酸素空孔の形成が適度な範囲に抑制される結果、高温負荷信頼性が向上するのではないかと考えられる。
また、Mn、Vは焼結性を促進するが、Caは焼結性を低下させる。よって、Ca/(Mn+V)値が80%よりも大きくなると、焼結性が低下し、信頼性が低くなると考えられる。
Although Mn and V are added to secure insulation resistance, they tend to increase the number of oxygen vacancies, and when too large, the reliability is lowered. On the other hand, Ca tends to reduce oxygen vacancies. Therefore, by controlling the Ca / (Mn + V) value to, for example, 10% or more, the formation of oxygen vacancies is suppressed to an appropriate range, and it is considered that the high temperature load reliability may be improved.
Mn and V promote sinterability, but Ca lowers sinterability. Therefore, when the Ca / (Mn + V) value is greater than 80%, the sinterability is considered to be reduced and the reliability is lowered.

したがって、本発明のように、Ca/(Mn+V)値を10%以上、80%以下とすることにより、高温負荷信頼性の高い積層セラミックコンデンサを得るとが可能になる。   Therefore, by setting the Ca / (Mn + V) value to 10% or more and 80% or less as in the present invention, it is possible to obtain a multilayer ceramic capacitor with high reliability in high temperature load.

本発明の実施形態にかかる積層セラミックコンデンサの構成を示す断面図である。FIG. 1 is a cross-sectional view showing a configuration of a laminated ceramic capacitor according to an embodiment of the present invention. 本発明の実施形態にかかる積層セラミックコンデンサの構成を示す斜視図である。FIG. 1 is a perspective view showing a configuration of a multilayer ceramic capacitor according to an embodiment of the present invention. 本発明の積層セラミックコンデンサの内部電極の厚みを測定する方法を説明する図である。It is a figure explaining the method to measure the thickness of the internal electrode of the laminated ceramic capacitor of this invention.

以下に本発明の実施形態を示して、本発明の特徴とするところをさらに詳しく説明する。   Hereinafter, the features of the present invention will be described in more detail by showing embodiments of the present invention.

[実施形態1]
A)誘電体原料粉末の作製
まず、主成分であるBaTiO3の出発原料として、高純度のBaCO3、TiO2の各粉末を準備し、調合した。
次に、この調合粉末をボールミルで湿式混合し、均一に分散させた後、乾燥処理を施して調整粉末を得た。
次いで、得られた調整粉末を1000℃から1200℃の温度(この実施形態では1200℃)で仮焼し、平均粒径が0.10μmの主成分粉末を得た。
Embodiment 1
A) Preparation of Dielectric Raw Material Powder First, powders of high purity BaCO 3 and TiO 2 were prepared and prepared as starting materials of BaTiO 3 which is the main component.
Next, this blended powder was wet mixed in a ball mill, dispersed uniformly, and then subjected to drying treatment to obtain a regulated powder.
Next, the obtained adjusted powder was calcined at a temperature of 1000 ° C. to 1200 ° C. (1200 ° C. in this embodiment) to obtain a main component powder having an average particle diameter of 0.10 μm.

他方、副成分として、Al23、SiO2、MgCO3、Dy23、MnO2、V25、CaCO3の各粉末を準備した。
次に、Al23、SiO2、MgCO3、Dy23、MnO2、V25、CaCO3の各粉末を、Tiに対するAl、Si、Mg、Dy、Mn、V、Caの含有量が所定となるように秤量し、上記のようにして得た主成分粉末に添加することによって、混合粉末を得た。
On the other hand, powders of Al 2 O 3 , SiO 2 , MgCO 3 , Dy 2 O 3 , MnO 2 , V 2 O 5 and CaCO 3 were prepared as additives.
Next, powders of Al 2 O 3 , SiO 2 , MgCO 3 , Dy 2 O 3 , MnO 2 , V 2 O 5 , and CaCO 3 were added to Al, Si, Mg, Dy, Mn, V, Ca with respect to Ti. The mixed powder was obtained by weighing so that the content would be predetermined and adding to the main component powder obtained as described above.

各添加成分の比率は、Ti=100モル%に対して、Dy=0.8モル%、Mg=1.1モル%、Al=0.5モル%、Si=1.3モル%となるようにした。   The ratio of each additive component is such that Dy = 0.8 mol%, Mg = 1.1 mol%, Al = 0.5 mol%, Si = 1.3 mol% with respect to Ti = 100 mol%. I made it.

また、Ca、Mn、V量は表1に示す比率で混合した。表1には、「{Caモル量/(Mnモル量+Vモル量)}×100」の値を併せて示す。   Further, the amounts of Ca, Mn and V were mixed at the ratios shown in Table 1. Table 1 also shows the value of “{Ca molar amount / (Mn molar amount + V molar amount)} × 100”.

Figure 0006519726
Figure 0006519726

次に、この混合粉末をボールミルで湿式混合し、均一に分散させた後、乾燥処理を施して、これをセラミック原料とした。このセラミック原料をICP分析したところ、調合組成と一致していることが確認された。   Next, the mixed powder was wet-mixed in a ball mill, dispersed uniformly, and then subjected to a drying treatment to obtain a ceramic raw material. ICP analysis of this ceramic raw material confirmed that it was consistent with the composition.

B)積層セラミックコンデンサの作製
次に、上記セラミック原料に、ポリビニルブチラール系バインダ、可塑剤および有機溶剤としてのエタノールを加え、これらをボールミルにより湿式混合し、セラミックスラリーを作製した。
B) Preparation of Multilayer Ceramic Capacitor Next, a polyvinyl butyral-based binder, a plasticizer and ethanol as an organic solvent were added to the above-mentioned ceramic raw material, and these were wet-mixed by a ball mill to prepare a ceramic slurry.

次いで、このセラミックスラリーをリップ方式によりシート成形し、矩形のセラミックグリーンシートを得た。   Then, the ceramic slurry was sheet-formed by a lip method to obtain a rectangular ceramic green sheet.

次に、上記セラミックグリーンシート上に、Niを含有する導電性ペーストをスクリーン印刷し、内部電極となるべき導電性ペースト膜(内部電極パターン)を形成した。   Next, a conductive paste containing Ni was screen-printed on the ceramic green sheet to form a conductive paste film (internal electrode pattern) to be an internal electrode.

次に、導電性ペースト膜が形成されたセラミックグリーンシートを、導電ペースト膜の引き出されている側が互い違いになるように複数枚積層し、コンデンサ本体となるべき未焼成の積層体を得た。   Next, a plurality of ceramic green sheets on which the conductive paste film was formed were stacked so that the drawn sides of the conductive paste film were alternately different, to obtain an unfired laminate to be a capacitor body.

次に、この積層体を、N2雰囲気中にて、300℃の温度で3時間加熱し、バインダを燃焼させた後、昇温速度100℃/min、酸素分圧10-9〜10-12MPa(この実施形態では10-9MPa)のH2−N2−H2Oガスからなる還元性雰囲気中において、1200℃で10min焼成し、コンデンサ本体である、焼結済みの積層体を得た。 Next, this laminate is heated in a N 2 atmosphere at a temperature of 300 ° C. for 3 hours to burn the binder, and then the temperature rising rate is 100 ° C./min, the oxygen partial pressure is 10 -9 to 10 -12. In a reducing atmosphere consisting of H 2 -N 2 -H 2 O gas of 10 MPa (in this embodiment, 10 -9 MPa), firing is carried out at 1200 ° C. for 10 minutes to obtain a sintered laminate which is a capacitor body. The

この積層体を溶解処理し、ICP分析を行ったところ、内部電極成分のNiを除いては、調合組成と一致していることが確認された。   The laminate was subjected to a dissolution treatment and subjected to ICP analysis, and it was confirmed that the composition was consistent with the composition except for the internal electrode component Ni.

次に、上記コンデンサ本体の両端面に、ガラスフリットを含有するCuペーストを塗布し、N2雰囲気中において、800℃の温度で焼き付け、内部電極と電気的に接続された外部電極を形成した。これにより、表1の試料番号1〜21の試料(積層セラミックコンデンサ)を得た。
この積層セラミックコンデンサの外部電極を除去した後の積層体を酸により溶解処理し、ICP発光分光分析を行った。その結果、内部電極成分のNiを除いては、調合組成と一致していることが確認された。
Next, a Cu paste containing a glass frit was applied to both end surfaces of the capacitor body, and baked at a temperature of 800 ° C. in an N 2 atmosphere to form an external electrode electrically connected to the internal electrode. Thus, the samples (laminated ceramic capacitors) of sample numbers 1 to 21 in Table 1 were obtained.
The laminate after removing the external electrode of this multilayer ceramic capacitor was subjected to dissolution treatment with acid and ICP emission spectral analysis was performed. As a result, it was confirmed that the composition was consistent with the composition except for the internal electrode component Ni.

この積層セラミックコンデンサ50は、図1および図2に示すように、積層されている複数の誘電体セラミック層11と、誘電体セラミック層11間の複数の界面に配設されている複数の内部電極12とを有するセラミック積層体(コンデンサ本体)10と、セラミック積層体10の両端面に、交互に逆側の端面に引き出された内部電極12と導通するように配設された一対の外部電極13a,13bとを備えた構造を有している。なお、外部電極13a,13bには、Niめっき層、Snめっき層を備えた構成とすることも可能である。   As shown in FIGS. 1 and 2, the multilayer ceramic capacitor 50 includes a plurality of laminated dielectric ceramic layers 11 and a plurality of internal electrodes disposed at a plurality of interfaces between the dielectric ceramic layers 11. 12 and a pair of external electrodes 13a disposed on both end surfaces of the ceramic laminate 10 so as to be electrically connected to the internal electrodes 12 drawn to the opposite end surface alternately. , And 13b. In addition, it is also possible to set it as the structure provided with Ni plating layer and Sn plating layer to external electrode 13a, 13b.

このようにして得た積層セラミックコンデンサの外形寸法は、図2のL方向の寸法を長さとし、W方向の寸法を幅、T方向の寸法を厚さとした場合に、長さL=0.6mm、幅W=0.3mm、厚さT=0.3mmであった。   The external dimensions of the multilayer ceramic capacitor thus obtained are as follows: when the dimension in the L direction in FIG. 2 is the length, the dimension in the W direction is the width, and the dimension in the T direction is the thickness, the length L = 0.6 mm The width W was 0.3 mm, and the thickness T was 0.3 mm.

また、その他の条件は以下の通りであった。
1)誘電体セラミック層1層の厚み :0.8μm、
2)内部電極1層の厚み :0.6μm、
3)有効誘電体セラミック層の数 :160層、
4)1層の誘電体セラミック層あたりの対向電極面積 :0.15mm2
Other conditions were as follows.
1) Thickness of one dielectric ceramic layer: 0.8 μm,
2) Thickness of internal electrode 1 layer: 0.6 μm,
3) Number of effective dielectric ceramic layers: 160 layers,
4) Counter electrode area per dielectric ceramic layer: 0.15 mm 2

なお、積層セラミックコンデンサの、誘電体セラミック層中のチタン酸バリウム結晶粒子の中央部をTEM−EDXにより分析したところ、Caは検出されなかった。   The central portion of the barium titanate crystal particles in the dielectric ceramic layer of the multilayer ceramic capacitor was analyzed by TEM-EDX, and Ca was not detected.

なお、内部電極層の厚みは以下の方法で測定した。
まず、表1の試料番号1〜21の各試料(積層セラミックコンデンサ)をそれぞれ3個準備し、試料の長さ方向(L方向)と厚み方向(T方向)により規定される面(LT面)が露出するような態様で、各試料の周囲を樹脂で固めた。
The thickness of the internal electrode layer was measured by the following method.
First, three samples (laminated ceramic capacitors) of sample numbers 1 to 21 in Table 1 are prepared, and a surface (LT surface) defined by the length direction (L direction) and thickness direction (T direction) of the sample Each sample was hardened with resin in such a manner that

次に、研磨機により、試料のLT側面を研磨した。このとき、試料の幅方向(W方向)の1/2程度の深さまで研磨を行い、研磨面であるLT面(LT研磨端面)を露出させた。そして、研磨による内部電極のダレをなくすために、研磨終了後、イオンミリングにより研磨表面を加工した。   Next, the LT side of the sample was polished by a polisher. At this time, the sample was polished to a depth of about 1/2 of the width direction (W direction) of the sample to expose the LT surface (LT polished end face) which is a polished surface. Then, in order to eliminate sagging of the internal electrode due to polishing, the polishing surface was processed by ion milling after the completion of polishing.

研磨した試料について、内部電極の厚みを測定した。内部電極の厚みを測定するにあたっては、まず、図3に示すように、試料のLT研磨端面のL方向の1/2程度の位置において、内部電極12とほぼ直交する直線L1を引く(想定する)。
次に、試料の内部電極12が積層されている領域をT方向に3等分に分割し、上部領域、中間領域、下部領域の3つの領域に分割した。
The thickness of the internal electrode was measured for the polished sample. In order to measure the thickness of the internal electrode, first, as shown in FIG. 3, a straight line L1 substantially perpendicular to the internal electrode 12 is drawn at a position about half the L direction of the LT polishing end face of the sample (assuming ).
Next, the region in which the internal electrode 12 of the sample is stacked is divided into three equal portions in the T direction, and divided into three regions of an upper region, an intermediate region, and a lower region.

各領域の最外の内部電極を除き、各領域で、直線L1上の内部電極を無作為に15層ずつ選び、厚みを測定した。ただし、上記直線L1上で内部電極が欠損し、該内部電極を挟む誘電体セラミック層がつながっている等により測定が不可能なものは除いた。なお、内部電極層の厚みは、走査型電子顕微鏡を用いて測定した。
したがって、この実施形態1での内部電極の平均厚みは、試料数3個×3つの領域×15層=135箇所における内部電極の厚みの平均値である。
ただし、内部電極が欠落しているなどの理由で測定できない部分は測定対象から除いた。
Except for the outermost internal electrode in each region, in each region, 15 layers of the internal electrode on the straight line L1 were randomly selected, and the thickness was measured. However, the internal electrodes were broken on the straight line L1 and those which could not be measured due to the connection of the dielectric ceramic layers sandwiching the internal electrodes were excluded. The thickness of the internal electrode layer was measured using a scanning electron microscope.
Therefore, the average thickness of the internal electrode in the first embodiment is an average value of the thickness of the internal electrode at the number of samples: 3 × 3 areas × 15 layers = 135.
However, the part which can not be measured because the internal electrode was missing etc. was excluded from the measuring object.

C)特性評価
次に、表1の試料番号1〜21の各試料(積層セラミックコンデンサ)について、以下のような評価を行なった。
C) Characteristic evaluation Next, the following evaluation was performed about each sample (laminated ceramic capacitor) of the sample numbers 1 to 21 of Table 1.

(1)高温負荷試験による寿命特性の測定
各試料についてそれぞれ72個のサンプル(被検試料である積層セラミックコンデンサ)を用意した。
(1) Measurement of Lifetime Characteristics by High-Temperature Load Test For each sample, 72 samples (laminated ceramic capacitors as test samples) were prepared.

そして、高温負荷信頼性試験では、各積層セラミックコンデンサに対し、85℃において6.3Vの直流電圧を印加し、一定時間(1000hr、2000hr、3000hr、4000hr)後、室温での絶縁抵抗を確認した。各積層セラミックコンデンサの絶縁抵抗値が1MΩ以下になった時点を故障とした。   Then, in the high temperature load reliability test, a DC voltage of 6.3 V was applied at 85 ° C. to each multilayer ceramic capacitor, and after a predetermined time (1000 hr, 2000 hr, 3000 hr, 4000 hr), the insulation resistance at room temperature was confirmed. . A failure was made when the insulation resistance value of each multilayer ceramic capacitor became 1 MΩ or less.

表2に試験の結果を示す。
なお、表2における、1000hr、2000hr、3000hr、4000hrの欄は、各時間における、故障の発生した試料数と、試験に供した試料数の関係(故障の発生した試料数/試験に供した試料数)を示している。
Table 2 shows the results of the test.
The columns of 1000 hr, 2000 hr, 3000 hr and 4000 hr in Table 2 show the relationship between the number of samples in which failure occurred and the number of samples used in the test (the number of samples in failure / the number of samples generated in the test). Number is shown.

Figure 0006519726
Figure 0006519726

なお、表1および表2において、試料番号に*を付した試料は、本発明の要件を備えていない試料である。   In Tables 1 and 2, the samples with * attached to the sample numbers are samples that do not have the requirements of the present invention.

表1および表2より、本発明の要件を備えていない試料番号1〜5,10,11,16,17,19の各試料では、高温負荷信頼性試験における1000hrの時点で、故障の発生が認められた。   From Tables 1 and 2, in each of the sample numbers 1 to 5, 10, 11, 16, 17, and 19 which do not have the requirements of the present invention, occurrence of failure occurs at 1000 hours in the high temperature load reliability test. Admitted.

これに対し、本発明の要件を満たす試料の場合、高温負荷信頼性試験の1000hrの時点ではもちろん、2000hrの時点でも故障の発生は認められず、高温負荷信頼性が大幅に向上していることが確認された。   On the other hand, in the case of the sample satisfying the requirements of the present invention, occurrence of failure is not recognized not only at the time of 1000 hr of the high temperature load reliability test but also at 2000 hr, and the high temperature load reliability is significantly improved. Was confirmed.

また、本発明の要件を満たす試料の場合、高温負荷信頼性試験の3000hrおよび4000hrの時点でも、本発明の要件を備えていない試料に比べて故障の発生数が少ないことが確認された。   In the case of the sample satisfying the requirements of the present invention, it was also confirmed that the number of failures occurred less at the time of 3000 hr and 4000 hr of the high temperature load reliability test as compared with the sample not having the requirement of the present invention.

この結果から、本発明の要件を備えること、すなわち、「{Caモル量/(Mnモル量+Vモル量)}×100」の値を10〜80%の範囲とすることにより、高温負荷信頼性の高い積層セラミックコンデンサが得られることがわかる。   From this result, high temperature load reliability can be achieved by providing the requirements of the present invention, that is, by setting the value of “{Ca molar amount / (Mn molar amount + V molar amount)} × 100” to 10 to 80%. It can be seen that a high laminated ceramic capacitor can be obtained.

[実施形態2]
焼成後に得られるセラミック積層体(コンデンサ本体)の内部電極の平均厚みを表3に示す範囲、すなわち、0.27〜0.73μmの範囲で変化させたことを除いては、上述の実施形態1の場合と同様にして積層セラミックコンデンサ(表3の試料番号22〜28の試料)を作製した。
Second Embodiment
Except that the average thickness of the internal electrodes of the ceramic laminate (capacitor body) obtained after firing is changed in the range shown in Table 3, ie, 0.27 to 0.73 μm, Embodiment 1 described above A laminated ceramic capacitor (samples of sample numbers 22 to 28 in Table 3) was produced in the same manner as in the above.

表3に、誘電体セラミック層中のCa、Mn、V量を示す。表3には、さらに「{Caモル量/(Mnモル量+Vモル量)}×100」の値、および、内部電極の厚みを併せて示す。   Table 3 shows the amounts of Ca, Mn and V in the dielectric ceramic layer. Table 3 further shows the value of “{Ca molar amount / (Mn molar amount + V molar amount)} × 100” and the thickness of the internal electrode together.

Figure 0006519726
Figure 0006519726

それから、作製した各試料について、実施形態1の場合と同じ方法、同じ条件で、高温負荷信頼性試験を行った。
その結果を表4に示す。
Then, for each of the prepared samples, a high temperature load reliability test was conducted in the same manner and under the same conditions as in Embodiment 1.
The results are shown in Table 4.

Figure 0006519726
Figure 0006519726

なお、表4における、1000hr、2000hr、3000hr、4000hrの欄は、各時間における、故障の発生した試料数と、試験に供した試料数の関係(故障の発生した試料数/試験に供した試料数)を示している。   The columns of 1000 hr, 2000 hr, 3000 hr and 4000 hr in Table 4 show the relationship between the number of samples in which failure occurred and the number of samples used in the test (the number of samples in failure / samples subjected to test) Number is shown.

表4より、内部電極の厚みが0.5μm以下の試料(試料番号25,26,27,28の試料)の場合、高温負荷信頼性試験の4000時間の時点でも故障の発生は認められず、高温負荷信頼性に特に優れた積層セラミックコンデンサが得られることが確認された。   From Table 4, in the case of the sample of which the thickness of the internal electrode is 0.5 μm or less (sample of sample numbers 25, 26, 27, 28), no occurrence of failure is recognized even at 4000 hours of the high temperature load reliability test. It has been confirmed that a multilayer ceramic capacitor having particularly excellent high temperature load reliability can be obtained.

したがって、本発明の積層セラミックコンデンサにおいて、さらに優れた高温負荷信頼性を望む場合には、内部電極の厚みを0.5μm以下とすることが望ましい。   Therefore, in the laminated ceramic capacitor of the present invention, in order to obtain further excellent high temperature load reliability, it is desirable to set the thickness of the internal electrode to 0.5 μm or less.

なお、本発明は上記実施形態に限定されるものではなく、発明の範囲内において種々の応用、変形を加えることが可能である。   The present invention is not limited to the above embodiment, and various applications and modifications can be made within the scope of the invention.

10 コンデンサ本体(セラミック積層体)
11 誘電体セラミック層
12 内部電極
13a,13b 外部電極
50 積層セラミックコンデンサ
L 積層セラミックコンデンサの長さ
T 積層セラミックコンデンサの高さ
W 積層セラミックコンデンサの幅
10 Capacitor body (Ceramic laminated body)
DESCRIPTION OF SYMBOLS 11 dielectric material ceramic layer 12 internal electrode 13a, 13b external electrode 50 laminated ceramic capacitor L length of laminated ceramic capacitor T height of laminated ceramic capacitor W width of laminated ceramic capacitor

Claims (3)

複数の誘電体セラミック層と、前記誘電体セラミック層を介して積層された複数の内部電極とを備えるセラミック積層体と、前記内部電極と導通するように前記セラミック積層体に配設された外部電極とを備えた積層セラミックコンデンサであって、
前記誘電体セラミック層は、BaとTiとを含むペロブスカイト型化合物と、Caと、Mnと、Vとを含有し、
Ti=100モル%に対して、
Ca=0.44モル%以下であり、
V=0.1〜0.45モル%であり、
前記ペロブスカイト型化合物の結晶粒子の中央部にはCaが含まれておらず、
下記の式(1)により求められる、Caのモル量の、MnとVの合計モル量に対する割合が、10〜57%の範囲にあることを特徴とする積層セラミックコンデンサ。
Caのモル量の、MnとVの合計モル量に対する割合(%)={Caモル量/(Mnモル量+Vモル量)}×100……(1)
A ceramic laminate comprising a plurality of dielectric ceramic layers and a plurality of internal electrodes laminated via the dielectric ceramic layer, and an external electrode disposed on the ceramic laminate so as to be conductive to the internal electrodes A laminated ceramic capacitor comprising
The dielectric ceramic layer contains a perovskite type compound containing Ba and Ti, Ca, Mn and V.
For Ti = 100 mol%,
Ca = 0.44 mol% or less,
V = 0.1 to 0.45 mol%,
The central part of the crystal particle of the perovskite type compound does not contain Ca,
Obtained by Equation (1) below, the molar amount of Ca, the ratio of the total molar amount of Mn and V, multilayer ceramic capacitors, characterized in that in the range of 10-57%.
Ratio (%) of the molar amount of Ca to the total molar amount of Mn and V = {Ca molar amount / (Mn molar amount + V molar amount)} × 100 (1)
前記式(1)により求められる、前記Caのモル量の、MnとVの合計モル量に対する割合が、30〜57%であることを特徴とする請求項1記載の積層セラミックコンデンサ。 The ratio of the molar amount of said Ca calculated | required by said Formula (1) with respect to the sum total molar amount of Mn and V is 30 to 57 %, The laminated ceramic capacitor of Claim 1 characterized by the above-mentioned. 前記内部電極の平均厚みが0.5μm以下であることを特徴とする請求項1または2記載の積層セラミックコンデンサ。   The average thickness of the said internal electrode is 0.5 micrometer or less, The multilayer ceramic capacitor of Claim 1 or 2 characterized by the above-mentioned.
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