JP6520754B2 - Method of predicting occurrence of slip dislocation, method of manufacturing silicon wafer using the method, method of heat treating silicon wafer, and silicon wafer - Google Patents

Description

  The present invention relates to a method for predicting the occurrence of slip dislocations, a method for producing a silicon wafer using the method, a heat treatment method for a silicon wafer, and a silicon wafer.

  For example, oxygen which is inevitably contained in a polished wafer produced by the Czochralski (CZ) method is a gettering site where some of the oxygen is deposited during heat treatment in a wafer manufacturing process or a device manufacturing process to capture heavy metals. Is formed.

  Here, when the heat treatment is performed on the silicon wafer, oxygen contained in the wafer reacts with the silicon to generate an oxygen deposit (Bulk Micro Defect, BMD). It is known that if this oxygen precipitation progresses excessively, the mechanical strength of the silicon wafer is reduced, and even if only a low thermal stress is applied to the silicon wafer, slip dislocations are generated and the wafer is warped. See, for example, Non-Patent Documents 1 and 2.

  Since the occurrence of such slip dislocations reduces the yield of silicon devices, it is important to prevent the occurrence of slip dislocations even when heat treatment is performed in a wafer manufacturing process or device fabrication process.

  Therefore, Patent Document 1 describes that by reducing the BMD size, the critical shear stress of slip dislocations generated from the BMD is increased, and the reduction in strength of the silicon wafer due to the precipitation of oxygen is suppressed. Further, Patent Document 2 describes that forming a BMD having a small size at a high density in a wafer and suppressing the density of the BMD having a large size to a low level is effective for suppressing the occurrence of slip dislocations. ing.

Furthermore, the present inventors have found that the critical shear stress tau _cri slip dislocation occurs in the device manufacturing step, the ratio Co / L of residual oxygen concentration Co to the size L of the oxygen precipitates in the wafer that has undergone a heat treatment performed in the wafer production process In Patent Document 3, in order to prevent slip dislocations from being generated in the device fabrication process, critical shear stress and residual stress that cause a silicon wafer to slip are disclosed in Patent Document 3. The relationship between the oxygen concentration Co and the size L of the oxygen precipitates is determined in advance, and a suitable heat treatment is applied to the silicon wafer in the wafer manufacturing process from the temperature conditions of the device manufacturing process and the thermal stress to which the silicon wafer is subjected. Suggested that.

International Publication No. 2006/003812 JP, 2008-103673, A JP, 2011-238664, A

B. Leroy and C. Plougonven, Journal of the Electrochemical Society, 1980, Vol. 127, p. 961 Hirofumi Shimizu, Tetsuo Watanabe and Yoshiharu Kakui, Japanese Journal of Applied Physics, 1985, Vol. 24, p. 815 Koji Sueoka, Masanori Akatsuka, Hisashi Katahama and Naoshi Adachi, Japanese Journal of Applied Physics, 1997, Vol. 36, p. 7095

  By the way, it is known that the above-mentioned slip dislocation also occurs from a scratch formed on the wafer surface as a starting point in addition to oxygen precipitates (see, for example, WO 2010/109873). Such scratches on the surface of the wafer are formed on the outer peripheral portion of the wafer by coming into contact with different materials such as wafer holders in the wafer manufacturing process and the device manufacturing process. It is in a difficult situation.

  Therefore, under the premise that such a scratch exists, it is important to prevent slip dislocation from being generated from the scratch on the wafer surface in the wafer manufacturing process and the device manufacturing process. For this purpose, when a predetermined heat treatment is performed in a wafer manufacturing process or a device manufacturing process, it is necessary to correctly determine whether or not slip dislocation occurs from a flaw on the wafer surface.

  However, the quantitative relationship between the occurrence of slip dislocation from a flaw on the wafer surface and the stress applied to the wafer is not clear, and when the predetermined heat treatment is performed in the wafer manufacturing process or device manufacturing process, the wafer surface A method has not been established that can predict with high accuracy whether slip dislocations will occur from the above scratches.

  Therefore, it is an object of the present invention to predict slip dislocation generation which can predict with high accuracy whether slip dislocations will be generated from scratches on the wafer surface during predetermined heat treatment in a wafer manufacturing process or device manufacturing process, the method It is an object of the present invention to propose a silicon wafer manufacturing method, a silicon wafer heat treatment method, and a silicon wafer.

  The present inventors diligently researched ways to solve the above problems. For that purpose, first, the relationship between the scratch on the wafer surface and the occurrence of slip dislocation was investigated in detail. As a result, it was found that the slip dislocation did not occur from all the flaws but only from the flaws accompanied by the cracks.

The present inventors further, critical shear stress τ _cri where slip dislocations are generated from scratches accompanied by the cracks, area A of slip dislocations after predetermined heat treatment in wafer manufacturing process and device manufacturing process, and oxygen concentration in silicon wafer This predetermined shear stress can be determined with high accuracy based on C _o , and the above-mentioned predetermined shear stress τ _cri is compared with the stress τ given to the silicon wafer at the time of predetermined heat treatment in the wafer manufacturing process and device manufacturing process. It has been found that it can be determined with high accuracy whether or not slip dislocation occurs from a flaw on the wafer surface during heat treatment, and the present invention has been completed.

That is, the gist configuration of the present invention is as follows.
(1) The area of the crack and the oxygen concentration in the silicon wafer in the flaw accompanied by the crack present on the outer peripheral surface of the silicon wafer subjected to the predetermined heat treatment are determined, and then the area of the crack and the oxygen concentration determined Based on the above, after determining the critical shear stress τ _{cri at} which slip dislocation is generated from the scratch during the predetermined heat treatment, the determined critical shear stress τ _cri and the thermal stress τ applied to the silicon wafer during the predetermined heat treatment In the case where the thermal stress τ is equal to or greater than the critical shear stress τ _cri , it is determined that a slip dislocation is generated from a flaw on the outer peripheral surface of the silicon wafer during the predetermined heat treatment in the silicon wafer. If the stress tau is below the critical shear stress tau _cri, in a silicon wafer, when the predetermined heat treatment Generating prediction method of slip dislocations and judging from the wound on the outer periphery of the wafer surface and the slip dislocation is not generated.

(2) The critical shear stress τ _cri is A: area of the crack, C 2 _O : concentration of oxygen, T: temperature of the heat treatment, ε: strain rate, k: Boltzmann's constant, a, b and c: constants The slip dislocation generation prediction method according to (1), given by the following formula (i).

(3) The slip dislocation generation prediction method according to (2), wherein a is 4.5, b is 5442, and c is 7.9 × 10 ⁻⁴ .

(4) The process for determining the area A of the crack and the oxygen concentration _CO is performed by subjecting the silicon wafer to the predetermined heat treatment, and then the area of the crack and the oxygen in the silicon wafer after the predetermined heat treatment The slip dislocation generation prediction method according to any one of the above (1) to (3), which is carried out by measuring the concentration.

(5) The process of determining the area A of the crack is performed by performing the predetermined heat treatment on the silicon wafer and then measuring the area of the crack in the silicon wafer after the predetermined heat treatment, and the predetermined The process for determining the oxygen concentration C 2 _O after the heat treatment of is performed by simulation calculation, and the slip dislocation generation prediction method according to any one of the above (1) to (3).

(6) Any one of the above (1) to (5), wherein the thermal stress τ is obtained based on the temperature distribution in the radial direction of the heated silicon wafer by charging the silicon wafer into a heat treatment apparatus and heating it. The method for predicting the occurrence of slip dislocation according to one item.

(7) The slip dislocation generation prediction method according to any one of (1) to (5), wherein the thermal stress τ is obtained by simulation calculation.

(8) Single crystal under growth conditions by which a silicon wafer is obtained which is judged not to generate slip dislocation from a flaw accompanied by a crack at the time of the predetermined heat treatment by the slip dislocation generation prediction method according to (1) to (7) A method of manufacturing a silicon wafer comprising: growing a silicon ingot; and subjecting the grown single crystal silicon ingot to a wafer processing process.

(9) The method for producing a silicon wafer according to (8), wherein the oxygen concentration after the predetermined heat treatment is 5 × 10 ¹⁷ atoms / cm ³ or more and 20 × 10 ¹⁷ atoms / cm ³ or less.

(10) The predetermined method for the silicon wafer such that it is determined that the slip dislocation does not occur from the flaw accompanied by the crack during the predetermined heat treatment according to the slip dislocation generation prediction method described in the above (1) to (7) A heat treatment method of a silicon wafer characterized by applying a heat treatment of

  According to the present invention, since critical shear stress which causes slip dislocation from a scratch on the wafer surface can be determined with high accuracy at the time of the predetermined heat treatment in the wafer manufacturing process and the device manufacturing process. Whether or not slip dislocation occurs can be predicted with high accuracy from the damage of

1 is a flowchart of an embodiment of a slip dislocation occurrence prediction method according to the present invention. It is a figure explaining the definition of the area of a crack. (A) The schematic diagram explaining a high temperature 4 point | piece bending test, and (b) It is a figure which shows the stress distribution given in a sample piece in a high temperature 4 point | piece bending test. It is a SEM image which shows a mode that a slip does not generate | occur | produce from (a) the crack which does not accompany a crack, and a SEM image which shows a mode that a slip occurs from the wound with a (b) crack. It is a figure explaining a high temperature 3 point | piece bending test. It is a figure which shows the relationship between indentation load and critical shear stress. It is a figure which shows the relationship between the reciprocal number of the area of a crack, and a critical shear stress. It is a figure which shows the relationship of the experimental value of critical shear stress, and a calculated value. It is a flowchart of one Embodiment of the manufacturing method of the silicon wafer which concerns on this invention. It is a flowchart of one Embodiment of the heat processing method of the silicon wafer which concerns on this invention. The present invention is a diagram showing that it is possible to predict with high accuracy whether or not slip dislocation occurs from a flaw accompanied by a crack on a wafer surface at a predetermined heat treatment.

(Method to predict slip dislocation occurrence)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a flow chart of an embodiment of the slip dislocation occurrence prediction method according to the present invention. First, in step S1, a silicon wafer subjected to a predetermined heat treatment is prepared.

  In the present invention, "predetermined heat treatment" means any heat treatment in a wafer manufacturing process and a device manufacturing process. In addition to the heat treatment intentionally performed such as the heat treatment in the device manufacturing process and the heat treatment for producing an annealed wafer, “heat treatment” is, for example, a silicon wafer as a substrate when producing an epitaxial wafer. Treatments such as exposure to high temperature environments (e.g., 900 ° C. to 1150 ° C.), formation of an epitaxial layer, etc. are also included.

  In addition, the silicon wafer itself is subjected to well-known outer peripheral grinding, slicing, lapping, etching, mirror polishing processing on a single crystal silicon ingot grown by the CZ method or the Floating Zone (FZ) method. What has predetermined thickness obtained by applying can be used.

  In the growth of the single crystal silicon ingot, the oxygen concentration, the carbon concentration, the nitrogen concentration, and the like can be appropriately adjusted so that the silicon wafer collected from the grown silicon ingot has desired characteristics. Further, with regard to the conductivity type, an appropriate dopant can be added to make it n-type or p-type.

  Next, in step S2, the area of the crack in the flaw accompanied by the crack present on the outer peripheral surface of the silicon wafer subjected to the predetermined heat treatment and the oxygen concentration in the silicon wafer are determined. Here, “the area of a crack” means the area between the tips of adjacent cracks in a crack accompanied with a crack when observing the surface of the outer peripheral part of a silicon wafer using a scanning electron microscope (SEM). Means the area of the polygon formed by connecting

  FIG. 2 is a diagram for explaining the definition of the area of a crack. As shown in this figure, the tips of adjacent cracks are connected to form a polygon (a square in the figure), and the area of this square is taken as the area of the crack.

  In addition, the oxygen concentration in the silicon wafer can be measured by a Fourier transform infrared spectrometer (FT-IR) in accordance with the infrared absorption method defined in ASTM F121-1979.

  The area of the crack “after the predetermined heat treatment” is a silicon wafer subjected to a predetermined heat treatment performed in a wafer manufacturing process or a device manufacturing process, or a heat treatment simulating such a predetermined heat treatment after the heat treatment It can obtain | require by measuring the area of a crack. Such heat treatment can be performed using a rapid thermal annealing (RTA) apparatus or the like.

  In general, the heat treatment performed in the device manufacturing process is composed of a plurality of steps, and in each step, the temperature is raised from the start temperature to a predetermined heat treatment temperature, and then held for a certain time, and then lowered to the end temperature Do the process. In the present invention, when the heat treatment applied in the device manufacturing process is constituted by a plurality of steps, the temperature of the step of giving the highest thermal stress τ is taken as the heat treatment temperature.

  In addition, the oxygen concentration is the same as in the case of obtaining the area of the crack, the silicon wafer is actually subjected to a heat treatment applied in a wafer manufacturing process or a device manufacturing process, or a heat treatment simulating such a heat treatment Oxygen concentration can be measured and determined. Alternatively, it can be determined by simulation calculation without actually performing predetermined heat treatment in a wafer manufacturing process or a device manufacturing process on a silicon wafer.

  Specifically, based on data of oxygen concentration (initial oxygen concentration), thermal history during growth, and dopant concentration in a single crystal silicon ingot grown under predetermined conditions, known numerical analysis techniques (for example, Sumio) (See Kobayashi, Journal of Crystal Growth, 1997, Vol. 174, p. 163). By such simulation calculation, the oxygen concentration after the predetermined heat treatment can be determined easily and in a short time as compared with the case where the heat treatment is actually performed on the silicon wafer.

  Subsequently, in step S3, based on the area of the crack and the oxygen concentration obtained in step S2, a critical shear stress causing slip dislocation originating from the crack in the silicon wafer during the predetermined heat treatment is determined. As described above, the present inventors have found that among the scratches on the wafer surface, slip dislocations are generated only from cracks accompanied by cracks. Hereinafter, the high temperature four-point bending test which led to this knowledge will be described.

  As shown in FIG. 3A, the “high-temperature four-point bending test” is a test method in which two action points for applying stress to the sample piece are used at two points with respect to the two supporting points supporting the sample piece. As shown in 3 (b), a constant stress can be applied to the sample piece. Therefore, it is an effective method to confirm the occurrence and non-occurrence of slip dislocation.

  Specifically, the high-temperature four-point bending test was performed as follows. First, the silicon wafer was subjected to heat treatment using a heat treatment furnace of a type supporting the outer peripheral portion, to prepare a silicon wafer in which various scratches were introduced in the outer peripheral portion. From this silicon wafer, a 14 mm × 40 mm sample piece including the outer periphery of the wafer was cut out, and the obtained sample piece was placed on a support rod with a distance between supporting points of 30 mm. The sample piece was introduced into a heat treatment furnace (not shown) and heated to 850 ° C., and then a stress of 28 MPa was applied to the sample piece. Thereafter, the temperature in the furnace was lowered to normal temperature, then the sample piece was taken out from the heat treatment furnace, and the surface of the sample piece was observed by SEM.

  The result of the obtained SEM observation is shown in FIG. Here, FIG. 4A shows an SEM image of a scratch in which slip dislocation has not occurred, and FIG. 4B shows a SEM image of a scratch in which slip dislocation has occurred. As shown in FIG. 4 (b), while the cracks are clearly present in the scratch where the slip dislocation is generated, the slip dislocation is generated as shown in FIG. 4 (a). It was found that no flaws were present in the cracks. In other words, it can be said that slip dislocation occurs only from a flaw accompanied by a crack.

  Next, the inventors conducted a high-temperature three-point bending test to determine the critical shear stress at which slip dislocation occurs from a crack accompanied by a crack. The “high-temperature three-point bending test” is a method capable of applying stress to a sample piece at any temperature, and at that temperature, the critical shear stress at which slip dislocation is generated from a flaw on the surface of the sample piece is determined. be able to. The high-temperature three-point bending test is different from the high-temperature four-point bending test in that the action point is one point with respect to two supporting points.

  Specifically, the high temperature three-point bending test was performed as follows. First, a sample of a silicon wafer having a predetermined oxygen concentration is prepared, and a 14 mm × 40 mm sample piece is cut out from this sample, and then a Vickers hardness tester is used on one surface of the sample piece as shown in FIG. A predetermined indentation load was applied to form indentations at a pitch of 1 mm. At that time, it was confirmed that cracks were formed in all the indentations.

The sample piece thus having an indentation formed thereon was placed on a support rod of 30 mm between fulcrums as shown in FIG. Subsequently, the arranged sample pieces were introduced into a heat treatment furnace (not shown), and stress of 250 MPa at 700 ° C., 100 MPa at 850 ° C., 50 MPa at 1000 ° C., and 30 MPa at 1150 ° C. was applied. At that time, the strain rate was set to 5.3 × 10 ⁻⁶ / cm ² . Thereafter, the temperature was lowered to room temperature, the sample piece was taken out from the heat treatment furnace, the surface of the sample piece was observed by SEM, and an indentation in which slip dislocation occurred was identified. Since the slip dislocation occurs in a band centered on the action point, this band width was measured. The critical stress at which slip dislocation occurs, ie, the critical shear stress τ _{cri at which} slip dislocation occurs from a crack accompanied by a crack, can be determined by the following equation (1) because it is stress applied to the tip of the band.

Here, τ _max is the maximum shear stress applied to the sample piece in the test, L is the distance between supporting points, and X is the band width of the slip dislocation. In this test, the applied load was read using a load cell and converted to shear stress. Since slip dislocations in silicon occur in the <110> direction in the (111) plane, taking it into consideration, the maximum shear stress τ _max was determined by the following equation.
Here, P is the maximum load read by the load cell, b is the width of the sample piece, and d is the thickness of the sample piece. The maximum shear stress τ _max was calculated by this method, and the distance between supporting _points and the band width of the slip dislocation were measured to calculate the critical shear stress τ _cri .

The calculation of the critical shear stress τ _cri is based on four levels of wafer oxygen concentration Co (5, 10, 15 and 20 × 10 ¹⁷ atoms / cm ³ , ASTM 1979), and six levels of indentation load (1, 10, 50, 100). , 200, 500 gf) and four levels of heat treatment temperature T (700, 850, 1000 and 1150 ° C.).

FIG. 6 shows the relationship between the indentation load and the critical shear stress τ _cri obtained by the high-temperature three-point bending test. It can be seen from this figure that as the indentation load increases, the critical shear stress τ _cri decreases. It can also be seen that the critical shear stress τ _cri increases as the oxygen concentration C 2 _O increases.

As the indentation load at the time of forming the indentation on the sample piece increases by SEM observation, the size of the crack formed in the indentation also increases. Therefore, the present inventors set parameters related to the size of the crack, We considered that it is possible to relate the critical shear stress τ _cri generated from a crack with a crack, and examined appropriate parameters related to the size of the crack. As a result, it was considered that the "area of crack" defined as described above was optimum.

FIG. 7 shows the relationship between the reciprocal of the area A of the crack and the critical shear stress τ _{cri at} which a slip dislocation is generated from the flaw accompanied by the crack. As shown in this figure, it can be seen that the critical shear stress τ _cri of slip dislocation is proportional to the reciprocal of the area A of the crack. From the relationship between 1 / A and τ _cri shown in this figure, the present inventors considered that the shear stress τ _A exerted by the area A of the crack can be expressed by the following equation (1).

Here, a and b are constants, T is temperature, and A is the area of the crack.

On the other hand, the influence of the change of the oxygen concentration C 2 _{O on} the critical shear stress τ _cri can be regarded as the behavior of the stress (locking force) to which the oxygen adheres as the slip dislocation generated from the crack accompanied with the crack. The locking force can be expressed by the following equation (4).
Here, c is a constant, ε is a strain rate, k is a Boltzmann constant, and T is a temperature.

By combining these two equations, it is considered that it is possible to express the critical shear stress τ _cri which causes slip dislocation from a flaw accompanied by a crack. For example, τ _cri can be expressed as the product of τ _A and τ _SL . However, in this case, since the oxygen concentration C _O critical shear stress tau _cri becomes 0, slip dislocation without load stress is generated in the case of 0, which is physically unnatural. Therefore, the present inventors considered to formulate τ _cri as the sum of τ _A and τ _SL . That is, the critical shear stress τ _cri is formulated as the following equation (5).

In the above equation (5), the critical shear stress τ _{cri which} causes slip dislocation during predetermined heat treatment in a wafer manufacturing process or device fabrication process is a stress component required to generate slip dislocation from a crack in a flaw on the wafer surface. This is expressed as the sum of τ _A and the generated slip dislocations as a stress component τ _SL for release from the adhesion due to oxygen in the vicinity of the crack, which is a physically very natural expression. Then, as described later, the critical shear stress τ _{cri in} which the slip dislocation is generated from the crack at the scratch on the wafer surface can be predicted with extremely high accuracy by the above-mentioned equation (5).

As a result of _{finding the} constants a, b and c in the above equation (5) by regression analysis, the critical shear stress τ _{cri at} which slip dislocation occurs in the device heat treatment step is as shown in the following equation (6).

FIG. 8 shows the relationship between the calculated value of the critical shear stress τ _cri obtained using the above equation (6) and the experimental value obtained from the above-described high-temperature three-point bending test. From this figure, it is understood that the critical shear stress τ _cri can be reproducibly calculated in the temperature range of 700 ° C. to 1150 ° C. by using the above equation (6). Therefore, in the present invention, the critical shear stress τ _{cri at} which the slip dislocation is generated from the flaw accompanied by the crack on the wafer surface is determined using the above-mentioned equation (6).

Thus, by substituting the area A of the crack obtained in step S2 and the oxygen concentration C 2 _O into the equation (6), the critical shear stress τ _{cri at} which the slip dislocation is generated from the crack on the wafer surface is highly accurate. Can be asked.

Subsequently, in step S4, the determined critical shear stress τ _cri is compared with the thermal stress τ applied to the silicon wafer during the predetermined heat treatment. Here, the thermal stress τ applied to the silicon wafer in the wafer manufacturing process and the device manufacturing process can be determined as follows. First, a silicon wafer is introduced into a heat treatment apparatus such as an RTA apparatus, and the silicon wafer is heated to apply thermal stress. Under normal RTA heating conditions, the heating distribution is adjusted so as not to cause a temperature difference in the wafer surface, but here, the heating balance is intentionally changed to generate thermal stress. Next, the temperature distribution T (r ′) in the radial direction of the silicon wafer is measured by a thermocouple. The radial and circumferential stresses are given by the following equations (7) and (8), respectively.

Where r is the radial position of the silicon wafer, R is the radius of the silicon wafer, α is the coefficient of thermal expansion, and E is the Young's modulus.

  In a single crystal such as a silicon wafer, since a plane and a direction in which slip dislocations occur are specified, analysis in consideration of the slip plane is required. Slip dislocations in silicon occur in the <110> direction in the {111} plane. Excluding the equivalent, there will be three <110> direction slips for the four {111} planes, and it is necessary to determine 12 types of shear stress.

  By converting the stress determined in the cylindrical coordinate system into the orthogonal coordinate system, shear stress in each sliding direction on each sliding surface is determined as shown in the following equation (9). However, the sliding surface is (ijk), and the sliding direction is [lmn].

  In the present invention, among the 12 types of shear stress obtained as described above, the maximum shear stress is taken as the thermal stress τ given to the silicon wafer in the predetermined heat treatment.

  The thermal stress τ applied to the silicon wafer in the predetermined heat treatment can be determined by simulation calculation instead of using the heat treatment apparatus as described above. Thereby, the thermal stress τ can be obtained simply and in a short time. Specifically, the radiant heat incident on the wafer from the heater and the heat conduction thereof are analyzed by the finite element method, and the temperature distribution in the wafer surface in the heat treatment process is determined. The thermal stress τ can be determined from the determined temperature distribution using equations (7), (8) and (9).

Thereafter, in step S4, it is determined whether or not slip dislocation is generated from a flaw accompanied by a crack on the surface of the silicon wafer during predetermined heat treatment. In the present invention, when the thermal stress τ given to the silicon wafer at the time of the predetermined heat treatment thus determined is equal to or more than the critical shear stress τ _cri determined by the equation (6), the silicon wafer at the predetermined heat treatment It is determined that a slip dislocation is generated from a crack accompanied by a crack, and it is determined that the slip dislocation is not generated from a crack accompanied by a crack even if the predetermined heat treatment is performed on the silicon wafer when the thermal stress τ falls below the critical shear stress τ _cri. Do. As shown in the later examples, according to the present invention, it can be predicted with high accuracy whether slip dislocations will be generated from scratches accompanied by cracks on the wafer surface.

When a predetermined heat treatment is performed on a plurality of silicon wafers in a heat treatment furnace in a wafer manufacturing process or a device manufacturing process, substantially the same flaws are formed on all the wafers (that is, A is the same) . In addition, when the initial oxygen concentration (the oxygen concentration at the stage of being cut out from the single crystal silicon ingot) is the same for a plurality of silicon wafers, the oxygen concentration after the predetermined heat treatment is also the same. Therefore, with respect to a plurality of silicon wafers having the same initial oxygen concentration, the critical shear stress τ _{cri at} which slip dislocations are generated from scratches accompanied by cracks is the same, and the determination result in step S4 is also the same. Therefore, for a plurality of silicon wafers having the same initial oxygen concentration, it may be determined whether slip dislocation is generated for only one wafer.

  In this way, it is possible to predict with high accuracy whether or not slip dislocation occurs from a flaw accompanied by a crack on the wafer surface during predetermined heat treatment in a wafer manufacturing process or a device manufacturing process.

(Method of manufacturing silicon wafer)
Next, a method of manufacturing a silicon wafer according to the present invention will be described. In the method of manufacturing a silicon wafer according to the present invention, the silicon wafer is determined not to generate slip dislocation from a crack accompanied by a crack during a predetermined heat treatment in a wafer manufacturing process or a device manufacturing process according to the slip dislocation generation prediction method described above. It is characterized in that a single crystal silicon ingot is grown under the obtained growth conditions, and a wafer processing process is performed on the grown single crystal silicon ingot.

  FIG. 9 shows a flow chart of an embodiment of a method of manufacturing a silicon wafer according to the present invention. Each step will be described below according to this flowchart. First, in step S11, a single crystal silicon ingot is grown. The single crystal silicon ingot can be grown by the CZ method or the Floating Zone (FZ) method. In the growth of a single crystal silicon ingot, the oxygen concentration, the carbon concentration, the nitrogen concentration, and the like can be appropriately adjusted so that the silicon wafer collected from the grown silicon ingot has desired characteristics. Further, with regard to the conductivity type, an appropriate dopant can be added to make it n-type or p-type.

  A silicon wafer having a predetermined thickness can be obtained by subjecting the grown single crystal silicon ingot to processing processing of known outer periphery grinding, slicing, lapping, etching and mirror polishing.

  The subsequent steps S12 to S14 respectively correspond to steps S2 to S4 in FIG. 1 and are steps relating to the slip dislocation generation prediction method according to the present invention described above, and the description will be omitted.

In the present invention, in step S14, it is possible to determine with high accuracy whether or not slip dislocation is generated from a flaw accompanied by a crack on the wafer surface during predetermined heat treatment in a wafer manufacturing process or device manufacturing process. When the thermal stress τ given to the silicon wafer at this time is equal to or more than the critical shear stress τ _cri determined by the equation (6), it is determined that slip dislocation occurs in the silicon wafer at the predetermined heat treatment, and the thermal stress τ is critical. If it is less than the shear stress τ _cri , it is determined that no slip dislocation occurs during the predetermined heat treatment.

  Then, a single-crystal silicon ingot is grown under growth conditions under which a silicon wafer determined to have slip dislocations not to be generated in step S14 is obtained, and a wafer processing process is performed on the grown single-crystal silicon ingot. It is possible to obtain a silicon wafer in which slip dislocation does not occur during predetermined heat treatment in a device manufacturing process.

If the thermal stress τ is greater than or equal to the critical shear stress τ _cri in step S14, the growth conditions of the single crystal silicon ingot are changed in step S15, and the single crystal silicon is reduced until the thermal stress τ falls below the critical shear stress τ _cri. The process from step S11 of growing the ingot to step S14 of determining whether slip dislocation occurs in the device manufacturing process is repeated.

The growth conditions of the single crystal silicon ingot are changed in such a manner that the critical shear stress τ _{cri for} causing slip dislocations to rise. Specifically, the oxygen concentration after the above-described predetermined heat treatment may be increased. That is, from equation (6), the higher the oxygen concentration Co, the higher the critical shear stress τ _cri . Therefore, when it is determined in step S14 that slip dislocation occurs, the conditions are adjusted so that the oxygen concentration becomes high, and a single crystal silicon ingot is grown.

The oxygen concentration C 2 _O after the predetermined heat treatment is preferably adjusted to 5 × 10 ¹⁷ atoms / cm ³ or more and 20 × 10 ¹⁷ atoms / cm ³ or less. This makes it possible to prevent the occurrence of slip dislocation even if higher stress is applied at high temperature.

  In this way, it is possible to manufacture a silicon wafer in which slip dislocation does not occur from a flaw accompanied by a crack at a predetermined heat treatment in a wafer manufacturing process or a device manufacturing process.

(Heat treatment method of silicon wafer)
Then, the heat treatment method of the silicon wafer concerning the present invention is explained. The heat treatment method for a silicon wafer according to the present invention is a silicon wafer which is determined not to generate slip dislocation from a crack accompanied by a crack during a predetermined heat treatment in a wafer manufacturing process or a device manufacturing process by the slip dislocation generation prediction method described above. The silicon wafer is subjected to the above-mentioned predetermined heat treatment so as to be obtained.

  FIG. 10 shows a flow chart of an embodiment of a heat treatment method of a silicon wafer according to the present invention. Steps S21 to S23 correspond to steps S1 to S3 in FIG. 1, respectively, and are steps relating to the slip dislocation generation prediction method according to the present invention described above, and therefore the description thereof is omitted.

Subsequent to step S23, in step S24, the silicon wafer is subjected to predetermined heat treatment in the wafer manufacturing process and device manufacturing process under the condition that the thermal stress τ does not exceed the critical shear stress τ _cri . That is, the critical shear stress tau _cri slip dislocation obtained in step S23 is generated, by comparing the thermal stress tau loaded on the silicon wafer by the predetermined heat treatment, thermal stress tau is a critical shear stress tau _cri In the case where it is predicted that slip dislocations will not occur from a flaw accompanied by cracks below a crack, a predetermined heat treatment is performed under the same conditions as those for obtaining the thermal stress τ. Thereby, the heat treatment can be performed without generating slip dislocation from a flaw accompanied by a crack on the wafer surface.

On the other hand, if the thermal stress τ is equal to or higher than the critical shear stress τ _cri and slip dislocations are predicted to be generated from a flaw accompanied by a crack, the conditions are changed to those for obtaining the thermal stress τ. Find the stress again. Specifically, changing the conditions reduces the temperature increase rate of the heat treatment or reduces the heat treatment temperature.

As described above, the heat treatment condition is changed to obtain the thermal stress τ, and the thermal stress τ is compared with the critical shear stress τ _cri obtained previously. If the thermal stress τ after changing the heat treatment conditions falls below the critical shear stress τ _cri , as described above, the heat treatment is performed without causing slip dislocation from a crack on the wafer surface under the changed heat treatment conditions. It can be performed.

On the other hand, when the thermal stress τ after changing the heat treatment condition is equal to or more than the critical shear stress τ _cri , the heat treatment condition is changed, the thermal stress τ applied to the silicon wafer is calculated, and the calculated thermal stress τ and the critical shear stress the comparison of the tau _cri, thermal stress tau is repeated to below the critical shear stress tau _cri.

  The predetermined heat treatment in step S24 can be performed on the silicon wafer determined to have no slip dislocation in step S23 and a silicon wafer having the same initial oxygen concentration as the silicon wafer.

  Thus, the heat treatment can be performed without generating slip dislocations from scratches accompanied by cracks on the wafer surface.

(Silicon wafer)
Next, a silicon wafer according to the present invention will be described. The silicon wafer according to the present invention has an oxygen concentration such that the thermal stress τ applied at the time of the predetermined heat treatment is lower than the critical shear stress τ _{cri at} which the slip dislocation is generated from the flaw with the crack on the surface at the predetermined heat treatment. It is a silicon wafer. In the silicon wafer according to the present invention, slip dislocation does not occur during predetermined heat treatment in a wafer manufacturing process or a device manufacturing process.

The oxygen concentration is preferably 5 × 10 ¹⁷ atoms / cm ³ or more and 20 × 10 ¹⁷ atoms / cm ³ or less. This makes it possible to prevent the occurrence of slip dislocation even if higher stress is applied at high temperature.

Examples of the present invention will be described below, but the present invention is not limited to the examples.
A simulated heat treatment simulating the heat treatment in a standard device fabrication process was applied to a sample wafer to predict whether or not slip dislocations would occur from a crack with a crack on the wafer surface. Here, two processes A and B are set as the above-mentioned simulated heat treatment, and the process A consists of four heat treatment steps, and the heat treatment temperature and heat treatment time of each step are different. Further, step B comprises six heat treatment steps, and as in step A, the heat treatment temperature and heat treatment time of each step are different, and the last step is RTA treatment.

  In step A, the input temperature and the extraction temperature of the sample wafer in steps 1 to 3 were both set to 600 ° C., and the temperature raising rate and the temperature lowering rate were both 8 ° C./min. The input temperature and the extraction temperature of the sample wafer in step 4 were both 800 ° C., and the temperature rising rate and the temperature falling rate were both 15 ° C./min. Further, in step B, for steps 1 to 5, the input temperature and the removal temperature of the sample wafer are both 600 ° C., and the temperature raising rate and temperature lowering rate are both 8 ° C./min. The input temperature and the output temperature of the wafer were both 650 ° C., the temperature rising rate was 150 ° C./sec, and the temperature falling rate was 75 ° C./sec. The heat treatment conditions in steps A and B are shown in Tables 1 and 2, respectively.

  The thermal stress τ given to the wafer in the above-described simulated heat treatment was measured with a thermocouple using the equations (7) to (9) to measure the in-plane temperature of the sample wafer introduced into the heat treatment furnace. As a result, in the step A, a stress of 5.5 MPa was applied at a heat treatment temperature of 1100 ° C. in the fourth step. Further, in step B, it was found that a thermal stress of 16.1 MPa was applied at a heat treatment temperature of 1000 ° C. in the sixth step.

In addition, the oxygen concentration Co after heat treatment of the sample wafer subjected to the steps A and B, the area A of the crack, the critical shear stress τ _cri , the critical shear stress τ _cri and the thermal stress τ applied to the silicon wafer in the heat treatment The relationship and the occurrence of slip dislocation are shown in Tables 3 and 4, respectively.

As described above, in the present invention, when the thermal stress τ applied to the sample wafer in the above simulated heat treatment is less than the critical shear stress τ _cri , that is, if τ <τ _cri , the silicon to which the above simulated heat treatment has been applied. It is determined that slip dislocation does not occur from a flaw accompanied by a crack in the wafer. As apparent from Tables 3 and 4, the judgment result in the present invention completely agrees with the result of whether or not slip dislocation has actually occurred. As described above, it can be understood that by using the equation (6), it is possible to predict with high accuracy whether slip dislocation is generated from a flaw accompanied by a crack on the wafer surface.

FIG. 11 shows the relationship between the oxygen concentration in the silicon wafer and the area A of the crack and the presence or absence of the occurrence of slip dislocation in the steps A and B. In this figure, the broken line is a line showing the critical shear stress τ _cri given by equation (6). As apparent from the figure, it can be seen that the occurrence of slip dislocation can be distinguished from the occurrence of slip dislocation with the broken line as the boundary. As described above, it can be understood that by using the equation (6), it is possible to predict with high accuracy whether slip dislocation is generated from a flaw accompanied by a crack on the wafer surface.

Further, in Tables 3 and 4, the sample wafers 3, 4, 8, 11, 12, 15, 16, 17, 20, and 24 in which slip dislocation has occurred have a higher oxygen concentration than those obtained by taking these sample wafers. Critical strain stress τ _cri is determined based on the area A of the crack after the above simulated heat treatment and the oxygen concentration Co in a silicon wafer having a raised oxygen concentration, grown from the grown ingot, and grown from the grown ingot. On the other hand, silicon that can raise critical shear stress τ _cri and satisfy τ <τ _cri than before changing the growth conditions, and does not generate slip dislocation from a crack accompanied by a crack even after the above-described simulated heat treatment A wafer could be obtained.

  According to the present invention, it is possible to obtain with high accuracy the critical shear stress that slip dislocation is generated from a flaw accompanied by a crack at a predetermined heat treatment in a wafer manufacturing process or device manufacturing process, and slip dislocation occurs at the predetermined heat treatment. It is useful in the semiconductor industry because it can be predicted with high accuracy.

Claims (10)

Based on the area of the crack and the oxygen concentration, the area of the crack and the oxygen concentration in the silicon wafer in the flaw with the crack present on the outer peripheral surface of the silicon wafer subjected to the predetermined heat treatment are determined. after determining the critical shear stress tau _cri slip dislocation is generated from the scratches during the predetermined heat treatment, compared with the thermal stress tau loaded on the silicon wafer at the critical shear stress tau _cri the predetermined heat treatment was determined If the thermal stress τ is equal to or greater than the critical shear stress τ _cri , it is determined that a slip dislocation is generated from a flaw on the surface of the outer peripheral portion of the silicon wafer during the predetermined heat treatment in the silicon wafer, and the thermal stress τ is wherein when below the critical shear stress tau _cri, a silicon wafer, wafer outer peripheral portion on the surface during the predetermined heat treatment Generating prediction method of slip dislocations and judging from scratches and slip dislocation is not generated. The critical shear stress τ _cri is A: area of the crack, C 2 _O : concentration of oxygen, T: temperature of the heat treatment, ε: strain rate, k: Boltzmann's constant, a, b and c: constants as follows The method of claim 1, given by (i).
The method according to claim 2, wherein a is 4.5, b is 5442 and c is 7.9 x ^10-4 . The process for determining the area A of the crack and the oxygen concentration _CO is performed by performing the predetermined heat treatment on the silicon wafer, and then measuring the area of the crack and the oxygen concentration in the silicon wafer after the predetermined heat treatment The method according to any one of claims 1 to 3, which is carried out by The treatment for determining the area A of the crack is performed by performing the predetermined heat treatment on the silicon wafer and then measuring the area of the crack in the silicon wafer after the predetermined heat treatment, and after the predetermined heat treatment The slip dislocation generation prediction method according to any one of claims 1 to 3, wherein the process of determining the oxygen concentration _CO is performed by simulation calculation.   The slip according to any one of claims 1 to 5, wherein the thermal stress τ is obtained based on a temperature distribution in a radial direction of the heated silicon wafer by charging the silicon wafer into a heat treatment apparatus, heating the heat treatment How to predict the occurrence of dislocations.   The method for predicting slip dislocation occurrence according to any one of claims 1 to 5, wherein the thermal stress τ is obtained by simulation calculation.   A single crystal silicon ingot is grown under growth conditions that provide a silicon wafer which is judged not to generate slip dislocation from a flaw accompanied by a crack during the predetermined heat treatment by the slip dislocation generation prediction method according to claim 1 to 7. A method of manufacturing a silicon wafer, comprising performing wafer processing on the grown single crystal silicon ingot. 9. The method for producing a silicon wafer according to claim 8, wherein the oxygen concentration after the predetermined heat treatment is 5 × 10 ¹⁷ atoms / cm ³ or more and 20 × 10 ¹⁷ atoms / cm ³ or less.   The silicon wafer is subjected to the predetermined heat treatment such that it is determined that the slip dislocation does not occur from the flaw accompanied by the crack during the predetermined heat treatment according to the slip dislocation generation prediction method according to claims 1 to 7. Heat treatment method for silicon wafers.