JP6521499B2 - Cryptographic processing apparatus, semiconductor memory and memory system - Google Patents

Description

  The present invention relates to cryptographic processing technology.

  Conventionally, various techniques have been proposed for cryptographic processing. For example, Patent Document 1 discloses a technique for performing cryptographic processing in a semiconductor memory.

Unexamined-Japanese-Patent No. 7-219852 gazette

  In the cryptographic processing apparatus, it is desirable that the content of the cryptographic processing performed by the cryptographic processing apparatus is not easily identified.

  Therefore, the present invention has been made in view of the above-described point, and an object of the present invention is to provide a technology that makes it difficult to identify the content of cryptographic processing in the cryptographic processing device.

In order to solve the above problems, one aspect of the cryptographic processing apparatus according to the present invention comprises a plurality of cryptographic processing units each having a cryptographic function, and the output data of at least one cryptographic processing unit of the plurality of cryptographic processing units is A combination of an encryption processing unit group that is used and that encrypts data to be encrypted that is different from the output data of the plurality of encryption processing units, and an encryption processing unit that is used for the encryption processing unit group and a control unit that executes a process of changing whether to use Te, before Symbol controller, whether to use any combination of the encryption processing section to be used, determined from a plurality of types of combinations, the cryptographic processing The group includes first and second cryptographic processing units, and in the combination of the plurality of types, data output from the first cryptographic processing unit is input to the second cryptographic processing unit as a session key, (2) A first combination in which data output from the encryption processing unit is used as data for encrypting the data to be encrypted, and data output from the second encryption processing unit is a session key A second combination in which data input to the first encryption processing unit and output from the first encryption processing unit is used as data for encrypting the data to be encrypted; A third method in which both the data output from the first encryption processing unit and the data output from the second encryption processing unit are used as data for encrypting the data to be encrypted. Including combinations.

Further, in one embodiment of the cryptographic processing apparatus according to the present invention, the first and second encryption processing section, Ru different encryption algorithm to be used with each other.

Further, in one embodiment of the cryptographic processing apparatus according to the present invention, first and second encryption processing section, Ru der mutually the same encryption algorithm to be used.

Further, in one embodiment of the cryptographic processing apparatus according to the present invention, the first and second encryption processing section, Ru different keys to be used together.

Further, in one embodiment of the cryptographic processing apparatus according to the present invention, the first and second encryption processing section, to be the same as the key used with each other.

  Further, one aspect of a semiconductor memory according to the present invention includes the above-described encryption processing device and a storage unit, and data read from the storage unit is encrypted by the encryption processing device.

  One aspect of a memory system according to the present invention includes the above-described semiconductor memory and a host device that controls the semiconductor memory.

In one aspect of the memory system according to the present invention, the control unit of the cryptographic processing device executes the process when the power of the memory system is turned on.

Further, in one aspect of the memory system according to the present invention, the control unit periodically executes the processing .

In one aspect of the memory system according to the present invention, the storage unit stores control data for executing the process in advance, and the control unit is configured to store the control data based on the control data stored by the storage unit. Execute the process

  According to the present invention, it is difficult to identify the content of cryptographic processing in the cryptographic processing device.

It is a figure which shows the structure of a cryptographic processing apparatus. It is a figure which shows the 1st usage aspect of several encryption processing parts. It is a figure which shows the 2nd usage aspect of several encryption processing parts. It is a figure which shows the 3rd usage aspect of several encryption processing parts. It is a figure which shows the 4th usage aspect of several encryption processing parts. It is a figure which shows the 5th usage aspect of several encryption processing parts. It is a figure which shows the 5th usage aspect of several encryption processing parts. It is a figure showing composition of a memory system. It is a flowchart which shows operation | movement of a memory system.

  FIG. 1 is a diagram showing the configuration of the cryptographic processing apparatus 1 according to the embodiment. The cryptographic processing apparatus 1 according to the present embodiment encrypts and decrypts data using, for example, a stream encryption method which is a type of common key encryption method. The cryptographic processing apparatus 1 may encrypt and decrypt data using a block encryption method, which is a type of common key encryption method. Further, the cryptographic processing apparatus 1 may encrypt and decrypt data using a public key cryptosystem. In the present embodiment, the term "data" means digital data composed of at least one bit for convenience of explanation. Further, for convenience of explanation, it is assumed that the value of data is a value in decimal notation.

  As shown in FIG. 1, the cryptographic processing apparatus 1 includes a cryptographic processing unit group 20 including a plurality of cryptographic processing units 2. Each encryption processing unit 2 has an encryption function. A fixed master key 9 is input to each encryption processing unit 2. In the plurality of cryptographic processing units 2, the cryptographic algorithms used may be the same as one another or may be different from one another. As an encryption algorithm used by the encryption processing unit 2, for example, DES (Data Encryption Standard) or AES (Advanced Encryption Standard) may be considered. Further, in the plurality of cryptographic processing units 2, the master keys 9 to be used may be the same as or different from each other.

  In the present embodiment, the cryptographic processing device 1 includes, for example, two cryptographic processing units 2. Hereinafter, one or the other of the two cryptographic processing units 2 may be referred to as a "first cryptographic processing unit 2a" and a "second cryptographic processing unit 2b", respectively. Also, the master key 9 input to the first encryption processing unit 2a and the master key 9 input to the second encryption processing unit 2b should be called "first master key 9a" and "second master key 9b", respectively. There is.

  The cryptographic processing apparatus 1 is provided with a first arithmetic circuit 3, a second arithmetic circuit 4, and a usage mode control unit 5 in addition to the cryptographic processing unit group 20. Each of the first arithmetic circuit 3 and the second arithmetic circuit 4 calculates and outputs an exclusive OR (XOR) of two input data.

  The usage mode control unit 5 controls the usage mode of the plurality of cryptographic processing units 2 based on a control signal 10 input from the outside of the cryptographic processing device 1. That is, the usage mode of the plurality of cryptographic processing units 2 is determined based on the control signal 10. In the present embodiment, the control signal 10 is composed of the first control data 11, the second control data 12 and the third control data 13. The use mode control unit 5 determines the use mode of the plurality of cryptographic processing units 2 from the plurality of types of use modes. In the present embodiment, for example, first to fifth use modes are defined. The first to fifth usage modes include a mode in which only one of the plurality of cryptographic processing units 2 is used, and a mode in which two of the plurality of cryptographic processing units 2 are used in combination. These usage modes will be described in detail later.

  The usage mode control unit 5 includes a first selection circuit 6, a second selection circuit 7, and a third selection circuit 8. The first selection circuit 6 selects one of the two input data based on the first control data 11 and outputs the selected one to the first encryption processing unit 2a. The first selection circuit 6 receives the data output from the second encryption processing unit 2 b and data in which all bits are zero (hereinafter referred to as “zero data”). The first selection circuit 6 selects and outputs the data output from the second encryption processing unit 2b when the first control data 11 composed of 1 bit indicates "1". On the other hand, when the first control data 11 indicates "0", the first selection circuit 6 selects and outputs zero data. When zero data is input from the first selection circuit 6, the first encryption processing unit 2a ignores the input of the zero data.

  The second selection circuit 7 selects one of the two input data based on the second control data 12 and outputs the selected one to the second encryption processing unit 2 b. Data and zero data output from the first encryption processing unit 2 a are input to the second selection circuit 7. The second selection circuit 7 selects and outputs the data output from the first encryption processing unit 2a when the second control data 12 formed of 1 bit indicates "1". On the other hand, when the second control data 12 indicates “0”, the second selection circuit 7 selects and outputs zero data. When zero data is input from the second selection circuit 7, the second encryption processing unit 2b ignores the input of the zero data.

  The third selection circuit 8 selects one of the three input data based on the third control data 13 and outputs the selected one to the second arithmetic circuit 4. The third selection circuit 8 receives data output from the first encryption processing unit 2 a, data output from the second encryption processing unit 2 b, and data output from the first arithmetic circuit 3. The third selection circuit 8 selects and outputs the data output from the first encryption processing unit 2a, when the third control data 13 composed of 2 bits indicates "0". Further, when the third control data 13 indicates "1", the third selection circuit 8 selects and outputs the data output from the first arithmetic circuit 3. Then, when the third control data 13 indicates "2", the third selection circuit 8 selects and outputs the data output from the second encryption processing unit 2b.

  The first arithmetic circuit 3 calculates the exclusive OR of the data output from the first encryption processing unit 2a and the second encryption processing unit 2b, and outputs the result to the third selection circuit 8. The second arithmetic circuit 4 calculates and outputs an exclusive OR of the data output from the third selection circuit 8 and the data to be encrypted (data to be encrypted). Thus, the data to be encrypted is encrypted. Further, the second arithmetic circuit 4 calculates and outputs an exclusive OR of the data output from the third selection circuit 8 and the encrypted data (encrypted data). Thus, the encrypted data is decrypted. Thus, the second arithmetic circuit 4 uses the data output from the third selection circuit 8 as a key stream (data for encrypting data) to encrypt or decrypt the input data. .

<Usage of Multiple Cryptographic Processing Units>
Next, an example of a plurality of types of usage modes regarding the plurality of cryptographic processing units 2 will be described. Hereinafter, assuming that the value of the first control data 11 is a, the value of the second control data 12 is b, and the value of the third control data 13 is c, the first control data 11, the second control data 12, and the third control data The value of 13 is represented by (a, b, c).

<About the first mode of use>
When the values of the first control data 11, the second control data 12, and the third control data 13 are (0, 1, 2), the usage mode of the plurality of cryptographic processing units 2 is the first usage mode. . FIG. 2 is a diagram showing an equivalent block diagram of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the first usage mode.

  When the usage mode of the plurality of cryptographic processing units 2 is the first usage mode, as shown in FIG. 2, the output data of the first cryptographic processing unit 2a is input to the second cryptographic processing unit 2b. Then, the output data of the second encryption processing unit 2 b is input to the second arithmetic circuit 4. The configuration of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the first usage mode may be referred to as “first configuration”.

  In the cryptographic processing apparatus 1 having the first configuration as shown in FIG. 2, the first cryptographic processing unit 2a performs its own initialization (initialization of its own cryptographic algorithm) based on the first master key 9a. Then, the first encryption processing unit 2a after initialization generates and outputs a session key SK using its own encryption function. In other words, the first encryption processing unit 2a after initialization performs encryption processing to generate and output a session key SK. The second encryption processing unit 2b performs its own initialization (initialization of its own encryption algorithm) based on the input key constituted by the session key SK from the first encryption processing unit 2a and the second master key 9b. . The second encryption processing unit 2b after initialization generates and outputs the key stream KS using its own encryption function. In other words, the second encryption processing unit 2b after initialization performs encryption processing to generate and output the key stream KS. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the key stream KS output from the second encryption processing unit 2 b and the data to be encrypted. Thus, the second arithmetic circuit 4 encrypts and outputs the input encryption target data. In addition, the second arithmetic circuit 4 calculates and outputs the exclusive logical sum of the key stream KS output from the second cryptographic processing unit 2 b and the cryptographic data. Thus, the second arithmetic circuit 4 decrypts the input encrypted data and outputs it.

<About the second mode of use>
When the values of the first control data 11, the second control data 12, and the third control data 13 are (1, 0, 0), the usage mode of the plurality of cryptographic processing units 2 is the second usage mode. . FIG. 3 is a diagram showing an equivalent block diagram of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the second usage mode.

  When the usage mode of the plurality of cryptographic processing units 2 is the second usage mode, as shown in FIG. 3, the output data of the second cryptographic processing unit 2b is input to the first cryptographic processing unit 2a. Then, the output data of the first encryption processing unit 2 a is input to the second arithmetic circuit 4. The configuration of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the second usage mode may be referred to as a "second configuration".

  In the cryptographic processing apparatus 1 having the second configuration as shown in FIG. 3, the second cryptographic processing unit 2b initializes itself based on the second master key 9b. Then, the second encryption processing unit 2b after initialization generates and outputs a session key SK using its own encryption function. The first encryption processing unit 2a initializes itself based on the input key including the session key SK from the second encryption processing unit 2b and the first master key 9a. The first encryption processing unit 2a after initialization generates and outputs the key stream KS using its own encryption function. The second arithmetic circuit 4 calculates and outputs the exclusive logical sum of the key stream KS output from the first encryption processing unit 2a and the data to be encrypted. Thus, the second arithmetic circuit 4 encrypts and outputs the input encryption target data. In addition, the second arithmetic circuit 4 calculates and outputs the exclusive logical sum of the key stream KS output from the first cryptographic processing unit 2 a and the cryptographic data. Thus, the second arithmetic circuit 4 decrypts the input encrypted data and outputs it.

  In the first configuration, when the encryption algorithms used in the first encryption processing unit 2a and the second encryption processing unit 2b are the same, and the master keys 9 used are the same, The cryptographic processing device 1 and the cryptographic processing device 1 of the second configuration perform the same operation.

<About the third mode of use>
When the values of the first control data 11, the second control data 12, and the third control data 13 are (0, 0, 2) or (1, 0, 2), the usage modes of the plurality of cryptographic processing units 2 Is the third mode of use. FIG. 4 is a diagram showing an equivalent block diagram of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the third usage mode.

  When the usage mode of the plurality of cryptographic processing units 2 is the third usage mode, output data of the second cryptographic processing unit 2 b is input to the second arithmetic circuit 4 as shown in FIG. 4. At this time, the first encryption processing unit 2a is not used. That is, when the usage mode of the plurality of cryptographic processing units 2 is the third usage mode, only the second cryptographic processing unit 2 b among the plurality of cryptographic processing units 2 is used. The configuration of the cryptographic processing apparatus 1 when the usage mode of the plurality of cryptographic processing units 2 is the third usage mode may be referred to as a “third configuration”.

  In the cryptographic processing apparatus 1 having the third configuration as shown in FIG. 4, the second cryptographic processing unit 2b initializes itself based on the second master key 9b. Then, the second encryption processing unit 2b after initialization generates and outputs the key stream KS using its own encryption function. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the key stream KS output from the second encryption processing unit 2 b and the data to be encrypted. In addition, the second arithmetic circuit 4 calculates and outputs the exclusive logical sum of the key stream KS output from the second cryptographic processing unit 2 b and the cryptographic data.

<About the 4th usage aspect>
When the values of the first control data 11, the second control data 12, and the third control data 13 are (0, 0, 0) or (0, 1, 0), the usage modes of the plurality of cryptographic processing units 2 Is the fourth mode of use. FIG. 5 is a diagram showing an equivalent block diagram of the cryptographic processing apparatus 1 in the case where the usage mode of the plurality of cryptographic processing units 2 is the fourth usage mode.

  When the usage mode of the plurality of cryptographic processing units 2 is the fourth usage mode, output data of the first cryptographic processing unit 2a is input to the second arithmetic circuit 4 as shown in FIG. At this time, the second encryption processing unit 2b is not used. That is, when the usage mode of the plurality of cryptographic processing units 2 is the fourth usage mode, only the first cryptographic processing unit 2 a among the plurality of cryptographic processing units 2 is used. The configuration of the cryptographic processing apparatus 1 in the case where the usage mode of the plurality of cryptographic processing units 2 is the fourth usage mode may be referred to as “fourth configuration”.

  In the cryptographic processing apparatus 1 having the fourth configuration as shown in FIG. 5, the first cryptographic processing unit 2a initializes itself based on the first master key 9a. Then, the first encryption processing unit 2a after initialization generates and outputs the key stream KS using its own encryption function. The second arithmetic circuit 4 calculates and outputs the exclusive logical sum of the key stream KS output from the first encryption processing unit 2a and the data to be encrypted. In addition, the second arithmetic circuit 4 calculates and outputs the exclusive logical sum of the key stream KS output from the first cryptographic processing unit 2 a and the cryptographic data.

  In addition, in the case where the encryption algorithms used in the first encryption processing unit 2a and the second encryption processing unit 2b are the same as each other and the master keys 9 used are the same as each other, the third configuration is employed. The cryptographic processing device 1 and the cryptographic processing device 1 of the fourth configuration perform the same operation.

<About the 5th usage mode>
When the values of the first control data 11, the second control data 12, and the third control data 13 are (0, 0, 1), the usage mode of the plurality of cryptographic processing units 2 is the fifth usage mode . FIG. 6 is a diagram showing an equivalent block diagram of the cryptographic processing apparatus 1 in the case where the usage mode of the plurality of cryptographic processing units 2 is the fifth usage mode.

  When the usage mode of the plurality of cryptographic processing units 2 is the fifth usage mode, as shown in FIG. 6, the output data of the first cryptographic processing unit 2a and the output data of the second cryptographic processing unit 2b are 1 is input to the arithmetic circuit 3 Then, the output data of the first arithmetic circuit 3 is input to the second arithmetic circuit 4. The configuration of the cryptographic processing apparatus 1 in the case where the usage mode of the plurality of cryptographic processing units 2 is the fifth usage mode may be referred to as a “fifth configuration”.

  In the cryptographic processing apparatus 1 having the fifth configuration as shown in FIG. 6, the first cryptographic processing unit 2a initializes itself based on the first master key 9a. Then, the first encryption processing unit 2a after initialization generates and outputs the first key stream KS1 using its own encryption function. In addition, the second encryption processing unit 2b initializes itself based on the second master key 9b. Then, the second encryption processing unit 2b after initialization generates and outputs the second key stream KS2 using its own encryption function. The first arithmetic circuit 3 calculates the exclusive OR of the first key stream KS1 from the first encryption processing unit 2a and the second key stream KS2 from the second encryption processing unit 2b, 3 Output as key stream KS3. The second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the third key stream KS3 output from the first arithmetic circuit 3 and the data to be encrypted. In addition, the second arithmetic circuit 4 calculates and outputs an exclusive logical sum of the third key stream KS3 and the encrypted data.

  Here, when the exclusive logical sum of the calculation result of the exclusive OR of the first key stream KS1 and the second key stream KS2 and the encryption target data (or the cryptographic data) is calculated, the first key stream KS1 In the case where the exclusive OR of the three data of the second key stream KS2 and the encryption target data (or encryption data) is calculated, the operation results obtained are the same. Therefore, when the first arithmetic circuit 3 and the second arithmetic circuit 4 are put together into one arithmetic circuit 34, the configuration shown in FIG. 6 is equivalent to the configuration using the arithmetic circuit 34 shown in FIG. In the configuration shown in FIG. 7, the arithmetic circuit 34 encrypts the encryption target data by calculating an exclusive logical sum of the first key stream KS1, the second key stream KS2, and the encryption target data. Do. The arithmetic circuit 34 decrypts the encrypted data by calculating an exclusive logical sum of the first key stream KS1, the second key stream KS2, and the encrypted data.

  In the present embodiment, the usage mode control unit 5 responds to the control signal 10 (the first control data 11, the second control data 12 and the third control data 13) in a plurality of cryptographic processing units in the cryptographic processing device 1. The use mode of 2 is changed between the first to fifth use modes. For example, when the values of the first control data 11, the second control data 12, and the third control data change from (0, 1, 2) to (1, 0, 0), the usage mode control unit 5 The usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing apparatus 1 is changed from the first usage mode to the second usage mode. In addition, when the values of the first control data 11, the second control data 12, and the third control data change from (0, 1, 2) to (0, 0, 1), the usage mode control unit 5 The usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 is changed from the first usage mode to the fifth usage mode. In addition, the usage mode control unit 5 is configured such that the values of the first control data 11, the second control data 12, and the third control data are (1, 0, 0) to (0, 0, 2) When it changes to), the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing apparatus 1 is changed from the second usage mode to the third usage mode. When the control signal 10 changes dynamically, the use mode control unit 5 dynamically changes the use mode of the plurality of cryptographic processing units 2.

  As described above, since the usage mode control unit 5 according to the present embodiment changes the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1, the content of the cryptographic processing in the cryptographic processing device 1 is specified. It becomes difficult. In other words, in the present embodiment, since the configuration of the cryptographic processing device 1 changes, it becomes difficult to identify the content of the cryptographic processing in the cryptographic processing device 1. Therefore, by using the cryptographic processing device 1 according to the present embodiment to realize the security of a device such as a semiconductor memory, the security strength of the device can be improved.

<Example of security implementation using cryptographic processing device>
Next, an implementation example of security using the cryptographic processing apparatus 1 according to the present embodiment will be described. Here, as an example, a case where security of a semiconductor memory is realized using the cryptographic processing device 1 will be described.

  FIG. 8 is a view showing the configuration of a memory system 100 having a semiconductor memory 200 in which security is realized by using the cryptographic processing apparatus 1. The memory system 100 includes a semiconductor memory 200 having the cryptographic processing device 1 and a host device 300 that controls the semiconductor memory 200. Memory system 100 is, for example, a computer system implemented in a game device. The game device includes a game device body and a game cartridge which can be attached and detached. The semiconductor memory 200 is incorporated in the game cartridge, and the host device 300 is incorporated in the game apparatus body. The host device 300 is a type of computer. The user can enjoy various types of games by exchanging game cartridges mounted on the game apparatus body.

  The semiconductor memory 200 is, for example, a mask ROM (Read Only Memory). The semiconductor memory 200 includes a host IF (interface) 210, a command decoder 220, a memory IF (interface) 230, a memory array 240 which is a storage unit, and a control register 250 in addition to the cryptographic processing device 1. There is.

  The cryptographic processing device 1 receives a command from the host device 300 through the host IF 210. The host device 300 is provided with an encryption processing device similar to the encryption processing device 1. The host device 300 encrypts a command using its own encryption processing device, and outputs the encrypted command to the semiconductor memory 200. The cryptographic processing device 1 decrypts the encrypted command from the host device 300 with the second arithmetic circuit 4 as described above, and outputs the decrypted command to the command decoder 220. Hereinafter, the encryption processing device included in the host device 300 may be referred to as a “host-side encryption processing device”.

  The command decoder 220 decodes the input command and analyzes the command. As a result of analyzing the input command, if the command is a read command instructing reading of data from the memory array 240, the command decoder 220 controls a control signal such as an address signal and a read signal through the memory IF 230 Output to array 240. Thereby, data is output from the memory array 240. The data output from the memory array 240 is input to the cryptographic processing apparatus 1. The memory array 240 stores, for example, a plurality of game programs and various data used in each game program. The command decoder 220 also extracts control data contained in the input command, and writes the extracted control data into the control register 250.

  The control register 250 includes a first register 251, a second register 252, a third register 253, and an initialization register 254. The first register 251 stores first control data 11 for controlling the first selection circuit 6 of the cryptographic processing apparatus 1. The second register 252 stores second control data 12 for controlling the second selection circuit 7 of the cryptographic processing apparatus 1. The third register 253 stores third control data 13 for controlling the third selection circuit 8 of the cryptographic processing apparatus 1. The initialization register 254 stores an initialization flag 14 which is control data for instructing initialization of the cryptographic processing apparatus 1. The first control data 11, the second control data 12, the third control data 13, and the initialization flag 14 are output from the host device 300.

  The cryptographic processing device 1 encrypts the data output from the memory array 240 by the second arithmetic circuit 4 as described above. The data encrypted by the cryptographic processing device 1 is input to the host device 300 through the host IF 210. The host device 300 decrypts the encrypted data from the semiconductor memory 200 using the host-side cryptographic processing device. When the game program in the memory array 240 is input from the semiconductor memory 200, the host device 300 executes the game program.

  In memory system 100 according to the present embodiment, host device 300 determines the use mode of the plurality of cryptographic processing units 2 in cryptographic processing device 1 of semiconductor memory 200, and control signal 10 corresponding to the determined use mode ( The first control data 11, the second control data 12, and the third control data 13) are output to the semiconductor memory 200. In the cryptographic processing device 1, the usage mode control unit 5 sets the usage mode of the plurality of cryptographic processing units 2 based on the control signal 10 from the host device 300. Here, since the content of the cryptographic processing in the cryptographic processing device 1 is determined according to the usage manner of the plurality of cryptographic processing units 2 in the cryptographic processing device 1, the security configuration in the semiconductor memory 200 is It can be said that it is decided. That is, the semiconductor memory 200 according to the present embodiment changes the security configuration by changing the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1. Hereinafter, the control signal 10 for determining the usage mode of the plurality of cryptographic processing units 2, that is, the control signal 10 for determining the security configuration in the semiconductor memory 200 may be referred to as a "security configuration flag 10".

  Next, the operation of the memory system 100 when the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 changes will be described. FIG. 9 is a flowchart showing the operation. In the following description, for example, the operation of the memory system 100 when the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 changes from the first usage mode to the second usage mode will be described.

  As shown in FIG. 9, in step s1, the host device 300 issues a security reconfiguration command. At this time, the host device 300 encrypts the security reconfiguration command by the host-side cryptographic processing device and then outputs it. The security reconfiguration command output from the host device 300 is input to the cryptographic processing device 1 through the host IF 210.

  The security reconfiguration command is a command for changing the security configuration in the semiconductor memory 200, that is, a command for changing the usage mode of the plurality of cryptographic processing units 2. The security reconfiguration command includes a security configuration flag 10 and an initialization flag 14. In this example, since the usage mode of the plurality of cryptographic processing units 2 changes from the first usage mode to the second usage mode, the security reconfiguration command has a security configuration flag corresponding to the second usage mode. Ten are included. That is, the values of the first control data 11, the second control data 12, and the third control data 13 that constitute the security configuration flag 10 included in the security reconfiguration flag correspond to the second usage mode (1, 0, 0)

  Next, in step s2, the cryptographic processing apparatus 1 decrypts the input encrypted security reconfiguration command. Here, since the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 is the first usage mode (see FIG. 2), in the cryptographic processing device 1, the second arithmetic circuit 4 is a second cryptographic circuit. By calculating the exclusive logical sum of the key stream KS output from the processing unit 2 b and the security reconfiguration command, the security reconfiguration command is decrypted. The decrypted security reconfiguration command is input to the command decoder 220.

  Next, in step s3, the command decoder 220 decodes the input security reconfiguration command, and extracts the security configuration flag 10 and the initialization flag 14 from the security reconfiguration command. Then, in step s4, the command decoder 220 transfers the extracted security configuration flag 10 to the control register 250. The control register 250 transmits the first control data 11, the second control data 12 and the third control data 13 constituting the transferred security configuration flag 10 to the first register 251, the second register 252 and the third register 253. I will remember each. The first control data 11, the second control data 12 and the third control data 13 stored in the first register 251, the second register 252 and the third register 253 are inputted to the cryptographic processing device 1.

  Next, in step s5, in the cryptographic processing device 1, the usage mode control unit 5 changes the usage mode of the plurality of cryptographic processing units 2 according to the security configuration flag 10 (control signal 10) output from the control register 250. Let Here, since the values of the first control data 11, the second control data 12 and the third control data 13 are (1, 0, 0), the usage mode control unit 5 The usage mode of is changed to the second usage mode. As a result, the configuration of the cryptographic processing device 1 changes from the configuration shown in FIG. 2 to the configuration shown in FIG.

  Next, in step s6, the command decoder 220 transfers the extracted initialization flag 14 to the control register 250. The control register 250 stores the transferred initialization flag 14 in the initialization register 254. The initialization flag 14 stored in the initialization register 254 is input to the cryptographic processing apparatus 1.

  Next, in step s7, in the cryptographic processing apparatus 1 that has received the initialization flag 14, initialization of each cryptographic processing unit 2 is performed. Here, since the usage mode of the plurality of cryptographic processing units 2 is the second usage mode, the second cryptographic processing unit 2b is initialized based on the second master key 9b. The first encryption processing unit 2a is initialized based on an input key including the session key SK output from the second encryption processing unit 2b after initialization and the first master key 9a. Thereafter, in the cryptographic processing device 1, the command from the host device 300 is decrypted by the key stream KS output from the first cryptographic processing unit 2a. Also, data from the memory array 240 is encrypted with the key stream KS output from the first encryption processing unit 2a.

  When the host device 300 issues a security reconfiguration command to change the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 of the semiconductor memory 200, the plurality of host-side cryptographic processing devices may The usage mode of the cryptographic processor is also changed in the same manner. For example, when the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing apparatus 1 changes from the third usage mode to the fifth usage mode, the use of the plurality of cryptographic processing units in the host-side cryptographic processing apparatus The aspect also changes from the third usage aspect to the fifth usage aspect. Thus, even when the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 of the semiconductor memory 200 changes, the host device 300 can appropriately decrypt data from the semiconductor memory 200. Also, the semiconductor memory 200 can appropriately decode the command from the host device 300.

  As described above, the operation of the memory system 100 changes the security configuration of the semiconductor memory 200. Thus, the security strength of the semiconductor memory 200 is improved. Therefore, the content of data such as a game program in the memory array 240 is difficult to specify. Thus, illegal copying of the game cartridge can be suppressed.

  In the present embodiment, for example, the host device 300 issues a security reconfiguration command each time the memory system 100 is powered on. Thus, each time the power of the memory system 100 is turned on, the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1 of the semiconductor memory 200 changes. In this case, in the cryptographic processing apparatus 1, the usage mode control unit 5 changes the usage mode of the plurality of cryptographic processing units 2 when the power of the memory system 100 is turned on.

  The host device 300 may periodically issue a security reconfiguration command. Thereby, the use aspect of the several encryption processing parts 2 in the encryption processing apparatus 1 changes regularly. In this case, in the cryptographic processing device 1, the usage mode control unit 5 periodically changes the usage mode of the plurality of cryptographic processing units 2.

  The use modes of the plurality of cryptographic processing units 2 may be changed in any order among the first to fifth use modes. For example, the mode of use of the plurality of cryptographic processing units 2 may be changed in the order of the first mode of use, the second mode of use, the third mode of use, the fourth mode of use, and the fifth mode of use. . In addition, the usage modes of the plurality of cryptographic processing units 2 may be changed in the order of the first usage mode, the third usage mode, the fifth usage mode, the second usage mode, and the fourth usage mode. .

  In the above example, the security configuration flag 10 (control signal 10) for controlling the usage mode of the plurality of cryptographic processing units 2 was included in the security reconfiguration command, but is stored in advance in the memory array 240. Also good. In this case, a plurality of security configuration flags 10 respectively corresponding to the first to fifth usage modes are stored in advance in the memory array 240. Then, in the semiconductor memory 200, when the security reconfiguration command is received from the host device 300, one of the plurality of security configuration flags 10 is read from the memory array 240 and stored in the control register 250. By changing the security configuration flag 10 written from the memory array 240 to the control register 250, the usage mode of the plurality of cryptographic processing units 2 changes.

  The semiconductor memory 200 notifies the host apparatus 300 of the security configuration flag 10 written from the memory array 240 to the control register 250, that is, the security configuration flag 10 used to control the usage mode of the plurality of cryptographic processing units 2. The host device 300 sets the usage mode of the plurality of cryptographic processing units in the host-side cryptographic processing device to the usage mode corresponding to the notified security configuration flag 10. Thereby, even if the semiconductor memory 200 changes the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing apparatus 1 itself, the usage mode of the plurality of cryptographic processing units 2 in the semiconductor memory 200; The mode of use of the plurality of cryptographic processing units in the host device 300 is matched. Thus, the host device 300 can appropriately decode the data from the semiconductor memory 200. Also, the semiconductor memory 200 can appropriately decode the command from the host device 300.

  In the above example, the first to fifth usage modes are defined as the usage modes of the plurality of cryptographic processing units 2 in the cryptographic processing apparatus 1, but at least one of the first to fifth usage modes is defined. Only two usage modes may be defined. In addition, usage modes other than the first to fifth usage modes may be defined.

  Further, in the above example, the cryptographic processing unit group 20 of the cryptographic processing device 1 is configured by two cryptographic processing units 2, but may be configured by three or more cryptographic processing units 2.

  When the cryptographic processing unit group 20 includes the first to third cryptographic processing units, various usage modes can be considered as usage modes of the first to third cryptographic processing units 2.

  For example, the output data of the first cryptographic processor 2 is input to the second cryptographic processor 2 as a first session key, and the output data of the second cryptographic processor 2 is output to the third cryptographic processor 2 as a second session key. It is conceivable that the output data of the third cryptographic processing unit 2 is used as a key stream.

  Further, the output data of the third encryption processing unit 2 is input to the second encryption processing unit 2 as a first session key, and the output data of the second encryption processing unit 2 is output to the first encryption processing unit 2 as a second session key. It is conceivable that the output data of the first encryption processing unit 2 is used as a key stream.

  Also, the output data of the first encryption processing unit 2 and the output data of the second encryption processing unit 2 are input to the third encryption processing unit 2 as a session key, and the output data of the third encryption processing unit 2 is used as a key stream It is conceivable that the

  Also, the output data of the second encryption processing unit 2 and the output data of the third encryption processing unit 2 are input to the first encryption processing unit 2 as a session key, and the output data of the first encryption processing unit 2 is used as a key stream It is conceivable that the

  Moreover, the aspect by which the output data of the 1st encryption processing part 2, the output data of the 2nd encryption processing part 2, and the output data of the 3rd encryption processing part 2 are used as a key stream can be considered.

  The cryptographic processor group 20 may include at least two cryptographic processors 2 having different cryptographic algorithms to be used, or at least two cryptographic processors 2 having the same cryptographic algorithm to be used. It may be

  For example, in the case where the cryptographic processing unit group 20 includes the first to third cryptographic processing units 2, the cryptographic algorithms used in the first and second cryptographic processing units 2 are the same, and The cryptographic algorithm used in the second cryptographic processing unit 2 and the cryptographic algorithm used in the third cryptographic processing unit 2 are made different from each other.

  In addition, when the cryptographic processing unit group 20 includes the first to fourth cryptographic processing units 2, for example, the cryptographic algorithms used by the first to third cryptographic processing units 2 are made different from each other, The cryptographic algorithms used in the third and fourth cryptographic processing units 2 are the same.

  Further, in the case where the cryptographic processing unit group 20 is configured by the first to fourth cryptographic processing units 2, for example, the cryptographic algorithms used in the first and second cryptographic processing units 2 are the same as each other, and And the fourth encryption processing unit 2 use the same encryption algorithm. Then, for example, the encryption algorithm used in the first and second encryption processing units 2 and the encryption algorithm used in the third and fourth encryption processing units 2 are made different from each other.

  When the cryptographic processor group 20 includes at least two cryptographic processors 2 having different cryptographic algorithms to be used, the usage mode of the plurality of cryptographic processors 2 in the cryptographic processor 1 is changed, It becomes more difficult to identify the content of the cryptographic processing in the cryptographic processing device 1. Therefore, by using the cryptographic processing apparatus 1 for the security of the semiconductor memory 200 or the like, the security strength can be further improved.

  Further, the cryptographic processor group 20 may include at least two cryptographic processors 2 having different master keys 9 to be used, or at least two cryptographic processors 2 having the same master key 9 to be used. You may include it.

  For example, in the case where the cryptographic processing unit group 20 includes the first to third cryptographic processing units 2, the master keys 9 used in the first and second cryptographic processing units 2 are mutually the same, and The master key 9 used by the second encryption processing unit 2 and the master key 9 used by the third encryption processing unit 2 are made different from each other.

  Further, when the cryptographic processing unit group 20 includes the first to fourth cryptographic processing units 2, for example, the master keys 9 used in the first to third cryptographic processing units 2 are made different from one another, The master keys 9 used in the first and fourth cryptographic processing units 2 are the same.

  Also, in the case where the encryption processing unit group 20 is configured by the first to fourth encryption processing units 2, for example, the master keys 9 used in the first and second encryption processing units 2 are mutually the same, The master keys 9 used in the third and fourth cryptographic processing units 2 are the same. Then, the master key 9 used in the first and second cryptographic processing units 2 and the master key 9 used in the third and fourth cryptographic processing units 2 are made different from each other.

  In the case where the cryptographic processing group 20 includes at least two cryptographic processing units 2 having different keys used, encryption can be performed by changing the usage mode of the plurality of cryptographic processing units 2 in the cryptographic processing device 1. It becomes more difficult to specify the content of the cryptographic processing in the processing device 1. Therefore, by using the cryptographic processing apparatus 1 for the security of the semiconductor memory 200 or the like, the security strength can be further improved.

  In the above example, the cryptographic processing unit 2 generates and outputs keys such as a session key and a key stream, but it is possible to encrypt input data and output encrypted data. good. In this case, for example, in the case where the usage mode of the plurality of cryptographic processing units 2 is the first usage mode as shown in FIG. 2, the second cryptographic processing unit 2b starts with the first cryptographic processing unit 2a. The input data (plaintext) is encrypted using the output session key SK, and the encrypted data is output. In addition, for example, when the usage mode of the plurality of cryptographic processing units 2 is the second usage mode as illustrated in FIG. 3, the first cryptographic processing unit 2 a is output from the second cryptographic processing unit 2 b. The session key SK is used to encrypt input data (plaintext) and output the encrypted data.

  As described above, the cryptographic processing device 1, the semiconductor memory 200, and the memory system 100 have been described in detail, but the above description is an exemplification in all aspects, and the present invention is not limited thereto. Further, the various modifications described above can be combined and applied as long as no contradiction arises. And, it is understood that innumerable modifications not illustrated may be assumed without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 cryptographic processor 2 cryptographic processor 5 usage mode controller 9 master key 100 memory system 200 semiconductor memory 240 memory array 300 host device

Claims (10)

A cryptographic processor, and
Each of the plurality of cryptographic processing units each having a cryptographic function, wherein output data of at least one cryptographic processing unit of the plurality of cryptographic processing units is used, and encryption is performed separately from output data of the plurality of cryptographic processing units Cryptographic processing units to which target data is encrypted;
And a control unit that executes a process of changing how to combine and use the encryption processing units to be used for the encryption processing unit group,
Before SL control unit, whether to use any combination of the encryption processing section to be used, determined from a plurality of types of combinations,
The encryption processing unit group includes first and second encryption processing units,
The combination of the plurality of types is
The data output from the first encryption processing unit is input to the second encryption processing unit as a session key, and the data output from the second encryption processing unit is for encrypting the data to be encrypted. The first combination used as data, and
The data output from the second cryptographic processor is input to the first cryptographic processor as a session key, and the data output from the first cryptographic processor is for encrypting the data to be encrypted. A second combination that is used as data, and
Thirdly, both the data output from the first encryption processing unit and the data output from the second encryption processing unit are used as data for encrypting the data to be encrypted. Cryptographic processing apparatus, including a combination of The encryption processing device according to claim 1, wherein
The first and second encryption processing units are encryption processing devices that use different encryption algorithms. The encryption processing device according to claim 1, wherein
The first and second cryptographic processors, wherein the cryptographic algorithms used are the same as one another. The encryption processing device according to any one of claims 1 and 2.
The first and second encryption processing units have different keys to be used. The encryption processing device according to any one of claims 1 and 2.
The first and second encryption processors, wherein the keys used are the same as each other. The cryptographic processing device according to any one of claims 1 to 5 .
And a storage unit,
Semiconductor memory in which data read from the storage unit is encrypted by the encryption processing device. A semiconductor memory according to claim 6 ;
And a host device that controls the semiconductor memory. The memory system according to claim 7 , wherein
Wherein the control unit of the encryption processing apparatus, when the power of the memory system is turned on, executes the processing, the memory system. A memory system according to any one of claims 7 and 8 .
The memory system, wherein the control unit periodically executes the process . A memory system according to any one of claims 7 to 9,
The storage unit stores control data for executing the process in advance.
The memory system, wherein the control unit executes the process based on the control data stored in the storage unit.

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