JP6521666B2 - Image pickup apparatus, image pickup method and image frame readout control circuit - Google Patents

Description

  The present invention is an imaging apparatus and imaging method using a CMOS type imaging device in which flicker occurring when imaging is performed at a frame frequency of 120 Hz under illumination where the power supply frequency is 100 Hz and the intensity change is 100 Hz. And an image frame readout control circuit.

  In the 50 Hz power supply frequency range, lighting equipment such as a fluorescent lamp exhibits a change in illumination intensity according to the pulsation frequency of 100 Hz after rectification. Under such illumination intensity, when the imaging frame frequency of the imaging device is 60 Hz, flicker occurs because the frequency of the illumination intensity change is not an integral multiple of the imaging frame frequency.

Therefore, as a countermeasure against such flicker, the electronic shutter period is (1/100) second (=
Setting to 10 milliseconds etc. is performed (refer patent documents 1-4). This is based on the knowledge that no flicker occurs because the amount of light incident for 10 milliseconds is kept constant no matter how the phase of the illumination intensity change and the phase of the electronic shutter are shifted.

  In recent years, development of super hi-vision has become active, and since it is urgent to establish measures against the above-mentioned flicker, if the above-mentioned method can be used, it is possible to use existing technology and it is efficient.

Unexamined-Japanese-Patent No. 5-091373 Japanese Patent Application Laid-Open No. 6-125495 JP 2000-299822 A JP 2007-104450 A

However, when imaging is performed with an imaging frame frequency of 120 Hz, which is a standard for Super Hi-Vision, under illumination with an illumination intensity change of 100 Hz, flicker of 20 Hz occurs. In this case, the imaging frame interval is (1/120) seconds = 8.3.
Since it is 33 milliseconds, if the electronic shutter period is set to 10 milliseconds, the electronic shutter period with respect to the imaging frame interval will be set to 6/5 which is larger than 1, so that the execution of imaging itself becomes difficult .

  The present invention has been made in view of the above circumstances, and in the case of an illumination intensity change of 100 Hz, an imaging device, an imaging method, and an imaging method capable of reducing flicker that occurs when imaging is performed at an imaging frame frequency of 120 Hz. It is an object of the present invention to provide an image frame readout control circuit.

The imaging device of the present invention is
A photoelectric conversion unit, which is formed corresponding to a plurality of pixels arranged in an XY matrix, and generates charges according to incident light;
A CMOS-type super having a row selection circuit unit for selecting and driving an address of Y rows to the photoelectric conversion unit, and an image frame read control unit including a column parallel read out circuit unit for reading out a signal every X columns It is a high-definition standard imaging device.
The plurality of pixels are set to any of 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame readout control unit sets the divided image frame interval to either 8.333 milliseconds or 8.342 milliseconds by using the non-progressive method, and one charge accumulation time of each pixel in the photoelectric conversion unit Is set to 10 milliseconds.

  Here, the above “XY matrix” refers to a state in which the two axes intersecting on the element surface of the imaging device are arranged in both directions when the X axis is the other and the Y axis is the other.

  Moreover, the above-mentioned "non-progressive system" refers to a so-called interlaced scanning system different from the progressive system which is a system in which scanning is sequentially performed from one direction of the image pickup device, and A method of performing the interlace scanning for each line or a scanning method in the case where the scan is apparently performed in the Y direction and the scanning is the interlace scanning is also included. In other words, the above-mentioned plurality of pixels are selected every N rows or M columns, and charge accumulation operation and signal readout are sequentially performed on each of N groups of rows or groups of M columns. This is a method to repeat the operation.

  Also, generally, in the above "image frame", a group of lines formed by interlace scanning, for example, a frame with only odd rows (odd frame: conceptually corresponding to the first field by NTSC) or only even rows Frames according to (even frame: conceptually corresponding to the second field by NTSC) are also included, and not only odd frames or even frames but also the interval between odd and even frames is also referred to as image frame interval There are many. However, in the specification of the present application, the interval between odd frames or even frames is referred to as an image frame interval, as it may be confusing in the essential part of the invention, but the interval between odd and even frames. Will be referred to as divided image frame intervals for convenience.

Preferably, the image frame readout control unit is configured to control so that one charge accumulation time of each pixel with respect to the image frame interval is 6/10.
Preferably, the non-progressive method is an interlace method.

  It is preferable that the photoelectric conversion unit is configured to share pixels across a plurality of pixels in at least one of the X direction and the Y direction.

  Preferably, each pixel circuit of the photoelectric conversion unit has a global shutter function.

In addition, the imaging method of the present invention is
In the pixel circuits provided corresponding to the plurality of pixels arranged in the XY matrix, photoelectric conversion is performed so that charges corresponding to light incident on the plurality of pixels are generated,
An image pickup device of a CMOS type super hi-vision standard which performs image frame readout in a predetermined order by designating an address of Y row and an address of X column to a plurality of pixels arranged in the XY matrix form Method,
The plurality of pixels are set to any of 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame readout uses a non-progressive method, sets an interval between divided image frames to either 8.333 milliseconds or 8.342 milliseconds, and one charge of each pixel for accumulating charges generated by the photoelectric conversion. The accumulation time is set to 10 milliseconds.

Further, the image frame readout control circuit of the present invention is
A circuit for transmitting an image frame read control signal to a photoelectric conversion unit which is formed corresponding to a plurality of pixels arranged in an XY matrix and generates charges according to incident light, and is an address of Y row And an image frame readout unit including a column parallel readout unit which selects a row selection unit for driving pixels included in the Y row and an address in the X column and reads out a signal from the pixels included in the X column. In the image frame readout control circuit in the imaging device of the CMOS super high vision standard ,
The plurality of pixels are set to any of 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame read out by the image frame read out unit uses the non-progressive method and sets the divided image frame interval to either 8.333 ms or 8.342 ms, and the pixels of the photoelectric conversion portion At least an accumulation start instruction signal and an accumulation end instruction signal corresponding to the plurality of pixels are directed from the image frame reading unit to the photoelectric conversion unit in a predetermined order so that the accumulation time can be set to 10 milliseconds. It is characterized by outputting.

  The imaging device according to the present invention is set to any of 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction, by non-progressive methods such as interlace method. By setting the frame frequency to 120 Hz and setting the electronic shutter period to 10 ms, the image frame interval between odd frames or even frames is 16.667 ms, and the divided image frame interval between odd frames and even frames is 16.67 ms. The signal readout is performed in 8.333 milliseconds, and the accumulation time of each pixel is 10 milliseconds.

  That is, when imaging is performed with an imaging frame frequency of 120 Hz, which is a standard for Super Hi-Vision, under illumination of which the illumination intensity change is 100 Hz, flicker of 20 Hz occurs. In order to prevent this, when the electronic shutter speed is set to 10 milliseconds, the imaging frame interval (division image frame interval) is (1/120) seconds = 8.333 milliseconds, so the imaging frame interval (division Since the electronic shutter period with respect to the image frame interval) is set to 6/5 larger than 1, it becomes difficult to perform imaging.

However, in the present invention, even if the electronic shutter speed is 10 milliseconds and the imaging frame interval is (1/120) seconds = 8.333 milliseconds, a non-progressive method such as an interlace method is adopted as a scanning method. Therefore, the electronic shutter period for the imaging frame interval (image frame interval (interval of the divided image frame interval: interval between odd frames or even frames)) is smaller than 1 (in the case of the interlace system, 6 / Since it can set to 10), generation | occurrence | production of the flicker which arises at the time of imaging of 120 Hz under the illumination intensity change of 100 Hz of power supply frequency 50-Hz range can be prevented.

It is a circuit diagram showing an equivalent circuit of a pixel circuit using four transistors according to a first embodiment of the present invention. It is a block diagram which shows the imaging device provided with the pixel array and image frame read-out control circuit which have a pixel circuit shown in FIG. 1 in XY array form. It is a time chart of the input signal to a pixel circuit in, when performing signal read-out using the pixel circuit of 4 transistor use shown in FIG. It is the schematic which shows the odd-numbered line (solid line) and the even-numbered line (broken line) at the time of performing signal reading using an interlace system in an image pick-up element. It is a time chart which shows an example of the time series relation of the illumination intensity change of 100 Hz, and the accumulation time in the odd line of an 120 Hz interlace scan, and the even line. It is a time chart which shows the time-sequential relationship of the picture from the odd line of an 120 Hz interlace scan, and the even line. FIG. 7 is a circuit diagram showing an equivalent circuit of a pixel circuit of a 2-pixel sharing type according to a second embodiment of the present invention, which uses 2.5 transistors per pixel. FIG. 8 is a time chart of an input signal to a pixel circuit in the case of performing signal readout using the pixel circuit using 2.5 transistors shown in FIG. 7. FIG. 8 is a circuit diagram showing an equivalent circuit of a pixel circuit of a 2-pixel sharing type according to a third embodiment of the present invention, which uses 4.5 transistors per pixel. FIG. 10 is a time chart of input signals to the pixel circuit in the case of performing signal readout using the pixel circuit of 4.5 transistors using the global shutter shown in FIG. 9. It is a 4 pixel sharing type which concerns on the 1st modification of the 2nd Embodiment of this invention, Comprising: It is an equivalent circuit schematic of the pixel circuit of 1.75 transistor use per pixel. It is a time chart of an input signal to a pixel circuit in the case of performing signal readout using a pixel circuit using 1.75 transistors per pixel in the imaging device according to the first modified example shown in FIG. FIG. 18 is an equivalent circuit diagram of a pixel circuit of a row direction two pixel sharing type according to a second modification of the second embodiment of the present invention, wherein 2.5 transistors are used per pixel. FIG. 14 is a schematic view showing an odd-numbered column (solid line) and an even-numbered column (broken line) in the case of using the scanning method in the second modified example shown in FIG. 13; It is a 4 pixel share type which concerns on the 3rd modification of the 2nd Embodiment of this invention, Comprising: It is an equivalent circuit schematic of the pixel circuit of 1.75 transistor use per pixel. FIG. 16 is a time chart of an input signal to a pixel circuit in the case of performing signal readout using a pixel circuit using 1.75 transistors per pixel in an imaging device according to a third modification example shown in FIG. 15.

  Hereinafter, embodiments of the present invention will be described with reference to the above drawings.

First Embodiment
First, an equivalent circuit diagram of a pixel circuit using four transistors used in a CMOS imaging device according to the first embodiment will be described with reference to FIG. The pixel circuit 10 shown in this equivalent circuit diagram is provided corresponding to each pixel (or each pixel group) of the pixel array of the CMOS imaging device (not limited to one-to-one correspondence).

  As shown in FIG. 1, the pixel circuit 10 includes a photodiode (PD) 11, a charge transfer transistor (TX) 12, a floating diffusion capacitance (FD) 13, a reset transistor (RST) 14, and a source follower amplifier (amplifying transistor: SF) 15, selection transistor (SEL) 16, pixel power supply unit (VDD) 17, and pixel output unit (OUT) 18.

Further, a large number of the pixel circuits 10 are arranged in the X direction (row direction) and the Y direction (column direction) to configure a pixel array 501 (see FIG. 2).
As shown in FIG. 2, the pixel array 501 constitutes an imaging device (image sensor) 550 together with the Y-direction operation unit 502, the X-direction operation unit 503, the timing generator 504, and the output circuit 505. In the imaging device 550, the Y-direction operation unit 502, the X-direction operation unit 503, the timing generator 504, and the output circuit 505 constitute an image frame read control circuit according to the present invention.

In each pixel circuit 10, the PD 11 accumulates negative charge in an amount corresponding to the intensity of incident light. The anode of this PD 11 is grounded, and the cathode is connected to the gate of SF 15 via TX 12. The gate of the TX 12 is connected to the signal line L _T from the Y-direction operation unit 502, and a transfer signal is input.

The SF 15 and the SEL 16 are connected in series between the VDD 17 and the output unit 18. The gate of SEL 16 is connected to the signal line L _S from the Y-direction operation unit 502, and a selection signal is input. The RST 14 is connected between the VDD 17 and the gate of the SF 15. The gate of the RST 14 is connected to the signal line L _R from the Y-direction operation unit 502, and receives a reset signal.
Moreover, FD13 is connected to the gate of SF15.

  In order to reset the PD 11, the SEL 16 is turned off, and the TX 12 and the RST 14 are turned on. As a result, the negative charge stored in the PD 11 is released to the VDD 17 through the TX 12 and the RST 14, and the reset operation is completed.

  At the end of the reset operation of the PD 11, charge accumulation by incident light starts. That is, when the transfer signal and the reset signal are in the “L” state and the TX 12 and the RST 14 are in the off state, charges of an amount corresponding to the intensity of incident light are stored in the PD 11 and charge storage time starts.

  On the other hand, the end of the accumulation time is performed as follows. That is, first, the selection signal is set to the “H” level to turn on the SEL 16, and the reset signal is set to the “H” level for a predetermined time to turn on the RST 14 to reset the FD 13. Next, the transfer signal is set to the “H” level only for a predetermined time to turn on the TX 12, whereby the accumulated charge of the PD 11 is moved to the FD 13 and the accumulation time of the PD 11 ends when the TX 12 is turned off.

Further, the timing generator 504 shown in FIG. 2 sends a row selection address signal and a drive control signal to the Y direction scanning unit 502, and sends a column selection address signal and a read control signal to the X direction scanning unit 503. The Y-direction scanning unit 502 has the functions of a Y-direction scanning circuit and a voltage level shift circuit, and sequentially selects a plurality of predetermined rows of the pixel array 501 according to the input row selection address signal and drive control signal. Then, the transfer signal, the reset signal, and the selection signal are sent to each pixel circuit 10 of the row via the signal lines L _T , L _R and L _S of the selected row.

Further, the X-direction scanning unit 503 has functions of an X-direction scanning circuit and a column circuit, and a plurality of Y-direction signal lines L from a plurality of pixel circuits 10 in a predetermined row selected by the Y-direction scanning unit 502. _The current output to _V is converted into a plurality of predetermined signals.
Further, the output circuit 505 outputs the plurality of pixel signals generated by the X-direction scanning unit 503 to the outside.

  Further, FIG. 3 is a time chart showing input signals of the respective transistors in the case of performing signal readout using the pixel circuit 10 shown in FIG. In the present embodiment (and the second and third embodiments below), the image frame rate is 120 Hz, and the interlace scanning is adopted.

In FIG. 3, each graph shows the signal waveform of SEL16, RST14 and TX12, and the numbers in parentheses after SEL, RST and TX indicate the corresponding pixel row in the screen. . Note that the accumulation time (exposure time) of each row is indicated by a black band. In the present embodiment, n is set to 4320 (rows).

In this pixel circuit 10, first, in order to reset the PD 11 for the first row (odd row) pixel, the SEL 16 is off (SEL (1) is “L” level) and RST 14 and TX 12 are simultaneously on (After RST (1) and TX (1) are set to “H” level), the off state (RST (1) and TX (1) are set to “L” level at the same time) (see arrow A in FIG. 3) . As a result, the signal charges of the PD 11 and the FD 13 are released to the VDD 17 through the TX 12 and the RST 14, and the reset process of the PD 11 is completed.
Immediately after this, the accumulation time of PD11 is started.

  In addition, after the accumulation time is started, the SEL 16 is turned on (SEL (1) becomes “H” level) (see the arrow B in FIG. 3), so that the relevant pixel is selected. When the RST 14 is turned on (RST (1) is at the “H” level), the FD 13 is reset, and the value (reset potential) in a state where the charge of the FD 13 is released by a predetermined amount is read.

Next, when TX12 turns on (TX (1) goes “H”) after RST14 goes off (RST (1) goes “L”) during the accumulation time, the signal stored in PD11 The charge is transferred to the FD 13 and the potential at this time is read (time chart of SEL (1), RST (1), TX (1), accumulation time (1) in FIG. 3: especially, see arrow C) . At this time, the accumulation time of the PD 11 ends. As described above, the time from when the pixel is selected to when the TX 12 is turned off after the RST 14 is turned off is one accumulation time of each pixel. The accumulation time is set to, for example, (1/100) seconds (= 10 milliseconds).

  Thereafter, the signal readout processing is similarly performed for the other pixels in the first row. In addition, the same process is sequentially performed on the pixels of the other odd-numbered lines (the first line, the third line,... N-1 line).

  On the other hand, the signal readout processing similar to the above processing of the first row is performed also for the second row (SEL (2), RST (2), TX (2) and storage time (2) time in FIG. 3). Refer to the chart), and the signal readout of the entire second line is completed. Thereafter, signal readout processing of other even-numbered rows such as the fourth row,..., N-th row is sequentially performed in the same manner.

  That is, in the image pickup apparatus according to the present embodiment, the read operation is performed by the interlace scan. First, the first row, the third row,. Signal is read out and the image signal recorded in the odd row is output. Subsequently, the second, fourth,... N-th rows are sequentially selected to read out the signals of all even-numbered rows, and output the image signals recorded in the even-numbered rows.

The time interval (divided image frame interval) of a frame (odd frame) composed of odd lines and a frame (even frame) composed of even lines is set to (1/120) seconds = 8.333 milliseconds. Also, the time interval (image frame interval) between frames (odd-numbered frames) in odd-numbered rows and frames (even-numbered frames) in even-numbered rows is (1/60) seconds = 16.
. It is set to 667 milliseconds.

Further, as described above, the divided image frame interval of the first line and the second line is 8.333 milliseconds, and when one is storing the charge, the other is configured to read out the signal. The same applies to the relationship between the third and fourth rows and the relationship between the n-1st row and the nth row.
In addition, it is set that the accumulation time of the odd-numbered line and the even-numbered line that follows is partially overlapped with each other, while setting each accumulation time to 10 milliseconds, between odd-numbered frames or even-numbered frames. This is to set the interval (image frame interval) to 16.667 milliseconds (60 Hz).

Hereinafter, the switching timing in this embodiment mentioned above is demonstrated using FIGS.
As described above, in the present embodiment, pixel readout scanning of the pixel array 501 is performed using the interlace method. That is, as shown in FIG. 4, the operation of performing pixel readout of only odd rows (represented by solid lines in FIG. 4) for all the rows of the pixel array 501 and only even rows (represented by dashed lines in FIG. 4) Are alternately performed. The interlace system is used in the NTSC system or the like, and is also called an interlace scan or the like.

  According to the present embodiment, as shown in FIG. 5 and FIG. 6, the image sensor (imaging device) 550 can be configured by adopting the interlace system under the illumination intensity of 100 Hz (the power supply frequency is 50 Hz) as the lighting equipment etc. The one charge storage time of the pixel (photodiode) is set to 10 milliseconds, and the occurrence of flicker is prevented while the imaging frame frequency is set to 120 Hz and adapted to Super Hi-Vision.

  That is, when the electronic shutter speed is set to 10 milliseconds in order to prevent the occurrence of flicker, the imaging frame interval (divided image frame interval) is (1/120) seconds = 8.333 milliseconds. The electronic shutter period with respect to the imaging frame interval is set to 6/5, which is larger than one.

Therefore, in the present embodiment, even if the electronic shutter speed is 10 milliseconds and the imaging frame interval is (1/120) seconds = 8.333 milliseconds, the interlace method is adopted, so the image frame interval The electronic shutter period for (odd-numbered frames or even-numbered frames) can be set to a value smaller than 1 (6/10 in the present embodiment because the interlace method is adopted). In imaging at 120 Hz under changes in illumination intensity, the occurrence of flicker can be prevented.

Second Embodiment
In addition, in this embodiment and Embodiment 3 shown below, since there are many parts which overlap with Embodiment 1, such a part is demonstrated easily suitably. In particular, since the apparatus configuration based on FIG. 2 and the operation according to FIGS. 4 to 6 are substantially the same, the detailed description thereof is omitted.

  Next, the main configuration of the pixel circuit in the imaging device according to the second embodiment will be described using an equivalent circuit diagram of a pixel circuit of a 2-pixel sharing type using 2.5 transistors per pixel using FIG. explain. Note that the pixel circuits shown in this equivalent circuit diagram are provided corresponding to two pixels arranged in parallel in the column direction (Y direction).

Further, in FIG. 7, the functions of the signal lines L _T , L _R , and L _S from the Y-direction scanning unit 502 connected to the gate portions of the transistors TX112A and B, RST114, and SEL116 are the functions described in FIG. Since they are similar, only the corresponding reference numerals are given in the drawings and the detailed description will be omitted (the description will be omitted in the same manner for the embodiment and the modified example described below).

As shown in FIG. 7, this pixel circuit 110 is a two-pixel sharing type, and includes two photodiodes (PD) 111A, B, two charge transfer transistors (TX) 112A, B,
A floating diffusion capacitance (FD) 113, a reset transistor (RST) 114, a source follower amplifier (SF) 115, a selection transistor (SEL) 116, a pixel power supply unit (VDD) 117, and a pixel output unit (OUT) 118 .

The PDs 111A and B and the TXs 112A and B are arranged in a two-pixel arrangement, and the FD 113, the RST 114, the SF 115, the SEL 116, the VDD 117 and the OUT 118 share two pixels. That is, since two transistors are configured by five transistors, it can be configured by 2.5 transistors per pixel, and one transistor is equivalent to 1.5 transistors per pixel compared to the first embodiment. This is desirable because the light receiving area can be expanded (the aperture ratio can be increased) by that amount, and the pixels can be further miniaturized.

  Further, FIG. 8 is a time chart showing input signals of respective transistors in the case of performing signal readout using the pixel circuit 110 shown in FIG. 7. In each graph, the numbers in parentheses indicate what number of lines the number is, and for example, SEL (1, 2) and RST (1, 2) are the first line And TX112B represented as TX (1) and TX112B represented as TX (2) represented as TX (1) indicate that pixel sharing is not performed, and accumulation time further (1) indicates the accumulation time of PD 111A, and accumulation time (2) indicates the accumulation time of PD 111B.

  Note that the accumulation time of each row is indicated by a black band. In the present embodiment, n is set to 4320 (rows).

  In the pixel circuit 110, first, in order to reset the PD 111A, the RST 114 and the TX 112A are simultaneously turned on (RST (1, 2) when the SEL 116 is turned off (SEL (1) is at the "L" level). And TX (1) are set to the “H” level, and then simultaneously turned off (RST (1, 2) and TX (1) are set to the “L” level). As a result, accumulation of charge is started in the PD 111A from the end of the reset (see arrow A in FIG. 8).

  Next, in order to reset PD 111 B, RST 114 and TX 112 B are simultaneously turned on (RST (1, 2) and TX (2) when SEL 116 is turned off (SEL (1) is at “L” level). Is set to the “H” level, and then simultaneously turned off (RST (1, 2) and TX (2) are set to the “L” level). Thereby, accumulation of charge is started in the PD 111 B from the end of the reset (see an arrow A ′ in FIG. 8).

In addition, when the SEL 116 is turned on (SEL (1) is at “H” level), the relevant pixel is selected (see the arrow B in the figure), and the RST 114 is turned on (RST (1, 2) is At the “H” level), the FD 113 is reset, and after the RST 114 is turned off (RST (1, 2) is at “L” level), the TX 112 A is turned on (TX (1) is at “H” level) Then, the charge is transferred to the FD 113, the voltage is read out, and when the TX 112A is turned off (TX (1) is at the “L” level), the accumulation time of the PD 111A ends (see arrow C in the figure). This accumulation time is (1/100) seconds (= 10 milliseconds) as in the first embodiment.
Set to

Further, when the SEL 116 is turned on (SEL (1) is at “H” level), the pixel is selected (see the arrow B ′ in the figure), and the RST 114 is turned on (RST (1, 2) By becoming “H” level, the FD 113 is reset, and the TX 112 B is turned on (TX (2) is “H” level) after the RST 114 is turned off (RST (1, 2) is “L” level) The charge is transferred to the FD 113, the voltage is read out, and the accumulation time of the PD 111B ends when the TX 112B is turned off (TX (2) is at the “L” level) (see arrow C ′ in the figure). This accumulation time is set to (1/100) seconds (= 10 milliseconds) as in the first embodiment.

  After all, FIG. 8 will be described in comparison with FIG. 3 showing the time chart of the input signal of the first embodiment. With regard to the input signal of SEL 116 in which pixels are shared, SEL (1) and SEL in FIG. The waveform obtained by combining (2) is used, and the RST 114 used to share pixels is a waveform obtained by combining RST (1) and RST (2) in FIG. On the other hand, with respect to TXs 112A and B in which pixel sharing is not performed, input signal waveforms similar to TX (1) and TX (2) in FIG. 3 are shown.

As described above, in the image pickup apparatus according to the present embodiment, the read operation is performed by the interlace scan, and first, the first row, the third row,. The signals of all the odd rows are read out, and the image signals recorded in the odd rows are output. Subsequently, the second, fourth,... N-th rows are sequentially selected to read out the signals of all even-numbered rows, and output the image signals recorded in the even-numbered rows. Note that the time interval (division image frame interval) of a frame (odd frame) consisting of odd rows and a frame (even frame) consisting of even rows is (1/120)
The second is set to 8.333 milliseconds.

  Thus, in the present embodiment, the occurrence of flicker can be prevented when performing imaging at 120 Hz under a 100 Hz illumination intensity change of the 50 Hz power supply frequency range.

Third Embodiment
Next, the main configuration of the pixel circuit in the imaging device according to the third embodiment is an equivalent circuit diagram of a pixel circuit mounted with a global shutter function of a 2-pixel sharing type and using 4.5 transistors per pixel. This will be described with reference to FIG. 9 (in the first and second embodiments described above, a rolling shutter is used). A pixel circuit shown in the equivalent circuit diagram is provided corresponding to two pixels arranged in parallel in the column direction (Y direction).

  As shown in FIG. 9, this pixel circuit 210 is a two-pixel sharing type, and includes two photodiodes (PD) 211A, B, two photodiode reset transistors (RPD) 221A, B, two global shutter transistors (GS) 222A, B, two charge holding capacitors (SD) 223A, B, two charge transfer transistors (TX) 212A, B, floating diffusion capacitance (FD) 213, floating diffusion capacitance reset transistor (RFD) 214, source A follower amplifier (SF) 215, a selection transistor (SEL) 216, a pixel power supply unit (VDD) 217, and a pixel output unit (OUT) 218 are provided.

The PDs 211A and B, the RPDs 221A and B, the GSs 222A and B, the SDs 223A and B, and the TXs 212A and B are provided side by side by two pixels, and the FDs 213, the RFDs 214, the SFs 215, and the SELs 216 share two pixels. That is, since two transistors are configured by nine transistors, it can be configured by 4.5 transistors per pixel, and while having the global shutter function, the number of transistors per pixel is minimized. It can be limited.

  Further, in the present embodiment, since the global shutter transistors (GS) 222A and 222B are provided, the shutter operation can be performed on all the pixels simultaneously (in fact, the odd frame pixels simultaneously and the even frame pixels simultaneously). Simultaneous readout of all pixels is possible. This makes it possible to prevent image distortion, particularly for subjects with fast motion.

  FIG. 10 shows a two-pixel sharing type shown in FIG. 9, in which signal readout is performed using the pixel circuit 210 of a CMOS imaging device equipped with a global shutter function using 4.5 transistors per pixel. It is a time chart showing the input signal of a transistor. In addition, it is an input signal waveform to SEL, RFD, TX, and the number in the parenthesis following SEL, RFD, TX has shown the line of the pixel. When two numbers, such as 1, 2 and 3, 4 etc., are described, it shows that sharing of a pixel is made. Note that the accumulation time of each row is indicated by a black band. In the present embodiment, n is set to 4320 (rows).

In this pixel circuit 210, first, PD21 for odd rows (1, 3,..., N−1)
In order to reset 1 A, the RPD 221 A is in the on state (RPD (1, 3,..., N−1
) Is set to “H” level, and then the off state (RPD (1, 3,..., N−1) becomes “
"L" level). Thereby, accumulation of charge is started in the PD 211A from the end of the reset (see the arrow D in FIG. 10).

After this, after a predetermined accumulation time has elapsed, the GS 222 A is turned on (GS (1, 3,..., N −
1) is set to “H” level, charge is transferred from PD 211A to SD 223A, and then GS222A is turned off (GS (1, 3,..., N−1) is at “L” level) As a result, the accumulation time ends (see arrow E in FIG. 10).

On the other hand, when the readout of the PD 211A is started, the SEL 216 is turned on (SEL (1, 2) is “H” level), the pixel to be read out is selected, and the RFD 214 is turned on (RFD (1,. 2) becomes “H” level, the FD 213 is reset, and then the RFD 214 is turned off (RFD (1, 2) is turned “L” level), and then the TX 212 A is turned on (TX (1) Becomes “H” level), and the charges in the SD 223A move to the FD 213. Thus, the signal charge stored in the PD 211A is read out in one storage time. This accumulation time is set to (1/100) seconds (= 10 milliseconds).

  In the above description, the first row of the odd rows is described, but as shown in FIG. 10, the timings of the other odd rows and even rows are shifted by a predetermined time, but The accumulation operation and the signal read operation are performed in the same manner as described above.

  As described above, in the image pickup apparatus according to the present embodiment, since the read operation is performed by the interlace scan, first, the first row, the third row,. The signals in all the odd rows are read out, and the image signals accumulated in each pixel in the odd rows are output. Subsequently, the second, fourth,... N-th rows are sequentially selected to read out the signals of all even rows, and output the image signals accumulated in each pixel of the even rows. A time interval (division image frame interval) of a frame (odd frame) composed of odd lines and a frame (even frame) composed of even lines is set to (1/120) seconds = 8.333 ms.

  According to the embodiment of the present invention, it is possible to suppress flicker that has conventionally occurred when performing imaging at 120 Hz under a 100 Hz illumination intensity change in the 50 Hz power supply frequency range.

  In the above embodiment, the image frame interval is 1/120 seconds = 8.333 milliseconds. However, instead of this, even if 1/120 seconds × 1001/1000 = 8.342 milliseconds, The substantially same effect as that of the embodiment can be obtained. Although the frame frequency is 120 Hz in the above embodiment, substantially the same effect as that of the above embodiment can be obtained by changing it to 120 × 1000/1001 = 119.88 Hz.

  Note that the imaging device according to the third embodiment described above can also be a backside illumination type in which light is emitted from the backside of the imaging unit.

  Furthermore, the imaging apparatus, the imaging method, and the image frame readout control circuit of the present invention are not limited to those of the above embodiment, and other various aspects may be employed. For example, in the second embodiment, although an example of a two-pixel sharing type element shared by two pixels aligned in the Y-axis direction is described, various other elements shared by a plurality of pixels are used Signal can be read out.

  Hereinafter, modifications of the second embodiment will be described with reference to the drawings.

<First variation>
For example, a shared pixel circuit can be used for a plurality of pixels larger than two. FIG. 11 shows an equivalent circuit diagram of a pixel circuit which is a 4-pixel sharing type and uses 1.75 transistors per pixel. Note that the pixel circuits shown in this equivalent circuit diagram are provided corresponding to four pixels arranged in parallel in the column direction (Y direction).

  As shown in FIG. 11, the pixel circuit 310 is configured as a four-pixel sharing type, and includes four photodiodes (PD) 311A to D, four charge transfer transistors (TX) 312A to D, and floating diffusion capacitance ( FD) 313, reset transistor (RST) 314, source follower amplifier (SF) 315, select transistor (SEL) 316, pixel power supply unit (VDD) 317, and pixel output unit (OUT) 318.

  The PDs 311A to D and TXs 312A to D are provided by arranging four pixels vertically, and the FDs 313, RST 314, SF 315, SEL 316, VDD 317, and OUT 318 are configured to share four pixels. That is, since four pixels are constituted by seven transistors, it can be constituted by 1.75 transistors per pixel, and for 2.25 transistors per pixel as compared with the first embodiment. In addition, the number of transistors per pixel may be smaller than that of the second embodiment by 0.75 for one pixel, and the light receiving area can be further expanded by that amount, which is desirable.

  Further, FIG. 12 is a time chart showing an input signal waveform of each transistor in the case of performing signal readout using the pixel circuit 310 shown in FIG.

In FIG. 12, each graph shows input signal waveforms of SEL 316, RST 314 and TXs 312A-D, and the numbers in parentheses after SELs 316, RST 314 and TXs 312A-D correspond to those in the pixel array. A row of pixels is shown. In addition, (1,2,3,4), (5,6,7,8), (n-3, n-2, n-1, n), etc., descriptions of the four numbers pertaining to SEL 316 and RST 314 are as follows: , Indicates the number of lines among the four pixel shared lines. In addition, the description of one numeral related to the TXs 312A to D, such as (1), (2), (n) in the parentheses, indicates the number of unshared lines. Note that the accumulation time of each row is indicated by a black band. Also, in the present variation, n is set to 4320 (rows).

  According to this modification, the read operation is performed by the interlace scan. First, the first row, the third row,... N−1th row are sequentially selected, the signals are read out, and the signals in all odd rows are read out , And output an image signal captured in an odd row. Subsequently, the second, fourth,... N-th rows are sequentially selected to read out the signals of all even-numbered rows, and output the image signals captured in the even-numbered rows. The time interval between the odd line frame (odd frame) and the even line frame (even frame) is set to 1/120 seconds = 8.333 milliseconds.

<Second variation>
For example, it is also possible to use pixel sharing pixel circuits arranged in parallel in the row direction (X direction). FIG. 13 shows an equivalent circuit diagram of a pixel circuit which is of a row direction two pixel sharing type and uses 2.5 transistors per pixel.

  As shown in FIG. 13, the pixel circuit 410 is configured as a two-pixel sharing type, and includes two photodiodes (PD) 411A, B, two charge transfer transistors (TX) 412A, B, and a floating diffusion capacitance It comprises the FD) 413, a reset transistor (RST) 414, a source follower amplifier (SF) 415, a selection transistor (SEL) 416, a pixel power supply unit (VDD) 417, and a pixel output unit (OUT) 418.

  FIG. 14 schematically shows the order of readout in this variation. The pixel circuit of this variation is configured to share two pixels arranged in parallel in the row direction (X direction), and adopts a method of alternately reading odd columns and even columns as shown in FIG. It is

  Note that the method of alternately reading odd columns and even columns as in this variation is not referred to as the interlace method, unlike the case of alternately reading odd rows and even rows, but one aspect of "non-progressive method" Are included in the imaging apparatus, imaging method, and image frame readout control circuit of the present invention.

  According to this variation, first, the first odd-numbered column, the second odd-numbered column, the third odd-numbered column,. Then, the signals of all even columns are read out by sequentially selecting the even column of the first row, the even column of the second row, the even column of the third row,. The image signal recorded in the even column is output.

<Third variant>
FIG. 15 shows an equivalent circuit diagram of a pixel circuit which is a 4-pixel sharing type and uses 1.75 transistors per pixel, which is the same as the first modified example described above. However, the pixel circuit shown in this equivalent circuit diagram is different from that of the first modification example described above, and corresponds to 4 pixels of 2 × 2 arranged in the row direction (X direction) and the column direction (Y direction). Provided.

  As shown in FIG. 15, the pixel circuit 510 is configured as a four-pixel sharing type, and includes four photodiodes (PD) 511A to D, four charge transfer transistors (TX) 512A to D, and a floating diffusion capacitance ( The FD 513, a reset transistor (RST) 514, a source follower amplifier (SF) 515, a selection transistor (SEL) 516, a pixel power supply unit (VDD) 517, and a pixel output unit (OUT) 518.

PDs 511A to D and TXs 512A to D are provided by arranging four pixels in two rows in the row direction (X direction) and two pixels in the column direction (Y direction) (2 × 2 pixel configuration) It is.
The FD 513, the RST 514, the SF 515, the SEL 516, the VDD 517, and the OUT 518 are shared by four pixels. That is, since four pixels are constituted by seven transistors, it can be constituted by 1.75 transistors per pixel, and for 2.25 transistors per pixel as compared with the first embodiment. In addition, the number of transistors per pixel may be smaller than that of the second embodiment by 0.75 for one pixel, and the light receiving area can be further expanded by that amount, which is desirable.

FIG. 16 is a time chart showing an input signal waveform of each transistor in the case of performing signal readout using the pixel circuit 510 shown in FIG.

In FIG. 16, each graph shows the input signal waveforms of SEL 516, RST 514 and TX 512 AD, and the numbers in parentheses after SEL 516, RST 514 and TX 512 AD correspond to the correspondence in the pixel array. A row of pixels is shown. In addition, four numbers related to SEL 516 and RST 514 such as (1, 2, 3, 4), (5, 6, 7, 8), (n-3, n-2, n-1, n) are 4 In the pixel array in which two pixels in the row direction and two pixels in the column direction are arranged among the pixel arrays considered to be pixel shared, what number pixel array when arranging each pixel in the order of upper left, upper right, lower left, lower right It shows what it is. In addition, one numeral according to TX 512A to D, such as (1), (2), (n) in the parentheses, indicates the order of 2 × 2 pixels and the vertical order of 2 × 2 pixels. Note that the accumulation time of each row is indicated by a black band. In the third variation, n is set to 8640 (2 pixels × 4320 rows).

  According to this variation, the read operation is performed by the interlace scan, and the first row, the third row,... Signal is read out, and an image signal captured in an odd row is output. Subsequently, the second, fourth,... N / 2-th rows are sequentially selected to read out the signals of all even-numbered rows, and output the image signals captured in the even-numbered rows. The time interval between the odd line frame (odd frame) and the even line frame (even frame) is set to 1/120 seconds = 8.333 milliseconds.

10, 110, 210, 310, 410, 510 Image pickup elements 11, 111A, B, 211A, B, 311A to D, 411A, B, 511A to D
Photodiode (PD)
12, 112A, B, 212A, B, 312A to D, 412A, B, 512A to D
Charge transfer transistor (TX)
13, 113, 213, 313, 413, 513 floating diffusion capacity (FD)
14, 114, 214, 314, 414, 514 reset transistor (RST)
15, 115, 215, 315, 415, 515 Source Follower Amplifier (SF)
16, 116, 216, 316, 416, 516 select transistor (SEL)
17, 117, 217, 317, 417, 517 pixel power supply unit (VDD)
18, 118, 218, 318, 418, 518 pixel output part (OUT)
221A, B Photodiode reset transistor (RPD)
222A, B Global shutter transistor (GS)
223A, B Charge Holding Capacity (SD)
214 Floating Diffusion Capacitance Reset Transistor (RFD)

Claims (7)

A photoelectric conversion unit, which is formed corresponding to a plurality of pixels arranged in an XY matrix, and generates charges according to incident light;
A CMOS-type super having a row selection circuit unit for selecting and driving an address of Y rows to the photoelectric conversion unit, and an image frame read control unit including a column parallel read out circuit unit for reading out a signal every X columns It is a high-definition standard imaging device.
The plurality of pixels are set to any of 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame readout control unit sets the division image frame interval to either 8.333 milliseconds or 8.342 milliseconds by using the non-progressive method, and stores one charge of each pixel in the photoelectric conversion unit. An imaging device characterized by setting a time to 10 milliseconds.   The image frame readout control unit is configured to control so that one charge accumulation time of each pixel is 6/10 of the readout period of each image frame. Imaging device.   The image pickup apparatus according to claim 1, wherein the non-progressive system is an interlace system.   The said photoelectric conversion part is comprised so that a pixel may be shared over the several pixel of at least one direction among the X direction and the Y direction, The any one of the Claims 1-3 characterized by the above-mentioned. Imaging device.   The image pickup apparatus according to any one of claims 1 to 3, wherein each pixel circuit of the photoelectric conversion unit has a global shutter function. In the pixel circuits provided corresponding to the plurality of pixels arranged in the XY matrix, photoelectric conversion is performed so that charges corresponding to light incident on the plurality of pixels are generated,
An image pickup device of a CMOS type super hi-vision standard which performs image frame readout in a predetermined order by designating an address of Y row and an address of X column to a plurality of pixels arranged in the XY matrix form Method,
The plurality of pixels are set to any of 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame readout uses a non-progressive method, sets an interval between divided image frames to either 8.333 milliseconds or 8.342 milliseconds, and one charge of each pixel for accumulating charges generated by the photoelectric conversion. An imaging method comprising setting an accumulation time to 10 milliseconds. A circuit, which is formed corresponding to a plurality of pixels arranged in an XY matrix, and transmits an image frame read control signal to a photoelectric conversion unit that generates electric charge according to incident light,
An image frame including a column parallel readout unit which selects an address of a Y row and drives a pixel included in the Y row and selects an address of an X column and reads a signal from the pixel included in the X column In an image frame readout control circuit in a CMOS type super high vision standard imaging device including a readout unit,
The plurality of pixels are set to any of 7680 pixels in the X direction and 4320 pixels in the Y direction, or 3840 pixels in the X direction and 2160 pixels in the Y direction,
The image frame readout operation by the image frame readout unit uses a non-progressive method and sets the divided image frame interval to either 8.333 milliseconds or 8.342 milliseconds, and each pixel in the photoelectric conversion unit In order to set one charge accumulation time of 10 ms, at least an accumulation start instruction signal and an accumulation end instruction signal corresponding to the plurality of pixels are specified from the image frame reading unit to the photoelectric conversion unit. An image frame readout control circuit for outputting in the order of