JP6522683B2 - Gaming machine - Google Patents

Description

  The present invention relates to a gaming machine such as pachislot or pachinko, for example.

  Conventionally, it is detected that a player operates a start lever by inserting a plurality of reels on which a plurality of symbols are arranged on each surface, game medals, coins and the like (hereinafter referred to as "medals and the like"), It detects that the player has pressed the start switch requesting the start of rotation of the plurality of reels and the stop button provided corresponding to each of the plurality of reels, and requests to stop the rotation of the corresponding reel A stepping motor for outputting a signal, a stepping motor provided corresponding to each of the plurality of reels and transmitting the respective driving force to each reel, and a stepping motor based on the signals outputted by the start switch and the stop switch Control of the motion of each reel, and a reel control unit for rotating and stopping each reel, and the start lever is operated When it is detected, the lottery is performed based on the random number value, and the reel rotation is performed based on the result of the lottery (hereinafter referred to as "internal winning combination") and the timing when it is detected that the stop button is operated. A so-called pachislot gaming machine is known which performs a stop.

  This type of game machine is provided with a cabinet that accommodates reels and the like, and a front door that is attached to the cabinet so as to be able to open and close. The reel housed in the cabinet is viewed by the player through a display window provided on the front door. The cabinet is provided with a main control board (main board) which constitutes a main control circuit. The main control circuit determines, for example, the determination of the internal winning combination performed using random numbers in the program, rotation and stop of the plurality of reels, presence or absence of a prize based on the symbol displayed in the display window when the plurality of reels are stopped. Control the main flow of the game in the gaming machine, such as the determination of. On the other hand, a sub control board (sub board) which constitutes a sub control circuit is disposed on the front door. The sub control circuit controls the execution of the effect by the display of sound and video. This effect is determined by the sub control circuit based on, for example, the operation of the start lever by the player, the internal winning combination determined by the main control circuit, or the like. Among the effects executed in this manner, for example, there is one that reports information that is advantageous to a player related to AT (assist time) or ART (a benefit that combines an assist time and a replay time). In addition, some gaming machines have an external output board having a plurality of output terminals for outputting external output information from a main control board to an external device such as a so-called hall computer as an external output function (see FIG. See, for example, Patent Document 1).

JP, 2010-221051, A

  However, in the gaming machine provided with the above-mentioned conventional external output function, a plurality of gaming machines are connected to the hall computer, and when the plurality of external output information is disorderly output without adjusting the output timing on the gaming machine side, The processing load on the hall computer is very large, and there is a risk that processing omission may occur.

  The present invention has been conceived under the above-mentioned circumstances, and when outputting a plurality of external output information to an external device, it is possible to adjust the output timing of those, and thus the processing load of the external device. It is an object of the present invention to provide a gaming machine capable of reducing the

The gaming machine of the present invention is
A control unit that performs various controls related to the game;
And external output means for outputting external output information from the control unit to an external device outside the gaming machine,
The control unit
Control processing means for performing control processing related to gaming;
The external output information is input from the control processing means at a first communication speed, and the external output information is output at a second communication speed higher than the first communication speed according to the output destination. Communication means, and
The external output means is
A second communication unit that receives the external output information from the first communication unit and outputs the external output information;
And output means for inputting the external output information from the second communication means and outputting the external output information converted into a relay output signal to the external device.
The control processing means
As the external output information, it is possible to output first external output information indicating payout of gaming media, and includes delay time information indicating that external output should be performed after a predetermined time has elapsed subsequent to the first external output information. While being able to output second external output information, it is also possible to output third external output information that is externally output at a timing different from that of the first external output information,
The first communication means is
The external output information input from the control processing means is distinguished into command information indicating the type of command and setting data indicating a parameter accompanying the command information, and the type of the command is determined by referring to the command information And output information generating means for executing processing according to the type of the command,
The output information generation means
First information generating means for generating first output information suitable for converting the external output information based on the first external output information, when the external output information is the first external output information; ,
A second information generation unit that generates second output information suitable for converting the external output information based on the second external output information when the external output information is the second external output information; ,
Third information generation means for generating third output information suitable for converting the external output information based on the third external output information, when the external output information is the third external output information; ,
It has an information output unit that outputs the first output information, the second output information, and the third output information to the second communication unit as an operable function.
The second communication means is
An information input unit that receives the first output information, the second output information, and the third output information output from the information output unit, and stores the output information in a storage area ;
When the first output information, the second output information, and the third output information input by the information input unit are different from the information of the storage area, the output unit may output the information to the output unit. A signal output unit that converts the relay output signal to the external device via the output unit is characterized as having an operable function.
In addition, other gaming machines of the present invention are:
Main control processing means for performing various main control processing relating to the game;
Secondary control processing means for performing various secondary control processes on a plurality of peripheral devices;
Main control output means for outputting main control information from the main control processing means to the sub control processing means;
And external output means for outputting external output information from the main control processing means to an external device outside the gaming machine.
The external output means is
A first communication unit that receives the external output information from the main control processing unit, encrypts the external output information, and outputs the encrypted information by a serial communication method;
A second communication unit that receives the encrypted external output information from the first communication unit and decrypts and outputs the external output information;
And output means for inputting the external output information from the second communication means and outputting the external output information to the external device in parallel signal system,
The main control processing means
The first external output information can be output as the external output information, and second external output information to be externally output can be output following the first external output information,
The first communication means is
The first external output information input from the main control processing means is distinguished into command information indicating the type of command and setting data indicating parameters accompanying the command information, and the command is referred to by the command. The first continuous output information suitable for the external output information is generated by the parallel signal system on the basis of the first external output information by processing according to the type of the command. The second external output information input from the main control processing means is divided into command information indicating the type of command and setting data indicating parameters accompanying the command information, and the command information is referred to. The type of command is determined, and the parallel processing is performed based on the second external output information by processing according to the type of the command. A continuous output information generation means for generating a second continuous output information appropriate to the external output information in issue method,
An information output unit that outputs the first continuous output information to the second communication unit and then outputs the second continuous output information to the second communication unit; Have
The second communication means is
Information input means for inputting the first continuous output information output from the information output means, and thereafter inputting the second continuous output information;
The first continuous output information input by the information input unit is output to the external device through the output unit as a first signal according to the parallel signal system, and then the second input is input by the information input unit And signal output means for outputting the continuous output information to the external device through the output means as a second signal in accordance with the parallel signal system.

  According to such a configuration, the first communication means can output the predetermined output method only by the main control processing means sequentially outputting the first external output information and the second external output information to the first communication means. Then, first continuous output information corresponding to the first external output information is generated, and thereafter, second continuous output information corresponding to the second external output information is generated by a predetermined output method. Then, after the first continuous output information is output to the second communication unit, the second continuous output information is output to the second communication unit, so that the second communication unit is an output unit. After the first signal corresponding to the first continuous output information is output to the external device by the predetermined output method through the second output signal, the second signal corresponding to the second continuous output information is output to the external device by the predetermined output method Will be output. Thereby, the main control processing means can continuously output the first external output information and the second external output information according to the serial communication system, and thereby the first signal according to the respective information and the second signal. Since the signal of 2 is sequentially and appropriately output to the external device, a plurality of information to be externally output can be input / output in order, and thus the processing load on the external device can be reduced.

In a preferred embodiment of the invention:
The signal output unit converts each of the first continuous output information and the second continuous output information into the first signal and the second signal according to a general-purpose input / output system as the predetermined output system. It is characterized by converting and outputting.

  According to such a configuration, the main control processing unit converts the first external output information and the second external output information to be output to the external device into, for example, port output data according to the general purpose input / output method. The first communication means and the second communication means can output the first external output information and the second external output information from the main control processing means as the first continuous output information. And the second continuous output information, and finally the first signal and the second signal according to the general-purpose input / output system are converted and output, so that the first communication means and the second communication Input / output of information between the means can be efficiently performed by the serial communication method.

In a preferred embodiment of the invention:
The first communication means is
An encryption unit that encrypts the first continuous output information and the second continuous output information using a common key encryption method;
And modulation means for modulating the first continuous output information and the second continuous output information encrypted by the encryption means according to a binary phase shift keying modulation method,
The second communication means is
Demodulation means for demodulating the first continuous output information and the second continuous output information modulated by the modulation means according to the binary phase shift keying system;
And decoding means for decoding the first continuous output information and the second continuous output information demodulated by the demodulation means according to the common key cryptosystem.

  According to such a configuration, the first external output information and the second external output information are output from the main control processing means to the first communication means, and from the first communication means to the second communication means. First continuous output information and second continuous output information according to the first external output information and the second external output information are output. At this time, the first continuous output information and the second continuous output information are encrypted according to the common key cryptosystem, and further modulated according to the binary phase shift keying and output. In the second communication means, the first continuous output information and the second continuous output information input from the first communication means are demodulated by the binary phase shift keying method and further demodulated into the first continuous output information After the second continuous output information is decrypted by the common key cryptosystem, the first signal and the second signal according to the information are output to the external device. Thereby, information can be correctly and stably input / output between the first communication means and the second communication means by the binary phase shift keying system. In addition, since the clock rate can be embedded when inputting and outputting information in the binary phase shift keying system, it is possible to efficiently input and output information also in the asynchronous communication system.

  According to the present invention, it is possible to provide a gaming machine capable of adjusting the output timing of a plurality of external output information to an external device when outputting the external output information, and thus reducing the processing load on the external device. it can.

1 is a perspective view showing an appearance of a gaming machine according to an embodiment of the present invention. It is a perspective view showing the internal structure of the game machine concerning one embodiment of the present invention. It is a block diagram showing composition of a main control circuit of a game machine concerning one embodiment of the present invention. It is a block diagram showing composition of a sub control circuit of a game machine concerning one embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a main board communication LSI and a sub board communication LSI of the gaming machine according to the embodiment of the present invention. It is a schematic diagram which shows the connection form of the main board | substrate and subboard of the game machine which concerns on one Embodiment of this invention. It is a schematic diagram which shows the AES circuit in main board | substrate communication LSI and sub board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is an explanatory view showing a flow of data of a game machine concerning one embodiment of the present invention. It is an explanatory view showing a flow of data of a game machine concerning one embodiment of the present invention. It is a schematic diagram which shows the connection form of the main board | substrate of the game machine which concerns on one Embodiment of this invention, and an external concentration terminal board. It is a block diagram showing composition of communication LSI for external output of a game machine concerning one embodiment of the present invention, and external terminal board control LSI. It is an explanatory view showing a flow of data and signals of a gaming machine according to an embodiment of the present invention. It is a timing chart which shows an example of command output of a game machine concerning one embodiment of the present invention. It is a timing chart which shows an example of command output of a game machine concerning one embodiment of the present invention. It is a timing chart which shows an example of command output of a game machine concerning one embodiment of the present invention. It is a timing chart which shows an example of command output of a game machine concerning one embodiment of the present invention. It is a timing chart which shows an example of command output of a game machine concerning one embodiment of the present invention. It is a timing chart which shows an example of command output of a game machine concerning one embodiment of the present invention. It is a timing chart which shows an example of command output of a game machine concerning one embodiment of the present invention. It is a timing chart which shows an example of command output of a game machine concerning one embodiment of the present invention. It is a timing chart which shows an example of command output of a game machine concerning one embodiment of the present invention. It is an explanatory view showing a symbol arrangement table and a symbol code of a game machine according to an embodiment of the present invention. It is an explanatory view showing a symbol combination table of a gaming machine according to an embodiment of the present invention. It is an explanatory view showing a bonus operation time table of the gaming machine according to one embodiment of the present invention. It is an explanatory view showing an internal lottery table for a general gaming state of a gaming machine according to an embodiment of the present invention. It is explanatory drawing which shows the internal lottery table for during RB operation of the game machine which concerns on one Embodiment of this invention. FIG. 16 is an explanatory view showing an internal winning combination determination table for a small winning combination / replay of a gaming machine according to an embodiment of the present invention. It is an explanatory view showing a bonus internal winning combination determination table of a gaming machine according to an embodiment of the present invention. It is an explanatory view showing an internal winning combination storing area of a gaming machine according to an embodiment of the present invention. It is an explanatory view showing a carryover combination storage area of a gaming machine according to one embodiment of the present invention. It is an explanatory view showing the flag storage area during operation of the gaming machine according to one embodiment of the present invention. It is a figure which shows the main flowchart by control of main CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the medal reception / start check process by main CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the internal lottery process by main CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reel stop control processing by main CPU of the game machine which concerns on one Embodiment of this invention. It is a flow chart which shows bonus operation check processing by main CPU of a game machine concerning one embodiment of the present invention. It is a flowchart which shows the bonus end check process by main CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the interruption processing by control of main CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception interruption process by sub CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the main board | substrate communication processing by sub CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows communication LSI reception data analysis processing by sub CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the effect registration task performed by sub CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the contents determination processing of an effect by sub CPU of the game machine which concerns on one Embodiment of this invention. It is the schematic which shows the menu screen of the game machine which concerns on one Embodiment of this invention. It is the schematic which shows the error information history screen of the game machine which concerns on one Embodiment of this invention. It is an explanatory view showing a code number of a receiving command used for a game machine concerning one embodiment of the present invention, classification, and a parameter. It is an explanatory view showing a communication log collecting area in a sub RAM of a gaming machine according to an embodiment of the present invention. It is explanatory drawing which shows the communication error preservation | save area | region in sub RAM of the game machine which concerns on one Embodiment of this invention. It is an explanatory view showing a frame of communication data used for a game machine concerning one embodiment of the present invention. It is an explanatory view showing a frame of communication data used for a game machine concerning one embodiment of the present invention. It is explanatory drawing which shows the reception status in the communication data of the game machine which concerns on one Embodiment of this invention. It is an explanatory view showing a packet classification in communication data of a game machine concerning one embodiment of the present invention. It is an explanatory view showing a flow of communication data of a gaming machine according to an embodiment of the present invention. It is an explanatory view showing a field picture in sub RAM of a game machine concerning one embodiment of the present invention. It is an explanatory view showing an error information history storage area and an error code in a sub RAM of a gaming machine according to one embodiment of the present invention. It is a flowchart which shows the main control sequence by main substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception interruption process by main substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the initialization processing by the main board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception process by main substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the transmission processing by main substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the main control sequence by subboard communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception interruption process by the sub board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the initialization processing by the sub board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception process by the sub board | substrate communication LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the transmission processing by subboard communication LSI of the game machine which concerns on one Embodiment of this invention. It is an explanatory view showing a command outputted outside in a game machine concerning one embodiment of the present invention. It is an explanatory view showing Bit arrangement of various areas relevant to external output of a game machine concerning one embodiment of the present invention. It is an explanatory view showing a software timer used for external output in a game machine concerning one embodiment of the present invention. It is a flowchart which shows the medal in command registration process for external output by main CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the medal out command registration process for external output by main CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the command external output processing by main CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the external signal edit process by main CPU of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the main control sequence by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception interruption process by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the timer interruption process by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flow chart which shows reception processing by communication LSI for external output of a game machine concerning one embodiment of the present invention. It is a flowchart which shows the command output conversion process by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flow chart which shows medal in output conversion processing by communication LSI for external output of a game machine concerning one embodiment of the present invention. It is a flowchart which shows the token out output conversion process by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the external output conversion process by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the external output ON output conversion process by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the external output OFF output conversion process by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the security output conversion process by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the output control processing by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flow chart which shows medal in output control processing by communication LSI for external output of a game machine concerning one embodiment of the present invention. It is a flowchart which shows the medal out output control processing by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the setting output control processing by communication LSI for external output of the game machine which concerns on one Embodiment of this invention. It is a flow chart which shows time return output control processing by communication LSI for external output of a game machine concerning one embodiment of the present invention. It is a flowchart which shows the main control sequence by the external terminal board control LSI of the game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the reception interruption process by the external terminal board control LSI of the game machine which concerns on one Embodiment of this invention. It is a schematic diagram which shows the connection form of the main board | substrate and subboard | substrate of the game machine which concerns on other embodiment of this invention. It is a schematic diagram which shows the connection form of the main board | substrate and subboard | substrate of the game machine which concerns on other embodiment of this invention. It is explanatory drawing which shows the flow of the data of the game machine which concerns on other embodiment of this invention. It is a schematic diagram which shows the connection form of the main board | substrate and subboard | substrate of the game machine which concerns on other embodiment of this invention. It is explanatory drawing which shows the flow of the data of the game machine which concerns on other embodiment of this invention. It is a perspective view which shows the external appearance of the game machine which concerns on other embodiment of this invention. It is a block diagram which shows the structure of the game machine which concerns on other embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

[Appearance configuration of gaming machine]
FIG. 1 is a perspective view showing the appearance of a gaming machine according to an embodiment of the present invention. As shown in the figure, in the present embodiment, a pachi slot 1 is applied as a gaming machine. The exterior body 2 of the pachi slot 1 has a cabinet 2a for accommodating a reel, a circuit board and the like, and a front door 2b attached to the cabinet 2a so as to be able to open and close. Handles 7 are provided on both sides of the cabinet 2a. The handle 7 is a concave portion which is used when carrying the pachislot 1.

  Inside the cabinet 2a, three reels 3L, 3C, 3R are provided side by side. Each of the reels 3L, 3C, 3R is referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively, when individually described. Each of the reels 3L, 3C, 3R has a cylindrical reel body and a translucent sheet material mounted on the peripheral surface of the reel body. On the surface of the sheet material, a plurality of (for example, 21) designs are drawn at predetermined intervals along the circumferential direction.

  A liquid crystal display device 10 is provided at the center of the front door 2b. The liquid crystal display device 10 has a display screen including a liquid crystal display area 10A and symbol display areas 4L, 4C, 4R, and is positioned in front of the three reels 3L, 3C, 3R when viewed from the front. It is provided. In the present embodiment, an image is displayed and effects are performed using the entire display screen including the liquid crystal display area 10A and the symbol display areas 4L, 4C, 4R.

  The symbol display areas 4L, 4C, 4R are provided corresponding to the three reels 3L, 3C, 3R, respectively. The symbol display areas 4L, 4C, 4R serve as display windows, and are configured to be able to transmit the respective reels 3L, 3C, 3R provided behind them. The symbol display areas 4L, 4C, 4R are respectively referred to as a left display window 4L, a middle display window 4C, and a right display window 4R when individually described.

  When the rotation of the reels 3L, 3C, 3R provided behind the display windows 4L, 4C, 4R is stopped, the upper stage in the frame of the plural types of symbols of the respective reels 3L, 3C, 3R, One symbol (three in total) is displayed in each of the middle and lower areas. It is an object to determine whether or not a pseudo line formed by combining any one of predetermined three areas among the upper, middle, and lower areas of the display windows 4L, 4C, and 4R is determined to be winning or not. It is defined as a line (winning judgment line).

  In the present embodiment, a center line 8 is provided as a winning determination line. The center line 8 is a combination of the middle of the left display window 4L, the middle of the middle display window 4C, and the middle of the right display window 4R.

  Below the display screen of the liquid crystal display device 10, a 7-segment display 6 consisting of a 7-segment LED is provided. The 7-segment display 6 digitally displays information such as the number of medals to be paid out to the player as benefits (hereinafter, the number of payouts) and the number of medals deposited inside the pachislot 1 (hereinafter, the number of credits). indicate.

  The front door 2b is provided with various devices to be operated by the player. The medal insertion slot 11 is provided to receive medals dropped from the outside by the player. The medals accepted in the medal insertion slot 11 will be inserted in one game with the predetermined number as the upper limit, and the portion exceeding the predetermined number can be deposited inside the pachislot 1 (So-called credit function).

  On the left of the medal insertion slot 11, a selection button 11A and a determination button 11B are provided. The player or the attendant can input the menu screen or the like displayed in the liquid crystal display area 10A with the selection button 11A and the determination button 11B.

  The maximum BET button 12 is provided to determine the maximum number of medals to be inserted into one game from the medals deposited inside the pachislot 1. The settlement button 14 is provided to pull out the medals deposited inside the pachislot 1 to the outside.

  The start lever 16 is provided to start the rotation of all the reels 3L, 3C, 3R. The stop buttons 17L, 17C, and 17R are associated with the three reels 3L, 3C, and 3R, respectively, and are provided to stop the rotation of the corresponding reels. The stop buttons 17L, 17C, and 17R are respectively referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R when individually described.

  The medal payout opening 18 guides the medals discharged by the driving of a medal payout device 34 described later to the outside. The medals discharged from the medal payout opening 18 are stored in the medal receiver 19. The lamp (LED or the like) 20 outputs light in a pattern of on / off according to the contents of the effect. The speaker holes 48, 49, 22L, 22R are provided to output sounds such as sound effects and music according to the contents of the effect.

  The pachi slot 1 is provided with a lock mechanism that switches the front door 2b to a locked state or an unlocked state in a state where the front door 2b is closed. This lock mechanism is operated by inserting the door key 110 into the door key hole 11C and rotating the door key 110.

  The door key 110 is inserted into the door key hole 11C and, for example, the front door 2b can be opened and closed by being turned right and the main control circuit 60 (see FIG. 3) described later is electrically turned by being turned left. It is supposed to be reset. That is, the door key 110 has a reset function of electrically resetting the pachi slot 1 in addition to the operation of the lock mechanism.

[Internal structure of gaming machine]
FIG. 2 is a perspective view showing the internal structure of the gaming machine according to the embodiment of the present invention. On the upper side inside the cabinet 2a, a main control board 6A (a main board 6A described later, and not shown in FIG. 2 but not shown in FIG. 2) constituting a main control circuit 60 (see FIG. 3) is disposed. The main control circuit 60 is a circuit for controlling the main flow of the game in the pachislot 1 such as determination of the internal winning combination, rotation and stop of the reels 3L, 3C, 3R, and determination of the presence or absence of winning. The specific configuration of the main control circuit 60 will be described later.

  Three reels 3L, 3C, 3R are provided at the center of the interior of the cabinet 2a. FIG. 2 shows a state in which the sheet material is removed from each of the reels 3L, 3C, 3R to expose the reel body. The stepping motors 50L, 50C, and 50R (see FIG. 3) are connected to the three reels 3L, 3C, and 3R through gears having predetermined reduction ratios.

  When the inside of the cabinet 2a is viewed from the front, a setting key type switch (not shown) and an external concentrated terminal plate 9A (not shown in FIGS. 2 and 3) are disposed on the right of the right reel 3R. It is done. The setting key type switch is used by using the setting key when changing or confirming the setting of the pachi slot 1. The external concentrated terminal plate 9A is attached to the side plate of the cabinet 2a. The external concentrated terminal plate 9A is provided to output signals such as a medal insertion signal, a medal payout signal, and a security signal to an external device (for example, a hall computer) outside the pachislot machine 1. Further, when the inside of the cabinet 2a is viewed from the front, an external relay board 8A (not shown in FIG. 2 and see FIGS. 3 and 10) is disposed on the left side of the left reel 3L. The external relay board 8A relays the wiring that connects the main control board 6A and the external concentrated terminal plate 9A via the optical fiber cable 100 (not shown in FIG. 2, see FIG. 10 etc.). Specific configurations of the external relay substrate 8A and the external concentrated terminal plate 9A will be described later.

  Below the inside of the cabinet 2a, a medal payout device (hereinafter, a hopper device) 34 having a structure capable of containing a large amount of medals and capable of discharging them one by one is provided. The hopper device 34 pays out the medals when the stored medals exceed 50, for example, or when the settlement button is pressed and the medals are settled. The medals paid out by the hopper device 34 are discharged from the medal payout opening 18 (see FIG. 2).

  When the inside of the cabinet 2a is viewed from the front, a medal auxiliary storage 35 for storing medals overflowing from the hopper device 34 is disposed on the right side of the hopper device 34. Further, when the inside of the cabinet 2a is viewed from the front, a power supply device 36 for supplying necessary power to each device of the pachi slot 1 is provided on the left side of the hopper device 34. Further, a sub speaker 37 is disposed between the hopper device 34 and the three reels 3L, 3C, 3R.

  A sub control board case 42 for accommodating a sub control board 7A (a sub board 7A described later, see FIG. 6 not shown in FIG. 2) is disposed on the upper side of the back surface of the front door 2b. The sub control board 7A is opposed to the main control board 6A inside the cabinet 2a via the sub control board case 42. The sub control board 7A constitutes a sub control circuit 70 (see FIGS. 3 and 4). The sub control board 7A is connected to the main control board 6A by an optical fiber cable 100 (not shown in FIG. 2, see FIG. 6) via a door relay board 53 described later. The sub control circuit 70 is a circuit that controls execution of effects by displaying a video or the like. The specific configuration of the sub control circuit 70 will be described later.

  When the front door 2b is viewed from the back side, a sub relay board 43 is disposed on the right side of the sub control board case 42. The sub relay board 43 is a board for relaying the wiring between the sub control board 7A and a board disposed around the sub control board 7A. In addition, as a board | substrate arrange | positioned around the sub control board 41, LED board 45A, 45B, 45C mentioned later and the sound I / O board 46 are mentioned.

  LED boards 45A, 45B, 45C and a sound I / O board 46 are disposed at appropriate portions on the back side of the front door 2b. The LED substrates 45A, 45B, and 45C display and control the blinking pattern by the lamp (LED or the like) 20 according to the effect executed by the control of the sub control circuit 70. The sound I / O board 46 outputs sound to speakers 48L, 48R, 49L, 49R (48, 49) described later.

  Below the sound I / O board 46, a gaming operation display board (not shown) is disposed. This game operation display board displays the number of inserted medals on the 7-segment indicator 6 when the three reels 3L, 3C, 3R are rotatable and when the player plays a game again, when accepting the insertion of medals. It is a substrate for

  Upper speakers 48 L and 48 R (48) are disposed on the left and right sides of the sound I / O substrate 46. The lower speakers 49L and 49R (49) are disposed below the rear surface of the front door 2b. The upper speakers 48L and 48R face the speaker holes 48 and 49, respectively, and the lower speakers 49L and 49R face the speaker holes 22L and 22R, respectively.

  A selector 51 and a door open / close monitoring switch 52 are disposed between the upper speaker 48R and the lower speaker 49R. The selector 51 is a device for selecting whether or not the material, shape, and the like of the medals are appropriate, and guides the appropriate medals accepted by the medal insertion slot 11 to the hopper device 34. A medal sensor (not shown) for detecting that a proper medal has passed is provided on a path through which the medal passes in the selector 51.

  The door open / close monitoring switch 52 is disposed on the left side of the selector 51 when the front door 2 b is viewed from the back side. The door opening / closing monitoring switch 52 outputs a security signal for notifying the opening / closing of the front door 2 b to the outside of the pachi slot 1.

  A door relay board 53 is disposed on the right side of the selector 51 when the front door 2b is viewed from the back side. The door relay board 53 is a board that relays wiring between the main control board 6A, various buttons and switches, the sub control board 7A, the game operation display board, and the selector 51. Examples of the various buttons and switches include a maximum BET button 12, a settlement button (C / P button) 14, a door open / close monitoring switch 52, and a maximum BET switch 13S and a start switch 6S described later.

  Under the door relay board 53, a 24h door open / close monitoring unit (not shown) is disposed. The 24h door opening and closing monitoring unit stores the opening and closing history of the front door 2b. When the front door 2b is opened or the selector 51 is removed, a signal for displaying an error on the liquid crystal display device 10 is output to the sub control board 7A (sub control circuit 70).

  Next, with reference to FIGS. 3 to 11, the electrical configuration of the pachislot 1 and the configuration related to the communication function will be described. FIG. 3 is a block diagram showing the configuration of the main control circuit. FIG. 4 is a block diagram showing the configuration of the sub control circuit. FIG. 5 is a block diagram showing configurations of a main board communication LSI and a sub board communication LSI. FIG. 6 is a schematic view showing a connection form of the main substrate and the sub substrate. FIG. 7 is a schematic view showing an AES circuit in the communication LSI. 8 and 9 are explanatory diagrams showing the flow of data. FIG. 10 is a schematic view showing the connection between the main substrate and the external concentrated terminal plate. FIG. 11 is a block diagram showing the configuration of the external output communication LSI and the external terminal board control LSI. In the following description, “reception” and “transmission” may be used as terms synonymous with “input” and “output”.

[Configuration of main control circuit]
The main control circuit 60 controls the progress of a series of games such as determination of an internal winning combination and rotation control of reels. The main control circuit 60 has a microcomputer 600 disposed on a main substrate 6A (see FIG. 6) as a main component, and is configured by adding a circuit for random number sampling to this. The microcomputer 600 includes a main CPU 601, a main ROM 602, and a main RAM 603.

  To the main CPU 601, a clock pulse generation circuit 604, a frequency divider 605, a random number generator 606, and a sampling circuit 607 are connected.

  The main CPU 601 determines the internal winning combination based on the random number value and the internal lottery table described later, and stops the rotation of the reels 3L, 3C, 3R based on the internal winning combination and the timing when the stop operation is detected. Let When stopping the rotation of the reels 3L, 3C, 3R, the main CPU 601 determines whether or not the combination is realized based on the combination of the symbols displayed in the symbol display areas 4L, 4C, 4R. If the player is awarded (winning), the player is given a profit such as paying out a medal according to the winning combination.

  Clock pulse generation circuit 604 and frequency divider 605 generate reference clock pulses. The random number generator 606 generates random numbers in the range of “0” to “65535”. The sampling circuit 607 extracts (samples) one random number value from the random number generated by the random number generator 606.

  The main CPU 601 stores the extracted random number value in a random number value storage area of the main RAM 603 described later. Then, the main CPU 601 determines an internal winning combination in an internal lottery process described later, based on the random number value stored in the random number storage area of the main RAM 603 every game.

  As means for random number sampling, random number sampling may be performed in the microcomputer 600, that is, on the operation program of the main CPU 601. In that case, the random number generator 606 and the sampling circuit 607 can be omitted. Alternatively, it is possible to leave it for backup of the random number sampling operation.

  The main ROM 602 stores programs related to the processing of the main CPU 601, various tables, and the like.

  Various information obtained by the processing of the main CPU 601 is set in the main RAM 603. For example, information for specifying the extracted random value, gaming state, internal winning combination, number of payouts, bonus carry-over status, setting value, etc., various counters, and a flag are set. A part of these pieces of information is transmitted as a command to the sub-substrate 7A (sub-control circuit 70) and the external concentrated terminal plate 9A.

  Examples of main peripheral devices whose operation is controlled by a control signal from the microcomputer 600 include a medal payout device (hopper device) 34, stepping motors 50L, 50C, 50R and the like. The exchange of signals between these actuators and the main CPU 601 is performed via the bus 60A.

  Each circuit for controlling the operation of each peripheral device described above is connected to the bus 60A in response to a control signal output from the main CPU 601. As each circuit, there are a motor drive circuit 39, a display unit drive circuit 340, and a hopper drive circuit 341.

  The motor drive circuit 39 drives and controls the stepping motors 50L, 50C, and 50R. As a result, the reels 3L, 3C, 3R are rotated or stopped.

  The display drive circuit 340 controls the display of the 7-segment display 6. As a result, the number of payouts, the number of credits, and the like are displayed on the 7-segment display 6.

  The hopper drive circuit 341 drives and controls the hopper device 34. As a result, the medals stored in the hopper device 34 are paid out.

  Further, to the bus 60A, switches and circuits that generate input signals that trigger output of control signals to the circuits and peripheral devices described above are connected. As each switch and each circuit, start switch 6S, stop switches 7LS, 7CS, 7RS, maximum BET switch 13S, settlement switch (C / P switch) 14S, medal sensor 22S, reel position detection circuit 50, payout completion signal circuit 342 There is. The stop switches 7LS, 7CS, 7RS are collectively referred to as a stop switch 7S.

  The start switch 6S detects the player's start operation on the start lever 16, and outputs a start signal for instructing start of the game to the microcomputer 600.

  The stop switches 7LS, 7CS, 7RS respectively detect the stop operation of the player for the stop buttons 7L, 7C, 7R and stop the rotation of the reels 3L, 3C, 3R corresponding to the detected stop buttons 7L, 7C, 7R A stop signal to be commanded is output to the microcomputer 600.

  The maximum BET switch 13S detects a player's insertion operation (pressing operation) for the maximum BET button 12, and outputs a signal instructing the microcomputer 600 to insert a medal from a credited medal.

  The settlement switch 14S detects the switching operation of the player on the settlement button 14, and outputs a signal for switching the credit mode or the payout mode to the microcomputer 600. Further, when the credit mode is switched to the payout mode, a signal instructing the payout of medals credited to the pachislot 1 is output to the microcomputer 600.

  The medal sensor 22S detects a medal inserted into the medal insertion slot 11 by the player's insertion operation, and outputs a signal indicating that the medal is inserted to the microcomputer 600.

  The reel position detection circuit 50 detects a pulse signal from a reel rotation sensor (not shown) and generates a signal for detecting the position of the symbol on each reel 3L, 3C, 3R.

  The payout completion signal circuit 342 completes the medal payout when the number of medals detected by the medal detection unit 34S (that is, the number of medals paid out from the hopper device 34) reaches the designated number. Generates a signal to indicate.

  To the main control circuit 60, a main substrate communication LSI 610 for transmitting information such as a command to the sub control circuit 70 is connected. The main substrate communication LSI 610 is mounted on the main substrate 6A (see FIG. 6) as an element constituting the main control circuit 60 together with the microcomputer 600. The main substrate communication LSI 610 is connected to the sub control circuit 70 via the door relay substrate 53 by an optical fiber cable 100 (see FIG. 6) as an optical transmission medium. The microcomputer 600 (main CPU 601) transmits various commands and the like to the sub control circuit 70 through the main substrate communication LSI 610. The main CPU 601 of the present embodiment incorporates the first UART 601A, and the main CPU 601 can transmit information to the main substrate communication LSI 610 through the first UART 601A (see FIG. 6). Details of such a main board communication LSI 610 and the first UART 601A will be described later.

  The sub control circuit 70 performs various processes such as determination and execution of effect data based on various commands transmitted from the main control circuit 60 including a start command described later. The sub control circuit 70 does not transmit a command, information or the like to the main control circuit 60, and communication is performed in one direction (one direction) from the main control circuit 60 to the sub control circuit 70.

  The main peripheral devices whose operations are controlled by the control signal from the sub control circuit 70 include the liquid crystal display device 10 as display means for displaying an image on the liquid crystal display area 10A, the speakers 48 and 49, the lamp 20 and the like. is there. The sub control circuit 70 determines and displays the image displayed on the liquid crystal display device 10 based on the determined effect data, determines and outputs the light emission pattern of the various lamps 20, and outputs the effect sound output from the speakers 48 and 49. It controls the determination and output of sound effects. The details of the sub control circuit 70 will be described later.

  Further, to the main control circuit 60, an external output communication LSI 610A for outputting information such as a command to the hall computer 1000 installed outside the pachislot 1 is connected. The external output communication LSI 610A is mounted on the main substrate 6A (see FIG. 10) as an element constituting the main control circuit 60 together with the microcomputer 600. The external output communication LSI 610A is connected to an external terminal board control LSI 910, which will be described later, of the external concentrated terminal board 9A via an external relay board 8A by an optical fiber cable 100 (see FIG. 10) as an optical transmission medium. The microcomputer 600 (main CPU 601) transmits various commands and the like to the external terminal board control LSI 910 of the external concentrated terminal board 9A through the external output communication LSI 610A. The main CPU 601 according to this embodiment incorporates a second UART 601B different from the first UART 601A, and the main CPU 601 can transmit information to the external output communication LSI 610A through the second UART 601B (see FIG. 10). . Details of such an external output communication LSI 610A and the second UART 601B will be described later.

  As shown in FIG. 10, the external concentrated terminal board 9A has an external terminal board control LSI 910 for outputting a command or the like from the external output communication LSI 610A to the hall computer 1000 (see FIG. 3). The external terminal board control LSI 910 does not transmit commands or information to the external output communication LSI 610A of the main control circuit 60, and communicates from the main board 6A toward the external concentrated terminal board 9A in a single direction (one direction) Is done. The external output communication LSI 610A and the external terminal board control LSI 910 have substantially the same configuration as the main substrate communication LSI 610. The details of the external output communication LSI 610A and the external terminal board control LSI 910 will be described later.

  In the pachi slot 1, when a signal to start the game is output from the start switch 6S by the operation of the player's start lever 16 on condition of medal insertion, a control signal is output to the motor drive circuit 39, and the stepping motor 50L , 50C, 50R (for example, excitation to each phase, etc.), rotation of the reels 3L, 3C, 3R is started. At this time, the number of pulses output to the stepping motors 50L, 50C, 50R is counted, and the count value is set in a predetermined area of the main RAM 603 as a pulse counter. In the pachi slot 1, when the pulse "16" is output, the reels 3L, 3C, 3R move by one symbol. The number of moved symbols is counted, and the count value is set in a predetermined area of the main RAM 603 as a symbol counter. That is, each time "16" pulses are counted by the pulse counter, the symbol counter is updated by "1". The symbol (see FIG. 22) at the symbol position indicated by the value of the symbol counter corresponds to the symbol located on the center line 8. For example, when the symbol counter of the left reel 3L is “0”, the bell of the symbol position “0” of the symbol arrangement table shown in FIG. 22A is located on the center line 8.

  Further, from the reels 3L, 3C, 3R, a reel index is obtained for each rotation, and the reel index is output to the main CPU 601 via the reel position detection circuit 50. The output of the reel index clears the pulse counter and the symbol counter set in the main RAM 603 to “0”. Thus, the symbol position within the range of one rotation is specified for each reel 3L, 3C, 3R. The distance by which each symbol moves one symbol by rotation of the reel is called one frame. That is, one symbol movement of the symbol corresponds to the symbol counter being updated by "1".

  A symbol arrangement table (see FIG. 22A) is stored in the main ROM 602 in order to associate the rotational positions of the reels 3L, 3C, 3R with the symbols drawn on the outer peripheral surface of the reels. This symbol arrangement table has code numbers from "00" to "20" sequentially given for each fixed rotation pitch of each reel 3L, 3C, 3R based on the position where the above-mentioned reel index is output The symbol is associated with a symbol code identifying the type of symbol provided corresponding to each code number.

  In addition, when the start signal is output from the start switch 6S, the random number generator 606 and the sampling circuit 607 extract random number values. In pachislot 1, when the random number value is extracted, it is stored in the random number value storage area of the main RAM 603. Then, the internal winning combination is determined based on the random number value stored in the random number value storage area.

  After the reels 3L, 3C, 3R reach constant speed rotation, when a stop signal is output from the stop switches 7LS, 7CS, 7RS by the stop operation, based on the output stop signal and the determined internal winning combination, A control signal for stopping and controlling the reels 3L, 3C, 3R is output to the motor drive circuit 39. The motor drive circuit 39 drives and controls the stepping motors 50L, 50C, and 50R to stop the rotation of the reels 3L, 3C, and 3R.

  The main CPU 601 pulls in the symbols related to the establishment of the internal winning combination by the maximum number of sliding symbols, that is, four frames from the time the stop operation is performed, and stops the rotation of the reels 3L, 3C, 3R. Specifically, after the detection of the stop operation is performed by the stop switches 7LS, 7CS, 7RS, the main CPU 601 determines whether or not there is a symbol relating to the establishment of the internal winning combination within four frames, and determines four frames. If there is a symbol relating to the establishment of the internal winning combination within, the number of sliding symbols is determined so that the symbol is stopped and displayed on the effective line, and the corresponding reel is stopped. When the main CPU 601 determines a plurality of winning combinations as an internal winning combination, if there are a plurality of symbols relating to the establishment of the internal winning combination within 4 frames, the symbol relating to the internal winning combination of higher priority. Determine the number of sliding symbols so as to make the stop display on the effective line.

  In addition, basically, the first priority (highest priority) is a combination of symbols relating to replay, and the second highest priority is a combination of symbols relating to a minor combination. Next, the third priority is a combination of symbols related to the bonus. Further, when the stop operation is detected by the stop switches 7LS, 7CS, 7RS, the stop of the rotation of the symbol positions corresponding to the symbol counters of the corresponding reels 3L, 3C, 3R, ie, the reels 3L, 3C, 3R is started The symbol position is called the "stop start position", and the symbol position obtained by adding the number of sliding symbols (numerical range "0" to "4") determined to the stop start position, that is, rotation of the reels 3L, 3C, 3R The symbol position to be stopped is referred to as "planned stop position." The number of sliding symbols is the amount of rotation of the reels 3L, 3C, 3R from when the stop operation is detected by the stop switches 7LS, 7CS, 7RS until the rotation of the corresponding reels 3L, 3C, 3R is stopped. In, for example, the maximum number of sliding symbols is defined as "4".

  When the rotation of all the reels 3L, 3C, 3R is stopped, the main CPU 601 searches the display combination based on the combination of the symbols displayed on the effective line including the center line 8, that is, determines the establishment or failure of the combination. Do the processing. The search for the display combination is performed based on a symbol combination table (see FIG. 23) described later stored in the main ROM 602. In this symbol combination table, a combination of symbols relating to a display combination and a corresponding payout are set.

  When it is determined by the search for the display combination that the combination of symbols relating to winning is displayed, a control signal is output to the hopper drive circuit 341, and the payout of medals is performed by the driving of the hopper device 34. At this time, the medal detecting unit 34S counts the number of medals paid out from the hopper device 34, and when the counted value reaches the designated number, the payout completion signal circuit 342 outputs a signal indicating the completion of medal payout. Ru. As a result, a control signal is output to the hopper drive circuit 341, and the driving of the hopper device 34 is stopped.

  When it is determined that the combination of symbols relating to winning is displayed when the settlement switch 14S switches to the credit mode, the number of payouts corresponding to the combination of symbols relating to winning is the credit counter of the main RAM 603. Add to Further, information on the number of medals paid out is sent to the sub control circuit 70, and based on this, the number of medals paid out and the number of updated credits are displayed in the liquid crystal display area 10A of the liquid crystal display device Be done. Here, there are cases where medal payouts or credits, which are performed when a combination of symbols relating to winning, is displayed, may be simply referred to as "payout".

[Configuration of sub control circuit]
The sub control circuit 70 performs control for producing effects relating to a game using video, sound, light and the like. The sub control circuit 70 determines effect data based on various commands and the like transmitted from the main control circuit 60 and performs various effect processes. The sub control circuit 70 includes a sub CPU 701 as processing means, a sub ROM 702, a sub RAM 703 as storage means, a rendering processor 704, a drawing RAM 705 (including a frame buffer 706), a driver 707, a DSP 708, an A / D converter 709A, It has an amplifier 709 B, an audio RAM 709 C, and a sub-substrate communication LSI 710 as communication means.

  The sub CPU 701 performs display control of the liquid crystal display device 10, output control of the speakers 48 and 49, light emission control of the lamp 20, and the like based on a program stored in the sub ROM 702. Specifically, the sub CPU 701 receives various commands and the like from the main control circuit 60, and causes the sub RAM 703 to store various information included in the received command. From the main control circuit 60, any information is transmitted by a command, and the sub control circuit 70 can determine the state of the main control circuit 60 one by one based on the received command. The sub CPU 701 executes the program while referring to the gaming state information, the internal winning combination information and the like stored in the sub RAM 703, thereby effecting the liquid crystal display device 10, the speakers 48 and 49, the lamp 20 and the like Determine the content of the effect The sub CPU 701 controls the liquid crystal display device 10 via the rendering processor 704 based on the determined effect data, and controls the sound to be output from the speakers 48 and 49 and the light emission of the various lamps 20.

  Further, the sub CPU 701 executes a random number acquisition program stored in the sub ROM 702 to acquire a random value used when determining effect data and the like. However, when the random number generator and the sampling circuit are provided in the sub control circuit 70 as in the main control circuit 60, the process is unnecessary.

  The sub ROM 702 has a program storage area for storing a program executed by the sub CPU 701, and a data storage area for storing various tables and the like. The program storage area stores an operating system, a device driver, various processes related to communication with the main control circuit 60, an effect registration task for determining the content of effect, and the like. On the other hand, the data storage area is a table storage area for storing an effect / lottery table etc., a drawing control data storage area for storing animation data such as character object data, and a voice control data storage area for storing sound data such as BGM and sound effects. , And an LED control data storage area and the like for storing a lighting pattern and the like of light.

  As shown in FIG. 54, the sub RAM 703 communicates with the sub control game data area 703a, the sub control game data sum value area 703b, the work area 703c, the error information history storage area 703d, and the communication log collection area 703e. And an error storage area 703f.

  The sub control game data area 703a is configured to store data stored in the sub RAM 703 among game data relating to the progress of the game. The sub-control game data sum value area 703b is adapted to store a checksum for the game data stored in the sub-control game data area 703a. The work area 703 c is adapted to store work data in various processes.

  The sub control game data area 703a and the work area 703c are used as temporary work storage means when the sub CPU 701 executes each program. The sub control game data area 703a stores, for example, information transmitted from the main control circuit 60, effect data information, gaming state information, internal winning combination information, display combination information, various counters, various flags, etc. It is supposed to be.

  As shown in FIG. 55 (a), the error information history storage area 703d includes all error information detected by a main board communication process (see FIG. 40) described later (see FIG. 41) and the communication LSI reception data analysis process (see FIG. 41). Is supposed to remember. In the error information history storage area 703 d, an error information history is created by sequentially storing error codes. The detected error is stored as a COM error in the error information history storage area 703 d.

  Specifically, as shown in FIG. 55 (a), the error information history storage area 703d has an error code (ERROR CODE in the figure), an error occurrence date ("occurrence" in the figure), and an error release date (In the figure, "cancel") is regarded as one set of error information, and 128 sets of error information can be stored. As described above, in the error information history storage area 703 d, an error information history is created by sequentially storing error codes.

  The error code is 1-byte data, and the contents thereof are, as shown in FIG. 55 (b), a data corruption error ("Sam error" in the figure) and various errors related to communication ("major" in the figure). Board communication LSI physical layer error, "main board communication LSI size insufficient", "sub board communication LSI physical layer error", "sub board communication LSI size insufficient", "sub board communication LSI CRC error", "sub CPU CRC error" "," Insufficient sub CPU size ") and other errors. The error occurrence date and error release date consist of year of 2-byte data, month of 1-byte data, day of 1-byte data, 1-byte data, 1-byte data, and 1-byte data seconds There is.

  In the present embodiment, the following procedure is adopted as an example to display the error information history stored in the error information history storage area 703 d on the liquid crystal display device 10. For example, when the clerk rotates the door key 110 to the right, the lock mechanism of the front door 2b is released, and when the setting key is inserted into the setting key type switch and turned on, the liquid crystal display area 10A displays the menu shown in FIG. The screen is displayed. Then, when the clerk operates the operation keys on the screen to select the “error information history” item 100a, an error information history screen as shown in FIG. 45 is displayed on the liquid crystal display area 10A. In addition, when the clerk rotates the door key to the left, the error is reset, and the error information history screen as shown in FIG. 45 is displayed on the liquid crystal display area 10A also by holding the state for a predetermined time, for example 5 seconds or more. Is to be displayed.

  As shown in FIG. 47, in the communication log collection area 703e, a data group consisting of a data set of 256 commands and parameters and one corresponding buffer index is stored in an appropriate number, and they function as a ring buffer. It has become. As shown in FIG. 48, the communication error storage area 703f stores 1024 data groups each consisting of a data set of 256 commands and parameters and one corresponding buffer index. Further, in the communication error storage area 703f, one buffer selection index is provided which indicates which buffer index of the 1024 buffer indexes is selected. In the communication log collection area 703e shown in FIG. 47 and the communication error storage area 703f shown in FIG. 48, the command consists of one character data, and the parameter consists of two character data.

  The sub CPU 701 collects information on a reception log (hereinafter also referred to as a communication log) and temporarily stores the communication log in the communication log collection area 703 e. Furthermore, the sub CPU 701 stores up to 1024 communication logs (hereinafter referred to as communication error logs) related to communication errors in the communication error storage area 703 f when an error related to communication is detected.

  FIG. 46 shows an example of command types and parameters. The numerical values in the figure indicate the number of characters of data, and one-character data indicates the command type, and two-character data indicates the parameter for the immediately preceding command. In the present embodiment, the numerical range of the reception command is 01H to 10H as shown in FIG.

  As shown in FIG. 4, the sub CPU 701 is connected with a sub substrate communication LSI 710 for receiving data such as a command transmitted from the main control circuit 60. The sub substrate communication LSI 710 is mounted on the sub substrate 7A (see FIG. 6) as an element of the sub control circuit 70. The sub board communication LSI 710 is connected to the main board communication LSI 610 in the main control circuit 60 via the door relay board 53 by an optical fiber cable 100 (see FIG. 6) as an optical transmission medium. The sub CPU 701 receives various commands and the like transmitted from the main control circuit 60 through the sub substrate communication LSI 710. The sub CPU 701 of the present embodiment incorporates a UART 701 A, and the sub CPU 701 can transmit and receive data to and from the sub substrate communication LSI 710 through the UART 701 A (see FIG. 6). Details of such a sub-substrate communication LSI 710 and the UART 701A will be described later.

  The rendering processor 704 performs processing for displaying an image on the liquid crystal display device 10 based on an image display command or the like from the sub CPU 701. Data necessary for processing performed by the rendering processor 704 is expanded in the drawing RAM 705 at startup. The rendering processor 704 generates image data by sequentially superimposing image data developed in the drawing RAM 705 from the background image located behind to the image located forward, and supplies the image data to the liquid crystal display device 10 via the driver 707 Do. As a result, an image corresponding to the effect data determined by the sub CPU 701 is displayed on the liquid crystal display area 10A by the liquid crystal display device 10.

  The drawing RAM 705 has two frame buffers 706 of a write image data area and a display image data area. The write image data area stores the image data for which the rendering processor 704 has generated the display image, and the display image data area stores the image data to be displayed on the liquid crystal display device 10. The rendering processor 704 causes the liquid crystal display device 10 to sequentially display image data by alternately switching these frame buffers (that is, switching banks).

  The DSP 708 generates sound data based on sound data in digital format that the sub CPU 701 selects based on the effect data. The audio RAM 709C temporarily stores sound data and is used as an audio buffer. The A / D converter 709A converts the sound data from the DSP 708 into sound data of an analog format and outputs it to the amplifier 709B. The amplifier 709 B amplifies the analog format sound data from the A / D converter 709 A based on the volume adjusted by the volume adjustment knob (not shown) and outputs it to the speakers 48 and 49. As a result, a sound corresponding to the effect data determined by the sub CPU 701 is output from the speakers 48 and 49.

[Configuration of main substrate communication LSI and sub substrate communication LSI]
FIG. 5 shows the configurations of the main substrate communication LSI 610 and the sub substrate communication LSI 710. The main substrate communication LSI 610 and the sub substrate communication LSI 710 have the same components. The functions of the components common to the main substrate communication LSI 610 and the sub substrate communication LSI 710 will be mainly described below, and the main substrate different in the functions of the components between the main substrate communication LSI 610 and the sub substrate communication LSI 710 The communication LSI 610 and the sub-substrate communication LSI 710 will be appropriately distinguished and described.

  As shown in FIG. 5, the main board communication LSI 610 and the sub board communication LSI 710 are each configured by dedicated controllers 611 and 711, setting registers 612 and 712, cache memories 613 and 713, AES (Advanced Encryption Standard) circuits 614 and 714, and a first UART Universal Asynchronous Receiver Transmitter 615, 715, second UART 616, 716, first SPI (Serial Peripheral Interface) 617, 717, second SPI (not shown), first to fourth Manchester circuits 618 to 621, 718 to 721, and clock Reset control circuits 622 and 722 are included as components. These components are connected to one another via internal buses 623, 723. The first UARTs 615 and 715 and the first Manchester circuits 618 and 718 are connected to each other, and the second UARTs 616 and 716 and the second Manchester circuits 619 and 719 are also connected to each other. The main board communication LSI 610 and the sub board communication LSI 710 are configured by, for example, an ASIC.

  The dedicated controllers 611 and 711 perform general control regarding transmission and reception. For example, the dedicated controllers 611 and 711 function as, for example, hardware timers, and perform timeout processing at transmission and reception. The setting registers 612 and 712 are storage circuits having the same function as that of the non-volatile memory. The setting registers 612 and 712 store, for example, encryption keys used by the AES circuits 614 and 714 described later and setting data and the like related to communication specifications. Data can be written to the setting registers 612 and 712, for example, only once at the time of mounting on a substrate through a second SPI described later. The cache memories 613 and 713 are mainly used as buffers. For example, data relating to transmission and reception is temporarily stored in the cache memories 613 and 713. The clock / reset control circuits 622 and 722 generate a clock signal and a reset signal based on an input signal by an oscillator (OSC: Oscillator) or an external reset, and control transmission / reception timing and a reset operation.

  The AES circuits 614 and 714 encrypt and decrypt data according to the common key block encryption system. The AES circuits 614 and 714 include a functional block based on the AES encryption algorithm and a functional block based on the AES decryption algorithm that is the inverse function of the AES encryption algorithm as a hardware configuration. The AES encryption algorithm encrypts plaintext data using a common key, and the AES decryption algorithm restores data encrypted using the same common key to the original plaintext data.

  Here, the AES encryption algorithm is a representative encryption algorithm of the common key encryption method, and the key length can be selected from 128 bits, 192 bits, and 256 bits, and the block length is, for example, an SPN of 128 bits. It is a block cipher of the Substitution Permutation Network Structure) structure. Most block ciphers are repetition ciphers that repeat the same round function in order to make the implementation cost efficient, and the SPN structure is a typical configuration method of repetition ciphers. Also, block encryption is a kind of common key encryption, and is a generic term for encryption that processes data of fixed length as a unit. Incidentally, a cipher that performs processing in units of bits or bytes is called stream cipher.

  FIG. 7 is a schematic view showing the configuration of the AES circuits 614 and 714. As shown in FIG. As shown in the figure, the AES circuits 614 and 714 are configured by functional blocks that repeatedly execute a matrix operation of a predetermined number of rounds in steps. The steps repeatedly executed by the AES circuits 614 and 714 include byte substeps 614A and 714A, row shift steps 614B and 714B, column mixing steps 614C and 714C, and round key addition steps 614D and 714D as final steps. The number of times these steps are repeatedly executed (the number of rounds) depends on the key length, and the key length is 128 bits, the number of rounds is 11, the key length is 192 bits, the number of rounds is 13, and the key length is 256 bits and the number of rounds is 15, It has become. However, the column mixing steps 614C and 714C are not performed in the final round in any case.

  In byte sub-steps 614A and 714A, first, fixed-length input data is divided into, for example, 16 bytes of 4 rows and 4 columns, and each byte is replaced by an S box. The S-box is a hardware implementation of the basic functions of the common key block encryption system, and provides a mechanism for breaking the correlation (linearity) between plaintext and ciphertext. The S-box is excellent in resistance to differential cryptanalysis and also in preventing approximation by linear cryptanalysis.

  Next, in row shift steps 614B and 714B, each row of the row and column bytes is shifted in the row direction based on a predetermined algorithm. Such row shifting steps 614B, 714B provide a mechanism to prevent different bytes of each row from interacting with corresponding bytes in other rows.

  Next, in column mixing steps 614C and 714C, the bytes of each column that have undergone row shifting steps 614B and 714B are multiplied by a matrix based on Galois Field operations. Such column mixing steps 614C, 714C provide a mechanism for causing each byte in each column to affect the other byte.

  Next, in the round key addition steps 614D and 714D, the encryption key (public key) stored in the setting registers 612 and 712 is converted based on a predetermined algorithm, and the converted data is passed to the next round as a round key. Be Then, in the round key addition steps 614D and 714D, an exclusive OR operation is performed on the round keys, which are different for each round, and the respective bytes subjected to the column mixing steps 614C and 714C or the row shift steps 614B and 714B. The encryption key (public key) serving as the original key for the round key and the setting data and the like related to the AES circuits 614 and 714 are set, for example, only once at the time of board mounting, through setting registers 612 and 712 through the second SPI described later. Is written to

  According to such AES circuits 614 and 714, the above-described byte sub-steps 614A and 714A, row shift steps 614B and 714B, column mixing steps 614C and 714C, and round key addition steps 614D and 714D are repeatedly performed for a predetermined number of rounds. As a result, encrypted data is output. The encrypted data is converted into the original plaintext data by the AES decryption algorithm reverse to the AES encryption algorithm by the AES circuits 614 and 714. As a result, the data transmitted from the main substrate communication LSI 610 to the sub substrate communication LSI 710 is hardly decrypted as AES encrypted data. That is, in the communication section between the main board communication LSI 610 and the sub board communication LSI 710, communication encryption can be sufficiently prevented by AES encryption.

  The first UARTs 615 and 715 are circuits that convert a serial signal in the asynchronous mode to a parallel signal or convert in the reverse direction. The first UARTs 615 and 715 do not require a synchronous clock signal line for timing transmission and reception. The first UARTs 615 and 715 have a function of detecting an error (physical layer error) during transmission and reception. The first UARTs 615 and 715 notify the dedicated controllers 611 and 711 that an error has occurred.

  As shown in FIG. 51, types of errors include parity errors, overrun errors, framing errors, and the like. A parity error occurs when there is an error in the parity bit of the received data. An overrun error occurs when the next data is received while the dedicated controllers 611 and 711 do not fetch the data stored in the reception data buffer (cache memories 613 and 713). A framing error occurs when the stop bit should not be received and it is not the stop bit logic value.

  The second UARTs 616 and 716 have the same functions as the first UARTs 615 and 715, and the description of the common functions will be omitted. The first UART 601A and the UART 701A (see FIG. 6) built in each of the main CPU 601 and the sub CPU 701 also have the same functions as the first UARTs 615 and 715, and the description of the common functions is omitted.

  The first SPIs 617 and 717 are interface circuits for serial communication in a synchronous mode. The first SPIs 617 and 717 can transmit and receive data at high speed as compared with asynchronous serial communication. A plurality of devices can be connected to the first SPIs 617 and 717. In the present embodiment, the first SPIs 617 and 717 are preliminarily provided as extended functions of the main substrate communication LSI 610 and the sub substrate communication LSI 710. The second SPI (not shown) has the same function as the first SPI 617 and 717, and the description of the common function is omitted. The second SPI of this embodiment is provided with a dedicated terminal used when writing an encryption key, setting data, and the like to the setting registers 612 and 712. That is, the second SPI is used as a connection circuit dedicated to a writing device such as an encryption key and setting data.

  The first Manchester circuits 618 and 718 are circuits that perform modulation (encoding) and demodulation (decoding) of serial data in digital form according to Binary Phase-Shift Keying (BPSK). The first Manchester circuit 618, 718 modulates serial data consisting of any bit string not including a relatively long string of consecutive "0" s or "1" s, and also modulates from the modulated serial data Demodulate digital data consisting of The first Manchester circuit 618, 718 can embed the clock rate used for modulation in the serial data. Basically, in Manchester modulation, a binary state consisting of digital input values "1" and "0" is defined as a transition, and digital output values for the rising edge and falling edge of a signal input as serial data Modulated serial data is generated by assigning logic levels "0" and "1" or vice versa. At the time of demodulation, demodulation is performed in the reverse procedure of modulation, and rising edges and falling edges or the reverse of the signals to be output for the logic level "0" and "1" as digital input values Demodulated serial data is generated by forming a signal waveform of

  In the present embodiment, as specifically shown in FIGS. 5 and 6, the first Manchester circuits 618 and 718 can be paired with the first UARTs 615 and 715, and can transmit and receive data through the first UARTs 615 and 715. Is configured as. The second Manchester circuits 619 and 719, the third Manchester circuits 620 and 720, and the fourth Manchester circuits 621 and 721 have the same functions as the first Manchester circuits 618 and 718. I omit it. Further, in the present embodiment, the first Manchester circuits 618 and 718 are provided in the wired optical communication system (the main substrate communication LSI 610 and the sub substrate communication LSI 710), but the Manchester circuits are generally suitable for wireless transmission. Therefore, a wireless communication system including a Manchester circuit may be constructed.

  The second Manchester circuits 619, 719 are configured to pair with the second UARTs 616, 716 and to transmit and receive data through the second UARTs 616, 716. The third Manchester circuits 620 and 720 are provided for transmission and reception via the first SPIs 617 and 717, and are configured to transmit and receive data through the first SPIs 617 and 717. The fourth Manchester circuits 621 and 721 are provided as independent units without being combined with other circuits, and are configured such that the fourth Manchester circuits 621 and 721 can transmit and receive data alone.

  In the present embodiment, as specifically shown in FIG. 8, the second Manchester circuit 619 of the main substrate communication LSI 610 mainly functions as a Manchester modulation circuit, while the second Manchester circuit 719 of the sub substrate communication LSI 710 It mainly functions as a Manchester demodulation circuit. The second Manchester circuit 619 as a modulation circuit takes exclusive OR of the clock signal 800c for synchronization and the input serial data 800d, and as a result, generates and outputs modulated serial data 800d '. The second Manchester circuit 719 as a demodulation circuit receives the clock signal 800c for synchronization and the modulated serial data 800d 'as an input to take their exclusive OR, and as a result, demodulates the original serial data 800d. Generate and output. Such second Manchester circuits 619 and 719 can transmit and receive digital data relatively inexpensively.

  As schematically shown in FIG. 6, in the main substrate 6A of this embodiment, data (packet data) including a command from the main CPU 601 is supplied from the first UART 601A to the first UART 615, and the physicals described later by the first UART 615 After layer error detection and the like are performed, they are encrypted by the AES circuit 614 and are further supplied to the second Manchester circuit 619 through the second UART 616, and are modulated by the second Manchester circuit 619. The data modulated in this manner is converted into serial data including a command, and is output as an optical signal by the light emitting element 630 of the optical communication device disposed at the light emitting side connection end of the optical fiber cable 100. Through the sub-substrate 7A.

  In the sub board 7A, serial data including a command transmitted from the main board 6A is transmitted as an optical signal while passing through the door relay board 53 from the light emitting side connection end of the optical fiber cable 100 to the light receiving side connection end. The light receiving element 730 of the optical communication device disposed at the light receiving side connection end of the cable 100 receives the light receiving element 730 and is supplied to the second Manchester circuit 719, and after being demodulated by the second Manchester circuit 719, the AES circuit through the second UART 716 The sub CPU 701 can receive a command from the main CPU 601 by being supplied to the 714 and being decoded by the AES circuit 714 and then being supplied to the UART 701A through the first UART 715.

  Further, as shown in FIG. 9, the data transmitted from the main CPU 601 to the main substrate communication LSI 610 is packet data consisting of plaintext of 8 bytes, and the communication speed (baud rate) at that time is 19200 bps. This conforms to the communication specification between the main CPU 601 and the main board communication LSI 610, specifically, the communication specification designed according to the processing specification of the main CPU 601. The data transmitted from the main substrate communication LSI 610 to the sub substrate communication LSI 710 is Manchester modulated and encrypted 16 bytes of data, and the communication speed at that time is 115,200 bps. This conforms to the communication specification between the main substrate communication LSI 610 and the sub substrate communication LSI 710, specifically, the communication specification designed according to the processing specifications of the main substrate communication LSI 610 and the sub substrate communication LSI 710, and the sub CPU 701. It is. The data transmitted from the sub substrate communication LSI 710 to the sub CPU 701 is 16 bytes of plaintext data that has been Manchester-demodulated and AES-decoded, and the communication speed at that time is set to 115,200 bps. This conforms to the communication specification between the sub substrate communication LSI 710 and the sub CPU 701, specifically, the communication specification designed according to the specifications of the sub CPU 701.

[Contents of communication data]
49 to 53 are explanatory diagrams showing the contents of communication data related to transmission and reception. Hereinafter, communication data will be described with reference to FIGS.

  As shown in FIG. 49, the external communication data transmitted from the main substrate communication LSI 610 to the sub substrate communication LSI 710 consists of data frames of 16 Byte fixed length divided by the byte unit number (byte number) of D0 to D15. .

  Packet reception numbers are assigned to the byte numbers D0 and D1 of the external communication data. The packet reception number can be assigned a value of 0 to 65535, and is incremented (incremented) by one packet reception or timeout during reception. The reception of one packet means that data transmitted from the main CPU 601 in a packet unit (transmission unit) of 1 byte, for example, is received. The timeout during reception means that when one packet of data is, for example, 1 byte, a timeout occurs in a situation where data less than 1 byte is received.

  The packet data transmitted from the main CPU 601 is assigned to the byte numbers D2 to D9 of the external communication data. The packet data corresponds to a command transmitted from the main CPU 601 to the sub CPU 701. Packet data is determined to have a fixed length of 8 bytes based on communication specifications.

  Communication information related to the main board communication LSI 610 is assigned to the byte numbers D10 and D11 of the external communication data. Specifically, the data size of packet data transmitted from the main board communication LSI 610 is assigned to the byte number D10. A main board communication LSI physical layer error or the like is assigned to the byte number D11 as a reception status (see FIG. 51). The main board communication LSI physical layer error is a communication error on hardware that can be detected by the first UART 615 when the main board communication LSI 610 receives data supplied from the main CPU 601, for example, an overrun error shown in FIG. , Framing error, parity error, etc. Since the data size of packet data is a fixed length of 8 bytes based on the communication specification, a fixed value indicating 8 bytes is always assigned to the byte number D10.

  Communication information related to the sub board communication LSI 710 is assigned to the byte numbers D12 and D13 of the external communication data. The byte numbers D12 and D13 are assigned a reception status or the like generated when data is received by the sub board communication LSI 710 as described later. Therefore, the byte numbers D12 and D13 in the external communication data are simply reserved as reserved areas, and a fixed value '0000H' is assigned as dummy data, for example.

  CRC data by cyclic redundancy check is assigned to the byte numbers D14 and D15 of the external communication data. The cyclic redundancy check is performed on byte numbers D0 to D13.

  As shown in FIG. 50, the internal communication data transmitted from the sub substrate communication LSI 710 to the sub CPU 701 basically includes a frame having the same structure as the communication data shown in FIG.

  The contents of the above-described external communication data byte numbers D0 to D11 are copied and assigned to the byte numbers D0 to D11 of the internal communication data as they are.

  Communication information related to the sub board communication LSI 710 is assigned to the byte numbers D12 and D13 of the internal communication data. Specifically, a sub board communication LSI physical layer error or the like is assigned to the byte number D12 as a reception status. The secondary substrate communication LSI physical layer error is a communication error on hardware that can be detected by the second UART 716 when the secondary substrate communication LSI 710 receives data supplied from the main substrate communication LSI 610, for example, as shown in FIG. There are run errors, framing errors, parity errors, etc. A logical error, which will be detected when the sub board communication LSI 710 receives data supplied from the main board communication LSI 610, is assigned to the byte number D13 as a packet type.

  Similar to the external communication data, CRC data by cyclic redundancy check is assigned to the byte numbers D14 and D15 of the internal communication data. The cyclic redundancy check is performed on byte numbers D0 to D13.

  As shown in FIG. 51, the reception status has a format divided by bit numbers B0 to B7 (bit numbers).

  An error count is assigned to bit numbers B0 to B3 of the reception status. The error count indicates the total number of errors related to parity, framing, and overrun, which is the total number of reception errors, and values of 0 to 15 can be assigned.

  The presence or absence of an overrun error is assigned to the bit number B4 of the reception status as a physical layer error. For example, if there is an overrun error, "1" is assigned to the bit number B4, and if there is no overrun error, "0" is assigned to the bit number B4.

  The presence or absence of a framing error is assigned to the bit number B5 of the reception status as a physical layer error. For example, if there is a framing error, "1" is assigned to the bit number B5, and if there is no framing error, "0" is assigned to the bit number B5.

  The presence or absence of a parity error is assigned to the bit number B6 of the reception status as a physical layer error. For example, when there is a parity error, "1" is assigned to the bit number B6, and when there is no parity error, "0" is assigned to the bit number B6.

  Time-out is assigned to the bit number B7 of the reception status. For example, when a timeout occurs, "1" is assigned to the bit number B7, and when no timeout occurs, "0" is assigned to the bit number B7.

  As shown in FIG. 52, the packet type has a format divided into bit unit numbers (bit numbers) of B0 to B7.

  The type of logic error is assigned to the packet type bit numbers B0 to B4. For example, if there is no logic error, a bit string of "00000" is assigned to bit numbers B0 to B4, and if there is a CRC error, a bit string of "00001" is assigned, the main board communication LSI 610 received from the main CPU 601 If the data size is insufficient, a bit string of "00010" is assigned, and if the secondary board communication LSI 710 receives data from the main board communication LSI 610, the bit size of "00100" is assigned, and other logic errors There is a bit string associated with that logic error. The CRC error assigned to the packet type bit numbers B0 to B4 may occur when the sub board communication LSI 710 receives data from the main board communication LSI 610. The size shortage at the time when the main board communication LSI 610 receives data from the main CPU 601 occurs when a timeout occurs as a reception status of the main board communication LSI 610. The shortage of size when the sub board communication LSI 710 receives data from the main board communication LSI 610 occurs when a timeout occurs as a reception status of the sub board communication LSI 710.

  A communication classification is assigned to the packet type bit numbers B5 to B7. For example, if the bit numbers B5 to B7 correspond to communication (main control communication) with the main control circuit 60, a bit string of "000" is assigned, and if they correspond to other communication, they are associated with the communication. Assigned bit string.

  As shown in FIG. 53 (a), the main CPU 601 transmits packet data P0 to P7 having a fixed length of 8 bytes including a command as serial data to the main board communication LSI 610. For example, packet data P0 indicates data related to a command, packet data P1 to P6 indicate parameter data corresponding to the command, and packet data P7 indicates, for example, BCC (Block Check Character) as a checksum of packet data P0 to P6. ). The main board communication LSI 610 checks the physical layer error and the like for the received packet data P0 to P7, and performs AES encryption on the data to which the reception result and the like are added.

  As shown in FIG. 53 (b), when the main board communication LSI 610 receives packet data P0 to P7 from the main CPU 601, it sets external communication data D0 to D15 having a fixed length of 16 bytes including the packet data P0 to P7 as serial data. Transmit to the sub substrate communication LSI 710. At this time, external communication data D0 to D15 encrypted by the AES circuit 614 and modulated by the second Manchester circuit 619 as a modulation circuit are carried on the serial data transmitted from the main substrate communication LSI 610. The packet data P0 to P7 are allocated to, for example, D2 to D9 among the external communication data D0 to D15 (see FIG. 49).

  As shown in FIG. 53 (c), when the sub substrate communication LSI 710 receives the external communication data D0 to D15 as serial data from the main sub substrate communication LSI 610, the variable length internal communication according to the external communication data D0 to D15 Data STX (Start of TeXt), DLE (Data Link Escape), and D0 to D15 are transmitted to the sub CPU 701 as serial data. At this time, the serial data transmitted from the sub substrate communication LSI 710 is loaded with internal communication data D0 to D15 decoded by the AES circuit 714 and demodulated by the second Manchester circuit 719 as a demodulation circuit. The packet data P0 to P7 from the main CPU 601 are arranged in, for example, D2 to D9 among the internal communication data D0 to D15 (see FIG. 50). D0 to D15 are transmitted as serial format binary data, while STX and DLE are transmitted as control characters as described later.

  For example, when there is nothing corresponding to control data (data corresponding to a received command, see FIG. 46) to be transmitted from the sub board communication LSI 710, only “STX” of the control character indicating the start of communication message The internal communication data STX, D0 to D15 with the prefix at the beginning are transmitted. At this time, as the data transmission size, the minimum number of transmission bytes is 17 bytes obtained by adding 1 byte of STX to 16 bytes of D0 to D15. On the other hand, when data transmitted from the sub substrate communication LSI 710 includes control data, “STX” is added to the head and a block including control data (byte number D12 as an example in FIG. 53 (c)) Internal communication data STX, DLE, D0 to D15 to which "DLE" of the control character indicating that is added before are transmitted. By this, assuming that the maximum transmission byte count includes the control data in all blocks D0 to D15 as the data transmission size, theoretically 16 bytes of D0 to D15 and the maximum 16 bytes of DLE corresponding to these And 1 byte of STX add up to 33 bytes. When detecting the control data in the data to be transmitted, the sub board communication LSI 710 escapes the block of the corresponding byte number, and adds the DLE before the block. The escape process is performed by calculating an exclusive OR of data of a corresponding block (byte number) and a predetermined value.

[Configuration of communication LSI for external output and external terminal board control LSI]
FIG. 10 schematically shows the connection form of the main board 6A and the external concentrated terminal board 9A, FIG. 11 shows the configuration of the external output communication LSI 610A and the external terminal board control LSI 910, and FIG. The flow of data and signals up to the hall computer 1000 is shown. As shown in FIG. 11, the external output communication LSI 610A and the external terminal board control LSI 910 have the same components as the main board communication LSI 610 and the sub board communication LSI 710 described above, dedicated controllers 611A and 911, setting register 612A, and 912, cache memory 613A, 913, AES circuit 614A, 914, first UART 615A, 915, second UART 616A, 916, first SPI 617A, 917, second SPI (not shown), first to fourth Manchester circuits 618A to 621A, 918 to 921 And clock and reset control circuits 622 A and 922. Since these components perform the same functions as those of the main substrate communication LSI 610 and the sub substrate communication LSI 710, the description thereof is omitted. The external output communication LSI 610A and the external terminal board control LSI 910 have GPIO (General Purpose Input / Output) interfaces 624A and 924 as components different from the main substrate communication LSI 610 and the sub substrate communication LSI 710 described above. These components are connected to one another via internal buses 623A and 923. Such an external output communication LSI 610A and the external terminal board control LSI 910 are also configured by, for example, an ASIC.

  In the main substrate 6A of this embodiment, a command is transmitted from the second UART 601B of the main CPU 601 to the external output communication LSI 610A, and after detection of a physical layer error or the like is performed by the external output communication LSI 610A, the AES circuit is performed. It is configured to be encrypted at 614A and to be supplied to the second Manchester circuit 619A through the second UART 616A and to be modulated by the second Manchester circuit 619A. The command thus modulated is used as data for external output according to the serial communication system, and is output as an optical signal by the light emitting element 630A of the optical communication device disposed at the light emitting side connection end of the optical fiber cable 100. The signal is transmitted to the external concentrated terminal plate 9A through the optical fiber cable 100.

  In the external concentrated terminal plate 9A, the external output data transmitted from the main substrate 6A is transmitted as an optical signal while passing through the external relay substrate 8A from the light emitting side connection end of the optical fiber cable 100 to the light receiving side connection end, It is supplied to the second Manchester circuit 919 of the external terminal board control LSI 910 by being received by the light receiving element 930 of the optical communication device disposed at the light receiving side connection end of the optical fiber cable 100 and demodulated by the second Manchester circuit 919 Thereafter, after being supplied to the AES circuit 914 through the second UART 916 and further decoded by the AES circuit 914, a plurality of on / off states according to the general purpose input / output system are generated based on the received external output data. These multiple signals from each output port of GPIO interface 924 It is supplied to the external output connector 950 via the over 940. A hall computer 1000 is connected to the external output connector 950, and the on / off states of a plurality of signals are transmitted to the hall computer 1000. In the hall computer 1000, various analysis processes are performed based on the on / off states of a plurality of signals from the external concentrated terminal plate 9A. As a signal of this embodiment, there are a medal in signal, a medal out signal, a security signal, and external signals 1 to 4.

  The main substrate 6A and the external concentrated terminal plate 9A are connected to each other via the optical fiber cable 100 in which the wiring is relayed by the external relay substrate 8A. Further, the main substrate 6A and the sub substrate 7A are also connected to each other via the optical fiber cable 100 in which the wiring is relayed by the door relay substrate 53. In the connection method using an optical fiber cable, it is not necessary to provide a relay substrate. Both ends of the optical fiber cable may be directly connected to both substrates to be connected, and these substrates may be directly connected to each other.

  Further, as shown in FIG. 12, the command transmitted from the main CPU 601 to the external output communication LSI 610A is plaintext data of 2 bytes, and the communication speed (baud rate) at that time is 19200 bps. This conforms to the communication specification between the main CPU 601 and the external output communication LSI 610A, specifically, the communication specification designed according to the processing specification of the main CPU 601. The external output data transmitted from the external output communication LSI 610A to the external terminal board control LSI 910 is Manchester-modulated and encrypted 1-byte data, and the communication speed at that time is 115,200 bps. This is the communication specification between the external output communication LSI 610A and the external terminal board control LSI 910, specifically, the communication specification designed according to the processing specifications of the external output communication LSI 610A, the external terminal board control LSI 910, and the hall computer 1000. In accordance with The parallel signal output from the external terminal board control LSI 910 to the hall computer 1000 is composed of a plurality of signals. The external output data to be transmitted from the external output communication LSI to the external terminal board control LSI may be data which has been subjected to Manchester modulation without being subjected to Manchester modulation. According to this, data can be efficiently transferred from the main substrate to the external concentrated terminal plate.

  More specifically, as shown in FIG. 66, the command is made up of 1 byte of command information (CMD) indicating the type of command and 1 byte of setting data (DATA) accompanying the parameter. It is a thing. In the present embodiment, for example, as command information in hexadecimal notation, a medal in command “90H” indicating medal in, a medal out command “A0H” indicating medal out, and various information related to gaming etc. are simply output to the outside. The external output command “B0H” indicating that, the external output chain command “B1H” indicating that the external output of the command relating to the medal out should be subsequently output after the external output of the command relating to the medal out end, An external output ON command "B2H" indicating that external output should be output, and an external output indicating that external output should be continued for a predetermined period of time after the external output of the command related to medal out is completed. The ON output command “B3H”, the various information concerned should be kept for a predetermined time and the external output should be turned off. An external output OFF command “B4H” indicating that the external output OFF chain indicates that the various types of information should be kept in the external output OFF state for a predetermined period of time after the external output of the command related to medal out ends. A command "B5H" and a security command "C0H" indicating that information concerning security is to be output to the outside are prepared.

  In addition, although information, such as a game state and a prize, is allocated to the command "B0H"-"B5H" which concerns on an external output, for example, it is not restricted to such information in particular, The various information required for every model is It can be determined appropriately. In addition to the information indicating the door open detection and the setting change start, the security command "C0H" includes, for example, a thumb error in the main RAM 603, insertion medal passage time, insertion medal passage check, insertion medal retrogression, auxiliary storage full, hopper Security information such as empty, hopper jam, illegal hit (unfair prize that the winning combination and the winning combination are different) is assigned.

  In the setting data of the medal in command "90H", 1 to 3 are set as numerical values indicating the number of inserted medals. In the setting data of the medal out command “A0H”, 1 to 15 are set as numerical values indicating the number of medals paid out. External signals 1 to 4 are set in the lower 4 bits of setting data of commands "B1H" to "B5H" relating to external output as information indicating the type. The upper 4 bits of the setting data of the external output command “B0H” and the external output chain command “B1H” are not used. The upper 4 bits of external output ON command "B2H", external output ON chain command "B3H", external output OFF command "B4H", and external output OFF chain command "B5H" are numerical values (time 0 to 7 are set as the value). In the upper 4 bits of the setting data of the security command "C0H", 0 to 7 can be arbitrarily set as a numerical value (time setting value) indicating time setting, and the least significant bit (Bit 0) of the lower 4 bits The presence / absence status (1/0) of security information is set. In the present embodiment, the actual time per time setting value “1” is predetermined to be, for example, about 500 ms. In the present embodiment, the most significant bit (Bit 7) of the command information (CMD) is always set to on (1), while the most significant bit (Bit 7) of the setting data (DATA) is always off (0). , And the external output communication LSI 610A is configured to execute the later-described reception processing (FIG. 76) in 1-byte units. As a result, the external output communication LSI 610A can perform data communication processing efficiently while distributing the command received from the main CPU 601 into command information (CMD) and setting data (DATA).

  The external output communication LSI 610A that has received the command generates a plurality of external output data from the received command, and transmits the plurality of external output data to the external terminal board control LSI 910 at appropriate timings. And reserve a plurality of software timer areas in the cache memory 613A. The working area includes an output state area for setting the output state of the external output data to be externally output at this time, an output editing area for editing the output state of the external output data, and an external output for the chain command A chain area for storing data, an external output ON area for storing data for external output related to an external output ON chain command, an external output OFF area for storing data for external output related to an external output OFF chain command , A recovery area after external output ON measurement to restore the output state of external output data after setting time of external output ON command (including chain), External output data of after setting time of external output OFF command (including chain) Return area after external output OFF measurement to restore output status A security measure after the return area for returning the output state of the data for external output after Interview utility command set time.

  As shown in FIG. 68, as software timers, software timer for medal in counting (1), software timer for medal out counting (2), software timer for external output ON command (3), external output OFF command There is a software timer for (4) and a software timer for security commands (5). In the cache memory 613A, a working area and an area of a software timer are secured, and a setting data storage area and a buffer area for temporarily saving received setting data are also secured. The software timer functions as a countdown timer, and software timers (6) to (8) are also provided as spares. The software timer area is a 1-byte area that indicates the operation status of the timer such as stop (0) / measurement (1) / reservation (2) / end (-1) for each timer address, and the timer actually A 2-byte counter area for holding the value of the counter is provided.

  As shown in FIG. 67, the working area consists of an area of 1 byte, and the status (1/0) of the command is assigned to each bit. Specifically, the states of the external signal 4 to the external signal 1 are set in Bit 0 to Bit 3 of the working area as the contents of the external output data. The external signals 4 to 1 become signal elements of parallel signals, and are output to the hall computer 1000 through the relays (2) to (5) 940 of the external concentrated terminal plate 9A and the external output connector 950. In Bit 4 of the working area, the state of the security signal is set as the content of the external output data. The security signal becomes one signal element of the parallel signal, and is output to the hall computer 1000 through the relay (1) 940 of the external concentrated terminal plate 9A and the external output connector 950. In Bit 5 of the working area, the state of the medal out signal is set as the content of the external output data. The medal out signal becomes one signal element of the parallel signal, and is output to the hall computer 1000 through the relay (6) 940 of the external concentrated terminal plate 9A and the external output connector 950. In Bit 6 of the working area, the state of the medal in signal is set as the content of the external output data. The medal-in signal becomes one signal element of the parallel signal, and is output to the hall computer 1000 through the relay (7) 940 of the external concentrated terminal plate 9A and the external output connector 950. Bit 7 in the working area is considered unused. The external output communication LSI 610A uses an external terminal according to a serial communication method using 1 byte of data in which the status of the above external signal 4 to external signal 1, the security signal, the medal out signal, and the medal in signal is set as a data set. Transmit to board control LSI 910.

  Specifically, as shown in FIG. 13, when the medal in command "90H" is transmitted from the main CPU 601 to the external output communication LSI 610A as a command, for example, setting data "03H" indicating the number of inserted medals 3 is The external output communication LSI 610A supports such commands (CMD: 90H, DATA: 03H) by executing medal in output conversion processing (see FIG. 78) and medal in output control processing (see FIG. 85) described later. The external output data is generated and transmitted to the external terminal board control LSI 910 while appropriately controlling the output state of the external output data. Thus, based on the received external output data, the external terminal board control LSI 910 sets the pulse period to 100 ms with a pulse width of 50 ms, for example, and relays the medal in signal in which the setting data (the number of inserted medals) is associated with the pulse number. 7) Output to the hall computer 1000 through 940.

  As shown in FIG. 14, when the medal out command "A0H" is transmitted from the main CPU 601 to the external output communication LSI 610A as a command, for example, setting data "0FH" indicating the medal payout number 15, the external output communication LSI 610A External output corresponding to such a command (CMD: A0H, DATA: 0FH) by executing medal out output conversion processing (see FIG. 79) and medal out output control processing (see FIG. 86) described later Data are generated and transmitted to the external terminal board control LSI 910 while appropriately controlling the output state of the external output data. As a result, the external terminal board control LSI 910 sets the pulse period to 100 ms with a pulse width of 50 ms, for example, based on the received external output data, and relays the token out signal in which the setting data (the number of medals paid out) is associated with the number of pulses. (6) Output to the hall computer 1000 through 940.

  As shown in FIG. 15, as a command, for example, the external signal 2 and the external signal 4 are turned on and the external signal 1 and the external signal 3 are turned off, together with setting data "05H". When “B0H” is transmitted from the main CPU 601 to the external output communication LSI 610A, the external output communication LSI 610A executes external output conversion processing (see FIG. 80) and output control processing (see FIG. 84) described later. Thus, external output data corresponding to such a command (CMD: B0H, DATA: 05H) is generated and transmitted to the external terminal board control LSI 910 while appropriately controlling the output state of the external output data. As a result, the external terminal board control LSI 910 is a relay (on which the output of the external signal 2 and the external signal 4 is on and the output of the external signal 1 and the external signal 3 is off) based on the received external output data. 4) Turn on the signal line leading to 940 and relay (2) 940, turn off the signal line leading to relay (5) 940 and relay (3) 940, and send external signals 1 to 4 to Hall computer 1000 And output.

  As shown in FIG. 16, as a command, for example, an external output chain command "B1H" is output from the main CPU 601 to the external output communication LSI 610A together with setting data "0AH" indicating that the external signal 1 and the external signal 3 are output on. When transmitted, the external output communication LSI 610A executes such external command (CMD: B1H, DATA) by executing an external output conversion process (see FIG. 80) and a setting output control process (see FIG. 87) described later. Data for external output corresponding to (: 0AH) is generated, and the output state of the external output data is transmitted to external terminal board control LSI 910 while appropriately adjusting the output state of the external output data corresponding to the medal out command. . Thereby, the external terminal board control LSI 910 ends the output of the medal out signal from the relay (6) 940 corresponding to the medal out command based on the received data for external output, and then the setting data (external signal 1 and external) The signal lines connected to the relay (5) 940 and the relay (3) 940 corresponding to the output of the signal 3 are turned on, and the external signal 1 and the external signal 3 are output to the hall computer 1000.

  As shown in FIG. 17, as a command, for example, the external output ON command "B2H" is together with setting data "25H" indicating that output is turned on after setting the external signal 2 and external signal 4 to the time setting value "2". When transmitted from the main CPU 601 to the external output communication LSI 610A, the external output communication LSI 610A performs external output ON conversion processing (see FIG. 81) and setting output control processing (see FIG. 87) described later. Data for external output corresponding to such a command (CMD: B2H, DATA: 25H) is generated, and transmitted to the external terminal board control LSI 910 while appropriately controlling the output state of the data for external output. As a result, the external terminal board control LSI 910 responds to the setting data (the external signal 2 and the external signal 4 are set to the time setting value “2” and the output is turned on) based on the received external output data (4) 940 and relay (2) The signal line leading to the relay 940 is turned on only for 1000 ms, and the external signal 2 and the external signal 4 are output to the hall computer 1000. The setting data in this case indicates external signals 1 to 4 to be turned on by setting one of the lower 4 bits corresponding to external signals 1 to 4 to on (1), The output state of the external signals 1 to 4 corresponding to off (0) among the lower 4 bits of the setting data is maintained as it is.

  As shown in FIG. 18, for example, external output ON chain command "B3H" together with setting data "1AH" indicating that output is turned on after setting external signal 1 and external signal 3 to time setting value "1" as a command. However, when the main CPU 601 transmits to the external output communication LSI 610A, the external output communication LSI 610A executes external output ON conversion processing (see FIG. 81) and setting output control processing (see FIG. 87) described later. Generates an external output data corresponding to such a command (CMD: B2H, DATA: 25H), and the output state of the external output data corresponds to the output state of the external output data corresponding to the medal out command. It transmits to the external terminal board control LSI 910 while adjusting. Thereby, the external terminal board control LSI 910 ends the output of the medal out signal from the relay (6) 940 corresponding to the medal out command based on the received data for external output, and then the setting data (external signal 1 and external) The signal line leading to the relay (5) 940 and the relay (3) 940 corresponding to the signal 3 after setting the time set value to “1” is turned on only for 500 ms, and the external signal 1 and the external signal 3 is output to the hall computer 1000. The setting data in this case also indicates external signals 1 to 4 to be turned on by setting any one of the lower 4 bits corresponding to external signals 1 to 4 to on (1), The output state of external signals 1 to 4 corresponding to off (0) among the lower 4 bits of setting data is maintained as it is.

  As shown in FIG. 19, as a command, for example, external output OFF command "B4H" together with setting data "23H" indicating that output is turned off after setting external signal 3 and external signal 4 to time set value "2" When transmitted from the main CPU 601 to the external output communication LSI 610A, the external output communication LSI 610A performs external output OFF conversion processing (see FIG. 82) and setting output control processing (see FIG. 87) described later. Data for external output corresponding to such a command (CMD: B4H, DATA: 23H) is generated, and is transmitted to the external terminal board control LSI 910 while appropriately controlling the output state of the data for external output. Thereby, the external terminal board control LSI 910 is a relay (3) corresponding to the setting data (the external signal 3 and the external signal 4 are set to the time setting value “2” and the output is turned off) based on the received external output data. 940 and relay (2) The signal line leading to the relay 940 is turned off only for 1000 ms, and the external signal 3 and the external signal 4 are output to the hall computer 1000. The setting data in this case indicates external signals 1 to 4 to be turned off by setting any one of lower 4 bits corresponding to external signals 1 to 4 to on (1), The output state of the external signals 1 to 4 corresponding to off (0) among the lower 4 bits of the setting data is maintained as it is.

  As shown in FIG. 20, for example, external output OFF chain command "B5H" together with setting data "1CH" indicating that output is turned off after setting external signal 1 and external signal 2 to time set value "1" as a command. However, when the main CPU 601 transmits to the external output communication LSI 610A, the external output communication LSI 610A executes external output OFF conversion processing (see FIG. 82) and setting output control processing (see FIG. 87) described later. Generates an external output data corresponding to such a command (CMD: B5H, DATA: 1CH), and the output state of the external output data corresponds to the output state of the external output data corresponding to the medal out command. It transmits to the external terminal board control LSI 910 while adjusting. As a result, after the external terminal board control LSI 910 ends the transmission of the medal out signal from the relay (6) 940 corresponding to the medal out command based on the received external output data, the setting data (external signal 1 and external The signal line leading to relay (5) 940 and relay (4) 940 corresponding to signal 2 as time set value “1” is turned off for only 500 ms, and external signal 1 and external signal 2 is output to the hall computer 1000. The setting data in this case also indicates external signals 1 to 4 to be turned off by setting one of the lower 4 bits corresponding to external signals 1 to 4 to on (1), The output state of the external signals 1 to 4 corresponding to off (0) among the lower 4 bits of the setting data is maintained as it is.

  As shown in FIG. 21, as a command, for example, the security command "C0H" is output from the main CPU 601 together with setting data "21H" indicating that the security signal S1 is set to "2" and the output is turned on. When transmitted to the communication LSI 610A, the external output communication LSI 610A executes such a command (CMD :) by executing security output conversion processing (see FIG. 83) and output control processing (see FIG. 84) described later. Data for external output corresponding to C0H, DATA: 21H) is generated, and is transmitted to the external terminal board control LSI 910 while appropriately controlling the output state of the data for external output. Thereby, external terminal board control LSI 910 is a signal that leads to relay (1) 940 corresponding to setting data (setting security signal S1 to time setting value “2” and then output on) based on the received data for external output. The line is turned on only for 1000 ms, and such a security signal S1 is output to the hall computer 1000.

  As shown in FIG. 21, when the security command "C0H" is transmitted from the main CPU 601 to the external output communication LSI 610A as a command, for example, the setting data "01H" indicating that the security signal S2 is simply turned on. The external output communication LSI 610A responds to such commands (CMD: C0H, DATA: 01H) by executing security output conversion processing (see FIG. 83) and output control processing (see FIG. 84) described later. The external output data is generated, and is transmitted to the external terminal board control LSI 910 while appropriately controlling the output state of the external output data. As a result, the external terminal board control LSI 910 turns on the signal line leading to the relay (1) 940 corresponding to the setting data (the output of the security signal S1 is simply turned on) based on the received external output data. The security signal S2 is output to the hall computer 1000.

  As described above, the main CPU 601 implements a main control processing unit that performs various main control processing related to the game. The sub CPU 701 implements a sub control processing unit that performs various sub control processes on a plurality of peripheral devices. The main board communication LSI 610 implements main control output means for outputting main control information (command) from the main control processing means to the sub control processing means. The external output communication LSI 610A and the external concentrated terminal board 9A realize external output means for outputting external output information (command) from the main control processing means to an external device (hall computer 1000) outside the gaming machine. . The external output communication LSI 610A implements a first communication unit that receives external output information from the main control processing unit, encrypts the external output information, and outputs the encrypted information by serial communication. The external terminal board control LSI 910 implements a second communication unit that inputs the encrypted external output information from the first communication unit and decodes and outputs the external output information. The relay 940 of the external terminal board control LSI 910 realizes output means for inputting external output information from the second communication means and outputting the external output information to an external device (hall computer 1000) in a predetermined output method. ing. The AES circuit 614A of the external output communication LSI 610A implements an encryption unit that encrypts output state instruction information or continuous output information (data for external output) using the common key encryption method. The second Manchester circuit 619A of the external output communication LSI 610A implements a modulation unit that modulates the output state indication information or the continuous output information encrypted by the encryption unit according to the binary phase shift keying system. The second Manchester circuit 919 of the external terminal board control LSI 910 implements a demodulation unit that demodulates the output state indication information or the continuous output information modulated by the modulation unit by the binary phase shift keying modulation method. The AES circuit 914 of the external terminal board control LSI 910 implements a decryption unit that decrypts the output state indication information or continuous output information demodulated by the demodulation unit according to the common key encryption system.

  Further, the main control processing means (main CPU 601) can output the external output information (command) including time information indicating a predetermined output time, and can also output without including the time information. When the first communication means (communication LSI for external output 610A) includes time information in the external output information inputted from the main control processing means, a clock means (time controller for measuring a predetermined output time based on the time information) An output state for instructing an external output ON state or an external output OFF state according to a predetermined output method based on external output information input from the main control processing means 611A and software timers (3) to (5)) Output state indication information generation means (working area of dedicated controller 611A and cache memory 613A) for generating indication information (data for external output), and when the external output information includes time information, the predetermined output time is made by the clock means While clocking, while outputting the output state instruction information to the second communication means, the external output information does not include time information. If, an output status indication information without the time constraints second information output means for outputting to the communication means (the dedicated controller 611A, first 2UART616A) and, as a possible operating functions. The second communication means (external terminal board control LSI 910) is an information input means (dedicated controller 911, second UART 916) for inputting the output state indication information outputted from the information output means, and an output state indication inputted by the information input means A signal output unit (dedicated controller 911, GPIO interface 924) for converting information into a signal according to a predetermined output method and outputting the signal to an external device through an output unit is provided as an operable function.

  Further, the main control processing means (main CPU 601) can output the external output information (external output OFF command, external output OFF chain command) including OFF time information indicating a predetermined time of the external output OFF state. The first communication means (external output communication LSI 610A) measures a predetermined time based on the OFF time information included in the external output information input from the main control processing means (dedicated controller 611A and software timer (4) And, based on external output information input from the main control processing means, generating first output state instruction information (data for external output) instructing an external output OFF state corresponding to a predetermined output method, An output state for generating second output state indication information (data for external output) instructing to maintain or restore the state of the external output before the first output state indication information is generated corresponding to a predetermined output method The first output during the clocking of a predetermined time by the instruction information generating means (the working area of the dedicated controller 611A and the cache memory 613A) and the clocking means Information output means (dedicated controller 611A) for outputting the second output state instruction information to the second communication means, while outputting the state instruction information to the second communication means, and when the clocking means finishes measuring the predetermined time. , And the second UART 616A) as an operable function. The second communication means (external terminal board control LSI 910) is an information input means (dedicated controller 911, second UART 916) for inputting the first output state indication information and the second output state indication information outputted from the information output means. And the first output state instruction information input by the information input means is output to the external device through the output means as a first signal according to a predetermined output method, and then the second output state inputted by the information input means Signal output means (dedicated controller 911, GPIO interface 924) for outputting instruction information as a second signal in accordance with a predetermined output method to an external device through the output means is provided as an operable function.

  Further, the main control processing means (main CPU 601) can output the first external output information (medal out command) as the external output information, and the first external output information should be output following the first external output information. It is possible to output 2 external output information (external output chain command, external output ON chain command, external output OFF chain command). The first communication unit (external output communication LSI 610A) is configured to perform first continuous output information (external output data) according to a predetermined output method based on the first external output information input from the main control processing unit. Continuous output information generation means for generating second continuous output information (data for external output) according to a predetermined output method based on the second external output information input from the main control processing means (Working area of dedicated controller 611A and cache memory 613A) and information for outputting the first continuous output information to the second communication means and thereafter outputting the second continuous output information to the second communication means And an output unit (dedicated controller 611A, second UART 616A) as an operable function. The second communication means (external terminal board control LSI 910) inputs the first continuous output information output from the information output means, and then inputs the second continuous output information (dedicated controller 911; The second UART 916) and the first continuous output information inputted by the information input means are outputted to the external device through the output means as a first signal in accordance with a predetermined output method, and then the second signal inputted by the information input means Signal output means (dedicated controller 911, GPIO interface 924) for outputting continuous output information as a second signal according to a predetermined output method to an external device through the output means is provided as an operable function.

  Further, the main control processing means (main CPU 601) can output the first external output information (medal out command) as the external output information, and outputs the external output after a predetermined time has elapsed following the first external output information. It is possible to output second external output information (external output OFF chain command) including delay time information indicating that it should be performed. The first communication means (external output communication LSI 610A) is a clock means (dedicated controller 611A and software timer) for measuring a predetermined time based on the delay time information included in the second external output information input from the main control processing means (4) and, based on the first external output information input from the main control processing means, generate first continuous output information (data for external output) according to a predetermined output method, and then the main control Based on the second external output information input from the processing means, while generating second continuous output information (data for external output) instructing the external output standby state corresponding to the predetermined output method, the predetermined output Means for generating continuous output information (dedicated controller 611A and cache memory) for generating third continuous output information (data for external output) instructing an external output valid state corresponding to the system. 613 A) and the first continuous output information to the second communication means, and then, while the predetermined time is being clocked by the clock means, the second continuous output information to the second communication means Information output means (dedicated controller 611A, second UART 616A) for outputting the third continuous output information to the second communication means when the clocking means finishes counting the predetermined time, as an operable function Have. The second communication means (external terminal board control LSI 910) receives the first continuous output information output from the information output means, and then receives the second continuous output information, and then the third continuous An information input unit (dedicated controller 911, second UART 916) for inputting output information, and a first continuous output information inputted by the information input unit are output to an external device through the output unit as a first signal according to a predetermined output method And then, the second continuous output information input by the information input unit is output to the external device through the output unit as a second signal according to a predetermined output method, and then, the third input input by the information input unit Signal output means for outputting continuous output information as a third signal according to a predetermined output method to an external device through the output means (dedicated controller 911, GP O interface 924), having as a possible operating functions.

  Also, the main control processing means (main CPU 601) can output the external output information (external output ON command, external output ON chain command, security command) including ON time information indicating a predetermined time of the external output ON state. is there. The first communication means (external output communication LSI 610A) counts a predetermined time based on the ON time information included in the external output information input from the main control processing means (dedicated controller 611A and software timer (3) , (5) and the first output state instruction information (data for external output) for instructing the external output ON state corresponding to the predetermined output method based on the external output information input from the main control processing means Second output state indication information (data for external output) instructing the state maintenance or state return of the external output before the first output state indication information is generated corresponding to the predetermined output method while being generated The first state is generated during a predetermined time by the output state instruction information generating means (the working area of the dedicated controller 611A and the cache memory 613A) to be generated and the clocking means Information output means for outputting the second output state instruction information to the second communication means when the output state instruction information is outputted to the second communication means, while the clocking means finishes measuring the predetermined time 611A, and the second UART 616A) as an operable function. The second communication means (external terminal board control LSI 910) is an information input means (dedicated controller 911, second UART 916) for inputting the first output state indication information and the second output state indication information outputted from the information output means. And the first output state instruction information input by the information input means is output to the external device through the output means as a first signal according to a predetermined output method, and then the second output state inputted by the information input means Signal output means (dedicated controller 911, GPIO interface 924) for outputting instruction information as a second signal in accordance with a predetermined output method to an external device through the output means is provided as an operable function.

  Next, configurations of various tables and the like stored in the main ROM 602 will be described with reference to FIGS. The main ROM 602 stores a symbol arrangement table, a symbol code, a symbol combination table, a bonus operation table, an internal lottery table, and an internal winning combination determination table.

[Symbol arrangement table and symbol code]
As shown in FIG. 22 (a), the symbol arrangement table is data for specifying the position of each symbol in the rotational direction of each reel and the type of symbol arranged at each position (hereinafter referred to as symbol code (FIG. 22 (b )) Are defined.

  The symbol arrangement table sets the positions of symbols existing in the middle stage (on the center line 8) in the display windows 4L, 4C, 4R when the reel index is detected as "0", and proceeds in the direction of reel rotation in each order. “0” to “20” are assigned to the positions of the symbols, respectively. Therefore, by referring to the symbol arrangement table while managing how many symbols have been rotated since the reel index was detected, the positions of the symbols mainly present in the middle of the display windows 4L, 4C, 4R and It is possible to always manage the type of the symbol.

[Symbol combination table]
In the present embodiment, when the combination of symbols displayed by the respective reels 3L, 3C, 3R along the center line 8 serving as a winning judgment line matches the combination of symbols specified by the symbol combination table, The main CPU 601 determines that the game is a winning, and provides the player with benefits such as payout of medals, activation of replay, and activation of a bonus game.

  As shown in FIG. 23, the symbol combination table defines a combination of symbols, a display combination, and the number of payouts predetermined according to the type of benefit. The display combination is data for identifying a combination of symbols displayed along the winning determination line (center line 8).

  The display combination is represented as 1-byte data in which a unique symbol combination is assigned to each bit. For example, when the symbol "bell" of each of the reels 3L, 3C, 3R is displayed along the winning determination line (center line 8), "bell (00000010)" is determined as the display combination.

  In addition, when one or more numerical values are determined as the number of payouts, the medals are paid out. In the present embodiment, medals are paid out when cherry, bell or watermelon is determined as the display role. Further, the number of dispensed sheets is defined in accordance with the number of inserted sheets, and basically, the number of dispensed sheets is determined when the number of inserted sheets is small.

  Further, when the replay is determined as the display combination, the replay is activated. When BB is determined as the display combination, the bonus is activated. When the combination of symbols displayed along the winning determination line (center line 8) does not match any of the combinations of symbols defined by the symbol combination table, it becomes a so-called "loss".

[Bonus activated table]
As shown in FIG. 24, the bonus operation table defines data to be stored in various storage areas provided in the main RAM 603 when the bonus operation is performed.

  The in-operation flag is data for identifying the type of bonus on which the operation is performed. In the present embodiment, as the types of bonus, BB (character continuous actuation device related to a first kind special character) and RB (first kind special character) are provided. The operation of RB is performed continuously while the operation of BB is performed.

  The operation of the BB ends when payout of medals reaching the specified number is performed. The operation of the RB ends either when the game reaches a specified number, when there is a prize reaching the specified number, or when the operation of the BB ends. The bonus end number counter, the possible game number counter and the possible game number counter are data for managing whether or not the specified number or the specified number of times serving as a bonus end trigger is reached.

  More specifically, the numerical value defined by the bonus operation time table is stored in each of the counters, and the subtraction is performed through the activation of the bonus. As a result, the operation of the corresponding bonus ends on condition that the value of each counter is updated to “0”.

[Internal lottery table]
As shown in FIGS. 25 and 26, as the internal lottery table, an internal lottery table for a general gaming state and an internal lottery table for RB operation are provided. The internal lottery table defines the data pointer and the lottery value according to the winning number. The data pointer is data acquired as a result of lottery performed with reference to the internal lottery table, and is data for specifying an internal winning combination defined by an internal winning combination determination table described later. The data pointer is provided with a small part / replay data pointer and a bonus data pointer.

  In this embodiment, random numbers extracted from a predetermined numerical range “0 to 65535” are sequentially subtracted by a lottery value corresponding to each winning number, and the result of the subtraction becomes negative (so-called An internal lottery is performed by making a determination of "whether or not a digit" has occurred. Thus, the larger the numerical value defined as the lottery value, the higher the probability that the data to which it is assigned (that is, the data pointer) is determined. In addition, the winning probability of each winning number can be represented by “lottery value corresponding to each winning number / number of all random number values that may be extracted (65536)”.

  Further, in the present embodiment, a plurality of types of internal lottery tables (the internal lottery table for the general gaming state of FIG. 25 and the internal for RB operation of FIG. 26 are used depending on the situation such as whether or not the bonus is activated). By properly using the lottery table), the type of the internal winning combination determined and the winning probability are changed, and as a result, the expectation held by the player is made uneven.

[Internal winning combination decision table]
As shown in FIGS. 27 and 28, as the internal winning combination determining table, a small winning combination / replay internal winning combination determining table and a bonus internal winning combination determining table are provided. The internal winning combination determination table defines an internal winning combination according to the data pointer. When the data pointer is determined, the internal winning combination is uniquely acquired.

  The internal winning combination is data for identifying a combination of symbols of the respective reels 3L, 3C, 3R permitted to be displayed along the prize determination line (center line 8). The internal winning combination, like the display combination, is represented as 1-byte data in which a unique symbol combination is assigned to each bit. When the data pointer is "0", the content of the internal winning combination is "loss", which indicates that display of any combination of symbols specified by the above-mentioned symbol combination table is not permitted.

  As shown in FIG. 27, the internal winning combination determination table for a small winning combination / replay defines an internal winning combination pertaining to the payout of medals or an internal winning combination pertaining to the operation of replay. As shown in FIG. 28, the bonus internal winning combination determination table defines an internal winning combination relating to the operation of the bonus.

  Next, configurations of various storage areas provided in the main RAM 603 will be described with reference to FIGS. The main RAM 603 is provided with an internal winning combination storing area, a display combination storing area, a carryover combination storing area, and an in-operation flag storage area.

[Internal winning combination storage area]
As shown in FIG. 29, the internal winning combination storing area stores an internal winning combination represented by the aforementioned 1 byte data. When the bit is "1", the display of the corresponding symbol combination is permitted. When all bits are "0", the content is lost. The main RAM 603 is provided with a display combination storage area in which the above-mentioned display combination is stored. The configuration of the display combination storage area is the same as the configuration of the internal winning combination storage area. When the bit "1" stands, the corresponding symbol combination is displayed along the winning determination line (center line 8).

[Hold over part storage area]
As shown in FIG. 30, the carryover combination storage area stores therein an internal winning combination associated with the activation of the bonus as a result of the above-described lottery. The internal winning combination (hereinafter referred to as a carryover combination) related to the operation of the bonus stored in the carryover combination storage area is not cleared until its corresponding symbol combination is displayed on the prize determination line (centerline 8). Is configured to be held by the Then, while the carryover combination is stored in the carryover combination storage area, it is stored in the internal winning combination storage area regardless of the result of the above-mentioned lottery.

[Operation flag storage area]
As shown in FIG. 31, the in-operation flag storage area stores an in-operation flag consisting of 1 byte. The active flag is assigned a unique bonus for each bit. When the bit is set to "1", the corresponding bonus is activated. In the present embodiment, a state where all bits are “0” is defined as a general gaming state.

  Next, processing executed by the main CPU 601 of the main control circuit 60 will be described with reference to FIGS. 32-38 and 69-72. The processes shown in FIGS. 69 to 72 are particularly processes relating to external output of commands, and these processes will be described later.

[Main flowchart by control of main CPU]
FIG. 32 shows a main flowchart under the control of the main CPU 601. As shown in FIG. 32, when the pachi slot 1 is powered on, the main CPU 601 first performs initialization processing (S1).

  Next, the main CPU 601 clears the designated storage area in the main RAM 603 (S2). For example, data stored in a storage area such as an internal winning combination storing area, a display combination storing area, etc. which needs to be erased for each game is cleared.

  Next, the main CPU 601 performs medal acceptance / start check processing described with reference to FIG. 33 (S3). In this process, the input of the medal sensor and the start switch is checked.

  Next, the main CPU 601 extracts random number values and stores them in the random number value storage area provided in the main RAM 603 (S4).

  Next, the main CPU 601 performs internal lottery processing described with reference to FIG. 34 (S5). In this process, the internal winning combination is determined by lottery based on random number values.

  Next, the main CPU 601 transmits a start command to the sub control circuit 70 (S6). The start command is configured to include a parameter specifying an internal winning combination and the like. The start command is supplied from the first UART 601A in the main CPU 601 to the sub CPU 701 through the main substrate communication LSI 610 and the sub substrate communication LSI 710.

  Next, the main CPU 601 requests the start of rotation of all the reels 3L, 3C, 3R (S7). When the start of rotation of all the reels 3L, 3C, 3R is requested, the driving of the stepping motors 50L, 50C, 50R is controlled by the interrupt process (see FIG. 38) executed in a fixed cycle (1.1173 msec). The rotation of each reel 3L, 3C, 3R is started.

  Next, the main CPU 601 performs an external output medal in command registration process described later with reference to FIG. 69 (S8). In this process, a command related to the medal in command to be output to the outside is set.

  Next, the main CPU 601 performs reel stop control processing described with reference to FIG. 35 (S9). In this process, the input of the stop switches 7LS, 7CS, 7RS is checked, and the rotation of the corresponding reels 3L, 3C, 3R is stopped based on the timing when the stop buttons 17L, 17C, 17R are pressed and the internal winning combination. Be done.

  Next, the main CPU 601 searches for a combination of symbols displayed along the winning determination line (center line 8), and determines the number of payouts and the like based on the result (S10). If the combination of symbols displayed along the winning determination line (center line 8) matches the combination of symbols defined by the symbol combination table as a result of the search, the corresponding display combination and the number of payouts are determined.

  Next, the main CPU 601 transmits a display command to the sub control circuit 70 (S11). The display command is configured to include parameters for specifying a display combination, the number of payouts and the like. The display command is supplied from the first UART 601 A in the main CPU 601 to the sub CPU 701 through the main substrate communication LSI 610 and the sub substrate communication LSI 710.

  Next, the main CPU 601 performs an external output medal out command registration process described later with reference to FIG. 70 (S12). In this process, a command related to the medal out command to be output to the outside is set.

  Next, the main CPU 601 performs medal payout processing (S13). The driving of the hopper device 34 and the update of the number of credits are performed based on the determined number of payouts.

  Next, the main CPU 601 updates the bonus end number counter based on the payout number (S14). A value determined as the number of payouts is subtracted from the bonus end number counter.

  Next, the main CPU 601 determines whether or not the bonus in-operation flag is on (S15). When the main CPU 601 determines that the flag under bonus operation is on, the main CPU 601 performs a bonus end check process described with reference to FIG. 37 (S16). In the bonus end check process, it is checked whether or not to end the bonus operation with reference to various counters for managing the bonus end trigger.

  After S16 or when determining that the flag under bonus operation is not on in S15, the main CPU 601 performs a bonus operation check process described with reference to FIG. 36 (S17). In the bonus operation check process, it is checked whether or not to start the bonus operation. When this process ends, the main CPU 601 shifts to S2.

[Medal acceptance and start check processing]
FIG. 33 shows medal acceptance / start check processing by the main CPU 601. As shown in FIG. 33, the main CPU 601 determines whether the automatic insertion counter is 0 or not (S31). When the main CPU 601 determines that the automatic insertion counter is 0, the main CPU 601 permits medal passage (S32). Thereby, the solenoid of the selector 51 is driven, and the passage of the medal in the selector is prompted.

  When the main CPU 601 determines that the automatic insertion counter is not 0, the main CPU 601 copies the automatic insertion counter to the insertion number counter (S33). Next, the main CPU 601 clears the automatic closing counter (S34). S33 and S34 are processes for performing re-game.

  After S32 or S34, the main CPU 601 sets 3 as the maximum value of the insertion number counter (S35). Next, the main CPU 601 determines whether or not the bonus in-operation flag is on (S36). When the main CPU 601 determines that the flag under bonus operation is on, the main CPU 601 changes the maximum value of the insertion number counter (S37). For example, the maximum value is changed to 2.

  After S37, or when determining that the bonus in-operation flag is not on in S36 after S37, the main CPU 601 determines whether or not passage of the medal has been detected (S38). When the main CPU 601 determines that the passage of the medal has been detected, the main CPU 601 determines whether the inserted number counter has reached the maximum value (S39). When the main CPU 601 determines that the insertion number counter has not reached the maximum value, the main CPU 601 adds 1 to the insertion number counter (S40).

  Next, the main CPU 601 stores 5 in the valid line counter (S41). Next, the main CPU 601 transmits a medal insertion command to the sub control circuit 70 (S42). The medal insertion command is configured to include parameters for specifying the number of inserted cards and the like. The medal insertion command is supplied from the first UART 601A in the main CPU 601 to the sub CPU 701 through the main board communication LSI 610 and the sub board communication LSI 710.

  When the main CPU 601 determines that the insertion number counter is the maximum value in S39, the main CPU 601 adds 1 to the credit counter (S43). After S43, after S42, or when determining that passage of medals has not been detected in S38 after S43, the main CPU 601 checks the bet switch 13S (S44). As a result, the numerical value corresponding to the bet button 12 is added to the insertion number counter while being subtracted from the credit counter.

  Next, the main CPU 601 determines whether the insertion number counter has reached the maximum value (S45). If the main CPU 601 determines that the insertion number counter has not reached the maximum value, it proceeds to S38, while if it determines that the insertion number counter has reached the maximum value, whether the start switch 6S is on or not It discriminates (S46).

  When the main CPU 601 determines that the start switch 6S is not turned on, it proceeds to S38, and when it determines that the start switch 6S is turned on, it prohibits medal passage (S47). The solenoid of the selector 51 is not driven, and discharge of the medal is prompted. When this process ends, the main CPU 601 ends the medal acceptance / start check process.

[Internal lottery process]
FIG. 34 shows an internal lottery process by the main CPU 601. As shown in FIG. 34, the main CPU 601 determines the internal lottery table and the number of times of lottery (S61). Thus, the in-operation flag storage area is referred to, and the internal lottery table and the number of times of lottery are determined in accordance with the presence or absence of the bonus operation or the like. The lottery number indicates the number of times the subtraction of the lottery value and the determination as to whether or not the digit has occurred for each winning number defined by the internal lottery table.

  Next, the main CPU 601 acquires the random number value stored in the random number value storage area, and sets it as a determination random number value (S62). Next, the main CPU 601 sets 1 as an initial value of the winning number (S63).

  Next, the main CPU 601 refers to the internal lottery table, and acquires a lottery value corresponding to the winning number (S64). Next, the main CPU 601 subtracts the lottery value from the determination random number value (S65). Next, the main CPU 601 determines whether or not digitization has been performed (S66). When the main CPU 601 determines that the digit is not performed, the main CPU 601 subtracts one from the number of lotteries and adds one to the winning number (S67).

  Next, the main CPU 601 determines whether the number of lotteries is 0 (S68). When the main CPU 601 determines that the number of lotteries is not 0, it shifts to S64, while when it is determined that the number of lotteries is 0, it sets 0 as the data pointer for small winning combination and replay and as the data pointer for bonus 0 is set (S69).

  When the main CPU 601 determines in S66 that the digit has been set, the main CPU 601 acquires a small winning combination / replay data pointer and a bonus data pointer according to the current winning number (S70). After S70 or S69, the main CPU 601 refers to the small winning combination / replay internal winning combination determination table, and acquires an internal winning combination based on the small winning combination / replay data pointer (S71).

  Next, the main CPU 601 stores the acquired internal winning combination in the internal winning combination storage area (S72). Next, the main CPU 601 determines whether the data stored in the carryover combination storage area is 0 (S73). When the main CPU 601 determines that the data stored in the carryover combination storage area is 0, the main CPU 601 refers to the bonus internal winning combination determination table and acquires an internal winning combination based on the bonus data pointer (S74) ). Next, the main CPU 601 stores the acquired internal winning combination in the carryover combination storage area (S75).

  After S75, or when it is determined that the data stored in the carryover combination storage area is not 0 after S75, the main CPU 601 ORs the carryover combination storage area and the internal winning combination storage area, and the result is Are stored in the internal winning combination storing area (S76). As a result, the internal winning combination associated with the activation of the bonus is carried over. When this process ends, the main CPU 601 ends the internal lottery process.

[Reel stop control processing]
FIG. 35 shows a reel stop control process by the main CPU 601. As shown in FIG. 35, the main CPU 601 determines whether or not the valid stop buttons 17L, 17C, 17R have been pressed (S101). When the main CPU 601 determines that the valid stop buttons 17L, 17C, and 17R are not pressed, the main CPU 601 stands by until this button is pressed.

  When the main CPU 601 determines that the valid stop button 17L, 17C, 17R is pressed, the main CPU 601 invalidates the operation of the corresponding stop button 17L, 17C, 17R (S102). The valid and invalid states of the respective stop buttons 17L, 17C, 17R are managed in a predetermined storage area provided in the main RAM 603.

  Next, the main CPU 601 sets 5 as the number of checks (S103). In this embodiment, since the maximum number of sliding symbols is “4”, the positions of the symbols in the middle of the corresponding display windows 4L, 4C, 4R when the stop buttons 17L, 17C, 17R are pressed are included. , From there to the position of the symbol four points ahead will be the target of the check. That is, any one of five numerical values “0”, “1”, “2”, “3” and “4” is determined as the number of sliding symbols.

  Next, based on the internal winning combination, the main CPU 601 positions the symbols in the middle of the display windows 4L, 4C, 4R corresponding to when the stop buttons 17L, 17C, 17R are pressed (hereinafter, stop start positions) Among the positions of each symbol within the range of the number of checks including, the position of the symbol with the highest priority is searched (S104). In this process, the position of the symbol at which the position of the symbol capable of displaying the combination of symbols permitted to be displayed by the internal winning combination along the prize determination line (center line 8) is the highest priority position It is determined as

  Next, the main CPU 601 determines the number of sliding symbols based on the search result (S105). The number of symbols from the stop start position to the position of the highest priority symbol is determined as the number of sliding symbols. Next, the main CPU 601 shifts to waiting for a planned stop position (S106). When the process shifts to waiting for a planned stop position, the driving of the stepping motors 50L, 50C, 50R is controlled by interrupt processing described later, and the position of the highest priority symbol reaches the middle row of the corresponding display windows 4L, 4C, 4R. The rotation of the corresponding reels 3L, 3C, 3R is stopped.

  Next, the main CPU 601 transmits a reel stop command to the sub control circuit 70 (S107). The reel stop command is configured to include parameters that specify the type and the like of the stopped reel. The reel stop command is supplied from the first UART 601A in the main CPU 601 to the sub CPU 701 through the main board communication LSI 610 and the sub board communication LSI 710.

  Next, the main CPU 601 determines whether there is a stop button 17L, 17C or 17R for which the operation is valid (S108). That is, it is determined whether or not there are reels 3L, 3C, 3R still rotating. When the main CPU 601 determines that there is a stop button 17L, 17C, 17R that is valid, the process proceeds to S101, while when it determines that there is no stop button 17L, 17C, 17R that is valid, the reel stop control process Finish.

[Bonus operation check process]
FIG. 36 shows a bonus operation check process by the main CPU 601. As shown in FIG. 36, the main CPU 601 determines whether the display combination is BB or not (S121). When the main CPU 601 determines that the display combination is BB, the main CPU 601 refers to the bonus operation table and performs BB operation processing (S122). In this process, the flag under BB operation is turned on, and a predetermined value is set in the bonus end number counter.

  Next, the main CPU 601 clears the carryover combination storage area (S123). Next, the main CPU 601 transmits a bonus start command to the sub control circuit (S124). The bonus start command is supplied from the first UART 601A in the main CPU 601 to the sub CPU 701 through the main substrate communication LSI 610 and the sub substrate communication LSI 710. When this process ends, the main CPU 601 ends the bonus operation check process.

  When the main CPU 601 determines that the display combination is not BB in S121, the main CPU 601 determines whether the display combination is a replay (S125). When the main CPU 601 determines that the display combination is replay, the main CPU 601 copies the value of the insertion number counter to the automatic insertion counter (S126).

  When the main CPU 601 determines that the display combination is not replaying in S125, the main CPU 601 determines whether the flag under BB operation is on (S127). When the main CPU 601 determines that the flag under BB operation is not on, it ends the bonus operation check process, while when determining that the flag under BB operation is on, the flag under RB operation is on or not. It is determined (S128).

  When the main CPU 601 determines that the flag under RB operation is on, it ends the bonus operation check process, while when determining that the flag under RB operation is not on, it refers to the bonus operation table and performs RB operation. The hour process is performed (S129). In this process, the RB in-operation flag is turned on, and predetermined values are set in the possible number-of-money counter and the possible number-of-games counter. When this process ends, the main CPU 601 ends the bonus operation check process.

[Bonus end check processing]
FIG. 37 shows a bonus end check process by the main CPU 601. As shown in FIG. 37, the main CPU 601 determines whether the bonus end number counter is 0 or not (S141). When the main CPU 601 determines that the bonus end number counter is 0, the main CPU 601 performs a BB end processing (S142). In this process, the flag under BB operation and the flag under RB operation are turned off, and various counters for managing an end trigger of the bonus are cleared. Next, the main CPU 601 transmits a bonus end command to the sub control circuit 70 (S143). The bonus end command is supplied from the first UART 601A in the main CPU 601 to the sub CPU 701 through the main substrate communication LSI 610 and the sub substrate communication LSI 710. When this process ends, the main CPU 601 ends the bonus end check process.

  When the main CPU 601 determines that the bonus end number counter is not 0 in S141, the main CPU 601 updates the possible number-of-winnings counter or the possible number-of-games counter (S144). As a result, the possible game number counter is decremented by one, and when there is a winning, the possible symbol counter is decremented by one. Next, the main CPU 601 determines whether the number-of-winning possible counter or the number-of-playable counter is 0 (S145).

  When the main CPU 601 determines that the possible wins counter or the possible games counter is not 0, it ends the bonus end check processing, while it determines that the possible wins counter or the possible games counter is 0, The process at the end of RB is performed (S146). In this process, the RB in-operation flag is turned off, and the possible prize number counter and the possible game number counter are cleared. When this process ends, the main CPU 601 ends the bonus end check process.

[Interrupt process under control of main CPU (1.1172 msec)]
FIG. 38 shows an interrupt process by the main CPU 601. The interrupt process by the main CPU 601 is a process that is executed every predetermined cycle (1.1173 milliseconds in the present embodiment). As shown in FIG. 38, the main CPU 601 interrupts the program being executed before calling this interrupt processing, and saves the address indicating the interrupted position and the values of various registers in a predetermined area of the main RAM 603. (S161). This is because, when the interrupt processing under control of the main CPU 601 is completed, the address indicating the interrupted position of the saved program and the values of various registers are restored, and the program is continuously executed from the point of interruption. It is.

  Next, the main CPU 601 performs input port check processing (S162). Specifically, the main CPU 601 checks the signals from the switches such as the maximum BET switch 13S.

  Next, the main CPU 601 performs reel control processing (S163). Specifically, when there is a request for starting rotation of the reels in the main flowchart (see FIG. 32), the main CPU 601 starts the rotation of the reels 3L, 3C, 3R and performs control for rotating at a constant speed. . Further, when the planned stop position is determined by the number of sliding symbols determined in the reel stop control process (see FIG. 35), the main CPU 601 indicates the value of the symbol counter of the corresponding reel indicates the planned stop position. Control is performed to stop the reel when the value becomes the same value. For example, when the value indicating the planned stop position is “4”, the main CPU 601 performs control for stopping the corresponding reel when the value of the symbol counter becomes “4”.

  Next, the main CPU 601 performs lamp 7 segment drive processing (S164). Next, the main CPU 601 divides the value of the external output counter by 4 and determines whether there is no remainder as a result of the division (S165). The external output counter is for executing command external output processing described later, which is performed every four times of the interrupt processing (4.4692 milliseconds elapsed), for example, 1 byte in a predetermined area of the main RAM 603. Set as a counter.

  When the main CPU 601 determines that there is no remainder as a result of dividing the value of the external output counter by 4 in S165, it performs command external output processing described later with reference to FIG. 71 (S166). In this process, a command to be externally output is output to the external output communication LSI 610A. After that, the main CPU 601 shifts to S167. On the other hand, when the main CPU 601 determines that the remainder is generated as a result of dividing the value of the external output counter by 4 in S165, the process proceeds to S167 without performing command external output processing.

  Next, the main CPU 601 adds 1 to the value of the external output counter to update it (S167). Thereafter, the main CPU 601 restores the register with reference to the value saved in the main RAM 603 in the process of S161 (S168). When this process ends, the main CPU 601 ends the interrupt process, and continues executing the interrupted program due to the occurrence of the interrupt process.

  Next, with reference to the flowcharts shown in FIGS. 39 to 43, the operation regarding the game of the sub control circuit 70 will be described.

[Receive interrupt processing]
FIG. 39 shows a reception interrupt process by the sub CPU 701. As shown in FIG. 39, the sub CPU 701 acquires reception data supplied from the main control circuit 60 (main CPU 601) via the main board communication LSI 610 and the sub board communication LSI 710 (S181). At this time, the received data is received as serial data through the UART 701A in the sub CPU 701.

  Next, the sub CPU 701 determines whether or not the received data is "STX" (S182). When the sub CPU 701 determines that the received data is “STX”, the sub CPU 701 clears the received data buffer and the reception counter, sets the reception error flag to OFF (S183), and shifts to S196 described later. The reception data buffer, the reception counter, and the reception error flag are secured in predetermined areas of the sub RAM 703. The receive data buffer is used to temporarily store receive data. The reception counter is used, for example, to count reception data by 1 byte in block units indicated by a byte number. The reception error flag is used to identify the presence or absence of an error at the time of data reception.

  If it is determined in S182 that the received data is not "STX", the sub CPU 701 determines whether the received data is "DLE" (S184). When the sub CPU 701 determines that the received data is "DLE", the sub CPU 701 sets the escape processing flag on (S185), and proceeds to S196 described later. The escape processing flag is secured in a predetermined area of the sub RAM 703. The escape process flag is used to identify whether or not the escape process needs to be performed.

  If it is determined in S184 that the received data is not "DLE", the sub CPU 701 determines whether the escape processing flag is on (S186). If the sub CPU 701 determines that the escape processing flag is on, the sub CPU 701 executes the escape processing on the received data (S 187), and then sets the escape processing flag to off (S 188).

  After S188, or when it is determined that the escape process flag is not on in S186, the sub CPU 701 stores the received data and the reception status in a predetermined area of the sub RAM 703 (S189). Next, the sub CPU 701 updates the reception counter by adding 1 (S190).

  Next, the sub CPU 701 sets a timeout timer (S191). The timeout timer is for determining the presence or absence of a communication error at the time of data reception based on the reception waiting time. In this embodiment, the timeout timer of the sub CPU 701 is a waiting time for receiving data of, for example, about 8 bytes longer than the reception waiting time measured by the timeout timer of the main board communication LSI 610 or the sub board communication LSI 710 described later. It is configured to be clocked.

  Next, the sub CPU 701 determines whether the reception counter has counted 16 bytes (S 192). If the sub CPU 701 determines that the reception counter has counted 16 bytes, the sub CPU 701 clears the timeout timer (S193), and then proceeds to S194. If the sub CPU 701 determines that the reception counter does not count 16 bytes, it proceeds to S 196 described later.

  Next, the sub CPU 701 extracts data corresponding to the command part and reception status data from the reception data, and registers these data in the reception data registration queue (S194). The reception data registration queue is secured in a predetermined area of the sub RAM 703.

  Next, the sub CPU 701 performs communication LSI received data analysis processing described with reference to FIG. 41 (S195). According to this communication LSI reception data analysis processing, a communication error between the main CPU 601 and the main substrate communication LSI 610, a communication error between the main substrate communication LSI 610 and the sub substrate communication LSI 710, and the sub substrate communication LSI 710 and the sub CPU 701 Various communication errors on the communication path, such as communication errors between them, are identified. This communication LSI reception data analysis process will be described later.

  Next, the sub CPU 701 determines whether or not there is a physical layer error in the received data supplied from the sub substrate communication LSI 710 (S 196). The process of determining the presence or absence of the physical layer error is mainly performed by the UART 701A built in the sub CPU 701. The physical layer error that can be detected at this time is not the reception status in the reception data (the reception status concerning the main board communication LSI 610 and the sub board communication LSI 710 indicated by the byte numbers D11 and D12), but the sub CPU 701 received the data. Such as an overrun error detected by the UART 701A, a framing error, and a parity error.

  If it is determined in S196 that there is a physical layer error in the received data, the sub CPU 701 sets the reception error flag on (S197). Thereafter, the sub CPU 701 ends the reception interrupt process. If it is determined that there is no physical layer error in the received data, the sub CPU 701 ends the reception interrupt process.

Main board communication process
FIG. 40 shows main board communication processing by the sub CPU 701. As shown in FIG. 40, the sub CPU 701 determines whether a time out has occurred (S201). The timeout occurs when 16 bytes of data are not received even after the waiting time counted by the timeout timer.

  If it is determined in S201 that a timeout has occurred, the sub CPU 701 registers 'COM3 ERR2' in the error information history storage area 703d of the sub RAM 703 as the corresponding error information (S202). On the other hand, if it is determined that a timeout has not occurred, the sub CPU 701 shifts to S204 described later. Next, the sub CPU 701 clears the reception data buffer and the reception counter (S203), and proceeds to S201.

  Next, the sub CPU 701 acquires reception data (command and reception status) from the reception data registration queue (S204). Then, the sub CPU 701 determines whether or not there is received data in the received data registration queue (S205).

  If it is determined in S205 that there is received data in the received data registration queue, the sub CPU 701 proceeds to the next S206. On the other hand, if it is determined that there is no reception data in the reception data registration queue, the sub CPU 701 proceeds to S201.

  Next, the sub CPU 701 determines whether or not the received data has an error based on the content of the acquired reception status (S206). If it is determined that there is no error in the received data, the sub CPU 701 checks the range of the command (S207). That is, the sub CPU 701 confirms the type of command. On the other hand, if it is determined that the received data has an error, the sub CPU 701 proceeds to S201.

  Next, the sub CPU 701 determines whether the command is within a predetermined range (predetermined command type) (S208). If it is determined that the command is within the predetermined range, the sub CPU 701 performs BCC check processing on the received data (S209). The BCC check process is performed based on whether the BCC recalculated as the checksum of the packet data P0 to P6 matches the BCC stored in the packet data P7. On the other hand, when determining that the command is not within the predetermined range, the sub CPU 701 shifts to S201.

  Next, the sub CPU 701 determines whether the BCC is normal or not as a result of the BCC check process (S210). If it is determined that the BCC is normal, the sub CPU 701 extracts the type of command from the command (S211). As the command type, for example, there are a start command, a display command, a medal insertion command, a reel stop command, a bonus start command, a bonus end command, and the like, as well as a non-operation command indicating a non-operation state. On the other hand, when determining that the BCC is not normal, the sub CPU 701 shifts to S201.

  Next, the sub CPU 701 determines whether the command type is a no-operation command (S212). If it is determined that the other command is not a non-operation command, the sub CPU 701 determines whether a command different from the previous command has been received as the current command (S213). On the other hand, if it is determined that the command is a no-operation command, the sub CPU 701 proceeds to S201.

  If it is determined in S213 that a command different from the previous command has been received as the current command, the sub CPU 701 registers the command received this time in the message queue (S214), and proceeds to S201. On the other hand, if it is determined that the same command as the previous command has been received as the current command, the sub CPU 701 proceeds directly to S201.

[Communication LSI received data analysis process]
FIG. 41 shows communication LSI received data analysis processing by the sub CPU 701. As shown in FIG. 41, the sub CPU 701 calculates a CRC by cyclic redundancy check on data of byte numbers D0 to D13 among the received data (S221).

  Next, the sub CPU 701 determines whether the calculated CRC is abnormal (S222). If it is determined that the CRC is abnormal, the sub CPU 701 registers 'COM3 ERR1' in the error information history storage area 703d of the sub RAM 703 as corresponding error information, and sets the reception error flag on (S223). On the other hand, if it is determined that the CRC is normal, the sub CPU 701 proceeds to the next step S224.

  Next, the sub CPU 701 acquires the main board communication LSI reception status from the reception data (S224). Then, the sub CPU 701 determines whether or not there is a physical layer error in the main board communication LSI reception status (S225).

  If it is determined in S225 that there is a physical layer error in the main board communication LSI reception status, the sub CPU 701 registers 'COM1 ERR1' as the corresponding error information in the error information history storage area 703d of the sub RAM 703 and the reception error. The flag is set on (S226). On the other hand, if it is determined that there is no physical layer error, the sub CPU 701 proceeds to the next S227.

  Next, the sub CPU 701 acquires the sub board communication LSI reception status from the reception data (S227). Then, the sub CPU 701 determines whether or not there is a physical layer error in the sub board communication LSI reception status (S228).

  If it is determined in S228 that there is a physical layer error in the sub board communication LSI reception status, the sub CPU 701 registers 'COM2 ERR1' as the corresponding error information in the error information history storage area 703d of the sub RAM 703 and the reception error. The flag is set on (S229). On the other hand, if it is determined that there is no physical layer error, the sub CPU 701 proceeds to the next S230.

  Next, the sub CPU 701 acquires the sub board communication LSI packet type from the received data (S230). Then, the sub CPU 701 determines whether there is insufficient main board communication LSI size as a logic error type from the acquired sub board communication LSI packet type (S231).

  If it is determined in S231 that there is a shortage of main board communication LSI size as a logic error type in the sub board communication LSI packet type, the sub CPU 701 sets 'COM1 ERR2' as the corresponding error information and stores the error information history storage area 703d of the sub RAM 703. And sets the reception error flag on (S232). On the other hand, when determining that the main substrate communication LSI size is not insufficient, the sub CPU 701 proceeds to the next step S233.

  Next, the sub CPU 701 determines whether there is a shortage in the sub board communication LSI size as the logic error type from the acquired sub board communication LSI packet type (S233).

  If it is determined in S233 that there is a shortage of sub board communication LSI size as a logic error type in the sub board communication LSI packet type, the sub CPU 701 sets 'COM2 ERR2' as the corresponding error information and stores the error information history storage area 703d of the sub RAM 703. And sets the reception error flag on (S234). On the other hand, if it is determined that there is no shortage of sub board communication LSI size, the sub CPU 701 proceeds to the next step S235.

  Next, the sub CPU 701 determines whether there is a CRC error of the sub board communication LSI as the logic error type from the acquired sub board communication LSI packet type (S235).

  If it is determined in S235 that there is a CRC error of the sub board communication LSI as the logic error type in the sub board communication LSI packet type, the sub CPU 701 sets 'COM2 ERR3' as the corresponding error information and stores the error information history storage area of the sub RAM 703. While registering in 703 d, the reception error flag is set on (S236). Thereafter, the sub CPU 701 ends the communication LSI reception data analysis process. On the other hand, if it is determined that there is no CRC error in the sub board communication LSI, the sub CPU 701 ends the communication LSI received data analysis processing.

[Subscription registration task performed by sub CPU]
FIG. 42 shows an effect registration task performed by the sub CPU 701. As shown in FIG. 42, the sub CPU 701 extracts a message from the message queue (S241). Next, the sub CPU 701 determines whether there is a message (S 242). When the sub CPU 701 determines that there is a message, the sub CPU 701 copies game information from the message (S 243). For example, various data such as an internal winning combination, a type of reel whose rotation has stopped, a display combination, an in-operation flag, etc. specified by the parameters are copied in a predetermined storage area provided in the sub RAM 703.

  Next, the sub CPU 701 performs effect content determination processing described with reference to FIG. 43 (S244). In this process, determination of effect contents, registration of effect data, and the like are performed according to the type of the received command.

  After S244 or when it is determined that there is no message in S242, the sub CPU 701 registers animation data (S245). Next, the sub CPU 701 registers sound data (S246). Next, the sub CPU 701 registers lamp data (S247). Registration of animation data, registration of sound data and registration of lamp data are performed based on the effect data registered in the effect content determination process. When this process ends, the process moves to S241.

[Determination content determination processing]
FIG. 43 shows effect content determination processing by the sub CPU 701. As shown in FIG. 43, the sub CPU 701 determines whether it is time to receive a start command (S261). When it is determined that the start command is received, the sub CPU 701 extracts a random number value for effect, randomly determines an effect number based on an internal winning combination, etc., and registers it (S 262). The effect number is data for specifying the content of the effect to be executed this time.

  Next, the sub CPU 701 registers effect data at the time of start based on the registered effect number (S263). The effect data is data specifying animation data, sound data, and lamp data. When the effect data is registered, corresponding animation data and the like are determined, and effects such as display of an image are executed. When this process ends, the sub CPU 701 ends the effect content determination process.

  Next, when it is determined that the start command is not received, the sub CPU 701 determines whether or not the reel stop command is received (S 264). When it is determined that the reel stop command is received, the sub CPU 701 registers effect data at the time of stop based on the registered effect number and the type of the stop button (S265). When this process ends, the sub CPU 701 ends the effect content determination process.

  Next, when it is determined that the reel stop command is not received, the sub CPU 701 determines whether or not the display command is received (S266). When determining that the display command is received, the sub CPU 701 registers effect data at the time of display based on the registered effect number (S267). When this process ends, the sub CPU 701 ends the effect content determination process.

  Next, when it is determined that the display command is not received, the sub CPU 701 determines whether the bonus start command is received (S268). When the sub CPU 701 determines that the bonus start command has been received, the sub CPU 701 registers effect data for the bonus start (S 269). When this process ends, the sub CPU 701 ends the effect content determination process.

  Next, if it is determined that the bonus start command has not been received, the sub CPU 701 determines whether or not the bonus end command has been received (S 270). When the sub CPU 701 determines that the bonus end command is not received, the effect content determination process is ended. On the other hand, if it is determined that the bonus end command has been received, the sub CPU 701 registers effect data for bonus end (S271). When this process ends, the sub CPU 701 ends the effect content determination process.

  As described above, according to the reception interrupt process, the main board communication process, and the communication LSI reception data analysis process by the sub CPU 701, error information related to various types of communication is registered in the error information history storage area 703d of the sub RAM 703.

  Next, the pachislot 1 when the clerk uses the error information history will be described. The sub CPU 701 of the pachislot 1 adopts two kinds of operation methods of a normal operation and a simple operation by a clerk in order to display the error information history shown in FIG. 45 on the liquid crystal display device 10. When executing the normal operation, the clerk rotates the door key 110 to the right to release the lock mechanism of the front door 2b, and turns on the setting key to turn on the setting key type switch, thereby the liquid crystal display area 10A. The menu screen shown in FIG. 44 is displayed. Then, when the clerk operates the operation key and selects the “error information history” item 100a, the error information history screen shown in FIG. 45 is displayed on the liquid crystal display area 10A. On the other hand, when executing the simple operation, the clerk rotates the door key 110 to the left to reset the error when an error occurs or during non-game, and holds the state for a predetermined time, for example, 5 seconds or more. As a result, an error information history screen shown in FIG. 45 is displayed in the liquid crystal display area 10A.

  When the sub-CPU 701 detects an operation to select the "error information history" item 100a using the selection button 11A and the determination button 11B, the sub CPU 701 displays the error information history in the liquid crystal display area 10A as shown in FIG. . In the error information history, for example, as indicated by hatching in the figure, as the COM error related to communication, the aforementioned "COM1 ERR1 (COM1 error 1)", "COM3 ERR2 (COM3 error 2)", "COM2 ERR1 (COM2)" There may be a case where an error 1), "COM2 ERR3 (COM2 error 3)" and the like are included.

  When the sub CPU 701 detects an operation in which the clerk selects, for example, the “COM 2 ERR 3 (COM 2 error 3)” item 100 b using the selection button 11 A and the determination button 11 B, the transmission information is generated based on the error information history. Alternatively, the transmission information may be configured to be transmitted to the hall computer 1000 or the like.

  Next, with reference to flowcharts shown in FIGS. 56 to 65, operations relating to communication of the main substrate communication LSI 610 and the sub substrate communication LSI 710 will be described.

[Main control sequence (main board communication LSI)]
FIG. 56 shows a main control sequence by the main board communication LSI. As shown in FIG. 56, the dedicated controller 611 of the main board communication LSI 610 performs the initial setting process described with reference to FIG. 58 (S401). According to this initial setting process, various setting information related to communication is set based on a predetermined communication specification. The initialization process will be described later.

  Next, the dedicated controller 611 performs the reception process described with reference to FIG. 59 (S402). According to this reception process, data such as a command supplied from the main CPU 601 is received based on the communication specification. The reception process will be described later.

  Next, the dedicated controller 611 determines whether there is a transmission request (S403). The presence or absence of such a transmission request is determined based on a transmission request flag described later. If it is determined that there is a transmission request, the dedicated controller 611 performs transmission processing described with reference to FIG. 60 (S404). Thereafter, the dedicated controller 611 proceeds to S402. On the other hand, when determining that there is no transmission request, the dedicated controller 611 proceeds to S402 without performing transmission processing. The transmission process will be described later.

[Receive interrupt processing (main board communication LSI)]
FIG. 57 shows reception interrupt processing by the main board communication LSI. As shown in FIG. 57, the dedicated controller 611 of the main board communication LSI 610 acquires the received data supplied from the main CPU 601 via the first UART 601A and the first UART 615 (S421).

  Next, the dedicated controller 611 determines whether there is a physical layer error in the received data supplied from the main CPU 601 (S422). The process of determining the presence or absence of the physical layer error is mainly performed by the first UART 615 built in the main substrate communication LSI 610. The physical layer errors that can be detected at this time are overrun errors detected by the first UART 615, framing errors, parity errors, and the like.

  If it is determined in S422 that there is a physical layer error in the received data, the dedicated controller 611 sets the detected physical layer error in the main substrate communication LSI reception status (S423), and then proceeds to S424. The main board communication LSI reception status is set to the block of the byte number D11 of the serial data transmitted from the main board communication LSI 610 to the sub board communication LSI 710, as shown in FIG. On the other hand, when determining that there is no physical layer error in the received data, the dedicated controller 611 proceeds to later S425.

  Next, the dedicated controller 611 updates the error count by adding one (S424). Such an error count is set to bit numbers B0 to B3 of the main board communication LSI reception status, and the error count indicates the total number of reception errors occurring (see FIG. 51).

  Next, the dedicated controller 611 sequentially stores the reception data from the main CPU 601 in the transmission buffer (cache memory 613) (S425), and then updates the reception counter by adding 1 (S426). The reception counter is used to count data sent from the main CPU 601 with a data size of 8 bytes fixed length.

  Next, the dedicated controller 611 sets a timeout timer (S427), and ends this reception interrupt process. The timeout timer is for determining the presence or absence of a communication error at the time of data reception based on the reception waiting time. In this embodiment, the timeout timer at reception in the main board communication LSI 610 counts a waiting time capable of receiving data of at least 1 byte in order to detect a communication error in packet units (transmission units). It is supposed to be. Specifically, the timeout timer of the main board communication LSI 610 measures 2.5 msec based on the communication speed 19200 bps, for example, as a waiting time capable of receiving 48 bits (6 bytes) of data. It is configured.

[Initial setting process (main board communication LSI)]
FIG. 58 shows an initialization process by the main board communication LSI. As shown in FIG. 58, the dedicated controller 611 of the main board communication LSI 610 initializes the first UART 615 (S441). Specifically, the dedicated controller 611 refers to setting data based on the communication specification and the like stored in advance in the setting register 612, and transmits the baud rate (the communication speed related to transmission and reception) to the control register of the first UART 615 Set length, parity, stop bit etc. In this embodiment, for example, the communication speed with the main CPU 601 is set to 19200 bps, the data length is 8 bits, the parity is an even parity, and the stop bit is 1 bit.

  Next, the dedicated controller 611 calculates a timeout value at the time of reception of the first UART 615 from the baud rate setting value of the communication speed related to reception (S 442). Specifically, for example, when the baud rate setting value is 19200 bps and data of at least 48 bits is received, the dedicated controller 611 obtains 2.5 msec as a timeout value by 1 / baud rate × 48. The timeout value thus obtained is set to the timeout timer.

  Next, the dedicated controller 611 initializes the second UART 616 (S 443), and ends this initialization process. Specifically, the dedicated controller 611 refers to setting data based on the communication specification and the like stored in advance in the setting register 612, and transmits the baud rate (the communication speed related to reception) to the control register of the second UART 616, data at transmission and reception. Set length, parity, stop bit etc. In this embodiment, for example, the communication speed with the sub board communication LSI 710 is set to 115,200 bps, the data length is 8 bits, the parity is an even parity, and the stop bit is 1 bit.

[Reception processing (main board communication LSI)]
FIG. 59 shows reception processing by the main board communication LSI. As shown in FIG. 59, the dedicated controller 611 of the main board communication LSI 610 determines whether a timeout has occurred by using a timeout timer when acquiring received data from the main CPU 601 (S461).

  If it is determined in S461 that a timeout has not occurred, the dedicated controller 611 ends the reception process. On the other hand, when it is determined that the timeout has occurred, the dedicated controller 611 adds 1 to the packet reception number and updates it (S462).

  Next, the dedicated controller 611 determines whether the received data is less than 8 bytes (S463). If it is determined that the received data is less than 8 bytes, the dedicated controller 611 sets a timeout as error information in the main substrate communication LSI reception status (S464). As shown in FIG. 51, the timeout as error information is set with the bit of bit number B7 in the main board communication LSI reception status as “1”. On the other hand, when it is determined that the received data is not less than 8 bytes, that is, at least 8 bytes of received data, the dedicated controller 611 proceeds to the next S465.

  Next, the dedicated controller 611 sets a transmission request flag (S465), and ends this reception process. The transmission request flag is secured in a predetermined area of the cache memory 613, and is used to identify the presence / absence of data to be transmitted by the main board communication LSI 610.

[Transmission processing (main board communication LSI)]
FIG. 60 shows transmission processing by the main board communication LSI. As shown in FIG. 60, the dedicated controller 611 of the main board communication LSI 610 determines whether there is a data transmission request based on the transmission request flag, that is, whether there is received data including a command from the main CPU 601 or the like. It discriminates (S481).

  If it is determined in S481 that there is a data transmission request, the dedicated controller 611 sets the packet reception number in the transmission buffer (S482). The transmission buffer is secured in a predetermined area of the cache memory 613, and is used to temporarily store communication data and the like including commands and the like supplied from the main CPU 601 to the sub CPU 701. On the other hand, when it is determined that there is no request for data transmission, the dedicated controller 611 ends the transmission processing.

  Next, the dedicated controller 611 sets the reception data (packet data: data fixed length 8 bytes) from the main CPU 601 in the transmission buffer (S483). Subsequently, the dedicated controller 611 sets the main board communication LSI reception status in the transmission buffer (S484). Further, the dedicated controller 611 sets dummy data in the transmission buffer (S485). Furthermore, the dedicated controller 611 calculates a CRC by cyclic redundancy check, and sets CRC data as a result of the calculation in the transmission buffer (S 486). As a result, from the transmission buffer, external communication data (see FIG. 49) consisting of 16 bytes of byte numbers D0 to D15 are sequentially output as 1 byte of serial format transmission data. The data transmitted from the main substrate communication LSI 610 to the sub substrate communication LSI 710 in this way is data of 16 bytes of fixed data length which has been Manchester modulated and AES encrypted in the main substrate communication LSI 610, and the communication speed is based on the communication specification. It is transmitted at 115,200 bps.

  Next, the dedicated controller 611 determines whether 16 bytes of data have been transmitted (S487). If it is determined that 16 bytes of data have not been transmitted, the dedicated controller 611 transmits transmission data from the transmission port of the second UART 616 (S488), and then returns to S487 again. On the other hand, when determining that 16 bytes of data have been transmitted, the dedicated controller 611 clears the reception data, the reception counter, and the transmission request flag (S489), and ends this transmission processing.

[Main control sequence (Sub board communication LSI)]
FIG. 61 shows a main control sequence by the sub board communication LSI. As shown in FIG. 61, the dedicated controller 711 of the sub board communication LSI 710 performs the initial setting process described with reference to FIG. 63 (S501). According to this initial setting process, various setting information related to communication is set based on a predetermined communication specification. The initialization process will be described later.

  Next, the dedicated controller 711 performs the reception process described with reference to FIG. 64 (S502). According to this reception process, external communication data including a command or the like supplied from the main CPU 601 through the main board communication LSI 610 is received based on the communication specification. The reception process will be described later.

  Next, the dedicated controller 711 determines whether there is a transmission request (S503). The presence or absence of such a transmission request is determined based on a transmission request flag described later. If it is determined that there is a transmission request, the dedicated controller 711 performs transmission processing described with reference to FIG. 65 (S504). Thereafter, the dedicated controller 711 proceeds to S502. On the other hand, when it is determined that there is no transmission request, the dedicated controller 711 proceeds to S502 without performing transmission processing. The transmission process will be described later.

[Reception interrupt processing (sub board communication LSI)]
FIG. 62 shows reception interrupt processing by the sub board communication LSI. As shown in FIG. 62, the dedicated controller 711 of the sub substrate communication LSI 710 acquires the received data supplied from the main substrate communication LSI 610 via the second UART 716 (S521).

  Next, the dedicated controller 711 determines whether or not there is a physical layer error in the received data supplied from the main substrate communication LSI 610 (S522). The process of determining the presence or absence of the physical layer error is mainly performed by the second UART 716 incorporated in the sub substrate communication LSI 710. Physical layer errors that can be detected at this time are overrun errors detected by the second UART 716, framing errors, parity errors, and the like.

  If it is determined in S522 that there is a physical layer error in the received data, the dedicated controller 711 sets the detected physical layer error in the sub board communication LSI reception status (S523), and then the process proceeds to S524. The sub board communication LSI reception status is set to the block of the byte number D12 of the serial data transmitted from the sub board communication LSI 710 to the sub CPU 701, as shown in FIG. On the other hand, when determining that there is no physical layer error in the received data, the dedicated controller 711 proceeds to later step S525.

  Next, the dedicated controller 711 updates the error count by adding one (S524). Such an error count is set to bit numbers B0 to B3 of the sub board communication LSI reception status, and the error count indicates the total number of reception errors occurring (see FIG. 51).

  Next, the dedicated controller 711 sequentially stores the reception data from the main substrate communication LSI 610 in the transmission buffer (cache memory 713) (S525), and then updates the reception counter by adding 1 (S526). The reception counter is used to count data sent from the main substrate communication LSI 610 with a data size of 16 bytes fixed length.

  Next, the dedicated controller 711 sets a timeout timer (S527), and ends this reception interrupt process. Such a timeout timer of the sub board communication LSI 710 is also configured to clock a waiting time capable of receiving data of at least 1 byte in order to detect a communication error in a packet unit (transmission unit). . Specifically, the timeout timer of the sub substrate communication LSI 710 measures, for example, about 0.4 msec based on the communication speed of 115,200 bps as a waiting time capable of receiving 48 bits (6 bytes) of data. Is configured.

[Initial setting process (sub board communication LSI)]
FIG. 63 shows an initial setting process by the sub board communication LSI. As shown in FIG. 63, the dedicated controller 711 of the sub board communication LSI 710 performs initial setting for the first UART 715 (S541). Specifically, the dedicated controller 711 refers to the setting data based on the communication specification and the like stored in advance in the setting register 712, and transmits the baud rate (the communication speed related to transmission and reception) to the control register of the first UART 715 Set length, parity, stop bit etc. In this embodiment, for example, the communication speed with the sub CPU 701 is set to 115,200 bps, the data length is 8 bits, the parity is an even parity, and the stop bit is 1 bit.

  Next, the dedicated controller 711 initializes the second UART 716 (S 542). Specifically, the dedicated controller 711 refers to the setting data based on the communication specification and the like stored in advance in the setting register 712, and transmits the baud rate (the communication speed related to reception) to the control register of the second UART 716 Set length, parity, stop bit etc. In this embodiment, for example, the communication speed with the main board communication LSI 610 is set to 115,200 bps, the data length is 8 bits, the parity is an even parity, and the stop bit is 1 bit.

  Next, the dedicated controller 711 calculates a timeout value at the time of reception of the second UART 716 from the baud rate setting value of the communication speed related to reception (S543), and ends this initial setting process. Specifically, for example, when the baud rate setting value is 115,200 bps and data of at least 48 bits is received, the dedicated controller 711 obtains about 0.4 msec as a timeout value by 1 / baud rate × 48. The timeout value thus obtained is set to the timeout timer.

[Reception processing (sub board communication LSI)]
FIG. 64 shows reception processing by the sub board communication LSI. As shown in FIG. 64, the dedicated controller 711 of the secondary substrate communication LSI 710 determines whether a timeout has occurred by using a timeout timer when acquiring received data from the main substrate communication LSI 610 (S561).

  If it is determined in S561 that the timeout has not occurred, the dedicated controller 711 ends the reception process. On the other hand, when it is determined that the timeout has occurred, the dedicated controller 711 determines whether the received data is 16 bytes (S562).

  If it is determined in S562 that the received data is not 16 Bytes, for example, less than 16 Bytes, the dedicated controller 711 sets a time-out as error information in the sub board communication LSI reception status (S563). As shown in FIG. 51, the timeout as error information is set with the bit of bit number B7 in the sub board communication LSI reception status as “1”. On the other hand, when it is determined that the received data is 16 bytes, the dedicated controller 711 proceeds to the next S564.

  Next, the dedicated controller 711 calculates a CRC by cyclic redundancy check on the data of the byte numbers D0 to D13 of the received data (S564).

  Next, the dedicated controller 711 determines whether the calculated CRC is normal (S565). If the CRC is determined to be normal, the dedicated controller 711 proceeds to later S567. On the other hand, when the CRC is determined to be abnormal, the dedicated controller 711 sets a CRC error as a logic error type in the sub board communication LSI packet type (S566). The sub board communication LSI packet type is set in the block of the byte number D13 of serial data transmitted from the sub board communication LSI 710 to the sub CPU 701, as shown in FIG.

  Next, the dedicated controller 711 sets a transmission request flag (S567), and ends this reception process. The transmission request flag is secured in a predetermined area of the cache memory 713, and is used to identify the presence or absence of data to be transmitted by the sub board communication LSI 710.

[Transmission processing (sub board communication LSI)]
FIG. 65 shows transmission processing by the sub board communication LSI. As shown in FIG. 65, the dedicated controller 711 of the sub substrate communication LSI 710 determines whether there is a data transmission request based on the transmission request flag, that is, it includes a command sent from the main CPU 601 through the main substrate communication LSI 610. It is determined whether or not there is received data (S581).

  If it is determined in S581 that there is a data transmission request, the dedicated controller 711 transmits the block of byte numbers D0 to D11 of the received data (external communication data: fixed data length of 16 Bytes) from the main board communication LSI 610 as a transmission buffer. Set to (S582). Subsequently, the dedicated controller 711 sets an error count in the sub board communication LSI reception status (S583), and sets the sub board communication LSI reception status in the transmission buffer as a block of the byte number D12 (S584).

  The dedicated controller 711 also sets the sub board communication LSI packet type in the transmission buffer as a block of the byte number D13 (S585). Furthermore, the dedicated controller 711 calculates a CRC by cyclic redundancy check for blocks of byte numbers D0 to D13 of the transmission buffer, and sets CRC data as a calculation result in the transmission buffer (S586). As a result, in the transmission buffer, internal communication data (see FIG. 50) consisting of 16 bytes of byte numbers D0 to D15 is temporarily stored as transmission data in serial format.

  Thus, when data (D0 to D15) to be transmitted to the transmission buffer is temporarily stored (standby), the dedicated controller 711 first transmits data corresponding to "STX" indicating the start of communication message from the transmission port of the first UART 715. Is sent (S587).

  Then, the dedicated controller 711 determines whether 16 bytes of data (D0 to D15) have been transmitted (S588). If it is determined that 16 bytes of data (D0 to D15) have been transmitted, the dedicated controller 711 clears the reception data, the reception counter, and the transmission request flag (S593), and ends this transmission processing.

  On the other hand, when it is determined in S588 that 16 bytes of data (D0 to D15) are not transmitted, the dedicated controller 711 determines that the transmission data output from the transmission buffer at the current timing is "STX" or "DLE". It is determined whether or not the same value is met (S589).

  If it is determined in S589 that the transmission data corresponds to the same value as "STX" or "DLE", the dedicated controller 711 corresponds to "DLE" indicating that the transmission port of the first UART 715 is a block including control data. Data is transmitted (S590), and escape processing is performed on the corresponding transmission data (S591). In the escape process, the data transmission order of the corresponding block and the blocks following the next order is advanced by one each. On the other hand, when it is determined that the transmission data does not correspond to the same value as “STX” or “DLE”, the dedicated controller 711 proceeds to the next S592 without performing “DLE” transmission or escape processing.

  Next, the dedicated controller 711 transmits the transmission data (D0 to D15) set in the transmission buffer from the transmission port of the first UART 715 (S592), and then returns to S588 again. As a result, from the transmission buffer, internal communication data (see FIG. 50) including byte numbers D0 to D15 are sequentially output as 1 byte of serial transmission data. The data transmitted from sub-substrate communication LSI 710 to sub-CPU 701 in this manner is Manchester-demodulated and AES-decoded in sub-substrate communication LSI 710, and blocks of byte numbers D0 to D15 in sub-substrate communication LSI 710. The data is of variable length 17 to 33 bytes including “STX” and “DLE”, and is transmitted at a communication speed of 115,200 bps based on the communication specification.

  Next, the operation relating to the external output of the main CPU 601, the external output communication LSI 610A, and the external terminal board control LSI 910 will be described with reference to the flowcharts shown in FIGS.

[External output medal in command registration process]
FIG. 69 shows an external output medal in command registration process by the main CPU. As shown in FIG. 69, the main CPU 601 sets a medal-in command in the external output storage area (0) of the main RAM 603 (S601). The external output storage area (0) is an area for outputting the command type (command information) of the commands, and is secured in the main RAM 603 as an area for one byte.

  Next, the main CPU 601 sets the number of inserted medals in the external output storage area (1) (S602), and ends this registration process. The external output storage area (1) is an area for outputting setting data of commands, and is secured in the main RAM 603 as an area of 1 byte. In this case, one of 1 to 3 is set in the external output storage area (1) as a value corresponding to the number of inserted medals. That is, when there is a command related to medal in to be output to the outside, the command is divided into command information (medal in command) and setting data (the number of inserted medals) before being transmitted to the external output communication LSI 610A. The respective information is set in the external output storage area (0) and the external output storage area (1).

[Medal out command registration process for external output]
FIG. 70 shows an external output medal out command registration process by the main CPU. As shown in FIG. 70, the main CPU 601 determines whether or not the number of paid-out medals is present (S621), and when it is determined that the number of paid-out medals is not present, this registration process is ended. On the other hand, if it is determined in S621 that there is a medal payout number, the main CPU 601 sets a medal out command in the external output storage area (0) (S622).

  Next, the main CPU 601 sets the medal payout number in the external output storage area (1) (S623), and ends this registration process. In this case, any one of 1 to 15 is set in the external output storage area (1) as a value corresponding to the number of medals paid out. That is, when there is a command related to medal out to be output to the outside, the command is sent to the command information (the medal out command) and the setting data (the number of medals paid out) before being transmitted to the external output communication LSI 610A. The information is divided and set in the external output storage area (0) and the external output storage area (1), respectively.

[Command external output processing]
FIG. 71 shows command external output processing by the main CPU. As shown in FIG. 71, the main CPU 601 determines whether there is data to be externally output in the external output storage area (0) or (1) (S641).

  In S641, when there is data to be externally output in the external output storage area (0) or (1), the main CPU 601 proceeds to S649 described later. On the other hand, when there is no data to be externally output in the external output storage areas (0) and (1), the main CPU 601 performs external signal editing processing described later with reference to FIG. 72 (S642). In this external signal editing process, commands relating to external signals 1 to 4 are set in the external output storage area.

  Next, the main CPU 601 determines again whether or not there is data to be externally output in the external output storage area (0) or (1) (S643).

  In S643, when there is data to be externally output in the external output storage area (0) or (1), the main CPU 601 proceeds to S649 described later. On the other hand, when there is no data to be externally output in the external output storage areas (0) and (1), the main CPU 601 performs security signal editing processing (S644). In this security signal editing process, an output state image of a security signal to be externally output is generated using the main RAM 603 after time setting as necessary.

  The main CPU 601 determines whether or not there is a change in the security signal, and whether or not the output state image of the security signal indicates a state change (S645). If the output state image of the security signal does not indicate a state change, the main CPU 601 ends this command external output processing. On the other hand, if the output state image of the security signal indicates a state change, the main CPU 601 sets the security command “C0H” in the external output storage area (0) (S646). At this time, status information (setting data) of the security signal is set in the lower 4 bits of the external output storage area (1).

  Further, the main CPU 601 determines whether or not there is one or more time setting value of the time to change in the output state image of the set security command (S647). If the time setting value is not 1 or more in S647, that is, the time setting value is 0 and the output state of the security signal is maintained, the main CPU 601 proceeds to S649 described later. On the other hand, when the time setting value is 1 or more in S647, the main CPU 601 sets the time setting value in the upper 4 bits of the external output storage area (1) (S648).

  Then, the main CPU 601 transmits the data (command information and setting data) finally set in the external output storage area (0) and the external output storage area (1) to the external output communication LSI 610A (S649) , This command ends external output processing. As a result, the commands set in the external output storage area (0) and the external output storage area (1) are promptly transmitted to the external output communication LSI 610A through the second UART 601B in the main CPU 601. After transmission of the command, the external output storage area (0) and the external output storage area (1) are cleared. In the command external output process of this embodiment, after the command information (1 byte) of the external output storage area (0) is transmitted, the setting data (1 of the external output storage area (1) is subsequently provided. By sending the byte), the command is sent in units of 2 bytes.

[External signal editing process]
FIG. 72 shows an external signal editing process by the main CPU. As shown in FIG. 72, the main CPU 601 determines whether or not there is a state output setting for the external signals 1 to 4, that is, whether or not the external signals 1 to 4 should simply be output continuously (S661) .

  In S661, when there is no state output setting in the external signals 1 to 4, that is, when the time setting value is 1 or more and the external signals 1 to 4 are limited for a predetermined time and externally output, the main CPU 601 Move to S666. On the other hand, when there is a state output setting in external signals 1 to 4, that is, when the time setting value is 0 and external signals 1 to 4 should be simply continuously output to the outside, main CPU 601 relates to external signals 1 to 4 An external output command is set in the external output storage area (0) (S662). At this time, “B0H” is set in the external output storage area (0) as temporary command information.

  Next, the main CPU 601 determines whether an external output command to be actually output to the outside corresponds to a chain command (S663). If the actual external output command does not correspond to a chain command in S663, the main CPU 601 proceeds to S665 described later. On the other hand, if the actual external output command corresponds to a chain command, the main CPU 601 adds one to the value of the external output storage area (0) to reset it to include the chain information (S664). As a result, “B1H” is set in the external output storage area (0) as an external output chain command corresponding to the actual command information.

  Thereafter, the main CPU 601 sets the state information (setting data) of the external signals 1 to 4 in the lower 4 bits of the external output storage area (1) (S665), and ends this external signal editing process. Thus, when there is an external output command or an external output chain command, these commands are sent to the external output communication LSI 610A before command information and setting data (state output setting information of external signals 1 to 4 And each information is set in the external output storage area (0) and the external output storage area (1).

  On the other hand, in S666, the main CPU 601 performs external signal generation processing. In this external signal generation processing, output state images of the external signals 1 to 4 to be externally output are generated using the external signal editing area of the main RAM 603 after time setting.

  Then, the main CPU 601 determines whether or not there is a change in the external signal editing area, that is, whether or not the output state image of the external signals 1 to 4 created in the external signal editing area indicates a state change (S667) ).

  In S667, when there is no change in the external signal editing area and the output state image of the external signals 1 to 4 does not indicate the state change, the main CPU 601 ends the external signal editing process. On the other hand, when there is a change in the external signal editing area and the output state image of the external signals 1 to 4 indicates a state change, the main CPU 601 further outputs the output state images of the external signals 1 to 4 as a change of the external signal editing area. It is determined whether a change from OFF to ON is indicated (S668).

  If the output state image of the external signals 1 to 4 indicates a change from OFF to ON in S668, the main CPU 601 sets the external output ON command related to the external signals 1 to 4 to the external output storage area (0). Set (S669) and move on to S671. At this time, “B2H” is set as temporary command information in the external output storage area (0). On the other hand, when the output state image of the external signals 1 to 4 indicates the change opposite to the change from OFF to ON, that is, the change from ON to OFF, the main CPU 601 turns off the external output related to the external signals 1 to 4 The command is set in the external output storage area (0) (S670), and the process proceeds to S671. At this time, “B4H” is set in the external output storage area (0) as temporary command information.

  Next, the main CPU 601 determines whether a command to be actually output to the outside corresponds to a chain command (S671). If the actual command does not correspond to a chain command in S671, the main CPU 601 proceeds to S673 described later. On the other hand, if the actual command corresponds to a chain command, the main CPU 601 adds one to the value of the external output storage area (0) to reset it to include the chain information (S672). As a result, "B3H" is set in the external output storage area (0) as the external output ON chain command corresponding to the actual command information, or "B5H" as the external output OFF chain command.

  Thereafter, the main CPU 601 sets data of the external signal editing area, that is, state information (setting data) of the external signals 1 to 4 in the lower 4 bits of the external output storage area (1) (S673).

  Further, the main CPU 601 determines whether or not the time setting value is 1 or more for the set external signals 1 to 4 (S674). If the time setting value is not 1 or more in S674, that is, the time setting value is 0, the main CPU 601 ends the external signal editing process. On the other hand, when the time setting value is 1 or more, the main CPU 601 sets the time setting value in the upper 4 bits of the external output storage area (1) (S675), and ends the external signal editing process. As a result, command information and setting data (external signal 1 (external signal 1) are also transmitted prior to transmission of the external output ON command, external output OFF command, external output ON chain command, and external output OFF chain command to the external output communication LSI 610A. The information is divided into an external output storage area (0) and an external output storage area (1).

[Main control sequence (Communication LSI for external output)]
FIG. 73 shows a main control sequence by the external output communication LSI. As shown in FIG. 73, the dedicated controller 611A of the external output communication LSI 610A performs the same initial setting process as the main substrate communication LSI 610 (S681). According to this initial setting process, various setting information relating to the external output is set based on the predetermined communication specification with the external concentrated terminal plate 9A.

  Next, the dedicated controller 611A performs the reception process described with reference to FIG. 76 (S682). According to this reception process, the command output from the main CPU 601 is received based on the communication specification. The reception process will be described later.

  Next, the dedicated controller 611A performs the output control process described with reference to FIG. 84 (S683). Thereafter, the dedicated controller 611 proceeds to S682. The output control process will be described later.

[Receive interrupt processing (Communication LSI for external output)]
FIG. 74 shows reception interrupt processing by the external output communication LSI. As shown in FIG. 74, the dedicated controller 611A of the external output communication LSI 610A acquires received data (command information or setting data) supplied from the main CPU 601 via the second UART 601B and the first UART 615A (S701).

  Next, the dedicated controller 611A determines whether or not there is a physical layer error in the reception data (command) supplied from the main CPU 601 (S702). The process of determining the presence or absence of the physical layer error is mainly performed by the first UART 615A built in the external output communication LSI 610A.

  If it is determined in S702 that there is no physical layer error in the received data, the dedicated controller 611A temporarily stores the received data from the main CPU 601 in the reception buffer area of the cache memory 613A (S703), and ends this reception interrupt processing. Do. On the other hand, when it is determined that there is a physical layer error in the received data, the dedicated controller 611A sets the command received flag to off (S704), and ends this reception interrupt process. In the present embodiment, the received data determined to have a physical layer error is discarded, but may be stored together with information indicating that a physical layer error is present.

[Timer interrupt processing (5 msec)]
FIG. 75 shows timer interrupt processing (5 msec) by the external output communication LSI. The timer interrupt process is a process that is periodically executed every five milliseconds, which is predetermined, for example, using a signal of a counter timer circuit or a signal of a programmable timer.

  As shown in FIG. 75, the dedicated controller 611A of the external output communication LSI 610A sets 5 as the number of software timers in the predetermined area of the cache memory 613A (S721), and the reference address of the software timer in the predetermined area of the cache memory 613A. It sets (S722). The software timer number “5” corresponds to the number of software 1 to 5 excluding the spare. As the reference address of the software timer, the first address assigned to the software timers (1) to (5) is set.

  Next, the dedicated controller 611A determines whether the current number of software timers is 0 (S723). In S723, when the number of software timers is 0, the dedicated controller 611A ends the timer interrupt process. On the other hand, when the number of software timers is not 0, the dedicated controller 611A determines whether the state of the software timer of the reference address is measurement (1) (S724).

  In S724, when the state of the software timer is not measurement (1), the dedicated controller 611A proceeds to S728 described later. On the other hand, when the state of the software timer is measurement (1), the dedicated controller 611A subtracts 1 from the value of the software timer counter to update it (S725). The software timer counter is used as a subtraction counter, and is basically in the timer measurement state until the value becomes zero.

  Next, the dedicated controller 611A determines whether the value of the software timer counter is 0 (S726). If the value of the software timer counter is not 0 in S726, the dedicated controller 611A proceeds to S728 described later. On the other hand, when the value of the software timer counter is 0, the dedicated controller 611A sets the state of the software timer of the reference address to end (-1) (S727).

  Next, the dedicated controller 611A adds and updates the address of the software timer by 3 bytes (S728). Thereafter, the dedicated controller 611A subtracts one from the number of software timers (S729), and returns to S723 again. According to such timer interrupt processing, time measurement is performed for each of the software timers (1) to (5). For example, by repeatedly performing 100 times, a time of 500 ms can be measured.

[Receive processing (Communication LSI for external output)]
FIG. 76 shows reception processing by the external output communication LSI. As shown in FIG. 76, the dedicated controller 611A of the external output communication LSI 610A determines whether the reception data from the main CPU 601 is in the reception buffer area of the cache memory 613A (S741).

  In S741, when there is no reception data from the main CPU 601, the dedicated controller 611A ends this reception process. On the other hand, when there is received data from the main CPU 601, the dedicated controller 611A determines whether or not the most significant bit Bit 7 of the received data is on (S742). As long as there is no communication error or the like in the received data, the most significant bit Bit7 is always on in the case of command information, and the most significant bit Bit7 is always in the case of setting data.

  In S742, when the most significant bit (Bit 7) of the received data is not on, the dedicated controller 611A proceeds to S745 described later. On the other hand, when the most significant bit (Bit 7) of the received data is on, the dedicated controller 611A sets the command received flag on (S743), and stores the received data as command information in a predetermined area of the cache memory 614A. (S744). Thereafter, the dedicated controller 611A ends the reception process.

  In S745, the dedicated controller 611A determines whether the command received flag is on. If the command received flag is not on, the dedicated controller 611A ends this reception process. On the other hand, when the command received flag is on, the dedicated controller 611A stores the received data as setting data in the setting data storage area of the cache memory 614A (S746).

  Then, the dedicated controller 611A executes command output conversion processing described later with reference to FIG. 77 (S747). In this command output conversion process, the command information and the setting data are combined into one set, and the command received from the main CPU 601 is converted into external output data suitable for a parallel signal. Thereafter, the dedicated controller 611A sets the command received flag to OFF (S748), and ends this reception process. According to such reception processing, it is possible to receive, for example, a command consisting of 2 bytes while efficiently discriminating command information and setting data for each byte.

Command output conversion process
FIG. 77 shows command output conversion processing by the external output communication LSI. As shown in FIG. 77, the dedicated controller 611A of the external output communication LSI 610A determines whether the received command is a medal in command or not by referring to the command information stored in the predetermined area of the cache memory 614A ( S761). In S761, when the received command is not a medal in command, the dedicated controller 611A proceeds to S763. On the other hand, when the received command is a medal in command, the dedicated controller 611A executes a medal in output conversion process described later with reference to FIG. 78 (S762). Thereafter, the dedicated controller 611A ends the command output conversion process. In the medal in output conversion process, external output data is generated according to a command related to medal in.

  Next, the dedicated controller 611A determines whether the received command is a medal out command or not by referring to the command information stored in the predetermined area of the cache memory 614A (S763). If the received command is not a medal out command in S763, the dedicated controller 611A proceeds to S765. On the other hand, when the received command is a medal out command, the dedicated controller 611A executes medal out output conversion processing described later with reference to FIG. 79 (S764). Thereafter, the dedicated controller 611A ends the command output conversion process. In the medal out output conversion process, data for external output corresponding to a command related to medal out is generated.

  Next, the dedicated controller 611A determines whether the received command is an external output command (including an external output chain command) or not by referring to the command information stored in the predetermined area of the cache memory 614A (S765) . If it is determined in S765 that the received command is not an external output command, the dedicated controller 611A proceeds to S767. On the other hand, when the received command is an external output command or an external output chain command, the dedicated controller 611A executes an external output conversion process described later with reference to FIG. 80 (S766). Thereafter, the dedicated controller 611A ends the command output conversion process. In the external output conversion process, external output data is generated according to the external output command relating to the external signals 1 to 4 or the command of the external output chain command.

  Next, the dedicated controller 611A determines whether the received command is an external output ON command (including an external output ON chain command) by referring to the command information stored in a predetermined area of the cache memory 614A ( S767). If the received command is not the external output ON command in S767, the dedicated controller 611A proceeds to S769. On the other hand, when the received command is the external output ON command or the external output ON chain command, the dedicated controller 611A executes the external output ON conversion process described later with reference to FIG. 81 (S768). Thereafter, the dedicated controller 611A ends the command output conversion process. In the external output ON conversion process, external output data is generated according to the external output ON command related to the external signals 1 to 4 or the command of the external output ON chain command.

  Next, the dedicated controller 611A determines whether the received command is an external output OFF command (including an external output OFF chain command) or not by referring to the command information stored in the predetermined area of the cache memory 614A ( S769). If it is determined in S769 that the received command is not an external output OFF command, the dedicated controller 611A proceeds to S771. On the other hand, when the received command is an external output OFF command or an external output OFF chain command, the dedicated controller 611A executes an external output OFF conversion process described later with reference to FIG. 82 (S770). Thereafter, the dedicated controller 611A ends the command output conversion process. In the external output OFF conversion process, external output data is generated according to the external output OFF command relating to the external signals 1 to 4 or the command of the external output OFF chain command.

  Next, the dedicated controller 611A determines whether the received command is a security command or not by referring to the command information stored in the predetermined area of the cache memory 614A (S771). In S771, when the received command is not a security command, the dedicated controller 611A ends the command output conversion process. On the other hand, when the received command is a security command, the dedicated controller 611A executes security output conversion processing described later with reference to FIG. 83 (S772). Thereafter, the dedicated controller 611A ends the command output conversion process. In the security output conversion process, data for external output is generated according to a command of a security command related to a security signal.

[Medal In-out conversion process]
FIG. 78 shows medal in output conversion processing by the external output communication LSI. As illustrated in FIG. 78, the dedicated controller 611A of the external output communication LSI 610A refers to the setting data stored in the setting data storage area of the cache memory 614A to determine whether the value of the setting data falls within 1 to 3 It is determined whether or not (S781).

  In S781, when the value of the setting data does not correspond to 1 to 3, the dedicated controller 611A discards the setting data relating to the medal in as invalid, and ends the medal in output conversion process. On the other hand, if the setting data value corresponds to 1 to 3, the dedicated controller 611A secures the area of the medal in counter in the cache memory 614A, and sets the value of the setting data in the medal in counter (S782).

  Next, the dedicated controller 611A accesses the output editing area provided in the cache memory 614A, and sets Bit 6 of the output editing area to the on state (1) (S783). Bit 6 of the output editing area corresponds to the medal in command.

  Next, the dedicated controller 611A sets 10 as the timer counter value of the software timer (1) (S784). The timer counter value 10 corresponds to 50 ms of the pulse width to be set when correlating the value of the setting data related to the medal-in as the number of pulses.

  Next, the dedicated controller 611A sets measurement (1) as a value indicating the state of the software timer (1) (S785), and ends the medal in output conversion process. According to such a medal in output conversion process, data for external output corresponding to the command related to the medal in and according to the medal in signal changing in state every unit time (pulse width) is efficiently generated.

[Medal out output conversion processing]
FIG. 79 shows medal out output conversion processing by the external output communication LSI. As shown in FIG. 79, the dedicated controller 611A of the external output communication LSI 610A refers to the setting data stored in the setting data storage area of the cache memory 614A to determine whether the value of the setting data falls within 1 to 15 It is determined whether or not it is (S801).

  In S801, when the value of the setting data does not correspond to 1 to 15, the dedicated controller 611A discards the setting data relating to the medal out as invalid, and ends the medal out output conversion processing. On the other hand, when the setting data value corresponds to 1 to 15, the dedicated controller 611A secures the area of the medal out counter in the cache memory 614A, and sets the value of the setting data in the medal out counter (S802). Thereafter, the dedicated controller 611A sets the medal out output flag on (S803). The medal out output flag is used to determine whether a medal out signal is in the external output.

  Next, the dedicated controller 611A accesses the output editing area provided in the cache memory 614A, and sets Bit 5 of the output editing area to the on state (1) (S804). Bit 5 of the output editing area corresponds to the medal out command.

  Next, the dedicated controller 611A sets 10 as the timer counter value of the software timer (2) (S805). The timer counter value 10 corresponds to 50 ms of the pulse width to be set when correlating the value of the setting data related to the medal out as the number of pulses.

  Next, the dedicated controller 611A sets measurement (2) as a value indicating the state of the software timer (2) (S806), and ends the token out output conversion process. According to such a medal out output conversion process, data for external output corresponding to a command related to a medal out and according to a medal out signal that changes state every unit time (pulse width) is efficiently generated. .

[External output conversion process]
FIG. 80 shows external output conversion processing by the external output communication LSI. As shown in FIG. 80, the dedicated controller 611A of the external output communication LSI 610A determines whether or not the medal output in progress flag is on for the external output chain command with respect to the received command related to the external output. (S821).

  If it is not the external output chain command or the medal out output flag is not on in S821, the dedicated controller 611A proceeds to S824 described later. On the other hand, if it is the external output chain command and the medal out output flag is on, the dedicated controller 611A acquires the values of Bit0 to Bit3 from the setting data stored in the setting data storage area of the cache memory 614A, The values of Bit0 to Bit3 of the setting data are set to Bit0 to Bit3 of the chain area provided in the cache memory 614A (S822). Bit 0 to bit 3 of the setting data indicate the states of the external signals 1 to 4.

  Next, the dedicated controller 611A sets the chain flag on (S823). Thereafter, the dedicated controller 611A ends the external output conversion process. The chain flag is used to determine whether there is another signal to be output subsequently after the external output of the medal out signal has ended.

  In S824, the dedicated controller 611A obtains the values of Bit0 to Bit3 from the setting data stored in the setting data storage area of the cache memory 614A, and outputs the values of Bit0 to Bit3 of the setting data to the cache memory 614A. Set Bit0 to Bit3 in the editing area. Thereafter, the dedicated controller 611A ends the external output conversion process. According to such external output conversion processing, external output data corresponding to the external output command related to the external signals 1 to 4 and corresponding to the external signals 1 to 4 in a monotonous output state is efficiently generated Be done.

[External output ON conversion process]
FIG. 81 shows external output ON conversion processing by the external output communication LSI. As shown in FIG. 81, the dedicated controller 611A of the external output communication LSI 610A is the external output ON chain command and whether the medal out output flag is ON or not for the received command related to the external output ON. It discriminates (S841).

  In S841, in the case of the external output ON chain command and the medal out in progress flag is ON, the dedicated controller 611A proceeds to S847 described later. On the other hand, if it is not the external output ON chain command or the medal out output flag is not ON, the dedicated controller 611A acquires the values of Bit0 to Bit3 from the setting data stored in the setting data storage area of the cache memory 614A. The values of Bit0 to Bit3 of the setting data are set to Bit0 to Bit3 of the output editing area provided in the cache memory 614A (S842). Bit0 to Bit3 of the setting data indicates that any of the external signals 1 to 4 is on, and the dedicated controller 611A identifies the Bit set to be on among Bit0 to Bit3 of the setting data. There is.

  Next, the dedicated controller 611A determines whether the time setting value is set in the upper bits of the setting data (S843). In S843, when the time setting value is not set in the setting data, the dedicated controller 611A discards the setting data relating to the external output ON as invalid, and ends the external output ON conversion processing.

  In S843, when the time setting value is set in the setting data, the dedicated controller 611A sets a value obtained by multiplying the time setting value by 10 as a timer counter value of the software timer (3) (S844). The timer counter value corresponds to the predetermined time when the external signal set to ON among the external signals 1 to 4 is externally output as the ON state for a predetermined time.

  Next, the dedicated controller 611A sets measurement (1) as a value indicating the state of the software timer (3) (S845). After that, the dedicated controller 611A acquires the values of Bit0 to Bit3 of the output state area, and only the value of the corresponding Bit set to ON by Bit0 to Bit3 of the setting data is regarded as the OFF state value (0) and turns on the external output. After measurement, it is stored in the return area (S846). Thereafter, the dedicated controller 611A ends the external output ON conversion process. According to this process, prior to the transmission of the external output data corresponding to the external output ON command, each state of the external signals 1 to 4 to be restored after a predetermined time set by the command is stored.

  In S847, the dedicated controller 611A sets the chain flag on. Next, the dedicated controller 611A determines whether the time setting value is set in the upper bits of the setting data (S848). In S848, when the time setting value is not set in the setting data, the dedicated controller 611A sets the values of Bit0 to Bit3 of the setting data to Bit0 to Bit3 of the chain area provided in the cache memory 614A (S853), End external output ON conversion processing.

  In S848, when the time setting value is set in the setting data, the dedicated controller 611A sets a value obtained by multiplying the time setting value by 10 as a timer counter value of the software timer (3) (S849). The timer counter value corresponds to the predetermined time when the external signal set to ON among the external signals 1 to 4 is externally output as the ON state for a predetermined time after the external output of the medal out signal.

  Next, the dedicated controller 611A sets reservation (2) as a value indicating the state of the software timer (3) (S850). Thereafter, the dedicated controller 611A sets the values of Bit0 to Bit3 of the setting data to Bit0 to Bit3 of the external output ON area provided in the cache memory 614A (S851).

  Then, the dedicated controller 611A acquires the values of Bit0 to Bit3 of the output state area, and sets only the value of the corresponding Bit set to ON by Bit0 to Bit3 of the setting data as the value of the OFF state (0). After measurement, it is stored in the return area (S852). Thereafter, the dedicated controller 611A ends the external output ON conversion process. According to this process, prior to the transmission of the external output data corresponding to the external output ON chain command, each state of the external signals 1 to 4 to be restored after a predetermined time set by the command is stored.

[External output OFF conversion process]
FIG. 82 shows external output OFF conversion processing by the external output communication LSI. As shown in FIG. 82, the dedicated controller 611A of the external output communication LSI 610A determines whether or not the medal output in progress flag is on for the external output OFF chain command and for the received command related to the external output OFF. It discriminates (S861).

  If it is the external output OFF chain command and the medal out output flag is on in S861, the dedicated controller 611A proceeds to S867 described later. On the other hand, when it is not the external output OFF chain command or the medal out output flag is not on, the dedicated controller 611A acquires the values of Bit0 to Bit3 from the setting data stored in the setting data storage area of the cache memory 614A. Only the value of Bit set to OFF in Bit0 to Bit3 of the setting data is set to Bit0 to Bit3 of the output editing area provided in the cache memory 614A as the OFF state value (0) (S862). Bit 0 to Bit 3 of the setting data indicates that any of the external signals 1 to 4 is set to off, and the dedicated controller 611A identifies the Bit set to be off among Bit 0 to Bit 3 of the setting data. There is.

  Next, the dedicated controller 611A determines whether the time setting value is set in the upper bits of the setting data (S863). In S863, when the time setting value is not set in the setting data, the dedicated controller 611A discards the setting data relating to the external output OFF as invalid, and ends the external output OFF conversion processing.

  If the time setting value is set in the setting data in S863, the dedicated controller 611A sets a value obtained by multiplying the time setting value by 10 as a timer counter value of the software timer (4) (S864). The timer counter value corresponds to the predetermined time when the external signal set to OFF among the external signals 1 to 4 is externally output as the OFF state (0) for a predetermined time.

  Next, the dedicated controller 611A sets measurement (1) as a value indicating the state of the software timer (4) (S865). After that, the dedicated controller 611A acquires the values of Bit0 to Bit3 of the output state area, and only the value of the corresponding Bit set to Off by Bit0 to Bit3 of the setting data is regarded as the ON state value (1), and the external output is OFF. After measurement, it is stored in the return area (S866). Thereafter, the dedicated controller 611A ends the external output OFF conversion process. According to this process, prior to transmission of the external output data corresponding to the external output OFF command, each state of the external signals 1 to 4 to be restored after a predetermined time set by the command is stored.

  At S867, the dedicated controller 611A sets the chain flag on. Next, the dedicated controller 611A determines whether the time setting value is set in the upper bits of the setting data (S868). In S868, when the time setting value is not set in the setting data, the dedicated controller 611A sets the value of Bit set to OFF in Bit 0 to Bit 3 of the setting data as the OFF state value (0) to the cache memory 614A. It sets to Bit0-Bit3 of the provided chain area (S873), and complete | finishes external output OFF conversion processing.

  In S868, when the time setting value is set in the setting data, the dedicated controller 611A sets a value obtained by multiplying the time setting value by 10 as a timer counter value of the software timer (4) (S869). The timer counter value corresponds to the predetermined time when the external signal of the external signals 1 to 4 is turned off is externally outputted as the off state for a predetermined time after the external output of the medal out signal.

  Next, the dedicated controller 611A sets reservation (2) as a value indicating the state of the software timer (4) (S870). Thereafter, the dedicated controller 611A sets only the value of Bit set to OFF in Setting data Bit0 to Bit3 as the OFF state value (0) to Bit0 to Bit3 of the external output OFF area provided in the cache memory 614A. (S871).

  Then, the dedicated controller 611A acquires the values of Bit0 to Bit3 of the output state area, and outputs only the value of the corresponding Bit set to Off by Bit0 to Bit3 of the setting data as the value of the on state (1). After measurement, it is stored in the return area (S872). Thereafter, the dedicated controller 611A ends the external output OFF conversion process. According to this process, prior to the transmission of the external output data corresponding to the external output OFF chain command, each state of the external signals 1 to 4 to be restored after the elapse of the predetermined time set by the command is stored.

[Security output conversion process]
FIG. 83 shows security output conversion processing by the external output communication LSI. As shown in FIG. 83, the dedicated controller 611A of the external output communication LSI 610A sets the value of Bit 0, which is the least significant bit of the received setting data, to Bit 4 of the output editing area (S881). In Bit 0 of the setting data, a value (0 or 1) indicating that there is security information to be externally output is set.

  Next, the dedicated controller 611A determines whether the time setting value is set in the upper bits of the setting data (S882). In S 882, when the time setting value is not set in the setting data, the dedicated controller 611 A ends the security output conversion process as it is. In this case, data for external output relating to the security signal S2 to be output to the outside simply and continuously is generated.

  In S882, when the time setting value is set in the setting data, the dedicated controller 611A sets a value obtained by multiplying the time setting value by 10 as a timer counter value of the software timer (5) (S883). The timer counter value corresponds to the predetermined time when the security signal S1 is externally output for a predetermined time.

  Next, the dedicated controller 611A sets measurement (1) as a value indicating the state of the software timer (5) (S884).

  Next, the dedicated controller 611A restores the post-security measurement area of the logically inverted value of Bit 0 of the setting data, that is, the value of the state to be restored after a predetermined time has elapsed (“0” when Bit 0 of the setting data is “1”). (S885). Thereafter, the dedicated controller 611A ends the security output conversion process. According to such security output conversion processing, data for external output corresponding to the security command and efficiently corresponding to the security signals S1 and S2 are generated.

[Output control processing]
FIG. 84 shows output control processing by the external output communication LSI. As shown in FIG. 84, the dedicated controller 611A of the external output communication LSI 610A performs medal in output control processing (see FIG. 85), medal out output control processing (see FIG. 86), setting output control processing (see FIG. 87), time The recovery output control process (see FIG. 88) is sequentially executed (S901 to S904). These processes will be described later.

  Thereafter, the dedicated controller 611A determines whether the output editing area and the output state area have the same content (S905). In S905, when the output editing area and the output state area have the same content, the dedicated controller 611A ends the output control process. On the other hand, when the output editing area and the output state area have different contents, the dedicated controller 611A overwrites and saves the contents of the output editing area in the output state area (S906).

  Next, the dedicated controller 611A transmits data (data for external output) indicated by the values of Bit 0 to Bit 7 in the output state area to the external terminal board control LSI 910, and ends the output control process. According to this output control process, external output data according to the command to be externally output is efficiently transmitted from the external output communication LSI 610A to the external terminal board control LSI 910.

[Medal-in output control processing]
FIG. 85 shows a token-in output control process by the external output communication LSI. As shown in FIG. 85, the dedicated controller 611A of the external output communication LSI 610A determines whether the state of the software timer (1) is end (-1) or not (S921).

  In S921, if the state of the software timer (1) is not over (-1), that is, if the state of the software timer (1) is in any of stop (0), measurement (1), or reservation (2), The dedicated controller 611A ends the medal in output control process. On the other hand, when the state of the software timer (1) is ended (-1), the dedicated controller 611A determines whether Bit 6 of the output editing area is in the on state (1) (S922).

  In S922, when Bit 6 of the output editing area is not in the on state but in the off state (0), the dedicated controller 611A proceeds to S926 described later. On the other hand, when Bit 6 of the output editing area is in the on state (1), the dedicated controller 611A sets Bit 6 of the output editing area to the off state (0) (S923).

  Next, the dedicated controller 611A sets 10 as the timer counter value of the software timer (1) (S924). The timer counter value corresponds to the pulse width when the medal in signal is output to the outside.

  Next, the dedicated controller 611A sets measurement (1) as a value indicating the state of the software timer (1) (S925). Thereafter, the dedicated controller 611A ends the medal in output control process.

  In S926, the dedicated controller 611A subtracts one from the value of the medal in counter. Next, the dedicated controller 611A determines whether the value of the medal in counter is 0 (S927).

  If the value of the medal in counter is 0 in S927, the dedicated controller 611A proceeds to S931 described later. On the other hand, if the value of the medal in counter is not 0, the dedicated controller 611A sets Bit 6 of the output editing area to the on state (1) (S928).

  Next, the dedicated controller 611A sets 10 as the timer counter value of the software timer (1) (S929). Thereafter, the dedicated controller 611A sets measurement (1) as a value indicating the state of the software timer (1) (S930). Thereafter, the dedicated controller 611A ends the medal in output control process.

  In S931, the dedicated controller 611A sets stop (0) as a value indicating the state of the software timer (1). Thereafter, the dedicated controller 611A ends the medal in output control process. According to such medal in output control processing, the output state image of the medal in signal which becomes the on state (1) / off state (0) every 50 ms and which has the pulse number corresponding to the number of inserted medals is output as data for external output Created in the editing area.

[Medal out output control processing]
FIG. 86 shows medal out output control processing by the external output communication LSI. As shown in FIG. 86, the dedicated controller 611A of the external output communication LSI 610A determines whether the state of the software timer (2) is end (-1) or not (S941).

  In S941, if the state of the software timer (2) is not over (-1), that is, if the state of the software timer (2) is in any of stop (0), measurement (1), or reservation (2), The dedicated controller 611A ends the medal out output control process. On the other hand, when the state of the software timer (2) is ended (-1), the dedicated controller 611A determines whether Bit 5 of the output editing area is in the on state (1) (S942).

  In S942, if Bit 5 of the output editing area is not ON but OFF (0), the dedicated controller 611A proceeds to S946 described later. On the other hand, when Bit 5 of the output editing area is in the on state (1), the dedicated controller 611A sets Bit 5 of the output editing area to the off state (0) (S943).

  Next, the dedicated controller 611A sets 10 as the timer counter value of the software timer (2) (S944). The timer counter value corresponds to the pulse width when the medal out signal is output to the outside.

  Next, the dedicated controller 611A sets measurement (1) as a value indicating the state of the software timer (2) (S945). Thereafter, the dedicated controller 611A ends the medal out output control process.

  In S946, the dedicated controller 611A subtracts one from the value of the medal out counter. Next, the dedicated controller 611A determines whether the value of the medal out counter is 0 (S947).

  In S947, when the value of the medal out counter is 0, the dedicated controller 611A proceeds to S951 described later. On the other hand, if the value of the medal out counter is not 0, the dedicated controller 611A sets Bit 5 of the output editing area to the on state (1) (S948).

  Next, the dedicated controller 611A sets 10 as the timer counter value of the software timer (2) (S949). Thereafter, the dedicated controller 611A sets measurement (1) as a value indicating the state of the software timer (2) (S950). Thereafter, the dedicated controller 611A ends the medal out output control process.

  At S951, the dedicated controller 611A sets stop (0) as a value indicating the state of the software timer (2). Thereafter, the dedicated controller 611A sets the medal out output flag to off (S952), and ends the medal out output control process. According to such medal out output control processing, the output state image of the medal out signal which becomes the on state (1) / off state (0) every 50 ms and which has the pulse number corresponding to the number of medals paid out is data for external output Is created in the output editing area as

[Setting output control process]
FIG. 87 shows setting output control processing by the external output communication LSI. As shown in FIG. 87, the dedicated controller 611A of the external output communication LSI 610A determines whether the chain flag is on and the medal out output flag is off (S961).

  In S961, if the chain flag is not on or the medal out output flag is not off, the dedicated controller 611A ends the setting output control process. On the other hand, when the chain flag is on and the medal out output flag is off, the dedicated controller 611A sets the chain flag to off (S962).

  Next, the dedicated controller 611A determines whether reservation (2) is set as a value indicating the state of the software timer (3) or the software timer (4) (S963).

  If the states of the software timer (3) and the software timer (4) are not set to reservation (2) in S963, the dedicated controller 611A proceeds to S970 described later. On the other hand, when either the software timer (3) or the software timer (4) is set to reservation (2), the dedicated controller 611A sets the state of the software timer (3) to reservation (2). It is determined whether or not (S964).

  If the state of the software timer (3) is not set to reservation (2) at S964, the dedicated controller 611A proceeds to S967 described later. On the other hand, when the state of the software timer (3) is set to reservation (2), the dedicated controller 611A newly sets the state of the software timer (3) currently in the reservation state as measurement (1) S965).

  Next, the dedicated controller 611A sets the values of Bit0 to Bit3 of the external output ON area to Bit0 to Bit3 of the output editing area (S966). Thereafter, the dedicated controller 611A ends the setting output control process.

  At S967, the dedicated controller 611A determines whether the state of the software timer (4) is set to reservation (2).

  In S967, when the state of the software timer (4) is not set to reservation (2), the dedicated controller 611A ends the setting output control process. On the other hand, when the state of the software timer (4) is set to reservation (2), the dedicated controller 611A newly sets the state of the software timer (4) currently in the reservation state as measurement (1) S968).

  Next, the dedicated controller 611A sets the values of Bit0 to Bit3 of the external output OFF area in Bit0 to Bit3 of the output editing area (S969). Thereafter, the dedicated controller 611A ends the setting output control process.

  In S970, the dedicated controller 611A sets the values of Bit0 to Bit3 of the chain area to Bit0 to Bit3 of the output editing area. Thereafter, the dedicated controller 611A ends the setting output control process. According to such setting output control processing, the output state image of the external signals 1 to 4 relating to the external output ON chain command or the external output OFF chain command to be externally output after the medal out signal is output as the external output data Created in the editing area.

[Time return output control process]
FIG. 88 shows a time recovery output control process by the external output communication LSI. As shown in FIG. 88, the dedicated controller 611A of the external output communication LSI 610A determines whether or not the state of the software timer (3) is end (-1) (S981).

  If the state of the software timer (3) is not ended (-1) in S981, the dedicated controller 611A proceeds to S984 described later. On the other hand, when the state of the software timer (3) is ended (-1), the dedicated controller 611A sets the values of Bit0 to Bit3 of the recovery area after external output ON measurement to Bit0 to Bit3 of the output editing area (S982) .

  Next, the dedicated controller 611A sets stop (0) as the state of the software timer (3) (S983). Thereafter, the dedicated controller 611A ends the time recovery output control process.

  In S984, the dedicated controller 611A determines whether the state of the software timer (4) is over (−1).

  If the state of the software timer (4) is not ended (-1) in S984, the dedicated controller 611A proceeds to S987 described later. On the other hand, when the state of the software timer (4) is ended (-1), the dedicated controller 611A sets the values of Bit0 to Bit3 of the recovery area after external output OFF measurement to Bit0 to Bit3 of the output editing area (S985) .

  Next, the dedicated controller 611A sets stop (0) as the state of the software timer (4) (S986). Thereafter, the dedicated controller 611A ends the time recovery output control process.

  In S987, the dedicated controller 611A determines whether the state of the software timer (5) is over (−1).

  If the state of the software timer (5) is not ended (-1) in S987, the dedicated controller 611A ends the time recovery output control process. On the other hand, when the state of the software timer (5) is ended (-1), the dedicated controller 611A sets the value of Bit 4 of the return area after security measurement to Bit 4 of the output editing area (S988).

  Next, the dedicated controller 611A sets stop (0) as the state of the software timer (5) (S989). Thereafter, the dedicated controller 611A ends the time recovery output control process. According to such time return output control processing, after the output of the external output ON command, the external output ON chain command, or the external signals 1 to 4 related to the external output OFF command or the external output OFF chain command, or the security signal S1. An output state image is created in the output editing area as data for external output.

[Main control sequence (external terminal board control LSI)]
FIG. 89 shows a main control sequence by the external terminal board control LSI. As shown in FIG. 89, the dedicated controller 911 of the external terminal board control LSI 910 performs the same initial setting processing as the external output communication LSI 610A, that is, the same as the main substrate communication LSI 610 (S1001). According to this initial setting process, various setting information related to the external output is set based on the predetermined communication specification with the main substrate 6A.

  Next, the dedicated controller 911 determines whether the data (data for external output) received by the reception interrupt process described later with reference to FIG. 90 and the output area have the same content (S1002). The output area is a working area provided in the cache memory 913, and is an area of 1 byte composed of a bit string similar to the output state area etc. The output state is set.

  In S1002, when the received data (data for external output) and the output area have the same contents, the dedicated controller 911 repeatedly executes the process of S1002 until they are recognized as different contents. On the other hand, if the received data (data for external output) and the output area have different contents, the dedicated controller 911 sets the received data in the output area (S1003).

  Then, the dedicated controller 911 outputs the data of the output area through the GPIO interface 924 (S1004). Thereafter, the dedicated controller 911 returns to S1002. According to such a main control sequence of the external terminal board control LSI 910, the external output data transmitted from the external output communication LSI 610A is output as it is, and signals (medal in signals, medal out) corresponding to various commands are output. The signal, the external signals 1 to 4 and the security signal can be externally output to the hall computer 1000 at an appropriate output timing while being a parallel signal in an appropriate output state. The signal output to the outside is input by the hall computer 1000, and the hall computer 1000 analyzes the gaming state and the security state based on the input signal.

[Receive interrupt processing (external terminal board control LSI)]
FIG. 90 shows reception interrupt processing by the external terminal board control LSI. As shown in FIG. 90, the dedicated controller 911 of the external terminal board control LSI 910 receives the external output data transmitted from the external output communication LSI 610A, and acquires the external output data as received data (S1021).

  Next, the dedicated controller 911 determines whether there is a physical layer error in the received data (data for external output) (S1022).

  If it is determined in S1022 that there is no physical layer error in the received data, the dedicated controller 911 temporarily stores the received data in the reception buffer area of the cache memory 913 (S1023), and ends this reception interrupt process. On the other hand, when it is determined that there is a physical layer error in the received data, the dedicated controller 911 ends the reception interrupt process without performing any error process. As described above, in the present embodiment, received data determined to have a physical layer error is discarded, but may be stored together with information indicating that a physical layer error is present. .

  As described above, according to the pachi slot 1 of the present embodiment, the following effects can be obtained.

  In the pachislot 1 of the present embodiment, whether the main CPU 601 transmits a command including time information or a command not including time information to the external output communication LSI 610A, does the external output communication LSI 610A include time information in the command? If time information is included, a predetermined time is measured based on the time information, and during measurement of the predetermined time, external output data corresponding to the general-purpose input / output system is sent to the external terminal board control LSI 910. Will be sent. On the other hand, when time information is not included in the command, external output data corresponding to the command in the general-purpose input / output method is transmitted to the external terminal board control LSI 910.

  As a result, when the time information is included in the command, the external terminal board control LSI 910 externally outputs the external signals 1 to 4 and the security signal according to the external output data in the general-purpose input / output method for a predetermined time. When the time information is not included, the external signals 1 to 4 and the security signal according to the data for external output in the general-purpose input / output system are rapidly output to the outside without being subject to time constraints. As a result, the main CPU 601 only needs to transmit a command conforming to the serial communication method, and it is not necessary to determine whether or not to measure time upon transmission, and it is not necessary to measure time itself. The program capacity can be reduced without scaling, and thus the design load in constructing a communication system can be reduced.

  Further, in the pachi slot 1 of the present embodiment, a command is transmitted from the main CPU 601 to the external output communication LSI 610A, and external output data is transmitted from the external output communication LSI 610A to the external terminal board control LSI 910. At this time, the external output data is encrypted according to the common key encryption system by the AES circuit 614A, and further modulated according to the binary phase shift keying modulation system with the second Manchester circuit 619A and then transmitted.

  Then, in the external terminal board control LSI 910, the external output data received from the external output communication LSI 610A is demodulated by the second Manchester circuit 919 by the binary phase shift keying modulation method, and the external output data further demodulated is AES After being decrypted by the common key encryption method in the circuit 914, a parallel signal based on the external output data is externally output.

  Thereby, according to the pachislot 1 of the present embodiment, it is possible to correctly and stably transmit and receive external output data by the binary phase shift keying system. In addition, when data for external output is transmitted / received between the external output communication LSI 610A and the external terminal board control LSI 910 by binary phase shift keying, the clock rate can be embedded in the data. Can also transmit and receive data efficiently.

  Further, in the pachislot 1 of the present embodiment, the external output communication LSI 610A simply transmits the external output OFF command including the OFF time information and the command related to the external output OFF chain command to the external output communication LSI 610A. A predetermined time is measured based on the OFF time information, and during the predetermined time measurement, external output data instructing an external output OFF state corresponding to the general-purpose input / output system is transmitted to the external terminal board control LSI 910.

  As a result, the external terminal board control LSI 910 turns off one of the external signals 1 to 4 corresponding to the external output data related to the external output OFF command or the external output OFF chain command in the general-purpose input / output mode over a predetermined time. Output. Thereafter, when the clocking of the predetermined time is completed, external output data instructing the state recovery of the external output corresponding to the general-purpose input / output system is transmitted to the external terminal board control LSI 910. As a result, the external terminal board control LSI 910 externally outputs the external signals 1 to 4 restored to the original state by the general purpose input / output method after a predetermined time has elapsed.

  Also in this case, the main CPU 601 only needs to transmit a command conforming to the serial communication method, and there is no need to measure time in the transmission, so that the load due to the communication processing of the main CPU 601 can be reduced.

  Further, in the pachislot 1 of the present embodiment, the main CPU 601 transmits a command related to the medal out command, and for example, immediately after that, the external output chain command, the external output ON chain command, and the command related to the external output OFF chain command are externally output It is also possible to transmit to the communication LSI 610A.

  In this case, after the external output communication LSI 610A generates external output data corresponding to the general-purpose input / output method according to the command related to the medal out command, the external output chain command, the external output ON chain command, and the external output OFF chain command Data for external output corresponding to the general-purpose input / output method according to the command related to.

  As a result, after the external output data corresponding to the medal out command is transmitted to the external terminal board control LSI 910, the external output data corresponding to the external output chain command, the external output ON chain command, and the external output OFF chain command The external terminal board control LSI 910 is transmitted. As a result, after the external terminal board control LSI 910 externally outputs the medal out signal in the general-purpose input / output method, the external output chain command, the external output ON chain command, and the external signal 1-4 corresponding to the external output OFF chain command are externally output. It will be output.

  Therefore, the main CPU 601 can also transmit commands relating to the external output chain command, the external output ON chain command, and the external output OFF chain command immediately after transmitting the command related to the medal out command according to the serial communication method. The medal out signal and the external signals 1 to 4 according to the respective commands can be outputted in order to the outside, and the processing load of the hall computer 1000 to which the signal is inputted can be alleviated.

  Further, in the pachislot 1 of the present embodiment, when the main CPU 601 transmits the command related to the medal out command and the command related to the external output OFF chain command to the external output communication LSI 610A, the external output communication LSI 610A generates the medal out command. After data for external output to the effect that a medal out signal corresponding to the general purpose input / output method according to the command should be externally output is generated, and designated according to the general purpose input / output method according to the external output OFF chain command While generating off-designated external output data for instructing the off state of the external signals 1 to 4, it generates on-designed external output data for instructing the on state of the external signals 1 to 4.

  Then, when the external output data relating to the medal out signal is transmitted to the external terminal board control LSI 910, the external terminal board control LSI 910 externally outputs the medal out signal by a general-purpose input / output method. Thereafter, the external output communication LSI 610A measures a predetermined time based on the setting data included in the external output OFF chain command, and during the predetermined time, the external output data designated for OFF corresponding to the general-purpose input / output system Transmit to external terminal board control LSI 910.

  As a result, the external terminal board control LSI 910 externally outputs the external signals 1 to 4 designated to be off in the general-purpose input / output method for a predetermined time as the off state. Then, when the clocking of the predetermined time is completed, the external output data that is turned on corresponding to the general purpose input / output method is transmitted to the external terminal board control LSI 910. As a result, the external terminal board control LSI 910 externally outputs the external signals 1 to 4 designated to be on after the elapse of a predetermined time as the on state.

  As a result, the main CPU 601 immediately transmits the command related to the medal out command and the external output OFF chain command according to the serial communication method, and the external signals 1 to 4 specified next to the medal out signal also take a predetermined time. The external signals are externally output in the off state, and the same external signals 1 to 4 are externally output as the on state after a delay, and therefore the load due to the communication processing of the main CPU 601 can be reduced.

  Further, in the pachislot 1 of the present embodiment, the external output ON command, the external output ON chain command, and the command related to the security command, which include setting data specifying the time setting value of the main CPU 601 in the on state, Send to LSI 610A.

  In this case, the external output communication LSI 610A measures a predetermined time based on such a time setting value, and during the predetermined time, the external output ON instructs the external output ON state according to the general-purpose input / output method. A command, an external output ON chain command, and data for external output corresponding to a security command are transmitted to the external terminal board control LSI 910.

  As a result, the external terminal board control LSI 910 externally outputs the external signals 1 to 4 and the security signal according to the external output data specified to be ON in the general-purpose input / output method over a predetermined time. On the other hand, when the clocking of the predetermined time is started or the clocking of the predetermined time is finished, the external output data instructing the state maintenance or the state return of the external output corresponding to the general purpose input / output method is transmitted to the external terminal board control LSI 910 Ru. As a result, the external terminal board control LSI 910 externally outputs the external signals 1 to 4 and the security signal as the original output state in the general-purpose input / output method before or after the start of counting of the predetermined time. As a result, the main CPU 601 only needs to transmit a command conforming to the serial communication method, and there is no need to measure time at the time of the transmission, so the load due to the communication processing of the main CPU 601 can be reduced.

  Further, in the present embodiment, various commands are transmitted from the main CPU 601 to the main substrate communication LSI 610 as the fixed data length 8 bytes, and the commands are included as the larger fixed data length 16 bytes from the main substrate communication LSI 610 to the sub substrate communication LSI 710. External communication data is transmitted, and further, internal communication data including a command as a variable data length of 17 to 33 bytes is transmitted from sub substrate communication LSI 710 to sub CPU 701.

  Thereby, the sub CPU 701 can receive internal communication data including not only commands but also information on other communication errors. That is, since the sub CPU 701 receives internal communication data whose reception data size is larger than that in the case where only the command is received from the main CPU 601, the reception waiting time can be prevented from being generated unnecessarily. A bottleneck in communication to the sub CPU 701 can be eliminated.

  Further, since the internal communication data received by the sub CPU 701 includes various information related to the communication error as the information other than the command, the sub CPU 701 may execute the processing related thereto based on the information of the communication error. Can be operated efficiently.

  Also, while the main board communication LSI 610 and the sub board communication LSI 710 can detect and receive commands and communication data in small increments for each 1 byte transmission unit, for example, the sub CPU 701 is limited to such transmission units. Instead, communication data can be received while being collectively detected for each larger amount of data, for example, 16 bytes, which is larger, for example, 16 bytes. Thereby, the main board communication LSI 610 and the sub board communication LSI 710 can periodically transmit and receive data efficiently, and the sub CPU 701 can efficiently receive communication data as a certain amount of data.

  In the present embodiment, a command is transmitted from the main CPU 601 to the main board communication LSI 610 at a communication speed of 19200 bps (first communication speed), and a faster communication speed of 115200 bps to the sub board communication LSI 710 from the main board communication LSI 610. Communication data including a command is transmitted at the second communication speed. Further, communication data including a command is transmitted from the sub substrate communication LSI 710 to the sub CPU 701 at a communication speed of 115,200 bps (second communication speed).

  At this time, in the main board communication LSI 610, the reception waiting time (first reception waiting time) for detecting the command every 1 byte serving as a predetermined transmission unit is calculated to be 2.5 msec based on the first communication speed. It is received by detecting a command for every predetermined transmission unit based on the calculated 1st reception waiting time (2.5 msec). On the other hand, in the sub board communication LSI 710, the reception waiting time (second reception waiting time) for detecting communication data including a command for each 1 byte serving as a predetermined transmission unit is approximately 0. 0 based on the second communication speed. It is received by detecting communication data for each predetermined transmission unit based on the calculated second reception waiting time (about 0.4 msec) calculated as 4 msec.

  That is, based on the first communication speed at which the main board communication LSI 610 receives a command based on the communication specification according to the relatively low specification main CPU 601 and the communication specification according to the relatively high specification sub CPU 701. Even if the second communication speed at which the secondary substrate communication LSI 710 receives communication data is set at a speed different from each other, the first reception waiting time (2.5 msec) and the second reception suitable for each communication speed Latency (about 0.4 msec) can be used.

  As a result, in the sub CPU 701 which receives the communication data at the end, it is possible to eliminate the occurrence of a dead time related to the reception waiting time as much as possible when receiving the communication data, and solve the communication bottleneck. The CPU 701 can be operated efficiently.

  Further, since the second reception waiting time (about 0.4 msec) in the sub board communication LSI 710 before the communication data reaches the sub CPU 701 is shorter than the first reception waiting time (2.5 msec) in the main board communication LSI 610, Accordingly, the process of receiving communication data in the sub CPU 701 can be reduced.

  Further, according to the present embodiment, it is optimal for the pachislot 1 having the main CPU 601 whose communication speed is relatively low at a low speed and the sub CPU 701 whose communication speed is relatively high at a high speed. A communication system can be realized.

  Further, in the present embodiment, a command is transmitted from the main CPU 601 to the main substrate communication LSI 610, and communication data including a command is transmitted from the main substrate communication LSI 610 to the sub substrate communication LSI 710, and further from the sub substrate communication LSI 710 to the sub CPU 701. Communication data including a command is transmitted.

  At that time, when the main board communication LSI 610 detects a size shortage or a physical layer error (first communication error) upon receiving a command, the main board communication LSI 610 commands the data size indicating them and the main board communication LSI reception status (first error information). In the communication data together with the corresponding packet data. In addition, when the sub board communication LSI 710 detects a logic error (second communication error) including a physical layer error or a size shortage upon reception of communication data from the main board communication LSI 610, the sub board communication LSI reception status or the The sub-board communication LSI packet type (second error information) is included in the communication data together with the command (packet data) and the first error information and transmitted.

  Furthermore, when the sub CPU 701 detects an error (third communication error) related to the occurrence of a CRC error or timeout upon reception of communication data, the 'COM3 ERR1', 'COM3 ERR2' (third error information) as error information indicating them Register). Further, the sub CPU 701 registers 'COM1 ERR1', 'COM1 ERR2' (first error information) as error information related to the main substrate communication LSI 610 based on the communication data received from the sub substrate communication LSI 710, and the sub substrate communication LSI 710 Register 'COM2 ERR1', 'COM2 ERR2', 'COM2 ERR3' (second error information) as error information related to.

  As a result, the sub CPU 701 distinguishes and registers 'COM1 ERR1', 'COM1 ERR2', 'COM2 ERR1', 'COM2 ERR2', 'COM2 ERR3', 'COM3 ERR1', 'COM3 ERR2', which are registered as communication errors. Based on the communication error cause and location can be identified and analyzed in detail.

  In addition, the secondary substrate communication LSI 710 includes commands and the like as binary data in communication data, and also controls characters such as STX indicating start of transmission of the binary data and DLE indicating control data in the binary data into communication data. After being included, the communication data is transmitted to the sub CPU 701. That is, commands are transmitted and received between the sub substrate communication LSI 710 and the sub CPU 701 as binary data whose data size is relatively smaller than text data requiring code conversion.

  As a result, the sub CPU 701 can receive binary data of a relatively small size based on control characters such as STX and DLE, and determine whether or not a predetermined amount of data has been acquired. Therefore, the reception waiting time can be prevented from occurring as much as possible, and data communication can be efficiently performed between the sub substrate communication LSI 710 and the sub CPU 701. In the present embodiment, binary characters and control characters are included in the communication data and transmitted between the sub substrate communication LSI 710 and the sub CPU 701, for example, between the main substrate communication LSI 610 and the sub substrate communication LSI 710. The control character may be included in the communication data and transmitted together with the binary data.

  Further, in the present embodiment, a command is transmitted from the main CPU 601 to the main board communication LSI 610, and communication data including a command from the main board communication LSI 610 to the sub board communication LSI 710 is encrypted by the AES encryption method, and further It is transmitted after being modulated by the modulation scheme. The sub substrate communication LSI 710 demodulates the communication data received from the main substrate communication LSI 610 according to the Manchester modulation method, and further demodulates the communication data that has been demodulated according to the AES encryption method, and then transmits the communication data to the sub CPU 701. Thus, in the present embodiment, communication data can be correctly and stably transmitted and received by the Manchester modulation method.

  Further, since the clock rate can be embedded in communication data exchanged by Manchester modulation, there is no need to separately provide a device or the like for generating a clock signal between the main substrate 6A and the sub substrate 7A. Thus, the transmission medium related to communication can be easily simplified as the optical fiber cable 100.

  Further, communication data can be transmitted and received as it is through the optical fiber cable 100 without optically generating a clock signal between the main substrate 6A and the sub-substrate 7A, and an inexpensive Manchester circuit can be used as a digital data modulation circuit. Also from the point of use, the main substrate 6A and the sub substrate 7A can be connected by inexpensive devices and transmission paths.

  Another embodiment of the present invention may be configured as shown in FIGS. In the following description, constituent elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals, and descriptions thereof will be omitted.

  FIG. 91 shows a connection between the main substrate and the sub substrate of a game machine according to another embodiment of the present invention. As shown in FIG. 91, in the present embodiment, the third Manchester circuits 620 and 720 are used in combination with the first SPIs 617 and 717, and are configured to be able to transmit and receive data through the first SPIs 617 and 717. Further, in the present embodiment, the third Manchester circuit 620 and the third Manchester circuit 720 are electrically connected to each other via a communication cable.

  In the main substrate 6A of the present embodiment, data (packet data) including a command from the main CPU 601 is supplied from the first UART 601A to the first UART 615, and after detection of physical layer error etc. is performed by the first UART 615, AES It is configured to be encrypted by the circuit 614 and further supplied to the third Manchester circuit 620 through the first SPI 617 as a master, and to be modulated by the third Manchester circuit 620. The data thus modulated is converted to serial data including a command, and is transmitted to the sub-substrate 7A through the communication cable.

  In the sub-substrate 7A, serial data including a command transmitted from the main substrate 6A is supplied to the third Manchester circuit 720 through the communication cable, and after being demodulated by the third Manchester circuit 720, the first SPI 717 which becomes a slave The sub CPU 701 can receive a command from the main CPU 601 by being supplied to the AES circuit 714 through the above and then being decoded by the AES circuit 714 and then supplied to the UART 701 A through the first UART 715.

  FIG. 92 shows a connection form of the main substrate and the sub substrate of a game machine according to another embodiment of the present invention. FIG. 93 is an explanatory drawing showing the flow of data in the connection configuration shown in FIG. In this embodiment, as shown in FIG. 92, Manchester modulation and demodulation are not performed. Specifically, the second UARTs 616 and 716 are not used in combination with a Manchester circuit or the like, and are configured to be able to transmit and receive data independently.

  In the main substrate 6A of the present embodiment, data (packet data) including a command from the main CPU 601 is supplied from the first UART 601A to the first UART 615, and after detection of physical layer error etc. is performed by the first UART 615, AES The data is encrypted by the circuit 614 and transmitted to the sub-substrate 7A through the second UART 616 as serial data including a command.

  In the sub-substrate 7A, serial data including a command transmitted from the main substrate 6A is supplied to the AES circuit 714 through the sixth UART 716, and after being decoded in the AES circuit 714, is supplied to the UART 701A through the first UART 715. Thus, the sub CPU 701 can receive a command from the main CPU 601.

  Further, as shown in FIG. 93, the data transmitted from the main CPU 601 to the main board communication LSI 610 is packet data consisting of plaintext of 8 bytes, and the communication speed (baud rate) at that time is 19200 bps. The data transmitted from the main substrate communication LSI 610 to the sub substrate communication LSI 710 is encrypted 16 byte data, and the communication speed at that time is set to 115,200 bps. The data transmitted from the sub substrate communication LSI 710 to the sub CPU 701 is 16 bytes of plaintext data that has been AES decrypted, and the communication speed at that time is set to 115,200 bps.

  FIG. 94 shows a connection form of a main substrate and a sub substrate of a game machine according to another embodiment of the present invention. FIG. 95 is an explanatory drawing showing the flow of data in the connection configuration shown in FIG. In this embodiment, as shown in FIG. 94, AES encryption and decryption are not performed. Specifically, in the main substrate communication LSI 610 and the sub substrate communication LSI 710, the fourth Manchester circuits 621 and 721 are mainly used, and the fourth Manchester circuits 621 and 721 are configured to be able to transmit and receive data independently. ing.

  In the main substrate 6A of the present embodiment, data (packet data) including a command from the main CPU 601 is supplied from the first UART 601A to the fourth Manchester circuit 621 and transmitted from the fourth Manchester circuit 621 directly to the sub substrate 7A. Be done.

  In the sub-substrate 7A, data including a command transmitted from the main substrate 6A is directly taken in through the fourth Manchester circuit 721 and supplied from the fourth Manchester circuit 721 to the UART 701A, whereby the sub CPU 701 operates as the main CPU 601. It is possible to receive commands from.

  Further, as shown in FIG. 95, the data transmitted from the main CPU 601 to the main board communication LSI 610 is packet data consisting of plaintext of 8 bytes, and the communication speed (baud rate) at that time is 19200 bps. The data transmitted from the main substrate communication LSI 610 to the sub substrate communication LSI 710 is Manchester-modulated 8-byte plaintext data, and the communication speed at that time is 19200 bps. The data transmitted from the sub substrate communication LSI 710 to the sub CPU 701 is Manchester-demodulated 8-byte plaintext data, and the communication speed at that time is 19200 bps.

  In the embodiment shown in FIGS. 94 and 95, a command is transmitted from the main CPU 601 to the main board communication LSI 610, and communication data including the command is modulated by the Manchester modulation method from the main board communication LSI 610 to the sub board communication LSI 710. Sent directly on. The sub board communication LSI 710 demodulates the communication data received from the main board communication LSI 610 according to the Manchester modulation method, and then transmits the communication data to the sub CPU 701 as it is. In such a configuration, communication data can be correctly and stably transmitted / received while modulating and demodulating data promptly by Manchester modulation.

  FIG. 96 is a perspective view showing the appearance of a game machine (pachinko) according to another embodiment of the present invention. FIG. 97 is a block diagram showing a configuration of a main control circuit and a sub control circuit of the gaming machine shown in FIG. The present invention is also applicable to pachinko 1 'as shown in FIG. As shown in FIG. 97, the pachinko 1 ′ is a special component display device 80, a normal symbol display device 81, a special symbol hold display device 82, and a normal symbol hold display device as unique components connected to the main control circuit 60. 83, count sensor 84, general winning ball sensor 85, passing ball sensor 86, start winning ball sensor 87, ordinary electric role solenoid 88, large winning hole solenoid 89, backup clear switch 90, payout / launch control circuit 350, payout device 34A, a launcher 35B, a card unit 34C, a lending operation unit 34D, and the like. Also in such a pachinko 1 ', the liquid crystal display device 10, the speakers 48 and 49, the lamp 20, and the like are connected to the sub control circuit 70. The main control circuit 60 and the sub control circuit 70 are provided with a main substrate communication LSI 610 and a sub substrate communication LSI 710, and the main substrate communication LSI 610 and the sub substrate communication LSI 710 mutually correspond to each other as in the embodiment described above. It is connected. Further, the main substrate on which the main control circuit 60 is formed is directly connected to the external concentrated terminal plate 9A as in the embodiment described above.

  The present invention is not limited to the above-described embodiments.

  The values relating to the communication speed, the reception waiting time as a timeout value, the transmission unit, etc. exemplified in each embodiment are merely given as an example, and these values correspond to the specifications of the CPU and the specifications of the communication LSI. It can be changed as appropriate.

  The communication means is not limited to the communication LSI, but may be, for example, an IC according to the scale of the integrated circuit.

  The communication means is not limited to communication between the main control circuit and the sub control circuit, and may be provided, for example, as performing communication between the hall computer and the sub control circuit.

  In the embodiment described above, the external output communication LSI 610A converts the received data from the main CPU 601 and outputs it to the external terminal board control LSI 910, but the external output communication LSI converts the received data from the main CPU Alternatively, the signal may be transmitted to the external terminal board control LSI, and various processing corresponding to the command may be performed by the external terminal board control LSI to output a signal to the hall computer.

  In the above-described embodiment, each process of the external output communication LSI 610A and the external terminal board control LSI 910 has been described with reference to FIGS. 73 to 90. However, the present invention is not limited to such each process, and may be output to the hall computer. Processing for outputting signals as shown in FIGS. 13 to 21 may be performed.

1 Pachislo (game machine)
1 'Pachinko (game machine)
6A Main control board (main board)
7A Sub control board (sub board)
9A external concentrated terminal board (external output means)
60 Main control circuit (main control processing means)
70 Sub control circuit (sub control processing means)
100 optical fiber cable 600 microcomputer 601 main CPU (main control processing means)
610 Main board communication LSI (main control output means)
610A Communication LSI for external output (external output unit, first communication unit)
611A dedicated controller (clocking means, output state indication information generating means, continuous output information generating means, information output means)
614A AES circuit (encryption means)
615A 1st UART
616A 2nd UART (information output means)
618A 1st Manchester circuit 619A 2nd Manchester circuit (modulation means)
620A 3rd Manchester circuit 621A 4th Manchester circuit 624A GPIO interface 701 sub CPU
910 External terminal board control LSI (external output means, second communication means)
911 Dedicated controller (information input means, signal output means)
914 AES circuit (decryption means)
915 1st UART
916 Second UART (information input means)
918 First Manchester circuit 919 Second Manchester circuit (demodulation means)
920 3rd Manchester circuit 921 4th Manchester circuit 924 GPIO interface (signal output means)
940 Relay (external output means, output means)
1000 Hall computer (external device)

Claims (1)

A control unit that performs various controls related to the game;
And external output means for outputting external output information from the control unit to an external device outside the gaming machine,
The control unit
Control processing means for performing control processing related to gaming;
The external output information is input from the control processing means at a first communication speed, and the external output information is output at a second communication speed higher than the first communication speed according to the output destination. Communication means, and
The external output means is
A second communication unit that receives the external output information from the first communication unit and outputs the external output information;
And output means for inputting the external output information from the second communication means and outputting the external output information converted into a relay output signal to the external device.
The control processing means
As the external output information, it is possible to output first external output information indicating payout of gaming media, and includes delay time information indicating that external output should be performed after a predetermined time has elapsed subsequent to the first external output information. While being able to output second external output information, it is also possible to output third external output information that is externally output at a timing different from that of the first external output information,
The first communication means is
The external output information input from the control processing means is distinguished into command information indicating the type of command and setting data indicating a parameter accompanying the command information, and the type of the command is determined by referring to the command information And output information generating means for executing processing according to the type of the command,
The output information generation means
First information generating means for generating first output information suitable for converting the external output information based on the first external output information, when the external output information is the first external output information; ,
A second information generation unit that generates second output information suitable for converting the external output information based on the second external output information when the external output information is the second external output information; ,
Third information generation means for generating third output information suitable for converting the external output information based on the third external output information, when the external output information is the third external output information; ,
It has an information output unit that outputs the first output information, the second output information, and the third output information to the second communication unit as an operable function.
The second communication means is
An information input unit that receives the first output information, the second output information, and the third output information output from the information output unit, and stores the output information in a storage area ;
When the first output information, the second output information, and the third output information input by the information input unit are different from the information of the storage area, the output unit may output the information to the output unit. A game machine characterized by having, as an operable function, signal output means for converting into a relay output signal and outputting the signal to the external device through the output means.

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