JP6524673B2 - Circuit device, physical quantity detection device, electronic device and moving body - Google Patents

Description

  The present invention relates to a circuit device, a physical quantity detection device, an electronic device, a movable body, and the like.

  Conventionally, there has been known a circuit device which performs digital signal processing such as digital filter processing by the DSP unit on A / D conversion of an input signal by an A / D conversion circuit and digital signal obtained by A / D conversion. ing. Patent Document 1 discloses an example of such a circuit device.

JP, 2005-1757751, A

  In a circuit device having such an A / D conversion circuit and a DSP unit, an anti-aliasing filter is provided on the front side of the A / D conversion circuit. By providing such a filter for anti-aliasing, aliasing noise due to the sampling operation can be removed.

  However, it has been found that in the input signal of the A / D conversion circuit, an unnecessary signal that can not be sufficiently removed by a filter for anti-aliasing may be mixed. Conventionally, no method has been proposed for achieving adequate A / D conversion by sufficiently reducing such a large unnecessary signal.

  According to some aspects of the present invention, the filter section provided on the front side of the A / D conversion circuit is effectively used to sufficiently reduce unnecessary signals mixed in the input signal of the A / D conversion circuit. It is possible to provide a circuit device that can be used, a physical quantity detection device, an electronic device, a movable body, and the like.

  The present invention has been made to solve at least a part of the above-mentioned problems, and can be realized as the following modes or embodiments.

  According to one aspect of the present invention, an A / D conversion circuit that A / D converts an input signal, a filter unit provided on the front side of the A / D conversion circuit, and a digital signal from the A / D conversion circuit A digital signal processing unit having a digital filter unit that performs digital filter processing, and the cut-off frequency fcd of the digital filter unit is a first digital filter cut-off frequency fcd1, the cut-off of the filter unit The off frequency fca is set to the first filter cut-off frequency fca1, and the cut-off frequency fcd of the digital filter section is the second digital filter cut-off frequency fcd2 lower than the first digital filter cut-off frequency fcd1. If there is a cutoff frequency fc of the filter section But related to the circuit device to be set to the first filter cut-off frequency lower than fca1 second filter cut-off frequency Fca2.

  According to one aspect of the present invention, in a circuit device including a filter unit, an A / D conversion circuit, and a digital signal processing unit, when the cutoff frequency fcd of the digital filter unit of the digital signal processing unit is fcd1, the filter The cutoff frequency fca of the unit is set to fca1. When the cutoff frequency fcd is fcd2 lower than fcd1, the cutoff frequency fca is set to fca2 lower than fca1. In this way, when the cutoff frequency of the digital filter section is lowered, for example, from fcd = fcd1 to fcd = fcd2, the cutoff frequency of the filter section is also from fca = fca1 to fca = fca2. It gets lower. Thus, the attenuation characteristic of the filter section whose cutoff frequency is set to a low frequency such as fca = fca2 is used to sufficiently attenuate the amplitude of the unnecessary signal mixed in the input signal of the A / D conversion circuit. It becomes possible. Therefore, it is possible to sufficiently reduce the unnecessary signal mixed in the input signal of the A / D conversion circuit by effectively utilizing the filter section provided on the front side of the A / D conversion circuit.

  In one aspect of the present invention, the control unit further includes a storage unit that stores an adjustment value of the cutoff frequency fca of the filter unit, and the adjustment value of the cutoff frequency fca is the cutoff frequency fcd of the digital filter unit. When it is the first digital filter cutoff frequency fcd1, the cutoff frequency fca of the filter unit is set to the first filter cutoff frequency fca1, and the cutoff frequency fcd of the digital filter unit is the above The second filter cut-off in which the cut-off frequency fca of the filter section is lower than the first filter cut-off frequency fca1 when the second digital filter cut-off frequency fcd2 is satisfied and fcd2 <fcd1 is satisfied Set to frequency fca2 It may be an adjustment value.

  In this way, when the cutoff frequency of the digital filter section is fcd = fcd1 using the adjustment value stored in the storage section, the cutoff frequency of the filter section is set to fca = fca1, fcd When = fcd2, fca = fca2 can be set.

  In one aspect of the present invention, the storage unit may be a non-volatile memory.

  In this way, for example, when the cutoff frequency of the digital filter unit is fcd = fcd1 by reading the adjustment value stored in the storage unit when, for example, the power is turned on, the cutoff frequency of the filter unit is set. When fca = fca1 and fcd = fcd2, fca = fca2 can be set.

  In one aspect of the present invention, the sampling frequency of the sampling operation of the A / D conversion circuit is fsm, the gain of the filter unit is Ga, and the amplitude of the unnecessary signal mixed in the input signal of the filter unit is VNF. When the resolution of the A / D conversion circuit is n bits and the conversion voltage range of the A / D conversion circuit is VFSR, the gain Ga of the filter unit is configured to sample the amplitude VNF of the unnecessary signal. The frequency fsm may be set to a gain that attenuates to a value smaller than a predetermined value determined by the resolution n bits and the conversion voltage range VFSR.

  In this way, it is possible to sufficiently attenuate the amplitude of the unwanted signal mixed in the input signal of the A / D conversion circuit to a value smaller than a predetermined value.

  In one aspect of the present invention, the cutoff frequency fcd for band limitation of the digital filter unit can be set in a range of fcd1 ≧ fcd ≧ fcd2, and the cutoff frequency fca of the filter unit is fca1 ≧. When the cut-off frequency fca of the filter unit is set to the first filter cut-off frequency fca1 when setting can be made in the range of fca ≧ fca2, and the cut-off frequency fca is the second filter In both cases where the cutoff frequency fca2 is set, the gain Ga of the filter unit is set to a gain that attenuates the amplitude VNF of the unnecessary signal to a value smaller than the predetermined value at the sampling frequency fsm. May be

  In this way, even if the cut-off frequency of the filter section is set to fca = fca1 or fca = fca2, the amplitude of the unnecessary signal mixed in the input signal of the A / D conversion circuit is It becomes possible to attenuate sufficiently.

  In one aspect of the present invention, when the cut-off frequency fcd for band limitation of the digital filter unit is changed, the cut-off frequency fca of the filter unit is interlocked with the change of the cut-off frequency fcd. May be changed.

  In this way, when the cut-off frequency fcd for band limitation of the digital filter unit is changed, the cut-off frequency fca of the filter unit can also be automatically changed in conjunction with this. Therefore, it is possible to effectively suppress the occurrence of a defect or the like caused by the inappropriate setting of the cutoff frequency.

  In one aspect of the present invention, there is provided a drive circuit for driving the physical quantity transducer in response to a feedback signal from the physical quantity transducer, and a clock signal generation circuit having an oscillation circuit and generating a clock signal by the oscillation circuit. And a detection circuit having the A / D conversion circuit and the digital signal processing unit, and a detection signal from the physical quantity transducer being input, wherein the A / D conversion circuit is based on the clock signal. The sampling operation of the input signal may be performed based on the generated sampling clock signal.

  In this way, it is possible to supply the sampling clock signal based on the clock signal generated by the clock signal generation circuit to the A / D conversion circuit to perform the sampling operation of the input signal. Then, for example, even when the problem of the interference frequency occurs because the sampling frequency component and the drive frequency component coincide with each other, the attenuation characteristic of the filter unit is effectively used for the amplitude of the unnecessary signal that is the cause of the interference frequency. It is possible to attenuate sufficiently.

  In one aspect of the present invention, the digital signal processing unit may operate based on an operation clock signal generated based on the clock signal.

  In this way, it is possible to supply an operation clock signal based on the clock signal generated by the clock signal generation circuit to the digital signal processing unit to perform various digital signal processing. Then, even when the problem of the interference frequency occurs due to the processing of the digital signal processing unit, the amplitude of the unnecessary signal corresponding to the interference frequency is sufficiently attenuated by effectively utilizing the attenuation characteristic of the filter unit. Becomes possible.

  Another aspect of the present invention relates to a physical quantity detection device including the circuit device described above and the physical quantity transducer.

  Another aspect of the present invention relates to an electronic device including the circuit device described in any of the above.

  Another aspect of the present invention relates to a mobile including the circuit device described in any of the above.

The structural example of the circuit apparatus of this embodiment. FIG. 2A and FIG. 2B are explanatory diagrams of unnecessary signals mixed in the input signal of the A / D conversion circuit. An example of a concrete structure of the circuit apparatus of this embodiment. FIGS. 4 (A) and 4 (B) are explanatory diagrams of the unnecessary signal caused by the interference frequency due to the sampling frequency component. 5 (A) and 5 (B) are explanatory views of the configuration of the filter unit and the setting of the cutoff frequency in the filter unit. 6 (A) and 6 (B) are explanatory diagrams of frequency characteristics of the filter unit. FIGS. 7A and 7B are explanatory diagrams of a method of setting a cutoff frequency according to the embodiment. Explanatory drawing about the structure of a digital filter part, a transfer function, etc. FIG. 7 shows a configuration example of a clock signal generation circuit. 6 shows a configuration example of a circuit device, an electronic device, and a gyro sensor (physical quantity detection device) according to the present embodiment. The detailed structural example of the circuit apparatus of this embodiment. Explanatory drawing of operation | movement of the detection circuit by the signal for operation | movement based on a clock signal. Explanatory drawing about interference frequency. Explanatory drawing of the method of setting an oscillation frequency to the frequency which avoided the interference frequency. The structural example of the circuit apparatus in the case of a multi-axis gyro sensor. Explanatory drawing about the interference frequency in the case of a multi-axis gyro sensor. The detailed structural example of a detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS The conceptual diagram which shows roughly the structure of the motor vehicle as an example of a mobile body.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are essential as the solution means of the present invention. Not necessarily.

1. Circuit Device FIG. 1 shows a basic configuration example of the circuit device of the present embodiment. The circuit device of the present embodiment includes a filter unit 90, an A / D conversion circuit 100, and a DSP (Digital Signal Processing) unit 110. The storage unit 130 can also be included. Note that the circuit device of the present embodiment is not limited to the configuration of FIG. 1, and various modifications may be made such as omitting some of the components or adding other components.

  The A / D conversion circuit 100 A / D converts the input signal ADI. Specifically, the sampling operation of the input signal ADI is performed based on the sampling clock signal of the sampling frequency fsm. Then, A / D conversion of the sampled signal is performed, and a digital signal ADQ (digital data) after A / D conversion is output.

  The filter unit 90 (analog filter unit) is provided on the front side of the A / D conversion circuit 100. The filter unit 90 generally functions as a filter for anti-aliasing of the A / D conversion circuit 100. That is, it functions as a filter for removing aliasing noise generated by the sampling operation (sampling) of the A / D conversion circuit 100. The filter unit 90 is, for example, a passive filter including passive elements such as a resistor and a capacitor, and has, for example, frequency characteristics of a low pass filter. The filter unit 90 may be provided at least on the front side of the A / D conversion circuit 100. For example, another circuit may be interposed between the filter unit 90 and the A / D conversion circuit 100.

  The DSP unit 110 (digital signal processing unit) performs digital signal processing on the digital signal ADQ from the A / D conversion circuit 100. Specifically, the DSP unit 110 has a digital filter unit 112, and the digital filter unit 112 performs digital filter processing on the digital signal ADQ from the A / D conversion circuit 100. For example, digital filter processing such as low pass filter processing is performed. Specifically, the digital filter unit 112 performs low-pass filter processing or the like for band limitation in accordance with the application.

  The storage unit 130 stores various types of information. For example, the storage unit 130 stores setting information of filter characteristics such as a cutoff frequency of the filter unit 90. Alternatively, the storage unit 130 may store setting information of filter characteristics such as a cutoff frequency of the digital filter unit 112. For example, the storage unit 130 can be configured by a non-volatile memory. As a non-volatile memory, for example, an EPROM, an EEPROM, or a flash memory can be used. As the EPROM, for example, OTP (one-time PROM) can be used, and as the OTP, for example, MONOS (Metal-Oxide-Nitride-Oxide-Silicon) can be used. A storage device other than the non-volatile memory (for example, a storage device using a fuse) may be adopted as the storage unit 130.

  Here, the cutoff frequency of the filter unit 90 is fca, and the cutoff frequency of the digital filter unit 112 is fcd.

  In this case, in the present embodiment, as shown in FIG. 1, when the cutoff frequency fcd of the digital filter unit 112 is the first digital filter cutoff frequency fcd1, the cutoff frequency fca of the filter unit 90 is , And the first filter cutoff frequency fca1.

  On the other hand, when the cut-off frequency fcd of the digital filter unit 112 is the second digital filter cut-off frequency fcd2 lower than the first digital filter cut-off frequency fcd1, the cut-off frequency fca of the filter unit 90 is The second filter cutoff frequency fca2 is set to be lower than the first filter cutoff frequency fca1.

  That is, when the cutoff frequency of the digital filter unit 112 is fcd = fcd1, the cutoff frequency of the filter unit 90 is set to fca = fca1. On the other hand, when the cut-off frequency of the digital filter unit 112 is set to a low frequency such as fcd = fcd2 (<fcd1), the cut-off frequency of the filter unit 90 is also set to a low frequency such as fca = fca2 (<fca1) It is set. That is, when the cut-off frequency fcd of the digital filter unit 112 is set low, the cut-off frequency fca of the filter unit 90 is set low accordingly. Similarly, when the cutoff frequency fcd of the digital filter unit 112 is set high, the cutoff frequency fca of the filter unit 90 is also set high in conjunction with it.

  The storage unit 130 also stores the adjustment value of the cutoff frequency fca of the filter unit 90. That is, the cutoff frequency fca of the filter unit 90 is set based on the adjustment value read from the storage unit 130.

  Specifically, the adjustment value of the cutoff frequency fca is an adjustment value for setting the cutoff frequency of the filter unit 90 to fca = fca1 when the cutoff frequency of the digital filter unit 112 is fcd = fcd1. . Further, when the cutoff frequency of the digital filter unit 112 is fcd = fcd2 <fcd1, it is an adjustment value for setting the cutoff frequency of the filter unit 90 to fca = fca2 <fca1. As an adjustment value of such a cutoff frequency fca, for example, an adjustment value of resistance value of a resistor R in FIG. 5B described later (on / off setting information of switch element) or the like can be used.

The sampling frequency of the sampling operation of the A / D conversion circuit 100 is fsm, the gain of the filter unit 90 is Ga, and the amplitude (maximum value of the amplitude) of the unnecessary signal mixed in the input signal VIN of the filter unit 90 is VNF. I assume. Further, it is assumed that the resolution of the A / D conversion circuit 100 is n bits, and the conversion voltage range of the A / D conversion circuit 100 is VFSR. VFSR is a voltage range (power supply voltage range) to be subjected to A / D conversion. In this case, as shown in equation (1) of FIG. 7A described later, the gain Ga of the filter unit 90 has an amplitude VNF of the unnecessary signal at a sampling frequency fsm with a resolution of n bits and a conversion voltage range VFSR. It is set to a gain that attenuates to a value smaller than a predetermined value (α × VFSR / 2 ⁿ⁻¹ ) to be determined.

  By doing this, it is possible to sufficiently attenuate the amplitude of the unnecessary signal mixed in the input signal ADI of the A / D conversion circuit 100 to a value smaller than a predetermined value. For example, the amplitude of the unwanted signal can be attenuated to the level of the noise floor of the A / D conversion circuit 100 or a level close to the noise floor, and deterioration in detection performance due to the mixing of the unwanted signal can be reduced.

  Also, the cutoff frequency fcd for band limitation of the digital filter unit 112 can be set in the range of fcd1 ≧ fcd ≧ fcd2, and the cutoff frequency fca of the filter unit 90 can be set in the range of fca1 ≧ fca ≧ fca2 Suppose that there was. That is, it is assumed that the cutoff frequency fcd for band limitation can be set from the outside by register access or the like, and the settable range is fcd1 ≧ fcd ≧ fcd2. Then, it is assumed that the cutoff frequency fca of the filter unit 90 can be set in the range of fca1 ≧ fca ≧ fca2 correspondingly.

In this case, both when the cut-off frequency of the filter unit 90 is set to fca = fca1 and when it is set to fca = fca2, the gain Ga of the filter unit 90 is the sampling frequency fsm of the amplitude VNF of the unwanted signal. Is set to a gain that attenuates to a value smaller than a predetermined value (α × VFSR / 2 ⁿ⁻¹ ). In this way, even if the cutoff frequency of the filter unit 90 that can be set in the range of fca1 ≧ fca ≧ fca2 is set to fca = fca1, or even if fca = fca2, the A / D is set. It becomes possible to sufficiently attenuate the amplitude of the unwanted signal mixed in the input signal ADI of the conversion circuit 100.

  Further, in the present embodiment, when the cutoff frequency fcd for band limitation of the digital filter unit 112 is changed, the cutoff frequency fca of the filter unit 90 is also changed in conjunction with the change of the cutoff frequency fcd. Is desirable. For example, it is assumed that the cutoff frequency fcd for band limitation of the digital filter unit 112 is changed due to access to the control register of the circuit device by an external controller or the like. In this case, in conjunction with the change of the cutoff frequency fcd, for example, the cutoff frequency fca of the filter unit 90 is also automatically changed. For example, it is assumed that the cutoff frequency of the digital filter unit 112 is changed from fcd = fcd1 to fcd = fcd2 by the access to the control register described above. In this case, the cutoff frequency of the filter unit 90 is also automatically changed from fca = fca1 to fca = fca2. In this way, for example, even when the cutoff frequency fcd for band limitation of the digital filter unit 112 is changed according to the application, the cutoff frequency fca of the filter unit 90 is also changed to an appropriate frequency according to the change. As a result, problems such as unexpected filter characteristics can be suppressed.

  FIGS. 2A and 2B are explanatory diagrams of the unnecessary signal (noise) mixed in the input signal ADI of the A / D conversion circuit 100. FIG.

  In A1 of FIG. 2A, the unnecessary signal of the amplitude VNF is mixed with the input signal VIN of the filter unit 90. Although the amplitude of the unnecessary signal is attenuated due to the low-pass filter characteristic of the filter unit 90, the unnecessary signal is left mixed with the input signal ADI of the A / D conversion circuit 100 as shown in A2. . That is, an unnecessary signal having an amplitude VNA (VNA <VNF) is mixed in the input signal ADI of the A / D conversion circuit 100. Then, when the A / D conversion circuit 100 samples the input signal ADI mixed with unnecessary signals with the sampling clock signal of the sampling frequency fsm and performs A / D conversion, the output of the DSP unit 110 as shown by A3. Problems such as fluctuation (variation) of the data DFQ occur.

  In particular, when the frequency difference Δf between the frequency component of the unnecessary signal shown in A2 and the sampling frequency fsm of the A / D conversion circuit 100 is small, aliasing noise to the signal band due to the sampling of the A / D conversion circuit 100 occurs. The problem of the fluctuation of the output data DFQ shown in A3 becomes remarkable.

  For example, the digital filter unit 112 of the DSP unit 110 performs low pass filter processing for limiting a signal band (frequency band of a desired signal). Then, if the frequency difference Δf between the frequency component of the unnecessary signal (for example, a drive frequency component to be described later) and the sampling frequency fsm is sufficiently larger than the cutoff frequency fcd of the low pass filter of the signal band limitation, , The aliasing noise can be sufficiently attenuated. However, when the frequency difference Δf is smaller than the frequency of the signal band, aliasing noise appears in the signal band, and a problem of fluctuation (variation) of the output data DFQ as shown in A3 occurs. For example, a phenomenon that the output data DFQ shakes at a frequency corresponding to the frequency difference Δf occurs.

  Then, as shown by A4 and A5 in FIG. 2B, as the amplitude VNA of unnecessary noise mixed in the input signal ADI of the A / D conversion circuit 100 increases, the amplitude of the oscillation appearing in the output data DFQ also increases. . Therefore, it is desirable that the amplitude VNA of unwanted noise mixed in the input signal ADI can be attenuated as much as possible.

  FIG. 3 shows an example of a specific configuration of the circuit device. In FIG. 3, the circuit device includes a drive circuit 30, a detection circuit 60, a storage unit 130, and a clock signal generation circuit 150. The circuit device and the physical quantity transducer 18 constitute a physical quantity detection device (sensor device).

  The drive circuit 30 receives the feedback signal DI from the physical quantity transducer 18 and drives the physical quantity transducer 18. For example, the drive circuit 30 receives a feedback signal DI from the physical quantity transducer 18 and outputs a rectangular wave or sine wave drive signal DQ to the physical quantity transducer 18. As a result, the physical quantity transducer 18 is driven at a constant drive frequency fdr, and vibrates at a frequency corresponding to the drive frequency fdr, for example.

  The clock signal generation circuit 150 has an oscillation circuit 190, and the oscillation circuit 190 generates a clock signal. That is, the clock signal is generated by the oscillation operation of the oscillation circuit 190. As the oscillator circuit 190, a CR oscillator circuit that oscillates using a resistor and a capacitor can be used.

  A detection signal from the physical quantity transducer 18 is input to the detection circuit 60. The detection circuit 60 performs detection processing of the physical quantity (desired signal) based on the detection signal from the physical quantity transducer 18. The detection circuit 60 also has a circuit operated by an operation signal based on the clock signal generated by the clock signal generation circuit 150. In FIG. 3, an A / D conversion circuit 100 and a DSP unit 110 are provided in the detection circuit 60 as circuits that operate according to an operation signal based on a clock signal.

  The operation signal based on the clock signal may be a signal obtained by dividing the clock signal, or may be a signal having the same frequency as the clock signal (clock signal itself or a signal obtained by buffering the clock signal). .

  For example, in FIG. 3, the operation signal based on the clock signal is a sampling clock signal of the A / D conversion circuit 100 or an operation clock signal of the DSP unit 110. The sampling clock signal and the operation clock signal are signals obtained by dividing the clock signal.

  For example, the A / D conversion circuit 100 performs a sampling operation of the input signal ADI to be A / D conversion target by the sampling clock signal (operation signal) generated based on the clock signal. Then, A / D conversion of the sampled signal is performed based on the sampling clock signal. The DSP unit 110 also performs digital signal processing on the digital signal ADQ from the A / D conversion circuit 100 based on an operation clock signal (operation signal) generated based on the clock signal. For example, digital filter processing (such as low-pass filter processing) is performed as digital signal processing. Alternatively, various digital correction processes are performed.

  For example, in FIG. 4A, the oscillation frequency of the oscillation circuit 190 is fos. In this case, a sampling clock signal obtained by dividing a clock signal of the oscillation frequency fos by, for example, i1 is supplied to the A / D conversion circuit 100, and the A / D conversion circuit 100 performs a sampling operation. The sampling frequency of this sampling clock signal can be expressed as fsm = fos / i1. Also, an operation clock signal obtained by dividing a clock signal of the oscillation frequency fos by, for example, i 2 is supplied to the DSP unit 110, and the DSP unit 110 performs digital signal processing. Then, the DSP unit 110 outputs the output data DFQ at a frequency of fs2 = fos / i3, for example.

  Then, when the A / D conversion circuit 100 performs the sampling operation at the sampling frequency fsm as described above, an unnecessary signal having a frequency component of, for example, fsm + Δf1 is an A / D conversion circuit as shown in FIG. When mixed with the 100 input signal ADI, the problem of the fluctuation of the output data DFQ as shown at A3 in FIG. 2A occurs. For example, a fluctuation of Δf1 appears in the output data DFQ. The same applies to harmonic components (2 × fsm, 3 × fsm) of the sampling frequency fsm.

  Then, when the drive circuit 30 drives the physical quantity transducer 18 at the drive frequency fdr as shown in FIG. 3, as will be described in detail later, the drive frequency component which is a harmonic component or a fundamental wave component of the drive frequency fdr A situation occurs in which the sensor circuit 60 gets around to the detection circuit 60 side. Then, when the unnecessary signal of the drive frequency component is mixed into the input signal ADI of the A / D conversion circuit 100 and the A / D conversion circuit 100 performs the sampling operation of the input signal ADI at the sampling frequency fsm, FIG. The problem of fluctuation of the output data DFQ shown in A3 of FIG. Specifically, aliasing noise corresponding to a frequency difference between the drive frequency component j × fdr and the sampling frequency component k × fsm (j, k is an integer of 1 or more) appears in the signal band of the desired signal. As a result, the problem of the fluctuation of the output data DFQ occurs.

  In this embodiment, in order to suppress the occurrence of such fluctuation of the output data DFQ, a method of effectively utilizing the filter unit 90 originally provided for anti-aliasing of the A / D conversion circuit 100 is adopted. That is, the low-pass filter characteristic of the filter unit 90 sufficiently attenuates the amplitude of the unnecessary signal shown at A2 in FIG. That is, as shown by A4 and A5 in FIG. 2B, if the amplitude VNA of the unnecessary signal mixed in the input signal ADI of the A / D conversion circuit 100 is sufficiently attenuated by the low pass filter characteristic of the filter unit 90, The amplitude of the fluctuation of the output data DFQ can also be reduced.

  For example, FIG. 5A shows a configuration example of the filter unit 90. As shown in FIG. In FIG. 5A, the filter unit 90 is a first-order low-pass filter (passive filter) composed of a resistor R and a capacitor C. FIG. 5A shows an expression of the gain Ga and the cutoff frequency fca of the low pass filter. A second or higher order low pass filter may be adopted as the filter unit 90.

  More specifically, as shown in FIG. 5 (B), the resistance R of the low pass filter is a variable resistance. That is, the resistor R is configured by resistance elements RM1, RM2, RM3, and RM4 connected in series, and switch elements SM1, SM2, SM3, and SM4 for variably adjusting the resistance value. Switch element SM1 is provided between a connection node of resistance elements RM1 and RM2 and input node NVI of signal VIN. Switch element SM2 is provided between a connection node of resistance elements RM2 and RM3 and input node NVI. Similarly, switch element SM3 is provided between a connection node of resistance elements RM3 and RM4 and input node NVI, and switch element SM4 is provided between a node at the other end of resistance element RM4 and input node NVI. .

  For example, when only SM1 of the switch elements SM1 to SM4 is turned on, the resistance value of the resistor R becomes the resistance value of RM1. When only the switch element SM2 is turned on, the resistance value of the resistor R becomes the resistance value of RM1 + RM2. In this manner, the on / off control of the switch elements SM1 to SM4 changes the resistance value of the resistor R. By changing the resistance value of the resistor R in this manner, as is apparent from the formulas of the cutoff frequency fca and the gain Ga in FIG. 5A, the cutoff frequency and gain characteristics of the low-pass filter of the filter unit 90 can be obtained. Frequency characteristics can be changed.

  One example is shown in FIGS. 6 (A) and 6 (B). For example, by changing the resistance value of the resistor R, a low pass filter of the filter unit 90 having cutoff frequencies fca = 22 Hz, 110 Hz, 220 Hz, and 440 Hz is realized.

  Here, in A1 of FIG. 2A, it is assumed that an unnecessary signal of a sampling frequency component (for example, fsm = 200 KHz, actually fsm + Δf1) is mixed with the input signal VIN of the filter unit 90.

  In this case, as shown by B1, B2, B3 and B4 in FIG. 6A, the attenuation characteristics of the filter unit 90 whose cutoff frequency is set to fca = 22 Hz, 110 Hz, 220 Hz and 440 Hz makes unnecessary signals Amplitude can be attenuated.

  Specifically, as shown in FIG. 6B, when the cut-off frequency of the filter unit 90 which is a first-order lowpass filter is set to fca = 22 Hz (B1 in FIG. 6A) The gain at the sampling frequency component (fsm) is Ga = −79 dB. Therefore, assuming that an unnecessary signal having an amplitude VNF of 100 mV is mixed with the signal VIN, the amplitude VNA of the unnecessary signal in the signal ADI becomes 0.01 mV as shown in FIG. The amplitude of the signal is sufficiently attenuated such that VNA <VNF.

  When the cut-off frequency of the filter unit 90 is set to fca = 110 Hz (B2), the gain at the sampling frequency component is Ga = −64 dB, and the amplitude VNA of the unwanted signal in the signal ADI is 0 It becomes .06mV.

  When the cutoff frequency of the filter unit 90 is set to fca = 220 Hz (B3), the gain at the sampling frequency component is Ga = −59 dB, and the amplitude VNA of the unwanted signal in the signal ADI is 0. It becomes 11mV.

  When the cutoff frequency of the filter unit 90 is set to fca = 440 Hz (B4), the gain at the sampling frequency component is Ga = −53 dB, and the amplitude VNA of the unnecessary signal in the signal ADI is 0. It becomes 22mV.

  As described above, as the cutoff frequency fca of the filter unit 90 is lower, the amplitude of the unwanted signal at the sampling frequency (fsm) can be attenuated. Therefore, in order to further attenuate the amplitude of the unnecessary signal, the cut-off frequency fca of the filter unit 90 may be set lower.

  However, if the cut-off frequency fca of the filter unit 90 is lowered, the signal is attenuated even in the signal band which is a low frequency band, for example, as indicated by C1 in FIG. 6 (A). Therefore, the amplitude of the desired signal to be passed through may be attenuated.

  On the other hand, the digital filter unit 112 of the DSP unit 110 performs low pass filter processing for band limitation in accordance with the application. For example, in the case of using a gyro sensor described later as an example, when using the gyro sensor for applications such as digital camera etc. for hand shake correction, the cutoff frequency of the band-limited low pass filter is set to fcd = 200 Hz, for example. On the other hand, when using a gyro sensor for applications, such as attitude control of a car, the cutoff frequency of the band-limited low pass filter is set to fcd = 10 Hz, for example.

  When the cutoff frequency of the band-limited low-pass filter is low, for example, fcd = 10 Hz, even if the cutoff frequency fca of the filter unit 90 is set to a low frequency, C1 in FIG. Attenuation of the signal by the filter section 90 in the signal band is not a major problem.

  That is, when the cutoff frequency of the band-limited low-pass filter is set to a low frequency such as fcd = 10 Hz, even if the cutoff frequency of the filter unit 90 is set to a low frequency such as fca = 22 Hz, As shown by C2 in FIG. 6A, the signal attenuation of the filter section 90 at a frequency of 10 Hz (0.01 KHz) is hardly present, and therefore, there is no problem.

  Therefore, in the present embodiment, when the cut-off frequency fcd of the digital filter unit 112 is low, the cut-off frequency fca in the filter unit 90 is also set to a low frequency accordingly.

  Specifically, as described in FIG. 1, in the present embodiment, when the cut-off frequency of the digital filter unit 112 is set to a high frequency such as fcd = fcd1 = 200 Hz, the cut of the filter unit 90 is performed. The off frequency is also set to a high frequency, for example, fca = fca1 = 440 Hz.

  By doing this, it is possible to prevent the occurrence of a situation where the amplitude of the desired signal to be passed through the signal band is attenuated due to the attenuation characteristic of the filter section 90 at C1 in FIG. 6 (A).

  On the other hand, when the cutoff frequency of the digital filter unit 112 is set to a low frequency such as fcd = fcd2 = 10 Hz, the cutoff frequency of the filter unit 90 is also set to a low frequency such as fca = fca2 = 22 Hz. Set

  By doing this, as shown by B1 in FIG. 6A, for the unnecessary signal of the sampling frequency component (fsm), for example, the amplitude may be attenuated with a large attenuation amount corresponding to the gain Ga = −79 dB. It will be possible. As a result, the amplitude of the fluctuation of the output data DFQ shown at A3 in FIG. 2A can be sufficiently attenuated.

  Further, even if the cut-off frequency fca of the filter unit 90 is set to a low frequency such as fca = 22 Hz as described above, the cut-off frequency of the band limitation of the digital filter unit 112 is also low such as fcd = 10 Hz. The frequency of the band is also low. Therefore, as described in C2 of FIG. 6A, the filter unit 90 does not unnecessarily attenuate the amplitude of the desired signal in the signal band.

  As described above, in the present embodiment, when the cutoff frequency fcd of the band limitation of the digital filter unit 112 changes according to the application, the cutoff frequency fca of the filter unit 90 is also changed accordingly. By doing this, the amplitude of the unnecessary signal of the sampling frequency component is sufficiently attenuated using the filter unit 112, while passing the signal band without unnecessarily attenuating the desired signal of the signal band. Becomes possible.

  FIG. 7A is a diagram for explaining in detail the method of setting the cutoff frequency according to the present embodiment. In FIG. 7A, VNF represents the amplitude of the unnecessary signal mixed in the input signal VIN of the filter unit 90, and VNA represents the amplitude of the unnecessary signal mixed in the input signal ADI of the A / D conversion circuit 100. It represents. Further, fca and fcd are cutoff frequencies in the filter unit 90 and the digital filter unit 112, respectively. fsm is a sampling frequency in the A / D conversion circuit 100, n is the number of bits representing the resolution of the A / D conversion circuit 100, and VFSR is a conversion voltage range of the A / D conversion circuit 100. Further, fb is a frequency corresponding to the upper limit of the signal band, for example, fb = 2 KHz.

  In this case, in the present embodiment, the cutoff frequency or the like is set so that the conditional expressions of Expression (1), Expression (2), and Expression (3) of FIG. 7A are satisfied.

For example, the value obtained by multiplying the gain Ga of the filter unit 90 at the sampling frequency fsm by the amplitude VNF of the unnecessary signal is smaller than α × VFSR / 2 ⁿ⁻¹ in equation (1) of FIG. 7A. It is a conditional expression. That is, the gain Ga of the filter unit 90 attenuates the amplitude VNF of the unnecessary signal to a value smaller than the predetermined value α × VFSR / 2 ⁿ⁻¹ determined by the resolution n bit and the conversion voltage range VFSR at the sampling frequency fsm. It is set to. More specifically, also when the cutoff frequency of the filter unit 90 is set to fca = fca1 or when fca = fca2, the gain Ga of the filter unit 90 is equal to the amplitude VNF of the unnecessary signal. The sampling frequency fsm is set to a gain that attenuates to a value smaller than a predetermined value α × VFSR / 2 ⁿ⁻¹ .

According to the conditional expression of this equation (1), when the unnecessary signal of the sampling frequency component is mixed, the amplitude VNA of the unnecessary signal in the input signal ADI of the A / D conversion circuit 100 has a predetermined value VFSR / 2 ⁿ It is guaranteed to be smaller than ⁻¹ × α. Here, the value of the parameter α can be determined depending on the specification of the circuit device, etc., depending on how many LSBs the fluctuation can be tolerated. Ideally, it is desirable that VFSR / 2 ^n-1 × α be equal to or less than the level of the noise floor of the A / D conversion circuit 100.

  Equation (2) in FIG. 7A is a condition that the signal is not attenuated in the signal band (fb) (the attenuation is an allowable level). The value of parameter β in equation (2) can be determined depending on how far the signal attenuation in the signal band is allowed. In D1 of FIG. 7A, β is set to 0.9. This ensures that the gain Ga of the filter unit 90 at the frequency fb of the signal band is 0.9 or more. For example, the attenuation of 0.1 is set to β = 0.9, assuming that it is within the range of error.

  Expression (3) in FIG. 7A is a conditional expression that the attenuation characteristic of the filter unit 90 is such that the passband of the desired signal of the digital filter unit 112 is not attenuated. For example, in the present embodiment, in the frequency band (fsm) indicated by D2 in FIG. 7A, the attenuation amount of the filter unit 90 is sufficiently large to attenuate the amplitude of the unnecessary signal of the sampling frequency component. In this case, in the frequency band indicated by D3 in FIG. 7A, the desired signal in the signal band is allowed to pass without being attenuated so that the influence of the attenuation of the filter section 90 hardly appears.

  FIG. 7B shows an example of specific setting values of the cutoff frequency fcd of the digital filter unit 112 and the cutoff frequency fca of the filter unit 90.

  For example, when the cut-off frequency of the digital filter unit 112 is set to fcd = 200 Hz in order to apply to applications such as camera shake correction, the cut-off frequency of the filter unit 90 is set to fcd = 440 Hz accordingly Ru. By doing this, it is possible to suppress a situation where the desired signal is attenuated by the attenuation characteristic of the filter unit 90.

  Similarly, when the cutoff frequency of the digital filter unit 112 is set to fcd = 100 Hz and 50 Hz, the cutoff frequency of the filter unit 90 is set to fcd = 220 Hz and 110 Hz, respectively.

  On the other hand, when the cut-off frequency of the digital filter unit 112 is set to fcd = 10 Hz, for example, to apply to the application of attitude control of a car, the cut-off frequency of the filter unit 90 is set to fca = 22 Hz accordingly Ru. This makes it possible to effectively use the anti-aliasing filter unit 90 to sufficiently attenuate the amplitude of the unnecessary signal of the sampling frequency component, and output data as shown in A3 of FIG. 2A. It will be possible to solve problems such as DFQ fluctuation.

  An exemplary configuration of the digital filter unit 112 is shown in FIG. The digital filter unit 112 is, for example, a second-order Butterworth filter of IIR, and its transfer function is shown by E1 in FIG. 8 and its frequency characteristic is shown by E2 in FIG. For example, the cutoff frequency fcd of the digital filter unit 112 can be changed by changing the values of the coefficients a0, a1, a2, b1 and b2 in FIG. 8 by register switching.

2. Clock Signal Generation Circuit FIG. 9 shows a configuration example of the clock signal generation circuit 150. In FIG. 9, the oscillation circuit 190 of FIG. 3 is realized by the CR oscillation circuit 170. The clock signal generation circuit 150 is not limited to the configuration shown in FIG. 9, and various modifications may be made such as omitting some of the components or adding other components.

  The voltage generation circuit 160 generates the power supply voltage VDOS and supplies it to the CR oscillation circuit 170. For example, as described later, the power supply voltage VDOS based on the work function difference is generated and supplied.

  The CR oscillation circuit 170 includes a capacitor C, a variable resistance circuit 196, a variable capacitance circuit 197, and an amplification circuit 180 (buffer circuit). The CR oscillation circuit 170 is supplied with the power supply voltage VDOS and operates to generate a clock signal CLK (oscillation signal). Specifically, the CR oscillation circuit 170 feeds back a signal to an input to generate an oscillation signal using an RC circuit configured of a capacitor and a resistor. Then, a signal obtained by shaping the generated oscillation signal is output as the clock signal CLK.

  The amplification circuit 180 (inversion amplification circuit) has inverter circuits IV0, IV1, and IV2. The output of the inverter circuit IV1 is fed back to the input node NI of the amplifier circuit 180 via the capacitor C. The output of inverter circuit IV2 is fed back to input node NI of amplification circuit 180 via variable resistance circuit 196 (R). The input of the inverter circuit IV0 becomes the input of the amplification circuit 180.

  The oscillation signal output from the inverter circuit IV2 is waveform-shaped by the inverter circuit IV3 and output as the rectangular wave clock signal CLK. For example, the oscillation signal has a waveform in which the rising edge and the falling edge are blunt. The inverter circuit IV3 shapes the oscillation signal having such a waveform into a rectangular wave whose rising edge and falling edge are steep. A divider circuit may be provided downstream of the inverter circuit IV3 to output one or more clock signals obtained by dividing the clock signal CLK.

  Thus, in FIG. 9, the oscillation circuit 190 of FIG. 3 is realized by the CR oscillation circuit 170. Then, the variable resistance circuit 196 of the CR oscillation circuit 170 functions as a first frequency adjustment unit, and the first frequency adjustment of the oscillation frequency is realized. The variable resistor circuit 196 is a resistor circuit that feeds back the signal of the amplifier circuit 180 to the input node NI of the amplifier circuit 180.

  In addition, the variable capacitance circuit 197 of the CR oscillation circuit 170 functions as a second frequency adjustment unit, and the second frequency adjustment of the oscillation frequency is realized. The variable capacitance circuit 197 is provided at the output node NQ of the amplifier circuit 180. That is, one end of the capacitance of the variable capacitance circuit 197 is connected to the output node NQ of the amplification circuit 180.

  The connection configuration of the variable resistance circuit 196 and the variable capacitance circuit 197 is not limited to that shown in FIG. 9, and various modifications can be made. For example, in FIG. 9, the output of the inverter circuit IV2 at the final stage of the amplifier circuit 180 is fed back to the input node NI of the amplifier circuit 180 via the variable resistance circuit 196. However, for example, the output of the first stage inverter circuit IV 0 of the amplifier circuit 180 may be fed back to the input node NI of the amplifier circuit 180 via the variable resistance circuit 196. Further, the connection position of the variable capacitance circuit 197 is not limited to the position shown in FIG. 9, and various modified implementations are possible as long as the connection configuration can change the capacitance value of the RC circuit.

  For example, in FIG. 9, before the physical quantity transducer 18 and the circuit device are connected, the oscillation frequency of the CR oscillation circuit 170 is adjusted by the variable resistance circuit 196 functioning as a first frequency adjustment unit. That is, the variable resistance circuit 196 is a circuit whose resistance value can be variably adjusted. By changing the resistance value of the variable resistance circuit 196, the resistance value of the RC circuit changes, and the CR oscillation circuit 170 is changed. The oscillation frequency of is adjusted.

  On the other hand, in a state in which the physical quantity transducer 18 and the circuit device are connected, the oscillation frequency of the CR oscillation circuit 170 is adjusted by the variable capacitance circuit 197 functioning as a second frequency adjustment unit. That is, the variable capacitance circuit 197 is a circuit whose capacitance value can be variably adjusted. By changing the capacitance value of the variable capacitance circuit 197, the capacitance value of the RC circuit is changed. The oscillation frequency is adjusted.

  By doing this, the first frequency adjustment (coarse adjustment) of the oscillation frequency before the physical quantity transducer 18 and the circuit device are connected, and the physical quantity transducer 18 and the circuit device are connected. It is possible to realize the second frequency adjustment (fine adjustment) of the oscillation frequency under the condition described above.

  The first frequency adjustment performed by the variable resistance circuit 196 (in a broad sense, the first frequency adjustment unit) is, for example, a rough adjustment of the oscillation frequency of the oscillation circuit 190. The second frequency adjustment performed by the variable capacitance circuit 197 (in a broad sense, a second frequency adjustment unit) is, for example, fine adjustment of the oscillation frequency. For example, the second frequency adjustment has higher adjustment resolution than the first frequency adjustment. For example, the adjustment range of the first frequency adjustment is wide, and the adjustment range of the second frequency adjustment is narrower than the adjustment range of the first frequency adjustment.

3. Detailed Configuration of Electronic Device, Gyro Sensor, Circuit Device FIG. 10 shows a circuit device 20 of the present embodiment, a gyro sensor 510 (a physical quantity detecting device in a broad sense) including the circuit device 20, an electronic device including the gyro sensor 510. 5 shows a detailed configuration example of 500.

  The circuit device 20, the electronic device 500, and the gyro sensor 510 are not limited to the configuration of FIG. 10, and various modifications may be made such as omitting some of the components or adding other components. . Further, as the electronic device 500 of the present embodiment, various devices such as a digital camera, a video camera, a smartphone, a mobile phone, a car navigation system, a robot, a game machine, a watch, a health appliance, or a portable information terminal can be assumed. In the following, the case where the physical quantity transducer is a piezoelectric vibrating reed (vibration gyro) and the sensor is a gyro sensor will be described as an example, but the present invention is not limited thereto. For example, the present invention can be applied to a vibrating gyroscope of an electrostatic capacitance detection method formed of a silicon substrate or the like, and a physical quantity transducer that detects physical quantities equivalent to angular velocity information and physical quantities other than angular velocity information.

  The electronic device 500 includes a gyro sensor 510 and a processing unit 520. In addition, a memory 530, an operation unit 540, and a display unit 550 can be included. The processing unit 520 (CPU, MPU, etc.) performs control of the gyro sensor 510 and the like and overall control of the electronic device 500. The processing unit 520 also performs processing based on angular velocity information (physical quantity in a broad sense) detected by the gyro sensor 510. For example, processing for camera shake correction, attitude control, GPS autonomous navigation, etc. is performed based on angular velocity information. The memory 530 (ROM, RAM, etc.) stores control programs and various data, and functions as a work area and a data storage area. The operation unit 540 is for the user to operate the electronic device 500, and the display unit 550 displays various information to the user.

  The gyro sensor 510 (physical quantity detection device) includes the vibrating reed 10 and the circuit device 20. The vibrating reed 10 (a physical quantity transducer in a broad sense) of FIG. 10 is a tuning fork type piezoelectric vibrating reed formed from a thin plate of a piezoelectric material such as quartz, and includes driving vibrating reeds 11 and 12 and a detecting vibrating reed 16. , 17 have. Drive terminals 2 and 4 are provided on the drive vibrating reeds 11 and 12, and detection terminals 6 and 8 are provided on the detection vibrating bars 16 and 17.

  The circuit device 20 includes a drive circuit 30, a detection circuit 60, a storage unit 130, a control unit 140, and a clock signal generation unit 150. Note that various modifications may be made such as omitting some of these components or adding other components.

  The drive circuit 30 outputs a drive signal (drive voltage) to drive the vibrating reed 10. Then, a feedback signal is received from the vibrating reed 10 to excite the vibrating reed 10. The detection circuit 60 receives a detection signal (detection current, charge) from the vibrating reed 10 driven by the drive signal, and detects a desired signal (Coriolis force signal) corresponding to the physical quantity applied to the vibrating reed 10 from the detection signal. (Extract.

  Specifically, an AC drive signal (drive voltage) from the drive circuit 30 is applied to the drive terminal 2 of the drive vibrating reed 11. Then, the drive vibrating reed 11 starts to vibrate due to the inverse piezoelectric effect, and the tuning fork vibration causes the drive vibrating reed 12 to start vibrating. At this time, a current (electric charge) generated by the piezoelectric effect of the drive vibrating reed 12 is fed back from the drive terminal 4 to the drive circuit 30 as a feedback signal. Thereby, an oscillation loop including the vibrating reed 10 is formed.

  When the drive vibrating reeds 11 and 12 vibrate, the detection vibrating reeds 16 and 17 vibrate at the vibration speed v in the direction shown in FIG. Then, current (electric charge) generated by the piezoelectric effect of the detection vibrating bars 16 and 17 is output from the detection terminals 6 and 8 as detection signals (first and second detection signals). Then, the detection circuit 60 receives the detection signal from the vibrating reed 10 and detects a desired signal (desired wave) which is a signal corresponding to the Coriolis force. That is, when the vibrating reed 10 (gyro sensor) rotates around the detection axis 19, the Coriolis force Fc is generated in the direction orthogonal to the vibration direction of the vibration velocity v. For example, assuming that the angular velocity when rotating about the detection axis 19 is ω, the mass of the vibrating reed is m, and the vibrational velocity of the vibrating reed is v, the Coriolis force is expressed as Fc = 2 m · v · ω. Accordingly, the rotational angular velocity ω of the gyro sensor can be obtained by detecting the desired signal which is a signal corresponding to the Coriolis force. Then, using the obtained angular velocity ω, the processing unit 520 can perform various processes for camera shake correction, attitude control, GPS autonomous navigation, and the like.

  The control unit 140 performs various control processes based on the clock signal from the clock signal generation circuit 150. For example, the drive circuit 30 and the detection circuit 60 are controlled based on a clock signal (a signal obtained by dividing the clock signal).

  The control unit 140 also performs a process of writing (storing) the frequency adjustment value to the storage unit 130 and a process of reading the frequency adjustment value from the storage unit 130.

  The clock signal generation circuit 150 is set to the operation enable state by releasing the power on reset, and supplies the clock signal to the control unit 140. Then, the control unit 140 which has started the operation by the supply of the clock signal activates the drive circuit 30 and the detection circuit 60 to start the operation of these circuits.

  The detection circuit 60 includes an A / D conversion circuit 100 and a DSP unit 110. The A / D conversion circuit 100 performs sampling operation of the input signal based on the sampling clock signal based on the clock signal from the clock signal generation circuit 150 to execute A / D conversion. For example, an analog detection signal (desired signal) is converted into a digital signal (digital data). The DSP unit 110 receives the digital signal from the A / D conversion circuit 100 and performs digital signal processing on the digital signal. The DSP (Digital Signal Processing) unit 110 operates with an operation clock signal based on the clock signal from the clock signal generation circuit 150 to execute various digital signal processing such as filter processing.

  In addition, although the example in case the vibrating reed 10 is a tuning fork type is shown in FIG. 10, the vibrating reed 10 of this embodiment is not limited to such a structure. For example, it may be T-shaped or double T-shaped. The piezoelectric material of the vibrating reed 10 may be other than quartz.

  FIG. 11 shows a more detailed configuration example of the circuit device 20 of the present embodiment. The circuit device 20 receives a feedback signal DI from the vibrating reed 10 (physical quantity transducer), receives a drive circuit 30 for driving the vibrating reed 10, and detection signals IQ1 and IQ2 from the vibrating reed 10, and outputs desired signals. It includes a detection circuit 60 for detecting. The circuit device 20 also includes a control unit 140 and a clock signal generation circuit 150. Furthermore, the power supply terminal TVDD to which the power supply voltage VDD is input, the regulator circuit 22, and the buffer circuit 24 can be included.

  For example, the external power supply voltage VDD is input to the power supply terminal TVDD. The power supply voltage VDD is supplied to the regulator circuit 22 and the buffer circuit 24. The power supply terminal TVDD is, for example, a pad in a circuit device (IC chip).

  The regulator circuit 22 performs voltage adjustment to step down the power supply voltage VDD supplied from the power supply terminal TVDD. Then, the regulated power supply voltage VDDL obtained by voltage adjustment is supplied to the drive circuit 30 and the detection circuit 60 as an operating power supply voltage. The regulator circuit 22 also supplies the regulated power supply voltage VDDL to the control unit 140 and the clock signal generation circuit 150. For example, when a voltage of 2.7 V to 3.3 V is supplied as the external power supply voltage VDD, the regulator circuit 22 performs voltage adjustment to step down the power supply voltage VDD to obtain a constant voltage of 1.8 V, for example. The regulated power supply voltage VDDL is supplied to the drive circuit 30, the detection circuit 60, the control unit 140, and the clock signal generation circuit 150.

  Then, voltage generation circuit 160 of clock signal generation circuit 150 shown in FIG. 9 generates power supply voltage VDOS based on this regulated power supply voltage VDDL. For example, the regulated power supply voltage VDDL is further stepped down to generate the power supply voltage VDOS.

  The buffer circuit 24 is supplied with the power supply voltage VDD. The power supply voltage VDD is used as a high potential side power supply voltage of the buffer circuit 24. Then, the buffer circuit 24 receives the drive signal DQ from the drive circuit 30, and outputs a high-amplitude drive signal (amplified drive signal) DQB in which the amplitude of the drive signal DQ is increased to the vibrating reed 10 (physical quantity transducer). . For example, when the amplitude of the drive signal DQ is a first amplitude, the drive signal DQB having a second amplitude larger than the first amplitude is output to the vibrating reed 10. In this case, the drive signals DQ and DQB may be rectangular wave signals or sine wave signals.

  Drive circuit 30 includes an amplifier circuit 32 to which feedback signal DI from vibrating reed 10 is input, a gain control circuit 40 performing automatic gain control, and a drive signal output circuit 50 outputting drive signal DQ to vibrating reed 10. . It also includes a synchronization signal output circuit 52 that outputs synchronization signal SYC to detection circuit 60. The configuration of drive circuit 30 is not limited to that shown in FIG. 11, and various modifications may be made such as omitting some of these components or adding other components.

  The amplification circuit 32 (I / V conversion circuit) amplifies the feedback signal DI from the vibrating reed 10. For example, the signal DI of the current from the vibrating reed 10 is converted into a signal DV of voltage and output. The amplification circuit 32 can be realized by a capacitor, a resistance element, an operational amplifier or the like.

  The drive signal output circuit 50 outputs a drive signal DQ based on the signal DV amplified by the amplifier circuit 32. For example, when the drive signal output circuit 50 outputs a rectangular wave (or sine wave) drive signal, the drive signal output circuit 50 can be realized by a comparator or the like.

  The gain control circuit 40 (AGC) outputs the control voltage DS to the drive signal output circuit 50 to control the amplitude of the drive signal DQ. Specifically, the gain control circuit 40 monitors the signal DV to control the gain of the oscillation loop. For example, in the drive circuit 30, in order to keep the sensitivity of the gyro sensor constant, it is necessary to keep the amplitude of the drive voltage supplied to the vibrating reed 10 (driving vibrating reed) constant. Therefore, a gain control circuit 40 for automatically adjusting the gain is provided in the oscillation loop of the drive vibration system. The gain control circuit 40 automatically adjusts the gain variably so that the amplitude (the vibration velocity v of the vibrating reed) of the feedback signal DI from the vibrating reed 10 becomes constant. The gain control circuit 40 is implemented by a full-wave rectifier that full-wave rectifies the output signal DV of the amplifier circuit 32, an integrator that integrates the output signal of the full-wave rectifier, or the like.

  The synchronization signal output circuit 52 receives the signal DV amplified by the amplification circuit 32, and outputs a synchronization signal SYC (reference signal) to the detection circuit 60. The synchronization signal output circuit 52 performs a binarization process on the sine wave (AC) signal DV to generate a rectangular wave synchronization signal SYC, and a phase adjustment circuit (phase shift circuit for performing phase adjustment of the synchronization signal SYC). It can be realized by a phaser or the like.

  The detection circuit 60 includes an amplification circuit 61, a synchronization detection circuit 81, an A / D conversion circuit 100, and a DSP unit 110. The amplification circuit 61 receives the first and second detection signals IQ1 and IQ2 from the vibrating reed 10 and performs differential signal amplification and charge-voltage conversion. The synchronous detection circuit 81 performs synchronous detection based on the synchronous signal SYC from the drive circuit 30. The A / D conversion circuit 100 performs A / D conversion of the signal after synchronous detection. The DSP unit 110 performs digital signal processing such as digital filter processing and digital correction processing on the digital signal from the A / D conversion circuit 100.

  The control unit 140 performs control processing of the circuit device 20. The control unit 140 can be realized by a logic circuit (such as a gate array) or a processor. Various switch control and mode setting in the circuit device 20 are performed by the control unit 140.

4. Interference Frequency In a circuit device that drives the vibrating reed 10 to detect a physical quantity such as angular velocity, the driving frequency of the vibrating reed 10 and the sampling clock signal (operation signal) of the A / D conversion circuit 100 of the detection circuit 60 Interference may degrade detection performance. For example, at an interference frequency at which the drive frequency component and the sampling frequency component of the A / D conversion circuit 100 coincide with each other, a variation in angular velocity code or the like occurs to deteriorate detection performance.

  In the present embodiment, the fundamental wave component (fundamental frequency component) and harmonic component (harmonic frequency component) of the drive frequency are referred to as drive frequency components, and the fundamental frequency component of the sampling frequency of the A / D conversion circuit 100 and The harmonic frequency components will be referred to as sampling frequency components.

  FIG. 12 is an explanatory diagram of a sampling clock signal of the A / D conversion circuit 100 supplied to the detection circuit 60 and an operation clock signal of the DSP unit 110.

  As shown in FIG. 12, the vibrating reed 10 is driven at the drive frequency fdr. Further, the synchronous detection circuit 81 performs synchronous detection processing based on the synchronous signal of the drive frequency fdr. The drive frequency fdr has variations due to individual differences of the vibrating bars 10.

  Here, as a method of the comparative example of the present embodiment, a method of operating the A / D conversion circuit 100, the DSP unit 110, and the like of the detection circuit 60 with a signal based on the drive signal of the drive frequency fdr can be considered. However, in the method of this comparative example, when the drive frequency fdr is, for example, about 100 KHz, the signal based on the drive signal is 100 KHz or less, so that high speed operation of the A / D converter circuit 100 or the DSP unit 110 can not be realized.

  Therefore, in the present embodiment, a clock signal generation circuit 150 having an oscillation circuit 190 is provided, and a method of operating the A / D conversion circuit 100, the DSP unit 110, etc. by an operation signal based on the generated clock signal is adopted. ing. For example, in FIG. 12, the clock signal of the oscillation frequency fos is divided by i, and the A / D conversion circuit 100 is operated based on the sampling clock signal of the sampling frequency fsm = fos / i obtained by division. Also, the DSP unit 110 is operated based on the operation clock signal of the clock frequency fdsp obtained by dividing the clock signal of the oscillation frequency fos.

  In such a circuit device of the present embodiment, there may be a problem of variation in angular velocity code due to interference with the frequency of the drive signal.

  FIG. 13 is an explanatory view of the interference frequency. The horizontal axis in FIG. 13 represents the oscillation frequency, and the vertical axis represents the magnitude of the angular velocity code variation. The problem of angular velocity code variation arises due to the interference between the drive frequency component and the operating frequency on the side of the detection circuit 60.

  For example, the oscillation frequency of the oscillation circuit 190 is fos, i, j, and k are integers of 1 or more, and the frequency of an operation signal such as a sampling clock signal is fos / i. In this case, as described above, the interference frequency is the oscillation frequency when j × fdr = k × fos / i holds. That is, assuming that the interference frequency is fin, the relational expression j × fdr = k × fos / i is established when fos = fin.

  For example, 1 × fdr = fsm = fos / i holds at the interference frequency shown by I1 in FIG. For example, assuming that the interference frequency of I1 is fos = fin1, 1 × fdr = fos / i = fin1 / i holds. This corresponds to the case of j = 1 and k = 1 in the relational expression (interference condition) of j × fdr = k × fos / i.

  Further, 2 × fdr = fsm = fos / i holds at the interference frequency shown in I2. For example, assuming that the interference frequency shown in I2 is fos = fin2, 2 × fdr = fos / i = fin2 / i holds. This corresponds to the case of j = 2 and k = 1 in the relational expression j × fdr = k × fos / i.

  Further, 3 × fdr = fsm = fos / i holds at the interference frequency shown in I3. For example, assuming that the interference frequency shown in I3 is fos = fin3, 3 × fdr = fos / i = fin3 / i holds. This corresponds to the case of j = 3 and k = 1 in the relational expression j × fdr = k × fos / i.

  At the interference frequency shown in I4, 3 × fdr = 2 × fsm = 2 × fos / i holds. For example, assuming that the interference frequency shown in I4 is fos = fin4, 3 × fdr = 2 × fos / i = 2 × fin4 / i holds. This corresponds to the case of j = 3 and k = 2 in the relational expression j × fdr = k × fos / i.

  At the interference frequency shown in I5, 5 × fdr = 2 × fsm = 2 × fos / i holds. For example, assuming that the interference frequency shown in I5 is fos = fin5, 5 × fdr = 2 × fos / i = 2 × fin5 / i holds. This corresponds to the case of j = 5 and k = 2 in the relational expression j × fdr = k × fos / i.

  Thus, at the interference frequency, the interference condition represented by the relational expression j × fdr = k × fsm = k × fos / i holds. Here, j × fdr corresponds to the harmonic component (j ≧ 2) of the drive frequency fdr and the fundamental component (j = 1). Further, fsm = fos / i is the sampling frequency of the A / D conversion circuit 100 (in a broad sense, the frequency of the operation signal). Therefore, in the interference condition j × fdr = k × fos / i, the harmonic component (j ≧ 2) of the drive frequency fdr and the fundamental component (j = 1) coincide with k times the sampling frequency fos / i It is a condition that

  Note that the angular velocity code variation at the interference frequency shown in FIG. 13 is caused by the sampling operation of the A / D conversion circuit 100 for the frequency component (drive frequency component) of the unnecessary signal mixed in the input signal of the A / D conversion circuit 100. It occurs due to folding back to the signal band and the like. Therefore, the angular velocity code variation at the interference frequency is not actually the case where j × fdr and k × fsm completely match, but when the frequency difference Δf between j × fdr and k × fsm is sufficiently small. It appears prominently. Specifically, aliasing noise due to the frequency difference Δf appears in the signal band if the frequency difference Δf is lower than the frequency (for example, 200 Hz to 10 Hz) of the signal band that is the frequency band of the desired signal. Problems will arise. When the frequency difference Δf is large, aliasing noise is sufficiently reduced by the low-pass filter for band limitation of the DSP unit 110, so that angular velocity code variation does not occur. Thus, it can be said that the interference frequency to be avoided in the present embodiment has a given frequency width (signal bandwidth, Δf).

  And in this embodiment, the method of setting the oscillation frequency of the oscillation circuit 190 to the frequency which avoided such an interference frequency is employ | adopted. That is, assuming that the oscillation frequency is fos, i and j are integers of 1 or more, and the frequency of the operation signal is fos / i, the oscillation frequency fos is set such that j × fdr ≠ fos / i. The frequency fos / i of the operation signal is the frequency of the sampling clock signal of the A / D conversion circuit 100 or the operation clock signal (output data rate) of the DSP unit 110.

  As described above, if the oscillation frequency fos is set to be j × fdr ≠ fos / i, the oscillation frequency fos can be set to a frequency that avoids the interference frequencies shown in I1, I2, and I3 of FIG. . Therefore, it is possible to reduce the occurrence of the angular velocity code variation of large values indicated by I1, I2, and I3, and it is possible to reduce the deterioration of the detection performance.

  Furthermore, in the present embodiment, when k is an integer of 1 or more, it is desirable to set the oscillation frequency fos such that j × fdr ≠ k × fos / i. That is, not only the interference frequency in the case of k = 1 shown in I1, I2 and I3 in FIG. 13 but also the interference frequency in the case of k ≧ 2 shown in I4 and I5 are oscillation frequencies Set fos. In this way, it is possible to prevent not only the occurrence of angular velocity code variations of large values as indicated by I1, I2 and I3, but also the occurrence of angular velocity code variations of relatively small values as indicated by I4 and I5. Become.

  In the present embodiment, the adjustment of the oscillation frequency fos such as j × fdr ≠ k × fos / i is realized by the adjustment of the capacitance value of the variable capacitance circuit 197 shown in FIG. Then, the frequency adjustment value (capacity adjustment value) of the oscillation frequency is stored in the storage unit 130.

  For example, in the method of the comparative example in which the circuit of the detection circuit 60 is operated by the signal based on the drive signal, the problem of the interference frequency as shown in FIG. 13 does not occur.

  On the other hand, in the present embodiment, in order to realize the high speed operation of the circuit of the detection circuit 60, the clock signal generation circuit 160 having the oscillation circuit 190 is provided, and the detection circuit is operated by the operation signal based on the generated clock signal. 60 circuits (A / D conversion circuit, DSP unit) are operated. The drive frequency of the drive signal and the oscillation frequency of the oscillation circuit 190 are independent of each other and have no correlation. Therefore, the problem of interference frequency as shown in FIG. 13 occurs. And in order to eliminate such a problem of an interference frequency, the adjustment method of the oscillation frequency which is demonstrated below is employ | adopted in this embodiment.

  FIG. 14 is an explanatory view of the adjustment method of the oscillation frequency of the present embodiment. In FIG. 14, the horizontal axis is the drive frequency, and the vertical axis is the target oscillation frequency for frequency adjustment.

  In FIG. 14, IL1 and IL2 are lines of the interference frequency described in FIG. A problem of angular velocity code variation occurs on the interference frequency lines IL1 and IL2. Further, in FIG. 14, examples of the vibrating reed A and the vibrating reed B are shown. The driving frequency (typical value) is different between the vibrating bars A and B. For example, there are two types of vibrating bars A and B as vibrating bars that are paired with the circuit device and incorporated into the package. By using the vibrating bars A and B having different driving frequencies, for example, it is possible to reduce inter-axis interference in a multi-axis gyro sensor.

  As shown in FIG. 14, there are individual differences in the drive frequency of the vibrating bars A and B, the drive frequency of the vibrating bar A varies in the range of RDA, and the drive frequency of the vibrating bar B varies in the range of RDB. RDA is a range of variation in drive frequency centered on the typical value fda of the drive frequency of the vibrating reed A. RDB is a variation range of the drive frequency centered on the typical value fdb of the drive frequency of the vibrating bar B.

  Then, depending on which of the vibrating reed A and the vibrating reed B is connected to the circuit device (according to which vibrating reed and the circuit device constitute the physical quantity detection device), the range of RCA in FIG. Make coarse adjustments. This coarse adjustment is realized by voltage adjustment of the power supply voltage VDOS supplied by the voltage generation circuit 160 of FIG. In FIG. 14, the voltage adjustment of the power supply voltage VDOS enables coarse adjustment of the oscillation frequency at, for example, 500 KHz / step.

  For example, when the vibrating reed connected to the circuit device is the vibrating reed A (in a broad sense, the first physical quantity transducer), the voltage generation circuit 160 supplies the first voltage as the power supply voltage VDOS. On the other hand, when the vibrating reed connected to the circuit device is the vibrating reed B having a different driving frequency from the vibrating reed A (the second physical quantity transducer in a broad sense), the voltage generation circuit 160 is used as the power supply voltage VDOS. A second voltage different from the first voltage is provided.

  Specifically, the vibrating reed A has a lower driving frequency than the vibrating reed B. For this reason, when the vibrating reed A is connected to the circuit device to constitute a physical quantity detection device, the adjustment range of the oscillation frequency may be set to a low frequency corresponding to the low driving frequency of the vibrating reed A desirable. Therefore, when the vibrating reed A is connected, the voltage generation circuit 160 uses the power supply voltage VDOS as the CR oscillation circuit 170 (oscillation circuit 190 in a broad sense) as the first voltage lower than the second voltage. Supply to By doing this, the oscillation frequency of the CR oscillation circuit 170 is lowered, and the adjustment range of the oscillation frequency can be set to a low frequency range corresponding to the low drive frequency of the vibrating reed A.

  On the other hand, the vibrating reed B has a higher driving frequency than the vibrating reed A. For this reason, when the vibrating reed B is connected to the circuit device to constitute a physical quantity detection device, the adjustment range of the oscillation frequency may be set to a high frequency corresponding to the high drive frequency of the vibrating reed B. desirable. Therefore, when the vibrating reed B is connected, the voltage generation circuit 160 supplies the CR oscillation circuit 170 with the second voltage higher than the first voltage as the power supply voltage VDOS. By doing this, the oscillation frequency of the CR oscillation circuit 170 is increased, and the adjustment range of the oscillation frequency can be set to a high frequency range corresponding to the high drive frequency of the vibrating bars B.

  Further, in FIG. 14, VLA is an adjustment line of the oscillation frequency in the case of the vibrating reed A, and VLB is an adjustment line of the oscillation frequency in the case of the vibrating reed B. For example, when the vibrating reed A is connected to the circuit device, the oscillation frequency is adjusted using the adjustment line VLA. The adjustment line VLA is a line set between the interference frequency lines IL1 and IL2.

  As shown by RDA in FIG. 14, there are variations in the drive frequency of the vibrating reed A due to individual differences. On the other hand, when the circuit device is connected to the vibrating reed A and packaged as a physical quantity detection device, the drive frequency of the vibrating reed A can be uniquely identified by measuring the drive frequency. When the measured drive frequency is fdr = fd1, as shown in FIG. 14, the target oscillation frequency ft1 is obtained from fdr = fd1 and the adjustment line VLA. For example, the target oscillation frequency ft1 can be obtained from the intersection of the line fdr = fd1 and the adjustment line VLA. Then, the frequency is adjusted by the variable capacitance circuit 196 so that the oscillation frequency is set to fos = ft1. That is, the capacitance value of the variable capacitance circuit 197 is adjusted.

  When the measured drive frequency is fdr = fd2, a target oscillation frequency ft2 is determined from fdr = fd2 and the adjustment line VLA. Then, the frequency is adjusted by the variable capacitance circuit 197 so that the oscillation frequency is set to fos = ft2.

  Similarly, as shown by RDB in FIG. 14, although there are variations due to individual differences in the drive frequency of the vibrating reed B, in the state where the circuit device is connected to the vibrating reed B, the drive frequency is measured. The driving frequency of the vibrating reed B can be uniquely identified. When the measured drive frequency is fdr = fd3, a target oscillation frequency ft3 is obtained from fdr = fd3 and the adjustment line VLB. Then, the frequency is adjusted by the variable capacitance circuit 197 so that the oscillation frequency is set to fos = ft3.

  By doing as described above, in the present embodiment, the oscillation frequency fos can be set to a frequency that avoids the interference frequency. That is, the oscillation frequency fos can be set such that j × fdr ≠ k × fos / i.

  Then, as shown in FIG. 14, the adjustment lines VLA and VLB of the oscillation frequency are located in the middle of the interference frequency lines IL1 and IL2. Therefore, even when the oscillation frequency fluctuates due to the temperature change, it is possible to reduce the occurrence of the angular velocity code fluctuation due to the interference frequency described in FIG. For example, when the drive frequency is fdr = fd1, if the fluctuation of the oscillation frequency due to the temperature change is within the frequency range RS1, the interference with the interference frequency lines IL1 and IL2 can be avoided. When the drive frequency is fdr = fd2, if the fluctuation of the oscillation frequency due to the temperature change falls within the frequency range RS2, the interference with the interference frequency lines IL1 and IL2 can be avoided. The same applies to the case of fdr = fd3.

  Furthermore, in the present embodiment, as described with reference to FIGS. 6A to 7B and the like described above, the attenuation characteristics of the filter unit 90 on the front side of the A / D conversion circuit 100 are effectively used to The amplitude of the unnecessary signal mixed in the input signal of the D conversion circuit 100 is attenuated. In this way, even if, for example, the oscillation frequency matches the interference frequency due to fluctuations in the oscillation frequency or the drive frequency, the attenuation characteristic of the filter unit 90 causes the interference frequency to be Can be sufficiently attenuated. Therefore, it becomes possible to more reliably avoid the occurrence of the problem of the interference frequency.

5. Multi-Axis Gyro Sensor Next, an oscillation frequency setting method of this embodiment in a multi-axis gyro sensor will be described. FIG. 15 is a configuration example of a circuit device 20 used for a multi-axis gyro sensor that detects rotational angular velocities around a plurality of axes. The circuit device 20 of this configuration example drives and detects the plurality of vibrating bars 10-1, 10-2, and 10-3. Here, for example, the vibrating reed 10-1 is a vibrating reed for detecting the rotational angular velocity around the X axis (the first axis in a broad sense). The vibrating reed 10-2 is a vibrating reed for detecting the rotational angular velocity about the Y axis (the second axis in a broad sense). The vibrating reed 10-3 is a vibrating reed for detecting the rotational angular velocity about the Z axis (in a broad sense, the third axis).

  In FIG. 15, the detection circuit 60 of the circuit device 20 includes a first detection signal from the vibrating reed 10-1 (in a broad sense, a first physical quantity transducer), and a vibrating reed 10-2 (in a broad sense, a second detection signal). The second detection signal from the physical quantity transducer of Further, a third detection signal from the vibrating reed 10-3 (in a broad sense, a third physical quantity transducer) is input to the detection circuit 60. The detection circuit 60 is provided with an amplification circuit 61-1, a synchronization detection circuit 81-1, a filter section 90-1, and an A / D converter ADCX as circuits for the vibrating reed 10-1. Further, in the detection circuit 60, an amplification circuit 61-2, a synchronous detection circuit 81-2, a filter section 90-2, and an A / D converter ADCY are provided as circuits for the vibrating reed 10-2. Further, as a circuit for the vibrating reed 10-3, an amplification circuit 61-3, a synchronous detection circuit 81-3, a filter section 90-3, and an A / D converter ADCZ are provided.

  The A / D conversion circuit 100 (ADC X to ADC Z) of the detection circuit 60 performs the sampling operation of the input signal based on the sampling clock signal of the sampling frequency fsm = fos / i1 obtained by dividing the clock signal from the clock signal generation circuit 150. I do. Specifically, the A / D conversion circuit 100 (ADC, ADCY) receives a first input signal corresponding to the first detection signal from the vibrating reed 10-1 and a second input signal from the vibrating reed 10-2. The sampling operation of the second input signal corresponding to the detection signal is performed based on the sampling clock signal which is the operation signal. The A / D conversion circuit 100 (ADCZ) performs a sampling operation of the third input signal corresponding to the third detection signal from the vibrating reed 10-3 based on the sampling clock signal.

  The DSP unit 110 of the detection circuit 60 performs digital signal processing on digital signals from the A / D conversion circuit 100 (ADC X to ADC Z) based on an operation clock signal of a clock frequency fdsp = fos / i2 obtained by dividing a clock signal. Do.

  Although the configuration of the drive circuit is not shown in FIG. 15, actually, drive circuits for the vibrating reed 10-1, the vibrating reed 10-2, and the vibrating reed 10-3 are provided. . In this case, the drive circuit receives the first feedback signal from the vibrating reed 10-1 (first physical quantity transducer) to drive the vibrating reed 10-1, and the vibrating reed 10-2 (second In response to the second feedback signal from the physical quantity transducer, the vibrating reed 10-2 is driven. The drive circuit also receives the third feedback signal from the vibrating reed 10-3 (third physical quantity transducer) to drive the vibrating reed 10-3.

  The configuration and operation of the amplification circuits 61-1 to 61-3, the synchronization detection circuits 81-1 to 81-3, the filter units 90-1 to 90-3, and the A / D converters ADCX to ADCZ are shown in FIG. The same as the amplification circuit 61, the synchronization detection circuit 81, the A / D conversion circuit 100, the filter unit 90, and the DSP unit 110 of FIG. 11, the detailed description is omitted. Further, in the A / D conversion circuit 110 of FIG. 15, although A / D converters ADCX to ADCZ are separately provided for the vibrating reed 10-1 to the vibrating reed 10-3, one A / D converter is used. In time division processing, A / D conversion may be performed on detection signals of the vibrating bars 10-1 to 10-3. Although FIG. 15 shows the case where the multi-axis gyro sensor is a three-axis gyro sensor, the multi-axis gyro sensor may be a two-axis gyro sensor. In this case, for example, the respective circuits and drive circuits of the detection circuit 60 corresponding to the vibrating bars 10-1 and 10-2 may be provided.

  In multi-axis gyro sensors, so-called inter-axis interference becomes a problem. In FIG. 15, the drive frequencies of the vibrating bars 10-1, 10-2, and 10-3 are made different in order to reduce the influence of the inter-axis interference. Specifically, the X-axis vibrating reed 10-1 is driven at a drive frequency fdr1 by a drive circuit (not shown). The Y-axis vibrating reed 10-2 is driven at a drive frequency fdr2 different from fdr1. The Z-axis vibrating reed 10-3 is driven at a drive frequency fdr3 different from both fdr1 and fdr2. By thus making the drive frequency of each axis different, it is possible to reduce the influence of inter-axis interference and to reduce the deterioration of detection performance.

  In this embodiment, the drive frequency of the vibrating reed 10-1 (first physical quantity transducer) is thus set to the first drive frequency fdr1, and the drive frequency of the vibrating reed 10-2 (second physical quantity transducer) The oscillation frequency fos is adjusted such that j × fdr1 ≠ fos / i and m × fdr2 ≠ fos / i, where Here, i, j and m are integers of 1 or more. Specifically, in the present embodiment, the storage unit 130 stores a frequency adjustment value for adjusting the oscillation frequency fos such that j × fdr1 ≠ fos / i and m × fdr2 ≠ fos / i. More preferably, when k and n are integers of 1 or more, the oscillation frequency fos is adjusted so that j × fdr1 ≠ k × fos / i and m × fdr2 ≠ n × fos / i, It is stored in the storage unit 130. The storage processing in the storage unit 130 is performed by the control unit 140 in FIG.

  In the present embodiment, j × fdr1 ≠ fos / i, m × fdr2 ≠ fos / i, where the drive frequency of the vibrating reed 10-3 (third physical quantity transducer) is the third drive frequency fdr3. Also, the oscillation frequency fos is adjusted so that p × fdr3 ≠ fos / i. Here, p is an integer of 1 or more. Specifically, in the present embodiment, the storage unit 130 adjusts the oscillation frequency fos so that j × fdr1 ≠ fos / i, m × fdr2 ≠ fos / i, and p × fdr3 ≠ fos / i. Store adjustment values. More preferably, when k, n and q are integers of 1 or more, j × fdr1 ≠ k × fos / i, m × fdr2 ≠ n × fos / i, and p × fdr3 ≠ q × fos / i The oscillation frequency fos is adjusted so as to be stored in the storage unit 130.

  FIG. 16 is a diagram for explaining the interference frequency in the multi-axis gyro sensor. The horizontal axis in FIG. 16 is the oscillation frequency, and the vertical axis is the angular velocity code variation. Compared to the case of the single-axis gyro sensor of FIG. 13, in the multi-axis gyro sensor of FIG. 16, many interference frequencies at which the drive frequency component and the sampling frequency component (frequency component of the operation signal) coincide are generated. That is, angular velocity code variation occurs at many interference frequencies. This is because, as shown in FIG. 15, in the multi-axis gyro sensor, drive frequencies fdr1, fdr2, fdr3 of the respective vibrating bars 10-1, 10-2, 10-3 are made different to reduce inter-axis interference. It is because

  As described above, in the multi-axis gyro sensor, the setting of the oscillation frequency avoiding the interference frequency is more severe than the case of the single-axis gyro sensor.

  In this respect, in the present embodiment, as described with reference to FIGS. 6A to 7B, the attenuation characteristics of the filter unit 90 on the front side of the A / D conversion circuit 100 are effectively used. The amplitude of the unnecessary signal mixed in the input signal of the A / D conversion circuit 100 is attenuated. Therefore, in the multi-axis gyro sensor in which it is difficult to set the oscillation frequency that avoids the interference frequency, even if the oscillation frequency matches the interference frequency, the attenuation characteristic of the filter unit 90 It is possible to sufficiently attenuate the amplitude of the unwanted signal that is the cause.

6. Detection Circuit FIG. 17 shows a detailed configuration example of the detection circuit 60. FIG. 17 shows an example of a detection circuit 60 of the fully differential switching mixer system.

  Differential Q1 and second detection signals IQ1 and IQ2 from the vibrating reed 10 are input to the Q / V conversion circuits 62 and 64 (charge-voltage conversion circuits). Then, the Q / V conversion circuits 62 and 64 convert the charge (current) generated in the vibrating reed 10 into a voltage. These Q / V conversion circuits 62, 64 are continuous charge-voltage conversion circuits having feedback resistors.

  The gain adjustment amplifiers 72 and 74 gain-adjust and amplify the output signals QA1 and QA2 of the Q / V conversion circuits 62 and 64, respectively. The gain adjustment amplifiers 72 and 74 are so-called programmable gain amplifiers, and amplify the signals QA1 and QA2 with the set gains. For example, the signal is amplified to a signal whose amplitude matches the voltage conversion range of the A / D conversion circuit 100.

  The switching mixer 80 is a mixer that performs differential synchronous detection based on the synchronous signal SYC from the drive circuit 30. Specifically, in the switching mixer 80, the output signal QB1 of the gain adjustment amplifier 72 is input to the first input node NI1, and the output signal QB2 of the gain adjustment amplifier 74 is input to the second input node NI2. Then, differential synchronous detection is performed by the synchronous signal SYC from the drive circuit 30, and differential first and second output signals QC1 and QC2 are output to the first and second output nodes NQ1 and NQ2. By this switching mixer 80, unnecessary signals such as noise (1 / f noise) generated by the circuit of the preceding stage (Q / V conversion circuit, gain adjustment amplifier) are frequency-converted to a high frequency band. Also, a desired signal, which is a signal corresponding to the Coriolis force, is dropped into the DC signal.

  The filter 92 receives the first output signal QC1 from the first output node NQ1 of the switching mixer 80. The filter 94 receives the second output signal QC2 from the second output node NQ2 of the switching mixer 80. These filters 92 and 94 are, for example, low-pass filters having frequency characteristics that remove (attenuate) unwanted signals and pass desired signals. For example, unnecessary signals, such as 1 / f noise, frequency-converted to a high frequency band by the switching mixer 80 are removed by the filters 92 and 94. Moreover, the filters 92 and 94 are passive filters comprised with a passive element (a resistance element, a capacitor, etc.), for example.

  The A / D conversion circuit 100 receives the output signal QD1 from the filter 92 and the output signal QD2 from the filter 94, and performs differential A / D conversion. Specifically, the A / D conversion circuit 100 performs the A / D conversion by sampling the output signals QD1 and QD2 using the filters 92 and 94 as anti-aliasing filters (pre-filters). In this embodiment, the output signal QD1 from the filter 92 and the output signal QD2 from the filter 94 are input to the A / D conversion circuit 100 without passing through the active element.

  As the A / D conversion circuit 100, for example, various types of A / D conversion circuits such as delta sigma type and successive approximation type can be adopted. In the case of adopting the delta sigma type, for example, A / D having functions of CDS (Correlated double sampling) or chopper for 1 / f noise reduction, for example, an A / D configured by a second-order delta sigma modulator etc. A converter circuit can be used. In addition, in the case of adopting the successive approximation type, for example, it has a function of DEM (Dynamic Element Matching) for reducing deterioration of the S / N ratio due to element variation of DAC, etc., and is configured by a capacitive DAC and successive approximation control logic. An A / D conversion circuit can be used.

  The DSP unit 110 performs various digital signal processing. For example, the DSP unit 110 performs band-limited digital filter processing according to the application of a desired signal, and digital filter processing for removing noise generated by the A / D conversion circuit 100 and the like. In addition, digital correction processing such as gain correction (sensitivity adjustment) and offset correction is performed.

  The circuit device 20 of the present embodiment is not limited to the configuration of the fully differential switching mixer system. For example, various configurations can be adopted, such as a configuration of a direct sampling system including a discrete Q / V conversion circuit and an A / D conversion circuit directly connected to the discrete Q / V conversion circuit.

  FIG. 18 shows an example of a mobile including the circuit device 20 of the present embodiment. The circuit device 20 of the present embodiment can be incorporated into various mobile objects such as, for example, a car, an airplane, a motorcycle, a bicycle, or a ship. The movable body is, for example, an apparatus or device that moves on the ground, in the sky, or in the sea, provided with a drive mechanism such as an engine or a motor, a steering mechanism such as a steering wheel or a rudder, and various electronic devices. FIG. 18 schematically shows a car 206 as an example of a mobile. The automobile 206 incorporates a gyro sensor 510 (sensor) having the vibrating reed 10 and the circuit device 20. The gyro sensor 510 can detect the posture of the vehicle body 207. A detection signal of the gyro sensor 510 can be supplied to the vehicle body posture control device 208. The vehicle attitude control device 208 can control the hardness of the suspension or control the brakes of the individual wheels 209 in accordance with the attitude of the vehicle body 207, for example. In addition, such attitude control can be used in various mobile bodies such as a biped robot, an aircraft, and a helicopter. The gyro sensor 510 can be incorporated to realize the attitude control.

  It should be understood by those skilled in the art that although the present embodiment has been described in detail as described above, many modifications can be made without departing substantially from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention. For example, in the specification or the drawings, the term (gyro sensor, vibrating piece, etc.) described at least once together with a broader or synonymous different term (physical quantity detection device, physical quantity transducer, etc.) Can be replaced with the different terms. Further, the configuration of the circuit device, the physical quantity detection device, the electronic device, the moving body, the structure of the vibrating reed, etc. are not limited to those described in the present embodiment, and various modifications can be made.

10, 10-1 to 10-3 vibrating bars, 18 physical quantity transducers, 20 circuit devices,
22 regulator circuit, 24 buffer circuit, 30, drive circuit,
32 amplifier circuit (I / V conversion circuit), 40 gain control circuit, 52 synchronization signal output circuit,
60 detection circuits, 61, 61-1 to 61-3 amplification circuits, 62, 64 Q / V conversion circuits,
72, 74 gain adjustment amplifier, 80 switching mixer,
81, 81-1 to 81-3 synchronous detection circuit, 90, 90-1 to 90-3 filter unit,
92, 94 filters, 100 A / D conversion circuits, 110 DSP sections,
130 storage unit, 140 control unit, 150 clock signal generation circuit,
160 voltage generation circuit, 170 CR oscillation circuit, 180 amplification circuit, 190 oscillation circuit,
196 variable resistance circuit, 197 variable capacitance circuit,
206 Moving body (car), 207 body, 208 body attitude control device, 209 wheels,
500 electronic equipment, 510 gyro sensor, 520 processing unit, 530 memory,
540 operation unit, 550 display unit

Claims (9)

A drive circuit for receiving the feedback signal from the physical quantity transducer and driving the physical quantity transducer;
A clock signal generation circuit having an oscillation circuit and generating a clock signal by the oscillation circuit;
A detection circuit to which a detection signal from the physical quantity transducer is input;
Including
The detection circuit
An A / D conversion circuit that A / D converts an input signal corresponding to the detection signal ;
A filter unit provided on the front side of the A / D conversion circuit;
A digital signal processing unit having a digital filter unit that performs digital filter processing on the digital signal from the A / D conversion circuit;
Including
The A / D conversion circuit
Performing a sampling operation of the input signal based on a sampling clock signal generated based on the clock signal;
When the cut-off frequency fcd of the digital filter unit is a first digital filter cut-off frequency fcd1, the cut-off frequency fca of the filter unit is set to the first filter cut-off frequency fca1.
When the cut-off frequency fcd of the digital filter unit is a second digital filter cut-off frequency fcd2 lower than the first digital filter cut-off frequency fcd1, the cut-off frequency fca of the filter unit is is set lower than the first filter cutoff frequency fca1 second filter cut-off frequency Fca2,
When the oscillation frequency of the oscillation circuit is fos, the drive frequency of the physical quantity transducer is fdr, and i and j are integers of 1 or more, the A / D conversion circuit has a sampling frequency fsm = fos / i The sampling operation is performed based on the sampling clock signal, and the oscillation frequency fos of the oscillation circuit is set such that j × fdr ≠ fos / i.
The sampling frequency of the sampling operation of the A / D conversion circuit is fsm, the gain of the filter unit is Ga, the amplitude of the unnecessary signal mixed in the input signal of the filter unit is VNF, and When the resolution is n bits and the conversion voltage range of the A / D conversion circuit is VFSR,
The gain Ga of the filter unit is set to a gain that attenuates the amplitude VNF of the unnecessary signal to a value smaller than a predetermined value determined by the resolution n bits and the conversion voltage range VFSR at the sampling frequency fsm circuit device characterized by there. In the circuit device according to claim 1,
A storage unit for storing an adjustment value of the cutoff frequency fca of the filter unit;
The adjustment value of the cutoff frequency fca is
When the cut-off frequency fcd of the digital filter unit is the first digital filter cut-off frequency fcd1, the cut-off frequency fca of the filter unit is set to the first filter cut-off frequency fca1;
When the cut-off frequency fcd of the digital filter unit is the second digital filter cut-off frequency fcd2 and satisfies fcd2 <fcd1, the cut-off frequency fca of the filter unit is set to the first filter cut-off A circuit device characterized in that the adjustment value is set to the second filter cutoff frequency fca2 lower than the frequency fca1. In the circuit device according to claim 2,
The circuit unit, wherein the storage unit is a non-volatile memory. The circuit device according to any one of claims 1 to 3 .
The cutoff frequency fcd for band limitation of the digital filter unit can be set in the range of fcd1 ≧ fcd ≧ fcd2, and the cutoff frequency fca of the filter unit can be set in the range of fca1 ≧ fca ≧ fca2 If it is
When the cutoff frequency fca of the filter section is set to the first filter cutoff frequency fca1, and when the cutoff frequency fca is set to the second filter cutoff frequency fca2,
The circuit device characterized in that the gain Ga of the filter unit is set to a value that attenuates the amplitude VNF of the unnecessary signal to a value smaller than the predetermined value at the sampling frequency fsm. The circuit device according to any one of claims 1 to 4 .
When the cut-off frequency fcd for band limitation of the digital filter unit is changed, the cut-off frequency fca of the filter unit is changed in conjunction with the change of the cut-off frequency fcd. Circuit equipment. In the circuit device according to any one of claims 1 to 5 ,
The digital signal processing unit
A circuit device that operates based on an operation clock signal generated based on the clock signal. A circuit device according to any one of claims 1 to 6 ;
The physical quantity transducer;
A physical quantity detection device characterized by including. An electronic device comprising the circuit device according to any one of claims 1 to 6 . A mobile unit comprising the circuit device according to any one of claims 1 to 6 .

Images