JP6525583B2 - Solar cell element and solar cell module - Google Patents

Description

  The present invention relates to a solar cell element and a solar cell module using the solar cell element.

  In recent years, as a highly efficient crystalline silicon solar cell, for example, a solar cell with a PERC (Passivated Emitter and Rear Cell) structure has been studied. Such a solar cell element includes a silicon substrate having a front main surface to be a light receiving surface and a back main surface located on the opposite side. In addition, on the back major surface of the silicon substrate, a passivation layer formed of an insulating film such as an oxide film or a nitride film or a laminated film of them is provided, and an aluminum electrode on the passivation layer. In this passivation layer, for example, a non-passivated portion to be a contact hole is formed by a method such as laser irradiation. Then, an aluminum paste is applied on the passivation layer and fired to form an aluminum electrode partially connected to the silicon substrate through the non-passivated portion (see, for example, Patent Documents 1 and 2 below).

JP 2005-150609 A JP, 2013-135155, A

  However, in a solar cell module formed by using a plurality of such solar cell elements, carriers generated by light incident on the solar cell module can not be collected, and there is a possibility that recombination loss is likely to occur.

  Therefore, one object of the present invention is to provide a solar cell element and a solar cell module capable of reducing recombination loss and improving output characteristics.

A solar cell element according to an embodiment of the present invention includes a semiconductor substrate having a front main surface and a back main surface located on the opposite side of the front main surface, and a peripheral portion on the back main surface of the semiconductor substrate. And a passivation portion provided on both of the first region and the second region surrounded by the first region. Then, on the back main surface of the semiconductor substrate, a large number of non-passivated portions without the passivation portion are provided in both the first region and the second region, and the back main surface of the semiconductor substrate is The ratio of the planar area occupied by the passivation portion in the first area to the planar area of the first area in plan view is the ratio of the planar area of the second area to the planar area of the second area. The semiconductor substrate has a first semiconductor region having a p-type conductivity type on the back major surface side, and an n-type conductivity type on the back major surface side. without a second semiconductor region, the semiconductor substrate has the second semiconductor region having n-type conductivity in the table main surface, wherein the passivation portion has a negative fixed charge density.

  Moreover, the solar cell module which concerns on one Embodiment of this invention is equipped with the said solar cell element.

  According to the above solar cell element and solar cell module, it is possible to reduce the recombination loss and improve the output characteristics of the solar cell module.

It is a top view which shows the external appearance of the surface main surface of the solar cell element which concerns on one Embodiment of this invention. It is a top view which shows the external appearance of the back main surface of the solar cell element which concerns on one Embodiment of this invention. It is an end elevation which shows the III-III cross section in FIG. It is the enlarged plan view which abbreviate | omitted the back surface current collection electrode in FIG. 2, (a) is an enlarged plan view which shows one Embodiment in (B) part, (b) shows one Embodiment in (A) part It is an enlarged plan view, and (c) is an enlarged plan view showing other embodiments in part (A). It is an enlarged plan view which shows other embodiment of (B) part which abbreviate | omits a back surface current collection electrode in FIG. It is a top view which shows the external appearance of the solar cell module which concerns on one Embodiment of this invention. It is an end elevation showing a section of a solar cell module concerning one embodiment of the present invention. It is an end elevation which shows an optical path between the solar cell elements of the solar cell module which concerns on one Embodiment of this invention. It is an enlarged plan view which shows the external appearance which abbreviate | omitted the back surface current collection electrode in the back main surface of the solar cell element which concerns on one Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The drawings are schematically illustrated, and the sizes and positional relationships of various structures in the drawings may be changed as appropriate. In FIG. 8, hatching indicating a cross section is omitted to facilitate understanding.

<Solar cell element>
As shown in FIGS. 1 to 3, a solar cell element 10 according to an embodiment of the present invention has a semiconductor substrate 1 having a front main surface 1a and a back main surface 1b located on the opposite side of the front main surface 1a. ing. In the back main surface 1b of the semiconductor substrate 1, a passivation portion 4a provided in both of a first region 10c located at the peripheral edge and a second region 10d surrounded by the first region 10c is provided. Furthermore, on the back main surface 1b of the semiconductor substrate 1, a large number of non-passivated portions 4b in which the passivation portion 4a is not formed are provided. When the back major surface 1b of the semiconductor substrate 1 is viewed in plan, the ratio of the planar area occupied by the passivation portion 4a to the first area 10c with respect to the planar area of the first area 10c is the planar area of the second area 10d. On the other hand, the structure is such that the ratio of the planar area occupied by the passivation portion 4a in the second region 10d is smaller. Here, the plane area refers to the area of the plane shape in plan view.

  Next, the specific configuration of the solar cell element 10 will be described. As shown in FIGS. 1 to 4, the solar cell element 10 has a front major surface 10 a and a back major surface 10 b. The front main surface 10a is a surface (light receiving surface) that mainly receives incident light. The back major surface 10 b is a surface (for example, a non-light receiving surface) located on the opposite side of the front major surface 10 a of the solar cell element 10.

  The solar cell element 10 further includes a semiconductor substrate 1, a passivation portion 4 a, a non-passivation portion 4 b, an antireflective layer 5, a front electrode 7 and a back electrode 8.

  The semiconductor substrate 1 has a first semiconductor region 2 and a second semiconductor region 3, and the first semiconductor region 2 and the second semiconductor region 3 form a pn junction. As such a semiconductor substrate 1, for example, a single crystal or polycrystalline silicon substrate having a predetermined dopant element such as boron or gallium and having one conductivity type (for example, p-type) is used. The thickness of the semiconductor substrate 1 may be, for example, 250 μm or less, and may be 150 μm or less. The shape of the semiconductor substrate 1 is not particularly limited. For example, if the shape is a square in plan view, the semiconductor substrate 1 can be easily manufactured. The semiconductor substrate 1 mainly corresponds to the first semiconductor region 2.

The second semiconductor region 3 is provided on the front main surface 1 a side of the semiconductor substrate 1. If the first semiconductor region 2 has a p-type conductivity type, the second semiconductor region 3 is formed to have an n-type conductivity type. In the case of forming the second semiconductor region 3 having n-type conductivity, it can be formed by diffusing a dopant element such as phosphorus on the front main surface 1 a side of the semiconductor substrate 1. At this time, a portion other than the second semiconductor region 3 in the semiconductor substrate 1 can be the first semiconductor region 2.

  Further, the uneven portion 6 is disposed on the front main surface 1 a of the semiconductor substrate 1. Here, the height of the projections in the uneven portion 6 may be, for example, about 0.1 to 10 μm, and the width of the projections may be, for example, about 1 to 20 μm. Moreover, the surface shape of the recessed part of the uneven part 6 should just be substantially spherical shape, for example.

  Passivation portion 4 a is disposed in direct contact with at least back main surface 1 b of semiconductor substrate 1. That is, the passivation portion 4 a is disposed on the back main surface 1 b side of the first semiconductor region 2. As a material of the passivation portion 4a, for example, silicon oxide or aluminum oxide may be employed. The effects of the passivation portion 4a include the electric field passivation effect by the built-in electric field (the formation of an electric field near the interface by the presence of the passivation portion 4a) and the passivation effect (chemical passivation) by terminating dangling bonds at the interface. There is. Here, the electric field passivation effect means that the larger the fixed charge density of the passivation portion 4a, the more effective the effect. For example, for p-type silicon, the passivation unit 4a preferably has a larger negative fixed charge density. Further, chemical passivation means that the smaller the interface state density, the more effective. When the passivation portion 4 a is present, recombination of minority carriers in the back major surface 1 b of the semiconductor substrate 1 is reduced by the above effect. Thereby, the open circuit voltage and the short circuit current of the solar cell element 10 are increased, and thus the output characteristics of the solar cell element 10 are improved. The average value of the thickness of the passivation portion 4a may be, for example, about 3 to 100 nm. The passivation portion 4 a may be formed on the front main surface 1 a side of the semiconductor substrate 1.

  As shown in FIG. 3, the non-passivation portion 4 b is a large number of regions where the passivation portion 4 a is not formed on the back major surface 1 b of the semiconductor substrate 1. The non-passivation portion 4 b functions as a contact hole for obtaining an electrical contact between the back surface current collecting electrode 8 b provided on the passivation portion 4 a and the semiconductor substrate 1. That is, a part of the back surface current collection electrode 8b exists in the non-passivation portion 4b. The shape of the non-passivated portion 4 b may be hole-like (or dot-like) or groove-like (or line-like). The diameter (or width) of the non-passivated portion 4b may be 10 to 150 μm, and the pitch may be about 0.05 to 2.0 mm. In the case where the non-passivated portion 4b is formed in a hole shape (or in a dot shape), as shown in FIG. 4, the non-passivated portion 4b may be formed in a lattice shape. It may be formed into a shape.

  The antireflective layer 5 has a role of reducing the reflection of light in the solar cell element 10. The antireflection layer 5 is disposed on the front main surface 1 a side of the semiconductor substrate 1. The material of the antireflective layer 5 may be, for example, silicon nitride or silicon oxide. The thickness of the antireflective layer 5 may be appropriately set according to the materials of the semiconductor substrate 1 and the antireflective layer 5. Thereby, in the solar cell element 10, the conditions which are hard to reflect with respect to the light of a specific wavelength area are realized. The above-mentioned "light of a specific wavelength range" refers to a wavelength range before and after the peak wavelength of the irradiation intensity of sunlight. When the semiconductor substrate 1 is a crystalline silicon substrate, the refractive index of the antireflective layer 5 may be, for example, about 1.8 to 2.3, and the average value of the thickness of the antireflective layer 5 is For example, it may be about 20 to 120 nm. The antireflection layer 5 may be provided on the side surface 1 c side of the semiconductor substrate 1.

  The front surface electrode 7 is disposed on the front main surface 1 a side of the semiconductor substrate 1. As shown in FIG. 1, the surface electrode 7 includes, for example, a plurality of surface bus bar electrodes 7a and a large number of linear surface finger electrodes 7b. At least a part of the surface bus bar electrodes 7a is electrically connected to the plurality of surface finger electrodes 7b by intersecting with the plurality of linear surface finger electrodes 7b. The width of the surface finger electrode 7b in the short direction may be, for example, about 50 to 200 μm. The width of the surface bus bar electrode 7a in the short direction may be, for example, about 1.3 to 2.5 mm. That is, the width in the lateral direction of the surface finger electrode 7b may be smaller than the width in the lateral direction of the surface bus bar electrode 7a. The distance between adjacent surface finger electrodes 7b among the plurality of surface finger electrodes 7b may be about 1 to 3 mm. Furthermore, the thickness of the surface electrode 7 may be, for example, about 10 to 40 μm. A surface auxiliary electrode 7c having the same shape as that of the surface finger electrode 7b may be provided on the peripheral portion of the semiconductor substrate 1 to electrically connect the surface finger electrodes 7b. In addition, silver, copper or the like is mainly used as the material of the surface electrode 7.

  The back electrode 8 is disposed on the back main surface 1 b side of the semiconductor substrate 1. As shown in FIG. 2, the back surface electrode 8 includes, for example, a plurality of back surface bus bar electrodes 8 a and a back surface current collecting electrode 8 b. The width in the short side direction of the back surface bus bar electrode 8a may be, for example, about 1.3 to 3 mm. Furthermore, the thickness of the back electrode 8 may be, for example, about 10 to 40 μm. In addition, silver, copper or the like is mainly used as a material of the back surface bus bar electrode 8a, and aluminum is mainly used as a material of the back surface current collection electrode 8b.

  The characterizing portion of the solar cell element 10 according to the embodiment of the present invention will be described. First, as shown in FIG. 2, in the back major surface 1 b of the semiconductor substrate 1, the solar cell element 10 has a region located at the peripheral portion as a first region 10 c and a region surrounded by the first region 10 c. The second area 10d is used. At this time, as shown in FIGS. 3 and 4, when the back major surface 1b of the semiconductor substrate 1 is viewed in plan, the planar area occupied by the passivation portion 4a in the first area 10c with respect to the planar area of the first area 10c. The ratio of is smaller than the ratio of the plane area occupied by the passivation portion 4a in the second area 10d to the plane area of the second area 10d.

  The ratio of the planar area occupied by the passivation part 4a in each area to the planar area of each area (the first area 10c and the second area 10d) is the same as that of the passivation part 4a in each area of the solar cell element 10. The ratio is calculated by the ratio of the planar area of the passivation portion 4a to the total planar area of the passivation portion 4b. For example, the ratio is calculated by obtaining a planar area occupied by the passivation portion 4a in a region of 5 mm × 5 mm or the like.

  With the above-described structure, the contact resistance between the back surface current collecting electrode 8b and the semiconductor substrate 1 is reduced in the first region 10c compared to the second region 10d, and the current collection efficiency is improved. In the solar cell module 20 described later, as shown in FIG. 8, incident light between the solar cell elements 10 is irregularly reflected, for example, by unevenness (not shown) on the surface of the back surface filler 25, and part of the reflected light is The light is reflected again by the transparent member 23 and is incident on the first area 10 c which is the peripheral portion of the solar cell element 10 (hereinafter referred to as multiple reflection). For this reason, more carriers are generated in the first area 10c than in the second area 10d. Then, since the first region 10c has a high current collection efficiency, generated carriers are efficiently collected to the back surface current collection electrode 8b, and the output characteristics of the solar cell element 10 are improved.

The range from the end of the solar cell element 10 to the distance W is the first region 10c, and may be, for example, about 5 to 15 mm. When a single crystal silicon substrate whose corner is an arc or the like is used as the semiconductor substrate 1, the range from the end to the distance W and the range from each end face of the corner to the distance W are the first region 10c. . The distance W may be determined by the thickness of the transparent member 23 and the surface filler 24 of the solar cell module 20. For example, of the light incident between the solar cell elements 10, when the light amount reaching the solar cell element 10 by multiple reflection is 10% or more of the light incident between the solar cell elements 10, the solar cell element The reflection angle of light incident on 10 is light of about 55 to 60 °. Therefore, when the total thickness of the transparent member 23 and the surface filler 24 is, for example, 4 mm, the distance W is about 13.8 (= 2 × 4 × tan 60 °) mm. When the total thickness of the transparent member 23 and the surface filler 24 is, for example, 1.5 mm, the distance W is about 5.2 (= 2 × 1.5 × tan 60 °) mm.

  Due to the multiple reflection, when the light incident on the solar cell element 10 is 10% or more, recombination loss is more likely to occur in the first region 10c than in the second region 10d. Therefore, the output characteristics of the solar cell module 20 are reduced. Therefore, it is preferable to provide the first region 10c in a range of 10% or more of light incident on the solar cell element 10 by multiple reflection.

  Further, the ratio of the planar area occupied by the passivation portion 4a in the first region 10c to the planar area of the first region 10c is equivalent to the planar area occupied by the passivation portion 4a in the second region 10d with respect to the planar area of the second region 10d. 10 to 50% of the ratio of The ratio of the plane area occupied by the passivation portion 4a in the first area 10c to the plane area of the first area 10c may be determined by the distance between the solar cell elements 10 in the solar cell module 20. When the distance between the solar cell elements 10 is long, the amount of light incident upon multiple reflection in the first region 10c increases and the amount of carriers generated increases, so the passivation portion 4a is larger than the planar area of the first region 10c. It is preferable to reduce the ratio of the plane area occupied in the first region 10c.

  Further, as shown in FIGS. 4A and 4B, it is preferable that the average distance between the non-passivated portions 4b adjacent to each other is smaller in the first region 10c than in the second region 10d. The average distance is the distance between the centers of the respective holes when the non-passivated portion 4b is in the shape of a hole, and the distance between the center lines of the respective grooves when the non-passivated portion 4b is in the shape of a groove. is there. And an average space | interval is the value which averaged the length of all the space | intervals in the non-passivation part 4b of ten places of adjacent hole shape, for example. By narrowing the distance between the non-passivated portions 4b adjacent to each other in the first region 10c, the contact resistance between the back surface current collecting electrode 8b and the semiconductor substrate 1 can be lowered to improve the current collection efficiency. The average distance between the non-passivated portions 4b adjacent to each other may be smaller by about 10 to 50% of the second region 10d in the first region 10c for the same reason as described above.

  Due to the multiple reflection, when the light incident on the solar cell element 10 is 10% or more, recombination loss is more likely to occur in the first region 10c than in the second region 10d. Further, the total reflection angle between the transparent member 23 and the air is about 40 to 43 degrees. The light that is multi-reflected at these angles has a larger amount of incident light and a larger amount of carriers generated than the light incident on the solar cell element 10. Therefore, it should be smaller by 10% or more. In addition, when the ratio of the planar area of the passivation portion 4 a is smaller than 50% in the first region 10 c than in the second region 10 d, the electric field passivation effect by the passivation layer 4 is reduced, and the solar cell module 20 is Output characteristics are degraded. From the above, the ratio of the plane area occupied by the passivation portion 4a in the first area 10c to the plane area of the first area 10c is equal to the ratio of the plane area of the second area 10d to the second area 10d. It is preferable that the ratio of the area occupied by the plane area be as small as about 10 to 50%.

Further, as shown in FIGS. 4A and 4C, the average plane area of the non-passivated portion 4b is preferably such that the first region 10c is wider than the second region 10d. The average plane area is, for example, a value obtained by dividing the area of all non-passivated portions 4b in the adjacent ten hole-shaped non-passivated portions 4b by the number of non-passivated portions 4b. First area 10c
In the above, the contact resistance between the back surface current collecting electrode 8b and the semiconductor substrate 1 in the first region 10c can be lowered by widening the planar area of each non-passivation portion 4b, and the current collection efficiency can be improved. The average plane area of the non-passivated portion 4b may be about 10 to 50% wider than the second region 10d for the same reason as described above.

  Moreover, as shown to Fig.5 (a), the average space | interval of said non-passivation part 4b to mutually adjacent | abut is from the center (center of solar cell element 10) of 2nd area | region 10d of back main surface 1b of semiconductor substrate 1. It is preferable for the direction of the first region 10c to be gradually or gradually reduced. Among the light incident between the solar cell elements 10, many carriers are generated also in the second area 10d near the first area 10c due to the multiple reflection. For this reason, the generated carriers are efficiently collected to the back surface current collection electrode 8b, and the output characteristics of the solar cell element 10 are further improved. However, it is preferable that the average interval on the first area 10 c side in the second area 10 d be larger than the average interval of the first area 10 c.

  Further, as shown in FIG. 5B, the average plane area of the non-passivated portion 4b is gradually increased from the center of the second region 10d of the back main surface 1b of the semiconductor substrate 1 toward the first region 10c. Or, it is preferable that the width is gradually increased. Among the light incident between the solar cell elements 10, many carriers are generated also in the second area 10d near the first area 10c due to the multiple reflection. For this reason, the generated carriers are efficiently collected to the back surface current collection electrode 8b, and the output characteristics of the solar cell element 10 are further improved. However, it is preferable that the average plane area on the first area 10 c side in the second area 10 d be narrower than the average plane area of the first area 10 c.

<Method of manufacturing solar cell element>
Next, an example of a method of manufacturing the solar cell element 10 will be described in detail.

  First, a substrate preparation process of the semiconductor substrate 1 (p-type polycrystalline silicon substrate) having the first semiconductor region (p-type semiconductor region) 2 will be described. The semiconductor substrate 1 is formed by, for example, an existing casting method. Although an example in which a p-type polycrystalline silicon substrate is used as the semiconductor substrate 1 will be described below, the semiconductor substrate 1 may have an n-type or a single crystal silicon substrate.

  First, a polycrystalline silicon ingot is manufactured by, for example, a casting method. Then, the ingot is sliced to a thickness of, for example, 250 μm or less. Thereafter, the surface of the semiconductor substrate 1 may be slightly etched with a solution such as NaOH, KOH, hydrofluoric acid or hydrofluoric-nitric acid in order to clean the mechanical damage layer and the contamination layer of the cut surface of the semiconductor substrate 1.

  Next, the uneven portion 6 is formed on the front major surface 1 a of the semiconductor substrate 1. As a method of forming the uneven portion 6, a wet etching method using an alkaline solution such as NaOH or an acid solution such as hydrofluoric-nitric acid, a dry etching method using RIE (Reactive Ion Etching) or the like can be used. The concave-convex portion 6 formed on the back major surface 1b side of the semiconductor substrate 1 may be removed as necessary, using a wet etching method.

  Next, the step of forming the second semiconductor region 3 is performed on the front main surface 1 a of the semiconductor substrate 1 having the concavo-convex portion 6 formed by the above steps.

In the second semiconductor region 3, a coating thermal diffusion method in which P ₂ O ₅ in a paste state is applied to the surface of the semiconductor substrate 1 for thermal diffusion, or a diffusion source of phosphorus oxychloride (POCl ₃ ) in a gas state Formed by the vapor phase thermal diffusion method or the like. The second semiconductor region 3 is formed to have a depth of about 0.2 to 2 μm and a sheet resistance of about 40 to 200 Ω / □. For example, in the vapor phase thermal diffusion method, the semiconductor substrate 1 is heat treated for about 15 to 30 minutes at a temperature of about 600 to 800.degree. C. in an atmosphere having a diffusion gas of POCl ₃ or the like to Form on the surface. Thereafter, the semiconductor substrate 1 is heat-treated for about 10 to 40 minutes at a high temperature of about 800 to 900 ° C. in an inert gas atmosphere such as argon or nitrogen, whereby phosphorus is diffused from the phosphorus glass to the semiconductor substrate 1 Second semiconductor region 3 is formed on front main surface 1 a of semiconductor substrate 1.

  Next, in the step of forming the second semiconductor region 3, when the second semiconductor region 3 is formed also on the back major surface 1b side, only the second semiconductor region 3 formed on the back major surface 1b side is Etch away. Thereby, the p-type conductivity type region is exposed on the back main surface 1b side. For example, only the back major surface 1b side of the semiconductor substrate 1 is immersed in a hydrofluoric-nitric acid solution to remove the second semiconductor region 3 formed on the back major surface 1b side. Thereafter, when forming the second semiconductor region 3, the phosphorus glass attached to the surface (the side of the front major surface 1a) of the semiconductor substrate 1 is etched away.

  As described above, the phosphorus glass is left on the front main surface 1a side and the second semiconductor region 3 formed on the back main surface 1b side is removed, whereby the second semiconductor region 3 on the front main surface 1a side is formed by the phosphorus glass. Can be eliminated or damage is reduced.

  Further, in the step of forming the second semiconductor region 3, a diffusion mask is previously formed on the back major surface 1b side, the second semiconductor region 3 is formed by vapor phase thermal diffusion method or the like, and then the diffusion mask is removed. You may A similar structure can be formed by this process as well. In this case, since the second semiconductor region 3 is not formed on the above-described back major surface 1 b side, the step of removing the second semiconductor region 3 on the back major surface 1 b side is unnecessary.

  The method of forming the second semiconductor region 3 is not limited to the above method, and a crystalline silicon film or the like including an n-type hydrogenated amorphous silicon film or a microcrystalline silicon film may be used, for example, using thin film technology. You may form.

  As described above, the semiconductor including the first semiconductor region 2 as the p-type semiconductor region, in which the second semiconductor region 3 as the n-type semiconductor region is disposed on the front main surface 1a side and the uneven portion 6 is formed on the surface The substrate 1 can be prepared.

  Next, on the back main surface 1b side of the semiconductor substrate 1, the passivation layer 4 to be the passivation portion 4a is formed. As a method of forming the passivation layer 4, for example, an atomic layer deposition (ALD) method or a plasma enhanced chemical vapor deposition (PECVD) method is used. At this time, the passivation layer 4 may be formed not only on the back major surface 1 b side but also on the front major surface 1 a side or the side surface 1 c side.

  When the ALD method is adopted, the semiconductor substrate 1 in which the second semiconductor region 3 is formed is placed in the chamber of the film forming apparatus. In a state where the semiconductor substrate 1 is heated in a temperature range of 100 to 250 ° C., the steps of supply of aluminum raw material, removal of aluminum raw material waste, supply of oxidant, supply of oxidant waste, are repeated several times to oxidize A passivation layer 4 having a desired thickness of aluminum is formed. As an aluminum raw material, for example, trimethylaluminum (TMA), triethylaluminum (TEA) or the like can be used, and as an oxidizing agent, for example, water, ozone gas or the like can be used.

  Further, a film of silicon nitride, silicon oxide or the like may be further formed on the aluminum oxide formed on the back major surface 1b by a method such as PECVD. Thus, it is possible to form the passivation layer 4 having both the interface passivation function of aluminum oxide and the function as a protective layer of silicon nitride, silicon oxide or the like.

  The passivation layer 4 is provided with a non-passivation portion 4 b which is a contact hole for obtaining an electrical connection between the back surface current collecting electrode 8 b and the silicon substrate 1. The non-passivated portion 4 b is formed by, for example, laser beam irradiation, etching after forming a patterned etching mask, or the like. When the non-passivated portions 4 b are formed by laser beam irradiation, the average distance between adjacent non-passivated portions 4 b adjusts the position of the laser beam. Thereby, the average space | interval of the non-passivation parts 4b adjacent to each other can be made into a desired value. In addition, the average plane area of the non-passivated portion 4b can be set to a desired value by adjusting the irradiation diameter of the laser beam. When the non-passivated portions 4b are formed using a patterned etching mask, the average spacing and average plane area of the non-passivated portions 4b adjacent to each other can be changed by changing the shape of the opening of the etching mask. It can be a value. By the above method, the non-passivated portion 4b shown in FIGS. 4 and 5 can be easily formed.

Next, the antireflective layer 5 is formed on the front main surface 1 a of the semiconductor substrate 1. As a method of forming the antireflective layer 5, for example, a PECVD method, an ALD method, a vapor deposition method, a sputtering method, or the like is employed. For example, in the case where the PECVD method is employed, a mixed gas of SiH ₄ gas and NH ₃ gas is diluted with N ₂ gas in a film forming apparatus, and is converted to plasma by glow discharge decomposition in a chamber. Silicon nitride is deposited on main surface 1a. Thereby, the antireflective layer 5 containing silicon nitride is formed. The temperature in the chamber at the time of deposition of silicon nitride may be, for example, about 500.degree. Then, the antireflective layer 5 is formed by a PECVD method other than the ALD method, a vapor deposition method, a sputtering method, or the like, whereby the antireflective layer 5 having a desired thickness is formed in a short time. Thereby, the productivity of the solar cell element 10 is improved.

  Next, the surface electrode 7 (surface bus bar electrode 7a and surface finger electrode 7b) and the back surface electrode 8 (back surface bus bar electrode 8a and back surface current collection electrode 8b) are formed as follows.

  The surface electrode 7 is produced using, for example, a metal powder containing silver as a main component, an organic vehicle, and a metal paste (first metal paste) containing a glass frit. First, the first metal paste is applied to the front main surface 1 a side of the semiconductor substrate 1. After this application, the solvent may be evaporated and dried at a predetermined temperature. Thereafter, the surface electrode 7 is formed by baking at a maximum temperature of 600 to 800 ° C. for several tens of seconds to several tens of minutes. A screen printing method etc. can be used as this application method. In addition, although the surface electrode 7 has the surface bus-bar electrode 7a and the surface finger electrode 7b, the surface bus-bar electrode 7a and the surface finger electrode 7b can be formed in one process by using the screen printing method.

  The back surface bus bar electrode 8a is manufactured using a metal powder containing silver as a main component, an organic vehicle, and a metal paste (second metal paste) containing a glass frit. First, the second metal paste is applied to the back major surface 1 b side of the semiconductor substrate 1. Thereafter, the back surface bus bar electrode 8a is formed by baking at a maximum temperature of 600 to 800 ° C. for several tens of seconds to several tens of minutes. A screen printing method etc. can be used as this application method.

  The back surface current collection electrode 8b is produced using a metal powder (a third metal paste) containing a metal powder containing aluminum as a main component, an organic vehicle and a glass frit. This third metal paste is applied onto the back major surface 1b so as to be in contact with a part of the previously applied second metal paste. At this time, coating may be performed on substantially the entire surface of the portion where the back surface bus bar electrode 8a is not formed on the back main surface 1b. By applying the third metal paste, the third metal paste is applied also on the back major surface 1b of the semiconductor substrate 1 located in the non-passivated portion 4b. A screen printing method etc. can be used as this application method. After this application, the solvent may be evaporated and dried at a predetermined temperature. The back surface current collection electrode 8b can be formed by baking the semiconductor substrate 1 to which the third metal paste is applied at a maximum temperature of 600 to 800 ° C. for several tens seconds to several tens minutes.

  The solar cell element 10 can be manufactured by the above steps.

<Solar cell module>
In the solar cell module 20 according to the embodiment of the present invention, when the back major surface 1b of the semiconductor substrate 1 is viewed in plan, the planar area occupied by the passivation portion 4a in the first area 10c with respect to the planar area of the first area 10c. The ratio of (1) is provided with one or more solar cell elements 10 smaller than the ratio of the plane area occupied by the passivation portion 4a in the second area 10d to the plane area of the second area 10d. For example, the solar cell module 20 may be provided with a plurality of solar cell elements 10 electrically connected. Such a solar cell module 20 is formed by connecting a plurality of solar cell elements 10 in series or in parallel, for example, when the electrical output of a single solar cell element 10 is small. And a practical electric output is taken out by combining a plurality of solar cell modules 20, for example. Below, an example in which the solar cell module 20 is equipped with the several solar cell element 10 is mentioned and demonstrated.

  As shown in FIG. 6, the solar cell module 20 is, for example, a laminate in which the transparent member 23, the front surface filling material 24, the plurality of solar cell elements 10, the wiring members 21, the back surface filling material 25 and the back surface protective material 26 are stacked. Is equipped. It is desirable that the solar cell elements 10 be disposed at an interval of about 1.5 to 4.0 mm. Here, the transparent member 23 is a member for protecting the light receiving surface of the solar cell module 20 that receives sunlight. The transparent member 23 may be, for example, a transparent flat member. As a material of the transparent member 23, for example, glass or the like is adopted. The surface filler 24 may be, for example, a transparent filler. Also, the back surface filler 25 may be, for example, a transparent or white filler. In addition, reflection of the light which injected between the solar cell elements 10 shown in FIG. 8 is the case where a white filler is used. As a material of the front surface filler 24 and the back surface filler 25, for example, ethylene / vinyl acetate copolymer (EVA) is adopted. The back surface protection material 26 is a member for protecting the solar cell module 20 from the back surface. As a material of the back surface protective material 26, for example, polyethylene terephthalate (PET) or polyvinyl fluoride resin (PVF) is adopted. The back surface protective material 26 may have a single layer structure or a laminated structure. At this time, the color of the back surface protective material 26 may be white.

  The wiring member 21 is a member (connection member) that electrically connects the plurality of solar cell elements 10. Among the plurality of solar cell elements 10 included in the solar cell module 20, the solar cell elements 10 adjacent to each other in one direction are the front surface electrode 7 of one solar cell element 10 and the back surface electrode 8 of the other solar cell element 10. Are connected by the wiring member 21. That is, when the solar cell element 10 shown in FIG. 3 is used, as shown in FIG. 7, the wiring member 21 is connected to the surface bus bar electrode 7 a and the back surface bus bar electrode 8 a of the solar cell element 10. Here, the thickness of the wiring member 21 may be, for example, 0.1 to 0.2 mm. The width of the wiring member 21 may be, for example, about 1 to 3 mm. Then, as the wiring member 21, for example, a member or the like in which the entire surface of the copper foil is covered with the solder is used.

  Further, among the plurality of solar cell elements 10 electrically connected in series, one end of the electrode of the first solar cell element 10 and one end of the electrode of the last solar cell element 10 are respectively output by the output extraction wiring 22 It is electrically connected to the terminal box 28 as an output extraction part. Although illustration is omitted in Drawing 7, as shown in Drawing 6, solar cell module 20 may be provided with frame 27 which holds the above-mentioned layered product from the circumference. As a material of the frame body 27, for example, aluminum or the like having both corrosion resistance and strength is adopted.

  In the solar cell module 20, when the back major surface 1b of the semiconductor substrate 1 is viewed in a plan view, the ratio of the planar area occupied by the passivation portion 4a to the first area 10c to the planar area of the first area 10c is the second area The solar cell element 10 has a smaller ratio of the planar area occupied by the passivation portion 4a in the second region 10d with respect to the planar area 10d. As shown in FIG. 8, light incident between the solar cell elements 10 is irregularly reflected by the unevenness of the surface of the back surface filling material 25. Thereby, the light reflected again on the surface of the transparent member 23 enters the first region 10c of the solar cell element 10, and more carriers are generated in the first region 10c than in the second region 10d. Then, since the first region 10 has a high current collection efficiency, the generated carriers are efficiently collected to the back surface current collection electrode 8 b, and the output characteristics of the solar cell module 20 are improved. In addition, even when the back surface filler 25 is transparent, the same result can be obtained by irregularly reflecting the surface of the back surface protective material 26.

  Moreover, when EVA is employ | adopted as a material of at least one of the surface filler 24 and the back surface filler 25, the acid acceptor containing magnesium hydroxide or a calcium hydroxide etc. may be added to this EVA. . As a result, the generation of acetic acid from EVA is reduced, so that the durability of the solar cell module 20 is improved, and the damage of the acetic acid on the passivation layer 4, the front electrode 7 and the back electrode 8 is further reduced. As a result, the reliability of the solar cell module 20 is secured for a long time.

<Method of manufacturing solar cell module>
Next, a method of manufacturing the solar cell module 20 will be described.

  First, the plurality of solar cell elements 10 are arranged in series and parallel at an interval of about 1.5 to 4 mm, and the solar cell elements 10 adjacent to each other are electrically connected by the wiring member 21. As a method of connecting the wiring members 21, a method such as soldering iron, hot air, laser, pulse heat or the like can be used. Wiring member 21 is soldered to surface bus bar electrode 7a and back surface bus bar electrode 8a by such a method. Further, among the plurality of solar cell elements 10 connected in series, an output extraction wiring 22 is connected to one end of the electrode of the first solar cell element 10 and one end of the electrode of the last solar cell element 10. The connection method of the output extraction wiring 22 is the same as the connection method of the wiring member 21.

  Next, after disposing the transparent member 23 and the surface filler 24, the solar cell element 10 connected by the wiring member 21 is disposed on the surface filler 24. Next, the back surface filler 25 and the back surface protective material 26 are sequentially laminated on the solar cell element 10 to produce a laminate. Next, the laminate is set in a laminating apparatus, decompressed, and heated at 100 to 200 ° C. for 15 minutes to 1 hour, for example, under pressure, to produce a solar cell panel.

  Next, the terminal box 28 is attached to the solar cell panel. Specifically, the terminal box 28 is attached on the back surface protection material 26 from which the output extraction wiring 22 is derived using an adhesive such as silicon. Then, the positive and negative output takeout wirings 22 are fixed to terminals (not shown) of the terminal box 28 by soldering or the like. Thereafter, a lid is attached to the terminal box 28.

  Finally, the frame 27 is attached to complete the solar cell module 20. Specifically, a frame 27 made of aluminum or the like is attached to the outer peripheral portion of the solar cell panel. The frame 27 can be attached, for example, by fixing its corner with a screw or the like. Thus, the solar cell module 20 is completed.

  The present invention is not limited to the above-described embodiment, and various changes, improvements, and the like can be made without departing from the scope of the present invention.

  For example, the back surface bus bar electrode 8a may be formed after the back surface current collection electrode 8b is formed. Further, back surface bus bar electrode 8 a may be in direct contact with semiconductor substrate 1, and passivation portion 4 a may be interposed between back surface bus bar electrode 8 a and semiconductor substrate 1.

  Moreover, after apply | coating each metal paste, you may bake and form the surface electrode 7 and the back surface electrode 8 simultaneously. Thereby, the productivity is improved, and the heat history applied to the semiconductor substrate 1 can be reduced, and the output characteristics of the solar cell element 10 and the solar cell module 20 can be improved.

  In addition, when the back surface current collection electrode 8b is formed by firing the third metal paste, the portion where the back major surface 1b of the semiconductor substrate 1 is in contact with the third metal paste is more than the first semiconductor region 2 A BSF (Back Surface Field) layer having p-type conductivity having a high dopant concentration may be formed.

DESCRIPTION OF SYMBOLS 1: Semiconductor substrate 1a: Front main surface 1b: Back main surface 1c: Side surface 2: First semiconductor region 3: Second semiconductor region 4: Passivation layer 4a: Passivation portion 4b: Non-passivation portion 5: Antireflection layer 6: Irregularities Part 7: Surface electrode 7a: Surface bus bar electrode 7b: Surface finger electrode 7c: Surface auxiliary electrode 8: Back surface electrode 8a: Back surface bus bar electrode 8b: Back surface current collecting electrode 10: Solar cell element 10a: Front surface 10b: Back surface 10c: first area 10d: second area 20: solar cell module 21: wiring member 22: output extraction wiring 23: transparent member 24: front surface filling material 25: back surface filling material 26: back surface protection material 27: frame 28: terminal box

Claims (7)

A semiconductor substrate having a front main surface and a back main surface located on the opposite side of the front main surface, and a first region located at a peripheral portion and the first region surrounded by the back main surface of the semiconductor substrate And a passivation portion provided on both sides of the second region,
In the back main surface of the semiconductor substrate, a large number of non-passivation portions without the passivation portion are provided in both the first region and the second region,
In a plan view of the back main surface of the semiconductor substrate, a ratio of a plane area occupied by the passivation portion in the first area to a plane area of the first area is a plane area of the second area. the passivation portion rather smaller than the ratio of the plane area occupied in the second region Te,
The semiconductor substrate has a first semiconductor region having a p-type conductivity type on the back major surface side, and does not have a second semiconductor region having an n-type conductivity type on the back major surface side.
The semiconductor substrate has a second semiconductor region having n-type conductivity in the table main surface,
The solar cell element whose said passivation part has a negative fixed charge density.   The solar cell element according to claim 1, wherein an average distance between the non-passivated portions adjacent to each other is smaller in the first region than in the second region.   The solar cell element according to claim 1, wherein an average plane area of the non-passivated portion is larger in the first region than in the second region.   The average distance between the non-passivated portions adjacent to each other is gradually or stepwise decreased from the center of the second region of the back main surface of the semiconductor substrate toward the first region. The solar cell element according to claim 2 or 3.   The average plane area of the non-passivated portion is gradually or stepwise increased in the direction from the center of the second region of the back main surface of the semiconductor substrate to the direction of the first region. Or the solar cell element as described in 3.   The solar cell element according to any one of claims 1 to 5, wherein the semiconductor substrate is made of silicon and the passivation portion is made of aluminum oxide.   A solar cell module comprising the solar cell element according to any one of claims 1 to 6.

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