JP6530446B2 - Semiconductor device and control method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a semiconductor device capable of suppressing the loss of power of a secondary battery when the charge path from the solar battery to the secondary battery is interrupted when controlling the charge from the solar battery to the secondary battery. It relates to a control method.

  As a charge control system for charging from a solar cell to a secondary battery, for example, as disclosed in Patent Document 1, backflow of current from the secondary battery to the solar cell is prevented, and from the solar cell to the secondary battery In order to reduce the loss of electric power when charging the battery, it is known to control the charging of the electric power from the solar cell to the secondary cell by a switch element.

  FIG. 10 schematically shows the charge control system disclosed in Patent Document 1. As shown in FIG. The system mainly includes a solar cell 1, a secondary battery 2, and a transmission path 3 connecting the solar battery 1 and the secondary battery 2. For convenience of explanation, the transmission path 3 connecting the positive electrode side of the solar cell 1 and the positive electrode side of the secondary cell 2 is referred to as a transmission path 3 H. The negative electrode side of the solar cell 1 and the negative electrode of the secondary cell 2 The transmission path 3 connecting to the side is distinguished as the transmission path 3L. The system further includes a transmission line 4 provided with a resistor R3 and a resistance R4 and connected to the transmission line 3H and the transmission line 3L, a resistor R1 and a resistance R2, and connected to the transmission line 3H and the transmission line 3L. And the transmission line 6. In the same system, the voltage of the secondary battery 2 divided by the resistors R3 and R4 of the transmission line 4 and the voltage of the solar cell 1 divided by the resistors R1 and R2 of the transmission line 6 And a P-type MOS transistor 12 provided on the transmission path 3H between the transmission path 4 and the transmission path 6 and blocking the transmission path 3 in accordance with the output of the comparator 7 ing. The secondary battery 2, the transmission line 3 and the transmission line 4 constitute a closed circuit.

  As the operation of the conventional system, the voltage of the secondary battery 2 divided by the resistors R3 and R4 of the transmission line 4 and the solar cell 1 divided by the resistors R1 and R2 of the transmission line 6 When the voltage difference between the voltage of the solar cell 1 and the voltage of the secondary battery 2 is equal to or greater than the specified value, the comparator 7 outputs a low level to output the P-type MOS transistor 12. Is turned on to charge the secondary battery 2 from the solar cell 1, and when the voltage difference between the voltage of the solar cell 1 and the voltage of the secondary battery 2 is less than the specified value, the comparator 7 outputs a high level Then, the P-type MOS transistor 12 is turned off to interrupt the charge from the solar cell 1 to the secondary cell 2.

JP-A-9-261861

  However, in the conventional charge control system as described above, when control is performed to turn off the switch element to shut off the charge from the solar cell to the secondary cell, the power of the secondary cell is wasted unnecessarily. There was a problem that. For example, in FIG. 10, when the P-type MOS transistor 12 is turned off, the current from the secondary battery 2 flows to the closed circuit formed by the secondary battery 2, the transmission path 3 and the transmission path 4. , Wasted consumption of the power of the secondary battery 2, that is, leading to loss.

  Therefore, the present invention provides a semiconductor device that suppresses the loss of power of the secondary battery when the charge path to the secondary battery is interrupted in order to solve the above-mentioned problems.

The semiconductor device according to the present invention is disposed between a first terminal to which one electrode of the secondary battery is electrically connected and a second terminal to which a charging voltage for charging the secondary battery is applied. Driving power is supplied from the first terminal and the second terminal, and the partial pressure of the secondary battery is compared with the partial voltage of the charging voltage, and the comparison result is output to the first a comparing unit for, was closed, partial pressures of and the charging voltage of the secondary battery is generated in response to a bias voltage driving power from the second terminal is output from the bias generator to be supplied And a voltage dividing circuit that generates a partial pressure of the secondary battery and cuts off a current path as the charging voltage decreases.

  According to the semiconductor device of the present invention, it is possible to suppress the loss of power of the secondary battery when the charge path to the secondary battery is interrupted.

It is a figure showing a 1st embodiment of a charge control system concerning the present invention. It is a figure which shows the concrete structure of the constant current bias production | generation part 80 concerning 1st Embodiment. It is a time chart which shows the charge condition of the charge control system concerning a 1st embodiment. It is a figure which shows the modification of the charge control system concerning 1st Embodiment. It is a figure which shows the other modification of the charge control system concerning 1st Embodiment. It is a figure showing a 2nd embodiment of a charge control system concerning the present invention. It is a figure which shows the concrete structure of the constant current bias production | generation part 80 concerning 2nd Embodiment. It is a figure which shows the modification of the charge control system concerning 2nd Embodiment. It is a figure which shows the other modification of the charge control system concerning 2nd Embodiment. It is a figure showing roughly the conventional charge control system indicated by patent documents 1.

  The charge control system according to the present invention will be described in detail below with reference to the drawings.

First Embodiment
FIG. 1 is a diagram showing a first embodiment of a charge control system according to the present invention.

  The charge control system according to the first embodiment includes a first transmission path 30 connected to the solar cell 10 and the solar cell 10 and transmitting the power output from the solar cell 10, and the first transmission path 30. A secondary battery 20 connected and receiving supply of power output from the solar battery 10, and a first transmission path 30, and a closed circuit 50 together with the first transmission path 30 and the secondary battery 20 Voltage based on the output from the solar cell 10, and voltage based on the output from the secondary battery 20 connected to the second transmission path 40 and transmitted via the second transmission path 40 And the first transmission path 30 is determined in the comparator 70 that the voltage output from the solar cell 10 is less than or equal to the voltage output from the secondary cell 20. The first transmission if The second transmission path 40 is provided with a P-type MOS transistor 120 as a first blocking portion for blocking 30. After the first transmission path 30 is blocked, the second transmission path 40 is connected to the second transmission path 40 as the power of the solar cell 10 decreases. It is characterized in that an N-type MOS transistor 42 is provided as a second blocking section for blocking the second transmission path 40.

  The charge control system according to the first embodiment will be described in detail below.

  The solar cell 10 is electrically connected to a solar panel (not shown) capable of absorbing sunlight, and is a power generation means capable of converting the absorbed sunlight into electric power.

  The secondary battery 20 is a storage battery having a function of storing power supplied from the solar cell 10.

  The first transmission path 30 transmits the power of the solar cell 10 to the secondary cell 20, and its start point 30a is on the positive electrode side of the solar cell 10 and its end point 30d is on the negative electrode side of the solar cell 10. The intermediate point 30 b is connected to the positive electrode side of the secondary battery 20, and the intermediate point 30 c is connected to the negative electrode side of the secondary battery 20. That is, the first transmission path 30 is configured as a closed circuit connecting the solar cell 10 and the secondary cell 20, and the power output from the solar cell 10 is transmitted through the first transmission path 30 to the secondary cell 20. Supplied to The low potential 30L side of the first transmission path 30 is, for example, the GND potential.

  Here, the first transmission path 30 is a transmission path connecting the positive electrode of the solar cell 10, the secondary cell 20, and the positive electrode for convenience of explanation, that is, the first transmission path from the starting point 30a to the middle point 30b. The transmission line 30 is referred to as the high potential 30H side, and is a transmission line connecting the negative electrode of the solar cell 10 and the negative electrode of the secondary cell 20, that is, the first transmission line 30 from the middle point 30c to the end point 30d. Is referred to as the low potential side 30L side. The first transmission path 30 is formed to be divided into a high potential 30H side and a low potential 30L side.

  The second transmission line 40 includes a resistance element 41 as a first resistance element and an N-type MOS transistor 42 as a second blocking portion, and the secondary battery 20 is formed on the first transmission line 30. And are connected in parallel. One end of the resistive element 41 is connected to the high potential 30H side of the first transmission path 30, and the N-type MOS transistor 42 is in series with the resistive element 41, and more specifically, the drain D is the other end of the resistive element 41 The source S is connected to the low potential 30 L side of the first transmission path 30. Thus, the second transmission line 40 is connected in parallel to the secondary battery 20, and constitutes a closed circuit 50 together with the first transmission line 30 and the secondary battery 20. In the second transmission path 40, the N-type MOS transistor 42 operates as a constant current source by a bias voltage VC supplied from a constant current bias generation unit 80 described later, and the resistance element 41 and the N-type MOS transistor 42 The voltage of the secondary battery 20 is divided.

  The third transmission path 60 is configured to include a resistive element 61 as a second resistive element and an N-type MOS transistor 62 as a third blocking portion, and the solar cell 10 side of the second transmission path 40 The first transmission line 30 is connected in parallel with the solar cell 10. One end of the resistive element 61 is connected to the high potential 30H side of the first transmission path 30, and the N-type MOS transistor 62 is in series with the resistive element 61, and more specifically, the drain D is the other end of the resistive element 61 The source S is connected to the low potential 30 L side of the first transmission path 30. Thus, the third transmission path 60 is connected in parallel to the solar cell 10, and forms a closed circuit together with the first transmission path 30 and the secondary cell 10. The third transmission path 60 operates as a constant current source by a voltage supplied from a constant current bias generation unit 80 described later by the N-type MOS transistor 62, and a solar cell is formed by the resistance element 61 and the N-type MOS transistor 62. The voltage of 10 is divided.

  The comparator 70 has an inverting input terminal (-) connected to the common connection point of the resistance element 41 and the N-type MOS transistor 42 constituting the second transmission path 40, and a non-inverting input terminal (+) has a third It is connected to the common connection point of the resistance element 61 and the N-type MOS transistor 62 which constitute the transmission path 60. Thereby, the voltage of the secondary battery 20 divided by the resistance element 41 and the N-type MOS transistor 42 is input to the inverting input terminal (−) of the comparator 70. Further, the voltage of the solar cell 10 divided by the resistance element 61 and the N-type MOS transistor 62 is input to the non-inversion input terminal (+) of the comparator 70.

  Here, for convenience of explanation, the voltage of the solar cell 10 is divided by VSC, the voltage of the solar cell 10 divided by the resistance element 61 and the N-type MOS transistor 62 is input solar cell voltage VSCin, the resistance element 41 and the N-type MOS transistor The voltage of the secondary battery 20 divided by 42 is defined as an input secondary battery voltage VDDin.

  The comparator 70 compares the input solar battery voltage VSCin with the input secondary battery voltage VDDin, and outputs “high” when “VSCin> VDDin”, and outputs “low” when “VSCin ≦ VDDin”. Do.

  The constant current bias generation unit 80 is connected to the high potential 30H side of the first transmission path 30, receives power supply from the solar cell 10, and generates a bias voltage generated using the power supplied from the solar cell 10. VC is applied to the gate G of the N-type MOS transistor 42. The bias voltage VC generated by the constant current bias generation unit 80 is also applied to the gate G of the N-type MOS transistor 62, that is, as a current mirror connection to the N-type MOS transistor 42 and the N-type MOS transistor 62. There is. Such current mirror connections are clarified in FIG. 2 below. When such current mirror connection is used, the bias voltage VC can be applied from the constant current bias generation unit 80 to the gates G of the N-type MOS transistor 42 and the N-type MOS transistor 62 at the same timing. The partial pressure applied to the voltage of the secondary battery 20 supplied to the comparator 70 via the transmission line 40 of FIG. 1 and the voltage of the solar cell 10 supplied to the comparator 70 via the third transmission line 60 , At the same time and at the same rate.

  In the first embodiment, the constant current bias generation unit 80 applies the bias voltage VC to the gate G of the N-type MOS transistor 42 and the N-type MOS transistor 62 using the power supplied from the solar cell 10. Therefore, when the charge control system is disposed, for example, in the dark, and the supply of power from the solar cell 10 is lost, the constant current bias generation unit 80 generates the N-type MOS transistor 42 and the N-type MOS transistor 62 The application of the voltage to the gate G is stopped. When the application of the voltage from the constant current bias generation unit 80 is stopped, the N-type MOS transistor 42 and the N-type MOS transistor 62 are turned off, so the second transmission path 40 and the third transmission path 60 are No current flows.

  One end of a resistive element 90 as a third resistive element is connected to the high potential 30H of the first transmission path 30.

  In the N-type MOS transistor 100, the drain D as one end is connected to the other end of the resistance element 90, the source S as the other end is connected to the low potential 30L side of the first transmission path 30, and the output of the comparator 70 is It is configured to be applied to the gate G. The connection point between the resistance element 90 and the N-type MOS transistor 100 is referred to as a “connection point 110” for the sake of convenience.

  The P-type MOS transistor 120 plays a role of a switch element that shuts off the conductive path of the first transmission path 30 to stop the supply of power from the solar cell 10 to the secondary cell 20 under certain conditions. The P-type MOS transistor 120 is located closer to the solar cell 10 than the connection point between the resistive element 90 and the first transmission line 30 and two more than the connection point between the third transmission line 60 and the first transmission line 30. It is connected in series to the high potential 30H side of the first transmission line 30 on the secondary battery 20 side. In other words, the resistive element 90 is connected to the high potential 30 H side of the first transmission path 30 and to the secondary battery 20 side more than the P-type MOS transistor 120. In the P-type MOS transistor 120, the source S is connected to the secondary battery 20 side, the drain D is connected to the solar cell 10 side, and the gate G is a connection point 110 between the drain D of the N-type MOS transistor 100 and the resistance element 90. It is connected to the. The P-type MOS transistor 120 turns on and off the first transmission path 30 according to the output of the comparator 70. More specifically, in the P-type MOS transistor 120, when the output from the comparator 70 is at high level, the N-type MOS transistor 100 is turned on, and the potential at the connection point 110 is the low potential 30L side of the first transmission path 30. It is almost the same as the above, whereby a low level is applied to the gate G to turn it on. On the other hand, when the output of the comparator 70 is at low level, the N-type MOS transistor 100 is turned off and the connection point 110 has the same potential as that of the secondary battery 20, thereby applying high level to the gate G to turn off. . That is, the P-type MOS transistor 120 performs on / off operation according to the potential between the resistive element 90 and the N-type MOS transistor 100 which fluctuates according to the operation of the N-type MOS transistor 100. While the P-type MOS transistor 120 is on, charging of power from the solar cell 10 to the secondary battery 20 is performed, and the charging is not performed while the P-type MOS transistor 120 is off.

  FIG. 2 shows a specific circuit configuration of the constant current bias generation unit 80 used in the first embodiment.

  The constant current bias generation unit 80 used in the first embodiment is connected to the first transmission path, and includes a first current mirror circuit 81, a second current mirror circuit 82, and a resistor R1. There is. The first current mirror circuit 81 is composed of a P-type MOS transistor P1 and a P-type MOS transistor P2. The second current mirror circuit 82 is composed of an N-type MOS transistor N1 and an N-type MOS transistor N2.

  Each of the P-type MOS transistor P1 and the P-type MOS transistor P2 is connected to the high potential 30H side of the first transmission path 30. Specifically, the source S is connected to the high potential 30H side of the first transmission path 30, and the gates G of the two are commonly connected to the drain D of the P-type MOS transistor P1.

  The drain D of the N-type MOS transistor N1 is connected to the drain D of the P-type MOS transistor P1, and the drain D of the N-type MOS transistor N2 is connected to the drain D of the N-type MOS transistor. The source S of the N-type MOS transistor N2 is connected to the low potential 30L side of the first transmission path 30, and the gates G of the N-type MOS transistor N1 and the N-type MOS transistor N2 are commonly connected. Furthermore, both gates G are commonly connected to the drain D of the N-type MOS transistor N2. The gates G of the N-type MOS transistor N1 and the N-type MOS transistor N2 are current mirror connected to the gates G of the N-type MOS transistor 42 and the N-type MOS transistor 62, respectively.

  One end of the resistor R1 is connected to the source S of the N-type MOS transistor N1, and the other end is connected to the low potential 30L side of the first transmission path 30.

  The bias voltage VC output from the constant current bias generation unit 80 having the above configuration is applied to the gates G of the N-type MOS transistor 42 and the N-type MOS transistor 62. The bias voltage VC applied to the N-type MOS transistor 42 and the N-type MOS transistor 62 is the electrical characteristics of the above-described P-type MOS transistor P1, P-type MOS transistor P2, N-type MOS transistor N1 and N-type MOS transistor N2. , And can be set appropriately by the resistor R1.

  FIG. 3 is a time chart showing the charge state of the charge control system according to the first embodiment. The operation of the charge control system according to the first embodiment will be described based on FIG.

  FIG. 3 shows temporal changes of the input solar battery voltage VSCin and the input secondary battery voltage VDDin input to the comparator 70, with the vertical axis representing the magnitude V and the horizontal axis representing the time lapse T, respectively. The voltage VSCin and the voltage VDDin are indicated by reference signs Y1 (solid line) and Y2 (dotted line), respectively.

  In periods T1, T2, T3, T4 and T5 shown in FIG. 3, times F, S, TH and FO respectively indicate the time of the boundary of periods T1-T2, T2-T3, T3-T4 and T4-T5, respectively. Time FI represents the end of the period T5.

  In the period T1, the solar cell 10 generates a large amount of sunlight and constant power generation is performed. Therefore, a constant voltage is applied from constant current bias generation unit 80 to each gate G of N-type MOS transistor 42 and N-type MOS transistor 62, and N-type MOS transistor 42 and N-type MOS transistor 62 are turned on. The current from the secondary battery 20 flows through the second transmission path 40, and the current from the solar cell 10 flows through the third transmission path 60. Further, in the period T1, “VSC> VDD” is established between the voltage VSC of the solar cell 10 and the voltage VDD of the secondary cell 20. In this case, “VSCin> VDDin” is established between the input solar battery voltage VSCin and the input secondary battery voltage VDDin. Therefore, the comparator 70 outputs a high level, which turns on the N-type MOS transistor 100 to make the potential at the connection point 110 equal to the potential at the low potential 30 L side. A low level is applied to turn on the P-type MOS transistor 120, and the power of the solar cell 10 is supplied to the secondary cell 20 via the first transmission path 30.

  In the period T2 to T4, the solar panel is not exposed to sunlight or hardly hit by a shade or the like, whereby the voltage VSC of the solar cell 10 decreases with time.

  When time F is reached and period T2 is reached, “VSC> VDD” is established between the voltage VSC of the solar cell and the voltage VDD of the secondary cell 20. In this case, the current from the solar cell 10 flows in the second transmission path 40 and the current from the secondary battery 20 flows in the third transmission path 60 as in the case of the period T1. In this case, “VSCin> VDDin” is established between the input solar battery voltage VSCin and the input secondary battery voltage VDDin. Therefore, as in the case of the period T1, the P-type MOS transistor 120 is turned on, and the power of the solar cell 10 is supplied to the secondary cell 20 via the first transmission path 30.

  On the other hand, at time S, “VSCin = VDDin” holds between the input solar battery voltage VSCin and the input secondary battery voltage VDDin. And in periods T3 and T4 after time S, “VSCin <VDDin” is established between the input solar battery voltage VSCin and the input secondary battery voltage VDDin.

  In the period T3, “VSCin ≦ VDDin” is established between the input solar battery voltage VSCin and the input secondary battery voltage VDDin. For this reason, when it becomes time S and "VSCin = VDDin", the comparator 70 outputs a low level, whereby the N-type MOS transistor 100 is turned off and the potential of the connection point 110 becomes the secondary battery 20. Since the potential is equal, a constant voltage is applied to the gate G of the P-type MOS transistor 120 to turn off the P-type MOS transistor 120, and a power supply path from the solar cell 10 to the secondary cell 20 The transmission line 30 of 1 is cut off.

  However, in the conventional charge control circuit, after time S when the first transmission path 30, which is a supply path of power from the solar cell 10 to the secondary cell 20, is cut off, the secondary cell 20 and the second Because the transmission line 40 is a closed circuit via the first transmission line 30, there is a problem that the current of the secondary battery 20 flows out toward the second transmission line 40. . For this reason, during a period when solar light is not applied to the solar panel and after time S, the power of the secondary battery 20 continues to be consumed wastefully, leading to a loss of power of the secondary battery 20. The

  On the other hand, in the charge control system according to the first embodiment, the power of the solar cell 10 is further reduced after the first transmission path 30 is cut off as the power of the solar cell 10 is reduced, and the voltage VSC is thus reduced. At time TH when the voltage becomes 0 V, and during a period T4 after the same time, the constant current bias generation unit 80 connected to the first transmission path 30 operates using the power of the solar cell 10 to the second transmission path The supply of power to the gates G of the N-type MOS transistor 40 of 40 and the N-type MOS transistor 62 of the third transmission path 60 is stopped. When the supply of power from the constant current bias generation unit 80 is stopped, both the N-type MOS transistor 42 and the N-type MOS transistor 62 are turned off. Therefore, the second transmission path 40 is an N-type MOS transistor. The third transmission path 60 is cut off by the N-type MOS transistor 62. Therefore, the secondary battery 20 and the second transmission line 40 do not have a closed circuit, and the power of the secondary battery 20 does not flow out toward the second transmission line 40. Power consumption can be reduced.

  In period T3 after time S and before time TH, "VSCin <VDDin" holds between input solar cell voltage VSCin and input secondary cell voltage VDDin as in the case of period T2. There is. At this time, the P-type MOS transistor 120 is turned off, and the first transmission path 30 which is a supply path of power from the solar cell 10 to the secondary cell 20 is cut off. In this case, since the solar cell 10 is not at 0 V in the period T3, the N-type MOS transistor 42 is on, and the power of the secondary cell 20 flows out toward the second transmission path 40. I will. However, since the time from time S to time TH, that is, the time until the voltage VSC of the solar cell 10 becomes 0 V after the sunlight does not reach the solar panel is less than one second, the secondary of that period is The power loss of the battery 20 is substantially negligible.

  When the time FO comes, the solar panel is again exposed to sunlight. Therefore, a constant voltage is applied from the constant current bias generation unit 80 to the gates G of the N-type MOS transistor 42 and the N-type MOS transistor 62, and the N-type MOS transistor 42 and the N-type MOS transistor 62 are turned on. The current from the solar cell 10 flows through the second transmission line 40, and the current from the secondary battery 20 flows through the third transmission line 60. Then, at time FI after a period T5, “VSCin> VDDin” holds again between the input solar battery voltage VSCin and the input secondary battery voltage VDDin. Therefore, the P-type MOS transistor 120 is turned on again, and the power of the solar cell 10 is supplied to the secondary cell 20 via the first transmission path 30.

  As described above, according to the charge control system according to the first embodiment, the closed circuit 50 is configured together with the first transmission path 30 and the secondary battery 20 as the power of the solar cell 10 decreases. By interrupting the second transmission path 40, the current of the secondary battery 20 is constituted by the first transmission path, the secondary battery, and the second transmission path when the first transmission path 30 is interrupted. Since the problem of continuing to flow in a closed circuit is eliminated, the loss of power of the secondary battery 20 can be suppressed.

  The driving power of the comparator 70 is preferably supplied from the solar cell 10 via the fourth transmission path 130 connected to the first transmission path 30 as shown in FIG. 1. The reason is that, firstly, if another voltage source is used as a drive power supply for the comparator 70, the area and volume of the charge control system will increase accordingly, and secondly, if the secondary battery 20 is used. Therefore, even if the P-type MOS transistor 120 is turned off, the driving power is supplied from the secondary battery 20 to the comparator 70, and the power loss of the secondary battery 20 is caused. It is because the problem of connecting arises. In view of the above, in the first embodiment, the drive power of the comparator 70 is supplied from the solar cell 10 to eliminate the occurrence of the above two problems.

  Preferably, resistance element 41 and resistance element 61 are formed to have the same resistance value, and N-type MOS transistor 42 and N-type MOS transistor 62 are preferably formed to have the same characteristics. The reason is that the voltage of the secondary battery 20 supplied to the comparator 70 via the second transmission line 40 and the voltage of the solar cell 10 supplied to the comparator 70 via the third transmission line 60. It is because the partial pressure to be made can be provided at the same rate.

  Moreover, it is preferable that the resistive element 41 or 61 is a variable resistance. This is because at least one of them is a variable resistor, and even when the resistor element 41 and the resistor element 61 are formed with different resistors, one of the resistance values is adjusted to adjust the resistor element 41. And the resistance element 61 can have the same resistance value. In addition, even when the comparator 70 has an input offset voltage, it is possible to adjust any resistance value to change the voltage division ratio and cancel the input offset voltage of the comparator 70.

  The P-type MOS transistor 120 is not provided on the low potential side 30L of the first transmission path 30, but is provided on the high potential 30H side. This is because, when the P-type MOS transistor 120 is provided on the low potential 30L side of the first transmission path 30, the source S of the P-type MOS transistor 120 is at the GND potential (0 V). This is because the voltage applied to the gate G of the MOS transistor 120 does not become less than 0 V, that is, the negative potential does not occur, which causes a problem that the P-type MOS transistor is not turned on.

  In the first embodiment, on / off of the P-type MOS transistor 120 is controlled via the resistance element 90 and the N-type MOS transistor 100. The reason is that when the output of the comparator 70 is simply directly input to the gate G of the P-type MOS transistor 120, the normal operation of the P-type MOS transistor 120 can not be realized. The reason is that the output of the comparator 70 is directly input to the gate G of the P-type MOS transistor 120, and the driving power of the comparator 70 is connected in parallel to the first transmission path 30. When the configuration is adopted in which the solar cell 10 supplies the voltage via the transmission line 130, the voltage supplied from the comparator 70 to the gate G of the P-type MOS transistor 120 becomes the voltage of the solar cell 10, while The voltage supplied to the source S of the MOS transistor 120 is the voltage of the secondary battery 20. Thereby, even if the solar cell 10 becomes 0 V, the potential of the gate G and the potential of the drain D still do not become the same potential, so the P-type MOS transistor 120 does not turn off.

  FIG. 4 shows a modification of the charge control system according to the first embodiment. In the present modification, in FIG. 4, the same components as those of the charge control system shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  First, the charge control system shown in FIG. 4 and the charge control system shown in FIG. 1 are P-type as a first MOS transistor instead of the resistance element 41 connected to the second transmission path 40. A MOS transistor 43 is provided, and secondly, in place of the resistance element 61 connected to the third transmission path 60, a P-type MOS transistor 63 as a second MOS transistor is provided. It is different.

  The P-type MOS transistor 43 is connected in series to the N-type MOS transistor 42 in the second transmission path 40. Specifically, the source S of the P-type MOS transistor 43 is connected to the high potential 30H side of the first transmission path 30, and the gate G and the drain D of the P-type MOS transistor 43 are common to the drain D of the N-type MOS transistor 42 The gate G of the P-type MOS transistor 43 and the drain D of the N-type MOS transistor 42 are formed at the same potential. By using the P-type MOS transistor 43, it is possible to divide the secondary battery 20 by a larger amount with a smaller constant current as compared to the case of using the resistance element 41. In the second transmission path 40, when it is intended to divide the secondary battery 20 with a smaller constant current, a relatively large circuit area is required because it is necessary to make the resistance high when the resistance element 41 is used. Needed. However, as shown in the present modification, if the constant current source circuit is configured only with the MOS transistor without using the resistance element 41, the constant size of the MOS transistors can be adjusted by adjusting the physical size of each other. The secondary battery 20 can be divided by this small constant current.

  The P-type MOS transistor 63 is connected in series to the N-type MOS transistor 62 in the third transmission path 60. Specifically, the source S of the P-type MOS transistor 63 is connected to the high potential 30H side of the first transmission path 30, and the gate G and the drain D of the P-type MOS transistor 43 are common to the drain D of the N-type MOS transistor 62. The gate G of the P-type MOS transistor 43 and the drain D of the N-type MOS transistor 62 are formed at the same potential. The merit of using the P-type MOS transistor 63 instead of the resistance element 61 in the third transmission path 60 is that the P-type MOS transistor 43 is used instead of the resistance element 41 in the second transmission path 40. Is the same as

  FIG. 5 is a view showing another modification of the charge control system according to the first embodiment. In the present modification, in FIG. 5, the parts having the same configurations as those of the charge control system shown in FIG. 1 or FIG.

  The charge control system according to the present modification includes a solar cell 10, a secondary cell 20, and a semiconductor chip 140.

  The semiconductor chip 140 is formed to include at least a first transmission line 30, a second transmission line 40, a third transmission line 60, a comparator 70, a constant current bias generation unit 80, and a P-type MOS transistor 120. . Specifically, the semiconductor chip 140 includes an electrode 150 a and an electrode 150 b as a first electrode electrically connected to the solar cell 10, and an electrode 150 c as a second electrode electrically connected to the secondary battery 20. And a first transmission path 30 which is electrically connected to the electrode 150d, the electrode 150a, the electrode 150b, the electrode 150c, and the electrode 150d, and transmits the power output from the solar cell 10 to the secondary cell 20; A second transmission path 40 connected to the first transmission path 30 and the secondary battery 20 to form a closed circuit 50, a voltage based on the output from the solar cell 10, and a second transmission path And a comparator 70 for comparing the voltage based on the output from the secondary battery 20 which is connected to the second transmission path 40 and transmitted via the second transmission path 40, and the first transmission path 30 is connected to the comparator 70. A P-type MOS transistor 120 for interrupting the first transmission path 30 when it is determined that the voltage output from the solar cell 10 is equal to or less than the voltage output from the secondary cell 20; The reference numeral 40 includes an N-type MOS transistor 42 that cuts off the second transmission path 40 as the power of the solar cell 10 decreases after the first transmission path 30 is cut off.

  The electrode 150 a is electrically connected to the positive electrode side of the solar cell 10 and electrically connected to the high potential 30 H side of the first transmission path 30 formed in the semiconductor chip 140. The electrode 150 b is electrically connected to the negative electrode side of the solar cell 10 and electrically connected to the low potential 30 L side of the first transmission path 30 formed in the semiconductor chip 140. The electrode 150 c is electrically connected to the positive electrode side of the secondary battery 20 and electrically connected to the high potential 30 H side of the first transmission path 30 formed in the semiconductor chip 140. The electrode 150 d is electrically connected to the negative electrode side of the secondary battery 20 and electrically connected to the low potential 30 L side of the first transmission path 30 formed in the semiconductor chip 140. As described above, the semiconductor chip 140 and the solar cell 10 are electrically connected through the electrode 150a and the electrode 150b, and the semiconductor chip 140 and the secondary cell 20 are electrically connected through the electrode 150c and the electrode 150d. .

  Although FIG. 5 shows the case where the resistive element 41 is adopted for the second transmission path 40 and the resistive element 61 is adopted for the third transmission path 60, the second transmission path 40 is As shown in FIG. 4, a P-type MOS transistor 43 is employed in place of the resistance element 41, and a P-type MOS transistor is used in the third transmission path 60 in place of the resistance element 61 as shown in FIG. 63 may be adopted.

Second Embodiment
FIG. 6 is a diagram showing a second embodiment of the charge control system according to the present invention. In the second embodiment, in FIG. 6, the same components as those of the charge control system shown in FIG. 1 are denoted by the same reference numerals and the description thereof will be omitted.

  The charge control system according to the second embodiment includes a first transmission path 30 connected to the solar cell 10 and the solar cell 10 and transmitting the power output from the solar cell 10, and the first transmission path 30. A secondary battery 20 connected and receiving supply of power output from the solar battery 10, and a first transmission path 30, and a closed circuit 50 together with the first transmission path 30 and the secondary battery 20 Voltage based on the output from the solar cell 10, and voltage based on the output from the secondary battery 20 connected to the second transmission path 40 and transmitted via the second transmission path 40 And the first transmission path 30 is determined in the comparator 70 that the voltage output from the solar cell 10 is less than or equal to the voltage output from the secondary cell 20. The first transmission if The second transmission path 40 is provided with the N-type MOS transistor 120a as a first blocking portion for blocking 30 and the second transmission path 40 is connected to the second transmission path 30 after the first transmission path 30 is blocked. It is characterized in that a P-type MOS transistor 42a is provided as a second blocking section for blocking the second transmission line 40.

  The charge control system according to the second embodiment will be described in detail below.

  The second transmission line 40 includes a resistance element 41a as a first resistance element and a P-type MOS transistor 42a as a second blocking portion. The second transmission line 40 includes the secondary battery 20 on the first transmission line 30. And are connected in parallel. One end of the resistive element 41a is connected to the low potential 30L side of the first transmission path 30, and the P-type MOS transistor 42a is in series with the resistive element 41a, and more specifically, the drain D is the other end of the resistive element 41a. The sources S are connected to the high potential 30H side of the first transmission path 30, respectively. Thus, the second transmission line 40 is connected in parallel to the secondary battery 20, and constitutes a closed circuit 50 together with the first transmission line 30 and the secondary battery 20. In the second transmission path 40, the P-type MOS transistor 42a operates as a constant current source circuit by the bias voltage VC supplied from the constant current bias generation unit 80, and the resistance element 41a and the P-type MOS transistor 42a The voltage of the secondary battery 20 is divided.

  The third transmission path 60 includes a resistive element 61a as a second resistive element and a P-type MOS transistor 62a as a third blocking portion, and a second transmission path of the first transmission path 30. The solar cell 10 is connected in parallel with the solar cell 10 on the side of the solar cell 10 rather than 40. One end of the resistive element 61a is connected to the low potential 30L side of the first transmission path 30, and the P-type MOS transistor 62a is in series with the resistive element 61a, and more specifically, the drain D is the other end of the resistive element 61a. The sources S are connected to the high potential 30H side of the first transmission path 30, respectively. Thus, the third transmission path 60 is connected in parallel to the solar cell 10, and forms a closed circuit together with the first transmission path 30 and the secondary cell 10. In the third transmission path 60, the P-type MOS transistor 62a operates as a constant current source by the bias voltage VC supplied from the constant current bias generation unit 80, and the solar cell is composed of the resistance element 61a and the P-type MOS transistor 62a. The voltage of 10 is divided.

  In the comparator 70, the non-inverted input terminal (+) is connected to the common connection point of the resistive element 41a and the P-type MOS transistor 42a that constitute the second transmission path 40, and the inverted input terminal (-) is the third transmission. It is connected to the common connection point of the resistive element 61a and the P-type MOS transistor 62a which constitute the path 60. As a result, the voltage of the secondary battery 20 divided by the resistance element 41 a and the P-type MOS transistor 42 a is input to the non-inversion input terminal (+) of the comparator 70. Further, the voltage of the solar cell 10 divided by the resistance element 61 a and the P-type MOS transistor 62 a is input to the inverting input terminal (−) of the comparator 70.

Here, for convenience of explanation, as in the first embodiment, the voltage of the solar cell 10 is divided by VSC, the voltage of the solar cell 10 divided by the resistance element 61a and the P-type MOS transistor 62a is input by the solar cell voltage VSCin. The voltage of the secondary battery 20 divided by the resistance element 41a and the P-type MOS transistor 42a is defined as an input secondary battery voltage VDDin.

The comparator 70 compares the input solar battery voltage VSCin with the input secondary battery voltage VDDin, and outputs “low” when “VSCin> VDDin”, and outputs “high” when “VSCin ≦ VDDin”. Do.

  In the second embodiment, the constant current bias generation unit 80 applies a bias voltage VC to the gate G of the P-type MOS transistor 42 a. The bias voltage VC generated by the constant current bias generation unit 80 is also applied to the gate G of the P-type MOS transistor 62a, that is, as a current mirror connection to the P-type MOS transistor 42a and the P-type MOS transistor 62a. There is. The reason for the same configuration is the same as that described in the first embodiment.

  In the first embodiment, the constant current bias generation unit 80 applies the bias voltage VC to the gates G of the P-type MOS transistor 42 a and the P-type MOS transistor 62 a using the power supplied from the solar cell 10. Therefore, when the charge control system is arranged, for example, in the dark and the supply of power from the solar cell 10 is lost, the constant current bias generation unit 80 generates the P-type MOS transistor 42a and the P-type MOS transistor 62a. The application of the bias voltage VC to the gate G is stopped. When the voltage application from the constant current bias generation unit 80 is stopped, the P-type MOS transistor 42a and the P-type MOS transistor 62a are turned off, and the second transmission path 40 is cut off by the P-type MOS transistor 42a. Thus, the current does not flow in the second transmission path 40, and the third transmission path 60 is cut off by the P-type MOS transistor 62a, and the current does not flow in the third transmission path.

  One end of a resistive element 90 a as a third resistive element is connected to the low potential 30 L of the first transmission path 30.

  In the P-type MOS transistor 100a, the drain D as one end is connected to the other end of the resistance element 90a, the source S as the other end is connected to the high potential 30H side of the first transmission path 30, and the output of the comparator 70 is It is configured to be applied to the gate G. The connection point between the resistive element 90a and the P-type MOS transistor 100a is referred to as a "connection point 110a" for the sake of convenience.

  The N-type MOS transistor 120 a plays a role of a switch element that shuts off the conductive path of the first transmission path 30 and stops the supply of power from the solar cell 10 to the secondary cell 20 under certain conditions. The N-type MOS transistor 120 a is closer to the solar cell 10 than the connection point between the resistive element 90 a and the first transmission line 30, and is more than two connection points between the third transmission line 60 and the first transmission line 30. The low potential 30L side of the first transmission path 30 on the secondary battery 20 side is connected in series. In other words, the resistance element 90 a is connected to the low potential 30 L side of the first transmission path 30 and to the secondary battery 20 side more than the N-type MOS transistor 120 a. In the N-type MOS transistor 120a, the source S is connected to the secondary battery 20 side, the drain D is connected to the solar cell 10 side, and the gate G is a connection point 110a between the drain D of the P-type MOS transistor 100a and the resistance element 90a. It is connected to the. The N-type MOS transistor 120 a turns on and off the first transmission path 30 according to the output of the comparator 70. Specifically, when the output from the comparator 70 is high, the N-type MOS transistor 120 a turns off the P-type MOS transistor 100 a and the potential at the connection point 110 a of the first transmission path 30 on the low potential 30 L side. It is almost the same as the above, whereby a low level is applied to the gate G to turn it off. On the other hand, when the output of the comparator 70 is at the low level, the P-type MOS transistor 100a is turned on and the connection point 110a has the same potential as that of the secondary battery 20, whereby a high level is applied to the gate G to turn it on. . That is, the N-type MOS transistor 120a performs an on / off operation according to the potential between the resistive element 90a and the P-type MOS transistor 100a which fluctuate in accordance with the operation of the P-type MOS transistor 100a. While the N-type MOS transistor 120 a is on, charging of power from the solar cell 10 to the secondary battery 20 is performed, and the charging is not performed while the N-type MOS transistor 120 a is off.

  In the second embodiment, an N-type MOS transistor 120a is provided as the first blocking portion in place of the P-type MOS transistor 120 of the first embodiment. It is preferable from the viewpoint that the element size of the MOS transistor used as the blocking portion 1 can be reduced.

FIG. 7 shows a specific circuit configuration of the constant current bias generation unit 80 used in the second embodiment.

  The constant current bias generation unit 80 used in the second embodiment is connected between the high potential 30H side and the low potential 30L side of the first transmission path 30, and the first current mirror circuit 81a and the second current mirror circuit 81a are used. A current mirror circuit 82a of 2 and a resistor R1a. The first current mirror circuit 81a is composed of a P-type MOS transistor P1a and a P-type MOS transistor P2a. The second current mirror circuit 82a includes an N-type MOS transistor N1a and an N-type MOS transistor N2a.

  One end of the resistor R1a is connected to the high potential 30H side of the first transmission path 30.

  The source S of the P-type MOS transistor P1a is connected to the high potential 30H side of the first transmission path 30. The source S of the P-type MOS transistor P2a is connected to the other end of the resistor R1a, and the gates G of the P-type MOS transistor P1a and the P-type MOS transistor P2a are commonly connected to each other. Furthermore, both gates G are commonly connected to the drain D of the P-type MOS transistor P1. The P-type MOS transistor P1 and the P-type MOS transistor P2 are current-mirror connected to the gates G of the P-type MOS transistor 42a and the P-type MOS transistor 62a.

  The drain D of the N-type MOS transistor N1a is connected to the drain D of the P-type MOS transistor P1a, and the drain D of the N-type MOS transistor N2a is connected to the drain D of the P-type MOS transistor P2a. The sources S of the N-type MOS transistor N1a and the N-type MOS transistor N2a are connected to the low potential 30L side of the first transmission path 30. Furthermore, the gates G of both transistors are commonly connected to the drain D of the N-type MOS transistor N2a.

  Here, it returns to the explanation of FIG. 6 again. The bias voltage VC output from the constant current bias generation unit 80 having the above configuration is configured to be applied to the gates G of the P-type MOS transistor 42 a and the P-type MOS transistor 62 a. The magnitude of the bias voltage VC applied to the P-type MOS transistor 42a and the P-type MOS transistor 62a is the same as that of the P-type MOS transistor P1a, the P-type MOS transistor P2a, the N-type MOS transistor N1a, and the N-type MOS transistor N2a described above. It can be appropriately set by the electrical characteristics and the resistor R1.

  Next, the operation of the charge control system according to the second embodiment will be described with reference to FIGS. 3 and 6.

  In the period T1, the solar cell 10 generates a large amount of sunlight and constant power generation is performed. Therefore, a constant voltage is applied from constant current bias generation unit 80 to each gate G of P-type MOS transistor 42a and P-type MOS transistor 62a, and P-type MOS transistor 42a and P-type MOS transistor 62a are turned on. The current from the secondary battery 20 flows through the second transmission path 40, and the current from the solar cell 10 flows through the third transmission path 60. Further, in the period T1, “VSC> VDD” is established between the voltage VSC of the solar cell 10 and the voltage VDD of the secondary cell 20. In this case, “VSCin> VDDin” is established between the input solar battery voltage VSCin and the input secondary battery voltage VDDin. Therefore, a low level is output from the comparator 70, which turns on the P-type MOS transistor 100a and the potential of the connection point 110a becomes the same potential as the potential on the high potential side 30H of the first transmission path. A high level is applied to the gate G of the MOS transistor 120a to turn on the N-type MOS transistor 120a, and the power of the solar cell 10 is supplied to the secondary cell 20 through the first transmission path 30.

  In the period T2 to T4, the solar panel is not exposed to sunlight or hardly hit by a shade or the like, whereby the voltage VSC of the solar cell 10 decreases with time.

  When time F is reached and period T2 is reached, “VSC> VDD” is established between the voltage VSC of the solar cell and the voltage VDD of the secondary cell 20. In this case, the current from the solar cell 10 flows in the second transmission path 40 and the current from the secondary battery 20 flows in the third transmission path 60 as in the case of the period T1. In this case, “VSCin> VDDin” is established between the input solar battery voltage VSCin and the input secondary battery voltage VDDin. Therefore, the N-type MOS transistor 120 a is turned on as in the case of the period T 1, and the power of the solar cell 10 is supplied to the secondary cell 20 via the first transmission path 30.

  On the other hand, at time S, “VSCin = VDDin” holds between the input solar battery voltage VSCin and the input secondary battery voltage VDDin. And in periods T3 and T4 after time S, “VSCin <VDDin” is established between the input solar battery voltage VSCin and the input secondary battery voltage VDDin.

  In the period T3, “VSCin ≦ VDDin” is established between the input solar battery voltage VSCin and the input secondary battery voltage VDDin. Therefore, at time S when "VSCin = VDDin", the comparator 70 outputs a high level, thereby turning off the P-type MOS transistor 100a and causing the potential at the connection point 110a to be the first transmission path. As the low potential 30L side of the 30 becomes the same potential, a voltage on the low potential 30L side of the first transmission path 30 is applied to the gate G of the N-type MOS transistor 120a to turn off the N-type MOS transistor 120a. The first transmission path 30 which is a supply path of power from the battery 10 to the secondary battery 20 is cut off.

  However, in the conventional charge control circuit, after time S when the first transmission path 30, which is a supply path of power from the solar cell 10 to the secondary cell 20, is cut off, the secondary cell 20 and the second Because the transmission line 40 is a closed circuit via the first transmission line 30, there is a problem that the current of the secondary battery 20 flows out toward the second transmission line 40. . For this reason, during a period when solar light is not applied to the solar panel and after time S, the power of the secondary battery 20 continues to be consumed wastefully, leading to a loss of power of the secondary battery 20. The

  On the other hand, in the charge control system according to the second embodiment, the power of the solar cell 10 is further reduced after the first transmission path 30 is cut off as the power of the solar cell 10 is reduced, and the voltage VSC is thus reduced. At time TH when the voltage becomes 0 V, and during a period T4 after the same time, the constant current bias generation unit 80 connected to the first transmission path 30 operates using the power of the solar cell 10 to the second transmission path The supply of power to the gates G of the P-type MOS transistor 42 a of 40 and the P-type MOS transistor 62 a of the third transmission path 60 is stopped. Then, when the supply of power from the constant current bias generation unit 80 is stopped, both the P-type MOS transistor 42 a and the P-type MOS transistor 62 a are turned off. As a result, the second transmission path 40 is cut off by the P-type MOS transistor 42 a, and the third transmission path 60 is cut off by the P-type MOS transistor 62 a. Therefore, the secondary battery 20 and the second transmission line 40 do not have a closed circuit, and the power of the secondary battery 20 does not flow out toward the second transmission line 40. Power consumption can be reduced.

  In period T3 after time S and before time TH, "VSCin <VDDin" holds between input solar cell voltage VSCin and input secondary cell voltage VDDin as in the case of period T2. There is. At this time, the N-type MOS transistor 120 a is turned off, and the first transmission path 30 which is a supply path of power from the solar cell 10 to the secondary cell 20 is cut off. In this case, since the solar cell 10 is not at 0 V in the period T3, the P-type MOS transistor 42a is turned on, and the power of the secondary cell 20 flows out toward the second transmission path 40. I will. However, since the time from time S to time TH, that is, the time until the voltage VSC of the solar cell 10 becomes 0 V after the sunlight does not reach the solar panel is less than one second, the secondary of that period is The power loss of the battery 20 is substantially negligible.

  When the time FO comes, the solar panel is again exposed to sunlight. Therefore, a constant voltage is applied from the constant current bias generation unit 80 to the gates G of the P-type MOS transistor 42a and the P-type MOS transistor 62a, and the P-type MOS transistor 42a and the P-type MOS transistor 62a are turned on. The current from the solar cell 10 flows through the second transmission path 40, and the current from the secondary battery 20 flows through the third transmission path 60. Then, at time FI after a period T5, “VSCin> VDDin” holds again between the input solar battery voltage VSCin and the input secondary battery voltage VDDin. Therefore, the N-type MOS transistor 120 a is turned on again, and the power of the solar cell 10 is supplied to the secondary cell 20 via the first transmission path 30.

  As described above, according to the charge control system of the second embodiment, when the first transmission path 30 for supplying power from the solar cell 10 to the secondary battery 20 is shut off, the power of the solar cell 10 is obtained. When the first transmission line 30 is cut off by cutting off the second transmission line 40 that constitutes the closed circuit 50 together with the first transmission line 30 and the secondary battery 20, Since the problem that the current of 20 continues to flow in the closed circuit constituted by the first transmission line, the secondary battery and the second transmission line is eliminated, the power loss of the secondary battery 20 can be suppressed. .

  The driving power of the comparator 70 is preferably supplied from the solar cell 10 via the fourth transmission path 130 a connected to the first transmission path 30 as shown in FIG. 6. The reason why the same configuration is preferable is the same as that described in the first embodiment.

  Preferably, resistance element 41a and resistance element 61a are formed to have the same resistance value, and P-type MOS transistor 42a and P-type MOS transistor 62a are preferably formed to have the same characteristics. The reason is that the voltage of the secondary battery 20 supplied to the comparator 70 via the second transmission line 40 and the voltage of the solar cell 10 supplied to the comparator 70 via the third transmission line 60. It is because the partial pressure to be made can be provided at the same rate.

  Moreover, it is preferable that the resistive element 41a or the resistive element 61a be a variable resistance. This is because at least one of them is a variable resistance, and even if the resistance element 41a and the resistance element 61a are formed with different resistances, one of the resistance values is adjusted to adjust the resistance element 41a. And the resistance element 61a can be made to have the same resistance value. In addition, even when the comparator 70 has an input offset voltage, it is possible to adjust any resistance value to change the voltage division ratio and cancel the input offset voltage of the comparator 70.

  Further, the N-type MOS transistor 120a is not provided on the high potential 30H side of the first transmission path 30, but is provided on the low potential 30L side. The reason is that, when the driving power of the comparator 70 is supplied from the solar cell 10 as described above, the N-type MOS transistor 120 a is provided on the high potential 30 H side of the first transmission path 30. While the drain D of the transistor 120a is at the same potential as the solar cell 10, the voltage applied to the gate G of the N-type MOS transistor 120a is also the voltage of the solar cell 10, so a normal on / off operation can be performed It is because it is gone.

  In the second embodiment, on / off of the N-type MOS transistor 120a is controlled via the resistance element 90a and the P-type MOS transistor 100a. The reason is that when the output of the comparator 70 is simply directly input to the gate G of the N-type MOS transistor 120a, the normal off operation of the N-type MOS transistor 120a can not be realized. The reason is that the output of the comparator 70 is directly input to the gate G of the N-type MOS transistor 120a, and the fourth transmission path 130a connected in parallel to the first transmission path 30 is used. In the case of adopting a configuration in which the solar cell 10 supplies power, the voltage supplied from the comparator 70 to the gate G of the N-type MOS transistor 120a becomes the voltage of the solar cell 10, while the source S of the N-type MOS transistor 120a Since the voltage supplied to the power supply is a negative potential with the voltage of the solar cell 10 as the reference 0 V, the potential of the gate G still exceeds the potential of the source S even if the solar cell 10 becomes 0 V, and the N-type MOS The transistor 120 a can not be turned off, and the current flows from the secondary battery 20 back to the solar cell 10. This is because leads to loss of power.

  FIG. 8 shows a modification of the charge control system according to the second embodiment. In the present modification, in FIG. 8, the same components as those of the charge control system shown in FIG. 6 are denoted by the same reference numerals, and the description thereof is omitted.

  First of all, the charge control system shown in FIG. 8 and the charge control system shown in FIG. 6 are N-type as a first MOS transistor instead of the resistance element 41 a connected to the second transmission path 40. A second MOS transistor 43a is provided, and secondly, an N-type MOS transistor 63a as a second MOS transistor is provided instead of the resistance element 61a connected to the third transmission path 60. It is different.

  The N-type MOS transistor 43 a is connected in series to the P-type MOS transistor 42 a in the second transmission path 40. Specifically, the drain D and gate G of the N-type MOS transistor 43a are commonly connected to the drain D of the P-type MOS transistor 42a, and the gate G of the N-type MOS transistor 43a and the drain D of the P-type MOS transistor 42a are It is formed at the same potential. By using the N-type MOS transistor 43a, it is possible to divide the secondary battery 20 by a larger amount with a smaller constant current as compared to the case of using the resistance element 41a. The merit of using the N-type MOS transistor 43a instead of the resistance element 41a is the same as the merit of using the P-type MOS transistor 43 instead of the resistance element 41 in the first embodiment.

  The N-type MOS transistor 63 a is connected in series to the P-type MOS transistor 62 a in the third transmission path 60. Specifically, the drain D and the gate G of the N-type MOS transistor 63a are commonly connected to the drain D of the P-type MOS transistor 62a, and the gate G of the N-type MOS transistor 63a and the drain D of the P-type MOS transistor 62a are the same. It is potential. The merit of using the N-type MOS transistor 63a instead of the resistance element 61a in the third transmission path 60 is that the N-type MOS transistor 43a is used instead of the resistance element 41a in the second transmission path 40. Is the same as

  FIG. 9 is a view showing another modification of the charge control system according to the second embodiment. In the present modification, in FIG. 9, parts having the same configurations as those in the charge control system shown in FIG. 6 or FIG. 8 are assigned the same reference numerals and descriptions thereof will be omitted.

  The charge control system according to the present modification includes a solar cell 10, a secondary cell 20, and a semiconductor chip 140a.

  The semiconductor chip 140a includes at least a first transmission path 30, a second transmission path 40, a third transmission path 60, a comparator 70, a constant current bias generation unit 80, and an N-type MOS transistor 120a. . Specifically, the semiconductor chip 140 a includes an electrode 150 aa and an electrode 150 ab as a first electrode electrically connected to the solar cell 10, and an electrode 150 ac as a second electrode electrically connected to the secondary battery 20. And a first transmission path which is electrically connected to the electrode 150ad, the electrode 150aa, the electrode 150ab, the electrode 150ac, and the electrode 150ad, and transmits the power output from the solar cell 10 to the secondary cell 20; A second transmission line 40 connected to the transmission line 30 and forming a closed circuit 50 together with the first transmission line 30 and the secondary battery 20, a voltage based on the output from the solar cell 10, and a second transmission line 40 And a comparator 70 for comparing the voltage based on the output from the secondary battery 20 connected to the second transmission line 40 and transmitted via the second transmission line 40, and the first transmission line 30 is An N-type MOS transistor 120a for interrupting the first transmission path 30 when it is determined in the data 70 that the voltage output from the solar cell 10 is equal to or less than the voltage output from the secondary battery 20; The transmission line 40 includes an N-type MOS transistor 42 a that shuts off the second transmission path 40 as the power of the solar cell 10 decreases after the first transmission path 30 is shut off.

  The electrode 150aa is electrically connected to the positive electrode side of the solar cell 10, and is also electrically connected to the high potential 30H side of the first transmission path 30 formed in the semiconductor chip 140a. The electrode 150ab is electrically connected to the negative electrode side of the solar cell 10, and is also electrically connected to the low potential 30L side of the first transmission path 30 formed in the semiconductor chip 140a. The electrode 150ac is electrically connected to the positive electrode side of the secondary battery 20, and is also electrically connected to the high potential 30H side of the first transmission path 30 formed in the semiconductor chip 140a. The electrode 150ad is electrically connected to the negative electrode side of the secondary battery 20, and is also electrically connected to the low potential 30L side of the first transmission path 30 formed in the semiconductor chip 140a. As described above, the semiconductor chip 140a and the solar cell 10 are electrically connected through the electrode 150aa and the electrode 150ab, and the semiconductor chip 140a and the secondary cell 20 are electrically connected through the electrode 150ac and the electrode 150ad. .

  Although FIG. 9 shows the case where the resistive element 41 a is adopted for the second transmission path 40 and the resistive element 61 a is adopted for the third transmission path 60, the second transmission path 40 is As shown in FIG. 8, an N-type MOS transistor 43a is employed in place of the resistance element 41a, and an N-type MOS transistor is used in the third transmission path 60 instead of the resistance element 61a as shown in FIG. You may adopt 63a.

DESCRIPTION OF SYMBOLS 10 solar cell 20 secondary battery 30 1st transmission path 40 2nd transmission path 50 closed circuit 60 3rd transmission path 70 comparator 80 constant current bias generation part 90 N type MOS transistor 100 resistance element 120 P type MOS transistor 120a N type MOS transistor

Claims (1)

A first blocking portion disposed between a first terminal to which one electrode of the secondary battery is electrically connected and a second terminal to which a charging voltage for charging the secondary battery is applied;
A comparison unit which is supplied with drive power from the second terminal, compares the voltage division of the secondary battery with the voltage division of the charging voltage, and outputs the comparison result to the first shutoff unit;
I have a,
The division of the secondary battery and the division of the charge voltage are generated according to a bias voltage output from a bias generation unit to which drive power is supplied from the second terminal,
The semiconductor device further comprising a voltage dividing circuit that generates a partial pressure of the secondary battery and cuts off a current path as the charging voltage decreases .