JP6540173B2 - Semiconductor device and control method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a control method of the semiconductor device.

  In the semiconductor memory device, the yield, which is a non-defective rate, is improved by switching a defective memory cell to a redundant memory cell. For example, in a semiconductor memory device including a plurality of memory blocks, shift registers for storing defect information for repairing defects are provided corresponding to the respective memory blocks, and the shift registers are connected in series via selectors. The shift register corresponding to the non-defective memory block is separated from the transfer path for transferring the defect information indicating the defective memory cell by the selector, and the defect information is transferred only to the shift register corresponding to the defective memory block. . Then, each memory block switches a defective memory cell to a redundant memory cell based on the information held in the shift register. As a result, defective memory cells are switched to redundant memory cells with less information as compared to the case where the shift register corresponding to a non-defective memory block is not separated from the transfer path (see, for example, Patent Document 1).

  In a semiconductor device including a plurality of memory macros, defect address information indicating the position of a defect is transferred from the fuse box to the memory macro via a common fuse bus. As a result, the size of a circuit for transferring the defect address information to the memory macro is reduced as compared to the case where the defect address information is individually transferred to the memory macro (see, for example, Patent Document 2).

  In addition, the semiconductor memory device replaces the defective memory cell with the redundant memory cell by decoding the defective address information received from the fuse circuit using the decode circuit that specifies the position of the defective memory cell. In this case, by setting the addresses to be assigned to the decode circuit so as to reduce the number of fuse elements to be cut, the cutting time of the fuse elements can be shortened as compared to the case of sequentially assigning the addresses to the decode circuit ( For example, refer to Patent Document 3).

JP 2013-30238 A Unexamined-Japanese-Patent No. 2006-107590 JP, 2005-222658, A

  When the shift register to which the defect information is transferred is provided corresponding to each memory block, the position of the shift register to which the defect information is transferred changes according to the condition of the defect. For example, if there is a defect in the memory block corresponding to the end shift register, the defect information is transferred to the end shift register through all other shift registers. When the shift register corresponding to a non-defective memory block is separated from the transfer path by the selector, the selector and the signal wiring for supplying information for controlling the selector to the selector are provided in the semiconductor memory device. Circuit scale increases.

  An object of the semiconductor device and the control method of the semiconductor device according to the present disclosure is to shorten the time for setting selection information in the holding unit without increasing the circuit size of the semiconductor device.

According to one aspect, the semiconductor device includes a plurality of circuit blocks each including a plurality of internal circuits and a selection unit which selects an internal circuit to be used among the plurality of internal circuits based on selection information, and a plurality of circuits Among the blocks, a storage unit for storing selection information supplied to the selection unit of the change circuit block, which is a circuit block for changing the selection state of the plurality of internal circuits from the initial state, and provided corresponding to each of the plurality of circuit blocks And a plurality of holding units connected in the order corresponding to the circuit blocks having a high probability of changing the selection state from the initial state, and holding selection information to be supplied to the selection units of the plurality of circuit blocks; , the holding unit corresponding to the changing circuit block comprises successively a control unit for transferring selected information stored in the storage unit, the storage unit is subjected to the selection unit changes the circuit blocks A plurality of first storage areas for storing selected information and a plurality of second information for storing interval information indicating an interval between two holding units corresponding to two of the plurality of holding units. And the control unit sequentially transfers selection information stored in the two first storage regions to the plurality of holding units based on the interval information, and the selection corresponding to the initial state is performed. Transfer information to multiple holders.

According to another aspect, a plurality of circuit blocks respectively including a plurality of internal circuits and a selection unit for selecting an internal circuit to be used among the plurality of internal circuits based on selection information and a plurality of circuit blocks are respectively supported And a plurality of holding units connected in the order corresponding to the circuit block having a high probability of changing the selection state of the plurality of internal circuits from the initial state and holding selection information to be supplied to the selection units of the plurality of circuit blocks And a plurality of first storage areas respectively storing selection information supplied to the selection unit of the change circuit block, which is a circuit block that changes the selection state of the plurality of internal circuits from the initial state among the plurality of circuit blocks And a plurality of second storage areas each storing interval information indicating an interval between two holding units corresponding to two changed circuit blocks among the plurality of holding units. Control method of a semiconductor device having a storage unit, among the plurality of circuit blocks, stores selection information supplied to the selection unit changes the circuit block is a circuit block for changing the selected state of the plurality of internal circuits from an initial state The selection information read out from the unit and transferred to the holding unit corresponding to the change circuit block among the plurality of holding units is sequentially transferred , and the selection information stored in the two first storage areas based on the interval information Is sequentially transferred to the plurality of holding units, the selection information corresponding to the initial state is transferred to the plurality of holding units .

  In one aspect, the semiconductor device and the control method of the semiconductor device according to the present disclosure can shorten the time for setting selection information in the holding portion without increasing the circuit size of the semiconductor device.

FIG. 7 is a diagram showing an embodiment of a semiconductor device and a control method of the semiconductor device. It is a figure which shows another embodiment of the control method of a semiconductor device and a semiconductor device. It is a figure which shows an example of the shift register shown in FIG. It is a figure which shows an example of the memory shown in FIG. It is a figure which shows an example of the defect condition of the memory shown in FIG. 2, and the information programmed by a program part. FIG. 7 is a diagram showing an example of an operation flow for setting defect information in the scan chain shown in FIG. 2; FIG. 7 is a diagram showing an example (continuation of FIG. 6) of an operation flow for setting defect information in the scan chain shown in FIG. 2; FIG. 7 is a diagram showing an example of an operation of setting defect information in the scan chain shown in FIG. 2; It is a figure which shows another embodiment of the control method of a semiconductor device and a semiconductor device. It is a figure which shows an example of the defect condition of the memory shown in FIG. 9, and the information programmed by a program part. It is a figure which shows another embodiment of the control method of a semiconductor device and a semiconductor device. FIG. 12 is a diagram showing an example of an adjustment circuit mounted in each memory shown in FIG. 11 and adjusting operation timing of a control circuit in each memory. It is a figure which shows an example of the operation timing of the control circuit in the memory shown in FIG. 11, and the information programmed by a program part. It is a figure which shows another embodiment of the control method of a semiconductor device and a semiconductor device. FIG. 15 is a diagram showing an example of operation timings of a control circuit in the memory shown in FIG. 14 and information programmed in a program unit. It is a figure which shows an example of the clock control part shown in FIG. FIG. 17 is a diagram showing an example of the operation of the clock control unit shown in FIG. 16; It is a figure which shows an example of the shift register shown in FIG. FIG. 19 is a diagram showing an example of operation of the shift register shown in FIG. 18; It is a figure which shows an example of the operation | movement flow which sets defect information to the scan chain shown in FIG. FIG. 21 is a diagram showing an example (continuation of FIG. 20) of an operation flow for setting defect information in the scan chain shown in FIG. 14; FIG. 15 is a diagram showing an example of an operation of setting defect information in the scan chain shown in FIG. 14; It is a figure which is mounted in each circuit block in a semiconductor device, and shows an example of the adjustment circuit which adjusts the voltage used by a circuit block.

  Hereinafter, embodiments will be described using the drawings.

  FIG. 1 shows an embodiment of a semiconductor device and a control method of the semiconductor device. The semiconductor device SEM1 of this embodiment includes a plurality of circuit blocks CBLK (CBLK1, CBLK2, CBLK3, CBLK4), a plurality of holding units HLD (HLD1, HLD2, HLD3, HLD4), a control unit CNTL, and a storage unit MEM.

  Each circuit block CBLK has a plurality of internal circuits IC (IC1, IC2) and a selection unit SEL (SEL1, SEL2, SEL3, SEL4) for selecting the internal circuit IC used in the circuit block CBLK based on selection information. . The holding unit HLD holds selection information SINT or selection information SI (SI1, SI2). The selection information SINIT is initial selection information held in the holding unit HLD1-HLD4, and the selection information SI1 and SI2 are selection information newly held by the holding units HLD1 and HLD2 holding the selection information SINIT.

  For example, the selection unit SEL1 selects the internal circuit IC1 when receiving the selection information SINIT from the holding unit HLD1, and selects the internal circuit IC2 when receiving the selection information SI1 from the holding unit HLD1. Similarly, selection unit SEL2-SEL4 selects internal circuit IC1 when it receives selection information SINIT from holding unit HLD2-HLD4, and selects selection information SI2-SI4 from holding unit HLD2-HLD4, respectively. Select circuit IC2. Then, the circuit block CBLK operates using the internal circuit IC selected by the selection unit SEL.

  In the example shown in FIG. 1, the selection unit SEL1 selects the internal circuit IC2 based on the selection information SI1, the selection unit SEL2 selects the internal circuit IC2 based on the selection information SI2, and the selection units SEL3 and SEL4 The internal circuit IC1 is selected based on the selection information SINIT. The internal circuit IC selected by the selection units SEL1 to SEL4 is indicated by a thick frame. The state in which the internal circuit IC1 is selected by the selection information SINIT is an initial state, and the state in which the internal circuit IC2 is selected by the selection information SI1 and SI2 is a changed state changed from the initial state.

  Each holding unit HLD is provided corresponding to each circuit block CBLK, and is connected to the control unit CNTL in the order corresponding to a circuit block having a high probability of changing the selection state of the internal circuit IC from the initial state. That is, the probability of changing the selection state of the internal circuit IC from the initial state is high in the order of the circuit blocks CBLK 1, BCLK 2, CBLK 3, and CBLK 4. Each holding unit HLD holds selection information (SINIT or SI1, SI2) to be set in the selection unit SEL of the circuit block CBLK.

  The storage unit MEM stores selection information SI (SI1, SI2) set in the circuit block CBLK to be changed from the initial state in which the internal circuit IC1 is selected to the selected state in which the internal circuit IC2 is selected. In the example shown in FIG. 1, since the selection state of the circuit blocks CBLK3 and CBLK4 is not changed from the initial state, the selection information SI3 and SI4 for changing the selection state of the circuit blocks CBLK3 and CBLK4 is not stored in the storage unit MEM. For example, the circuit block CBLK which changes the selected state from the initial state is determined by the test apparatus which tests the semiconductor device SEM1. The test apparatus stores selection information in the storage unit MEM based on the test result.

  The control unit CNTL reads out, from the storage unit MEM, the selection information SI2 and SI1 set in the selection unit SEL of the circuit block CBLK that changes the selection state of the internal circuit IC from the initial state among the plurality of circuit blocks CBLK. The control unit CNTL sequentially transfers the read selection information SI2 and SI1 to the holding units HLD1 and HLD2 corresponding to the circuit block CBLK (in this example, CBLK1 and CBLK2) that changes the selection state of the internal circuit IC from the initial state. Do.

  The probability of changing the selected state from the initial state is high in the order of the circuit blocks CBLK 1, CBLK 2, CBLK 3, and CBLK 4. Therefore, the selection information SI is transferred to change the selected state from the initial state as compared to the case where the holding unit HLD corresponding to the circuit block CBLK is connected without considering the probability of changing the selected state from the initial state. The number of holding parts HLD can be reduced. As a result, the time required to set the setting information SI1 and SI2 in the holding unit HLD before operating the semiconductor device SEM1 can be shortened compared to the case where the probability of changing the selected state from the initial state is not considered.

  For example, the probability of changing the selected state from the initial state is higher as the area of the circuit block CBLK is larger. In this case, the areas of the circuit blocks CBLK increase in the order of CBLK1, CBLK2, CBLK3, and CBLK4, and the holding units HLD1-HLD4 are connected to the control unit CNTL in the order corresponding to the circuit blocks CBLK1-CBLK4 having the large areas. Alternatively, the probability that the selected state is changed from the initial state is higher as the timing margin of the circuit block CBLK is smaller or as the voltage margin of the circuit block CBLK is smaller. An example in which the probability of changing the selection state of the internal circuit IC from the initial state depends on the area of the circuit block CBLK will be described with reference to FIGS. An example in which the probability of changing the selection state of the internal circuit IC from the initial state depends on the timing margin of the circuit block CBLK will be described with reference to FIGS. An example in which the probability of changing the selection state of the internal circuit IC from the initial state depends on the voltage margin of the circuit block CBLK will be described with reference to FIG.

  As described above, in the embodiment illustrated in FIG. 1, the holding unit HLD is connected to the control unit CNTL in descending order of the probability of changing the selection state of the internal circuit IC from the initial state. As a result, by transferring the setting information to the predetermined number of holding units HLD positioned closer to the control unit CNTL, it is possible to set the selection state of all the circuit blocks CBLK. As a result, even when setting the selection state of the circuit block CBLK by sequentially transferring the selection information SI to the plurality of holding units HLD connected in series, the time until the setting information SI is set in the holding unit HLD Can be shortened compared to the prior art. Therefore, the time until the operation of the semiconductor device SEM1 becomes possible (for example, the start-up time) can be shortened as compared with the related art.

  In addition, since it is not necessary to provide the storage unit MEM with an area for holding setting information to be set in the holding unit HLD corresponding to the selection units SEL of all circuit blocks CBLK, the circuit scale of the storage unit MEM is reduced compared to the prior art. be able to. Furthermore, the control unit CNTL transfers the selection information SI to the selection unit SEL of each circuit block CBLK via the holding units HLD connected in series. Therefore, the number of signal lines can be reduced as compared to the case where selection information SI is transferred in parallel from the control unit CNTL to the selection unit SEL of each circuit block CBLK using a plurality of bus lines. Therefore, the circuit scale of the semiconductor device SEM1 including the plurality of circuit blocks CBLK which change the selection state can be reduced as compared to the prior art. As a result, the time for setting the defect information in the holding unit HLD can be shortened without increasing the circuit size of the semiconductor device SEM1.

  FIG. 2 shows another embodiment of a semiconductor device and a control method of the semiconductor device. The semiconductor device SEM2 of this embodiment includes an operation control unit 10, a transfer control unit 20, a program unit 30, a scan chain SCANC, and a plurality of memories M (in the example shown in FIG. 2, M1, M2, and so on) integrated on a semiconductor chip. 10 of M3, ..., M10).

  The memories M <b> 1 to M <b> 10 are semiconductor memories such as static random access memories (SRAMs) or ferroelectric memories, and include redundant circuits for repairing defects generated in the manufacturing process. The memories M1-M10 are an example of a circuit block. The memory M1 has a larger area than the memory M2, the memory M2 has a larger area than the memory M3, and the memory M10 has a smaller area than the other memories M. That is, the area of the memory M connected to the transfer control unit 20 on the upstream side of the scan chain SCINC is the area of the memory M connected to the far side from the transfer control unit 20 on the downstream side of the scan chain SCINC. Larger than The areas of a predetermined number of memories M arranged adjacent to each other in the memories M1 to M10 may be equal to each other.

  For example, since the semiconductor devices SEM2 (semiconductor chips) are manufactured using a common semiconductor process, the defect densities of the memories M1 to M10 are the same as one another. Therefore, the number of defects included in the memory M increases as the area of the memory M increases, and the probability (probability) of occurrence of defects in the memory M increases as the area increases. In this embodiment, the area of the memory M is larger as that of the memory M connected to the shift register SR located upstream of the scan chain SCINC. Therefore, the probability that a defect occurs in the memory M is higher in the memory M connected to the shift register SR closer to the transfer control unit 20. In other words, the probability of using a redundant circuit (redundant memory cell unit RMC shown in FIG. 4) for repairing a defect is higher in the memory M connected to the shift register SR closer to the transfer control unit 20.

  The scan chain SCNC has a plurality of shift registers SR (10 in the example shown in FIG. 2, SR1, SR2, SR3,..., SR10 in the example shown in FIG. 2) connected in series to the transfer control unit 20 at the first stage. Have. The shift registers SR1 to SR10 are provided corresponding to the respective memories M1 to M10, and are connected to the corresponding memories M1 to M10, respectively. That is, the shift registers SR1 to SR10 are connected to the transfer control unit 20 in the order corresponding to the memories M1 to M10 in which the probability of occurrence of a defect is high. The shift registers SR <b> 1 to SR <b> 10 are an example of holding units that respectively hold defect information supplied to the redundancy switching switches RSW (FIG. 4) of the memories M <b> 1 to M <b> 10.

  Each shift register SR1-SR10 includes a predetermined number (e.g., seven) of flip-flop circuits connected in series. Each flip-flop circuit of shift registers SR1 to SR10 is set to an initial value (default value) in synchronization with reset signal RST. The shift registers SR1 to SR10 hold the data DT in synchronization with the scan clock signal SCLK, and sequentially transfer the held data DT from the upstream side to the downstream side. Data DT includes a defect code CD for relieving a defect in memory M and a redundancy enable bit REN indicating that a defect exists in memory M. The defect code CD and the redundancy enable bit REN are an example of selection information. An example of the operation of the scan chain SCANC is shown in FIG.

  The transfer control unit 20 includes a counter FLINE, an IRAM, an ICB, a reset generation unit RSTGEN1, and a clock generation unit CLKGEN1. The reset generation unit RSTGEN1 generates a reset signal RST based on the activation signal PON. The clock generation unit CLKGEN1 generates the scan clock signal SCLK after the selection information held in the shift registers SR1 to SR10 is reset to the initial value by the reset signal RST. Here, the initial value set in each of the shift registers SR1 to SR10 is a value indicating that there is no defect in the memory M corresponding to each shift register SR and that the process of repairing the defect in the memory M is not performed. Then, transfer control unit 20 transfers data DT (selection information) to scan chain SCINC based on the information programmed in program unit 30 in synchronization with scan clock signal SCLK. After transferring data DT to scan chain SCINC, transfer control unit 20 stops generation of scan clock signal SCLK and outputs operation enable signal OPE to operation control unit 10.

  The counters FLINE, IRAM, ICB are used when transferring the data DT to the scan chain SCANC based on the information programmed in the program unit 30. Examples of using the counters FLINE, IRAM, and ICB will be described with reference to FIGS. The transfer control unit 20 is an example of a control unit that sequentially transfers selection information stored in the program unit 30 to the shift register SR corresponding to the memory M for repairing a defect. Examples of the operation of the transfer control unit 20 are shown in FIG. 6 to FIG.

  Program unit 30 has a plurality of program elements whose information is programmed by program signal PGM. The program element is a non-volatile storage element such as a fuse circuit, a flash memory or a ferroelectric memory. An example of the program unit 30 is shown in FIG.

  The operation control unit 10 has a power control unit 12. The operation control unit 10 controls the overall operation of the semiconductor device SEM2. The power supply control unit 12 generates a power supply voltage IVDD to be supplied to the functional block mounted on the semiconductor device SEM2, and activates the operation signal PON based on the supply of the power supply voltage IVDD to the functional block. Output The memories M1-M10 are a type of functional block. Power supply voltage IVDD is supplied to a circuit area including at least memories M1-M10 and shift registers SR1-SR10.

  The power supply control unit 12 may generate a voltage control signal for controlling a power supply generation circuit that generates the power supply voltage IVDD, instead of generating the power supply voltage IVDD. For example, the power supply voltage IVDD is an internal power supply voltage generated in the semiconductor device SEM2 using the external power supply voltage supplied to the semiconductor device SEM2.

  For example, the semiconductor device SEM2 includes functional blocks such as a central processing unit (CPU), peripheral circuits, and an input / output interface circuit as well as the memory M illustrated in FIG. The peripheral circuits are a DMAC (Direct Memory Access Controller), a timer, an image processing circuit, and the like. That is, the semiconductor device SEM2 is a SoC (System on a Chip). When the semiconductor device SEM2 includes a plurality of functional blocks, the power supply control unit 12 may control the power supply voltage for each predetermined number of functional blocks, and may output the activation signal PON for each predetermined number of functional blocks. . After outputting the activation signal PON, the operation control unit 10 recognizes that the memories M1-M10 are enabled based on the operation enable signal OPE from the transfer control unit 20, and the memories M1-M10 can be accessed. Notify the CPU etc.

  For example, activation signal PON is set to the inactive level during the sleep mode for stopping the operation of the functional blocks including memories M1-M10 and shift registers SR1-SR10, based on the transition from the sleep mode to the normal operation mode. Is set to the activation level. In this case, the power supply control unit 12 stops the supply of the power supply voltage IVDD to the circuit area including the memories M1-M10 and the shift registers SR1-SR10 during the sleep mode. Then, based on the return from the sleep mode to the normal operation mode, the power supply control unit 12 sets the activation signal PON to the activation level after the power supply voltage IVDD exceeds a predetermined value.

  For example, when memories M1 and M2 have a defect and memories M3-M10 do not contain a defect, redundancy enable bits REN of shift register SR3-SR10 corresponding to memories M3-M10 are initially set to logic that does not use a redundancy circuit. Are reset (reset). Thereby, setting of data DT to shift register SR3-SR10 can be omitted. As a result, after the activation signal PON is output, the time until the memory M1-M10 becomes operable can be shortened compared to the case where data is set in all the shift registers SR1-SR10.

  FIG. 3 shows an example of the shift register SR1 shown in FIG. The shift register SR2-SR10 has a configuration similar to that of the shift register SR1 shown in FIG.

  The shift register SR1 has a plurality of flip flop circuits FF connected in series. Each flip-flop FF receives the reset signal RST at the reset terminal RESET and receives the scan clock signal SCLK at the clock terminal CK. The flip-flop circuit FF in the first stage receives the data DT output from the transfer control unit 20 at the data input terminal D, and the flip-flop circuit FF in the second and subsequent stages receives data of the flip-flop circuit FF in the previous stage at the data input terminal D. Receives data output from output terminal Q. The data output from the data output terminal Q of the flip flop circuit FF in the final stage is output to the shift register SR2.

  After predetermined failure information is set in the shift register SR1, the flip-flop circuits FF excluding the flip-flop circuit FF in the final stage output the failure code CD to the memory M1. The flip-flop circuit FF in the final stage outputs the value of the redundancy enable bit REN to the memory M1. The shift registers SR1 to SR10 may have a master slave flip flop circuit MSFF1 shown in FIG. 18 instead of the flip flop circuit FF.

  FIG. 4 shows an example of the memory M1 shown in FIG. Memory M2-M10 has the same configuration as memory M1 shown in FIG. 4 except that the area is different.

  The memory M1 has an address decoder ADEC, a memory cell array ARY, a redundancy switching switch RSW, and 64 data input / output terminals IO (IO0 to IO63). The address decoder ADEC decodes the address signal AD output from the CPU or the like, and sets one of the word lines WL (WL0, WL1, WL2, WL3, WL4,...) Indicated by the address AD to an activation level. Do.

  Memory cell array ARY is used in place of memory cell unit MC (MC0, MC1, MC2, MC3,..., MC62, MC63) corresponding to each data input / output terminal IO and either of memory cell unit MC. And a redundant memory cell unit RMC. Memory cell units MC0 to MC63 have a plurality of memory cells connected to each word line WL, and redundant memory cell units RMC are connected to each word line WL, and a plurality of memory cell units having a defect are repaired. It has redundant memory cells. Each of memory cell units MC0 to MC63 and redundant memory cell unit RMC is an example of an internal circuit.

  The redundancy switching switch RSW switches a plurality of switches for switching the memory cell unit MC connecting the input / output terminals IO0 to IO63 and the redundancy memory cell unit RMC based on the defect code CD and the redundancy enable bit REN held in the shift register SR1. Have. Redundancy switching switch RSW is an example of a selection unit for selecting a memory cell unit MC and a redundant memory cell unit RMC to be used among the memory cell unit MC and the redundant memory cell unit RMC based on the defect code CD and the redundancy enable bit REN. It is.

  In a state in which shift registers SR1 to SR10 are reset by reset signal RST, redundancy switching switch RSW sets data input / output terminals IO0 to IO63 to an initial state of connecting memory cell units MC0 to MC63. That is, in the initial state, each memory M is set in a state where there is no defect and the redundant memory cell unit RMC is not used. Thereafter, a defect code CD indicating a defect in the memory cell array ARY and a redundancy enable bit REN are supplied to the redundancy switching switch RSW via the shift register SR. Then, the connection state between the memory cell units MC0 to MC63 and the redundant memory cell units RMC and the data input / output terminals IO0 to DO63 is switched by the redundancy changeover switch RSW, and the defect of the memory cell array ARY is relieved.

  In the example shown in FIG. 4, the redundancy changeover switch RSW operates based on the defect code CD and the redundancy enable bit REN, and the defect (indicated by the mark X) of the memory cell connected to the word line WL4 in the memory cell unit MC2 is relieved. Be done. More specifically, data input / output terminal IO2 is connected to memory cell unit MC3, data input / output terminals IO61 and IO62 are connected to memory cell units MC62 and MC63, and data input / output terminal IO63 is connected to redundant memory cell unit RMC. . As described above, the data input / output terminals IO0 to IO63 are connected to the memory cell array ARY while avoiding the memory cell portion MC2 including the defect, so that the defect of the memory M1 is relieved.

  FIG. 5 shows an example of the defect status of the memory M1-M10 shown in FIG. 2 and the information programmed in the program unit 30. For example, a defect in the memories M1 to M10 is detected by a test apparatus such as an LSI (Large Scale Integration) tester which tests the semiconductor device SEM2. The test apparatus stores the defect data FDT for each of the memories M1 to M10 identified by the memory number MN based on the test result of the memories M1 to M10. In FIG. 5, the memory M corresponding to the memory number MN is shown in parentheses on the right side of the memory number MN for the sake of clarity. The test apparatus stores the number indicating the memory cell unit MC for remedying the defect as the defective data FDT when there is a repairable defect in the memory M, and indicates the non-defective item when the memory M does not have a defect. Are stored as defect data FDT.

  In the example shown in FIG. 5, the defects exist in the memory cell unit MC2 of the memory M1, the memory cell unit MC10 of the memory M2, and the memory cell unit MC22 of the memory M6, and in the memories M3-M5 and M7-M10. There is no defect. In the following description, it is assumed that a defect that is difficult to be relieved does not occur, such as a defect existing in a plurality of memory cell units MC.

  The test apparatus outputs the program signal PGM shown in FIG. 2 to the program unit 30 based on the failure status of the memories M1-M10 to program the information in the program unit 30.

  Program unit 30 has a storage area for storing difference FDIF of the memory number MN of the memory M in which the defect occurs, a storage area for storing a defect code CD which is the number of the defective memory cell unit MC, and a redundant enable bit REN. It has a plurality of lines including a storage area for storing logic. The program unit 30 is an example of a storage unit which stores defect information (a defect code CD and a redundancy enable bit REN) to be supplied to the memory M for repairing a defect among the memories M1 to M10. Of the memories M1 to M10, the memory M for which a defect is relieved is changed by the redundancy switching switch RSW shown in FIG. 4 to a selection state for selecting the redundancy memory cell unit RMC from the initial state not selecting the redundancy memory cell unit RMC. Is an example of a modified circuit block.

  In the program unit 30, storage regions for storing the logic of the defect code CD and the redundancy enable bit REN respectively store the defect code CD and the redundancy enable bit REN which are selection information supplied to the memory M for repairing the defect. Is an example of a storage area of In the program unit 30, the storage area for storing the difference FDIF is an example of a second storage area for storing the difference FDIF indicating the interval between the two shift registers SR corresponding to the memory M for relieving the defect. The difference FDIF is an example of interval information. The lines of the program unit 30 are identified by the value of the counter FLINE, so that in the following, the lines of the program unit 30 are indicated using the symbol FLINE.

  Defect code CD is 6 bits to identify 64 memory cell units MC0 to MC63, and the sum of the number of bits of defect code CD and redundancy enable bit REN (stored in each shift register SR1 to SR10 The number of bits of information) is 7 bits. As described in FIG. 7, in order to set the defect code CD and the redundancy enable bit REN in each shift register SR, the code bit number NCB, which is the maximum value set in the counter ICB shown in FIG. 6 ”. The code bit number NCB indicates the number of shifts for storing information such as the defect code CD and the redundancy enable bit REN in each shift register SR1 to SR10.

  First, the test apparatus calculates the difference ("4") between the largest memory number MN (= 6) and the second largest memory number MN (= 2) among the memory numbers MN indicating the memory M having a defect. And store it in the area of the difference FDIF in the first line FLINE0. The test apparatus stores a value (“010110” in binary) indicating the defective memory cell unit MC22 of the memory M6 corresponding to the largest memory number MN in the area of the defective code CD in the row FLINE0. The test apparatus stores “1” in the region of the redundant enable bit REN in the row FLINE 0 to indicate that the defect is to be repaired (using the redundant memory cell unit RMC).

  Next, the test apparatus determines that the difference ("1") between the second largest memory number MN (= 2) and the third largest memory number MN (= 1) among the memory numbers MN indicating the memory M having a defect. ) And store in the area of the difference FDIF in the second line FLINE1. The test apparatus stores a value ("001010" in binary) indicating the defective memory cell unit MC10 of the memory M2 corresponding to the second largest memory number MN in the area of the defective code CD in the row FLINE1. The tester stores "1" in the area of the redundant enable bit REN in the row FLINE1.

  The test apparatus stores the same value as the memory number MN in the area of the difference FDIF in the row FLINE2 as a difference with respect to the smallest memory number MN (= 1) among the memory numbers MN indicating the memory M having a defect. The test apparatus stores a value ("000010" in binary) indicating the defective memory cell unit MC2 of the memory M1 corresponding to the smallest memory number MN in the area of the defective code CD in the row FLINE2. The test device stores “1” in the area of the redundant enable bit REN in the row FLINE2. Thus, the value of the difference FDIF, the defect code CD and the redundancy enable bit REN are sequentially stored in the row FLINE in the descending order of the memory number MN. Then, the program of the program unit 30 by the test apparatus is completed. An area not to be programmed in the program unit 30 indicates "0".

  When the memories M2, M3 and M6 have a defect and the other memories M1, M4, M5 and M7-M10 are non-defective products, the area of the difference FDIF of the row FLINE0 is the memory number MN of the memories M6 and M3. “3” indicating the difference is stored. In the area of the difference FDIF of the line FLINE1, "1" indicating the difference between the memory numbers MN of the memories M3 and M2 is stored. In the area of the difference FDIF of the line FLINE2, "2" indicating the memory number MN of the memory M2 is stored.

  In the example shown in FIG. 5, since program unit 30 has five lines FLINE 0 -FLINE 5, when there is a defect in more than five memories M, program unit 30 lacks an area for storing information indicating a defect. . In this case, the test apparatus treats the semiconductor device SEM2 as a defective product. By increasing the number of rows FILNE provided in the program unit 30, it is possible to increase the number of memories M for repairing a defect. The line FLINE of the program unit 30 may be 2 or more and less than the number of memories M (= 10).

  6 and 7 show an example of an operation flow for setting defect information in the scan chain SCANC shown in FIG. Here, the defect information is the defect code CD and the redundancy enable bit REN stored in the program unit 30 shown in FIG. The processes shown in FIGS. 6 and 7 show a control method of the semiconductor device SEM2, and are executed by the transfer control unit 20 shown in FIG. The processes shown in FIGS. 6 and 7 are executed using the hardware of the transfer control unit 20. However, when the transfer control unit 20 includes a processor such as a CPU, the processes may be executed using software.

  First, in step S100, the transfer control unit 20 waits for reception of the activation signal PON from the power supply control unit 12. When the start signal PON is received, in step S102, the transfer control unit 20 initializes the counters FLINE, IRAM, and ICB to "0". Next, in step S104, the transfer control unit 20 outputs the reset signal RST to the shift registers SR1 to SR10. The shift registers SR1 to SR2 are initialized to default values based on the reset signal RST. For example, the default value is a value at which the relief process of the memories M1 to M10 is not executed, and is, for example, all “0”.

  Next, in step S106, the transfer control unit 20 reads out the difference FDIF, the defect code CD and the redundancy enable bit REN stored in the row FLINE of the program unit 30 indicated by the value of the counter FLINE. Next, in step S108, when the read difference FDIF indicates "0", the transfer control unit 20 determines that the setting of the defect information to the scan chain SCINC is completed, and the process proceeds to step S126 illustrated in FIG. Transition. On the other hand, when the read difference FDIF indicates other than “0” (positive value), the transfer control unit 20 shifts the process to step S110 shown in FIG. 7 in order to set the defect information in the scan chain SCINC.

  In step S110 of FIG. 7, the transfer control unit 20 sets the value indicated by the difference FDIF acquired in step S106 in the counter IRAM. Next, in step S112, the transfer control unit 20 increments the redundant enable bit REN and the defect code CD in the scan chain SCINC while incrementing the counter ICB until the value of the counter ICB reaches the shift number NCB (= "6"). Forward. That is, the transfer control unit 20 sequentially transfers the redundancy enable bit REN and the defect code CD to the scan chain SCINC and increments the counter ICB by "1", and the value of the counter ICB is the code bit number. Repeat until NCB.

  Next, in step S114, the transfer control unit 20 decrements the value of the counter IRAM by "1", and resets the counter ICB to "0" in step S116. Next, in step S118, when the value of the counter IRAM is "0", the transfer control unit 20 extends the redundancy enable bit REN and the defect code CD stored in the target row FLINE to a predetermined position of the scan chain SCINC. Judge that it has been transferred. Then, the transfer control unit 20 transfers the process to step S122. On the other hand, when the value of the counter IRAM is other than “0” (positive value), the transfer control unit 20 moves the redundancy enable bit REN and the defect code CD stored in the target row FLINE to a predetermined position of the scan chain SCINC. Judge that it has not transferred. Then, the transfer control unit 20 transfers the process to step S120.

  In step S120, the transfer control unit 20 transfers "0" to the scan chain SCINC while incrementing the counter ICB until the value of the counter ICB reaches the shift number NCB (= "6"). That is, the transfer control unit 20 repeats the operation of sequentially transferring "0" to the scan chain SCINC and the operation of incrementing the counter ICB by "1" until the value of the counter ICB reaches the code bit number NCB. Then, the processes of steps S114, S116, and S120 are repeated until the value of the counter IRAM becomes "0". As a result, the default value is set in the shift register SR corresponding to the memory (M3 to M5 in FIG. 5 or the like) in which there is no defect between the two memories (M2 or M6 in FIG. 5 or the like).

  In step S122, the transfer control unit 20 increments the counter FLINE by "1". Next, in step S124, the transfer control unit 20 determines whether the value of the counter FLINE is the maximum number of lines of the program unit 30 (= 5 lines). When the value of the counter FLINE is the maximum number of lines of the program unit 30, it is determined that all the defect codes CD and the redundancy enable bit REN stored in the program unit 30 have been set in the predetermined shift register SR It is transferred to S126. The transition from step S124 to step S126 is performed when the defect code CD and the redundancy enable bit REN are stored in all the rows FLINE0 to FLINE4 of the program unit 30 shown in FIG. On the other hand, when the value of the counter FLINE does not reach the maximum number of lines of the program unit 30, there is a possibility that the transfer control unit 20 does not read out all the defect codes CD and redundant enable bits REN stored in the program unit 30. There is. Therefore, the process proceeds to step S106 illustrated in FIG. Then, the reading of the defect code CD and the redundancy enable bit REN for the next row FLINE and the transfer to the scan chain SCINC are executed.

  In step S126, the transfer control unit 20 outputs the operation enable signal OPE to the operation control unit 20 shown in FIG. 2 since the setting of the defect information to the scan chain SCINC is completed. Operation control unit 20 notifies CPU in semiconductor device SEM2, peripheral circuits, and the like that memory M1-M10 is enabled based on the reception of operation enable signal OPE. Then, the semiconductor device SEM2 starts operation as a system for realizing a predetermined function.

  By the processing shown in FIGS. 6 and 7, redundant enable bit REN and defect code CD are set in shift register SR corresponding to memory M having a defect, and default values to shift register SR corresponding to memory M having no defect are present. Is set. At this time, the probability of repairing a defect using the redundant memory cell unit RMC is lower in the memory M connected to the shift register SR located downstream than in the memory M connected to the shift register SR located upstream. . Then, among the shift registers SR in which the defect information is set, the shift register SR further downstream than the shift register SR located on the most downstream side is set to the default value by the reset signal RST. Setting can be omitted. Therefore, the setting time of the information to scan chain SCINC can be shortened compared with the past, and the starting time of semiconductor device SEM 2 can be shortened compared with the past.

  FIG. 8 shows an example of an operation of setting defect information in the scan chain shown in FIG. FIG. 8 shows operations of the transfer control unit 20 and the scan chain SCANC in the case of transferring the defect information of the program unit 30 shown in FIG. 5 to the scan chain SCANC. The underlined numbers in FIG. 8 indicate that the values have changed. Defect information set in the shift registers SR1 to SR10 is indicated by a bold frame.

  First, the transfer control unit 20 sets a default value (= "0") to all the shift registers SR1 to SR10 by the reset signal RST (Fig. 8 (a)). As a result, setting of information in the shift registers SR7 to SR10 on the downstream side by the scan operation of the scan chain SCCAN can be omitted. Next, the transfer control unit 20 reads the difference FDIF, the defect code CD and the redundancy enable bit REN stored in the line FLINE 0 of the program unit 30 (FIG. 8 (b)).

  Next, the transfer control unit 20 sets the value (= "4") indicated by the difference FDIF in the counter IRAM, and scans the defect code CD ("22" in decimal) and the redundancy enable bit REN ("1"). Transfer to chain SC ANc (FIG. 8 (c)). Thereafter, the transfer control unit 20 transfers the default value "0" to the scan chain SCINC until the value of the counter IRAM becomes "0" (Fig. 8 (d), (e), (f)). As a result, the values set in the shift register SR corresponding to the memories M3, M4, and M5 having no defect are transferred to the scan chain SCINC.

  Next, the transfer control unit 20 increments the counter FLINE by “1” (= “1”), and the value of the counter FLINE does not reach the maximum value, so the difference FDIF stored in the row FILNE1, the defect code CD and the redundancy The enable bit REN is read (FIG. 8 (g)). After this, the transfer control unit 20 sets the value (= “1”) indicated by the difference FDIF in the counter IRAM as in FIG. 8C, and the defect code CD (“10” in decimal) and the redundancy enable The bit REN ("1") is transferred to the scan chain SCINC (Fig. 8 (h)). Since the value of the counter IRAM is decremented to "0", the transfer to the scan chain SCINC of the default value "0" is not executed.

  Next, the transfer control unit 20 increments the counter FLINE by “1” (= “2”) as in FIG. 8 (g). Since the value of the counter FLINE has not reached the maximum value, the transfer control unit 20 reads the difference FDIF, the failure code CD and the redundancy enable bit REN stored in the row FILNE 2 (FIG. 8 (i)).

  After that, the transfer control unit 20 sets the value (= “1”) indicated by the difference FDIF in the counter IRAM as in FIG. 8C, and the defect code CD (“2” in decimal) and the redundancy enable The bit REN ("1") is transferred to the scan chain SCINC (Fig. 8 (j)).

  Next, the transfer control unit 20 increments the counter FLINE by “1” (= “3”). Since the value of the counter FLINE has not reached the maximum value, the transfer control unit 20 reads “0” stored in the area storing the difference FDIF of the line FILNE3, the defect code CD and the redundancy enable bit REN (FIG. 8). (K)). Since the value indicating the difference FDIF is “0”, the transfer control unit 20 determines that the setting of the defect information to the scan chain SCINC is completed, and outputs the operation enable signal OPE.

  As described above, also in the embodiments shown in FIGS. 2 to 8, as in the embodiment shown in FIG. 1, the shift register SR is connected to the transfer control unit 20 in the order corresponding to the memory M having a high probability of occurrence of defects. . As a result, the time until the defect information is set in the shift register SR can be shortened compared to the conventional case, and the startup time until the operation of the semiconductor device SEM2 becomes possible can be shortened compared to the conventional case. Further, the program unit 30 does not have an area for holding information set in all shift registers SR, and the semiconductor device SEM2 does not have a selector or the like for separating the shift register SR corresponding to the non-defective memory M from the transfer path. . As a result, the time for setting defect information in the shift register SR can be shortened without increasing the circuit size of the semiconductor device SEM2.

  Furthermore, in the embodiment shown in FIGS. 2 to 8, the transfer control unit 20 outputs the reset signal RST before transferring the defect information to the scan chain SCINC, and does not execute the defect relief process of the memory M A default value is set in each shift register SR. As a result, it is possible to omit setting the default value by the scan operation in the shift register SR further downstream than the shift register SR located at the most downstream side where defect information is set. Therefore, the setting time of the information to scan chain SCINC can be shortened compared with the past, and the starting time of semiconductor device SEM 2 can be shortened compared with the past. In other words, since the transfer control unit 20 can output the operation enable signal OPE earlier than in the conventional case, the operation control unit 10 can notify the CPU that the memories M1-M10 can be accessed as compared to the conventional case. We can notify you early. As a result, the performance of the semiconductor device SEM2 can be improved as compared to the prior art.

  The transfer control unit 20 transfers the default value to the shift register SR based on the difference FDIF stored in the program unit 30. Thus, even when the default value set in the shift register SR by the reset signal RST is lost due to the transfer of defect information, the default value can be reset.

  FIG. 9 shows another embodiment of a semiconductor device and a control method of the semiconductor device. Elements that are the same as or similar to the elements described in the embodiment shown in FIGS. 2 to 7 are given the same reference numerals, and detailed descriptions thereof will be omitted.

  The semiconductor device SEM3 of this embodiment has a transfer control unit 20A and a program unit 30A instead of the transfer control unit 20 and the program unit 30 shown in FIG. The semiconductor device SEM3 further includes a scan chain SCINC1 connected to six memories M1 to M6 and a scan chain SCANCE2 connected to four memories M7 to M10. The memories M1-M10 are similar to the memories M1-M10 shown in FIG. That is, in the memories M1 to M6, the probability that a defect occurs is higher in the memory M connected to the shift register SR closer to the transfer control unit 20A. Further, in the memories M7 to M10, the probability that a defect occurs is higher in the memory M connected to the shift register SR closer to the transfer control unit 20A. In other words, the probability that the redundant memory cell unit RMC shown in FIG. 4 is used in each of the scan chains SCANC1 and SCANCE2 is higher for the memory M connected to the shift register SR closer to the transfer control unit 20A. As in FIG. 2, the probability that a failure occurs in each of the memories M1 to M6 is higher than the probability that a failure occurs in each of the memories M7 to M10. The memories M1-M6 are an example of a first circuit block group, and the memories M7-M10 are an example of a second circuit block group.

  Scan chain SCANC1 has shift registers SR1-SR6 connected in series corresponding to each of memories M1-M6. The first-stage shift register SR1 receives data DT1 output from the transfer control unit 20A. Each shift register SR1-SR6 is set to a default value "0" based on reset signal RST1, and sequentially transfers data DT1 from the upstream side (transfer control unit 20A side) to the downstream side in synchronization with scan clock signal SCLK1. Do.

  Scan chain SCINC2 includes shift registers SR7-SR10 connected in series corresponding to each of memories M7-M10. The first-stage shift register SR7 receives the data DT2 output from the transfer control unit 20A. Each shift register SR7-SR10 is set to the default value "0" based on reset signal RST2, and sequentially transfers data DT2 from the upstream side (transfer control unit 20A side) to the downstream side in synchronization with scan clock signal SCLK2. Do.

  The transfer control unit 20A includes a reset generation unit RSTGEN2 that generates a reset signal RST1 output to the scan chain SCANDC1 and a reset signal RST2 output to the scan chain SCAND2. The transfer control unit 20A has a clock generation unit CLKGEN2 that generates a scan clock signal SCLK1 to be output to the scan chain SCINC1 and a scan clock signal SCLK2 to be output to the scan chain SCANC2. The reset generation unit RSTGEN2 has the same function as the reset generation unit RSTGEN1 shown in FIG. 2, and the clock generation unit CLKGEN2 has the same function as the clock generation unit CLKGEN1 shown in FIG.

  The transfer control unit 20A also has counters FLINE1, IRAM1, ICB1 used to transfer defect information to the scan chain SCANC1, and counters FLINE2, IRAM2, ICB2 used to transfer defect information to the scan chain SCANC2. The counters FLINE1 and FLINE2 are used to identify the lines of the program unit 30A, similarly to the counter FLINE shown in FIG. Similar to the counter IRAM shown in FIG. 2, the counters IRAM1 and IRAM2 are used to set the default value "0" in the shift register SR by the scan operation of the scan chains SCINC1 and SCINC2. The counters ICB1 and ICB2 are used to count the number of shifts for storing information in each shift register SR, like the counter ICB shown in FIG.

  The transfer control unit 20A transfers the defect information to the scan chain SCANC1 using the counters FLINE1, IRAM1, and ICB1, and transfers the defect information to the scan chain SCANC2 using the counters FLINE2, IRAM2, and ICB2. The transfer control unit 20A transfers defect information to the scan chains SCINC1 and SCCAN2 except for the procedure for reading out the defect information from the program unit 30A, and the transfer control unit 20 shown in FIG. 2 transfers the defect information to the scan chain SCINC. It is similar to the operation.

  The transfer control unit 20A includes the counter groups FLINE1, IRAM1, and ICB1, and the counter groups FLINE2, IRAM2, and ICB2, and thus can transfer defect information in parallel to the scan chains SCINC1 and SCANCE2. The transfer control unit 20A may sequentially transfer defect information to each of the scan chains SCINC1 and SCINC2 using one counter group FLINE, IRAM, and ICB as in FIG.

  Similar to program unit 30 shown in FIG. 2, program unit 30A has a plurality of program elements in which information is stored by program signal PGM. An example of the program unit 30A is shown in FIG.

  FIG. 10 shows an example of the failure status of the memory M1-M10 shown in FIG. 9 and information programmed in the program unit 30A. Elements that are the same as or similar to those in FIG. 5 are given the same reference numerals as in FIG. 5, and detailed descriptions thereof will be omitted. The defect statuses of the memories M1-M10 are the same as the defect statuses shown in FIG. 5 except that there is a defect in the memory M8, and can be found out by the test apparatus for testing the semiconductor device SEM3.

  The configuration of program unit 30A is the same as that of program unit 30 shown in FIG. However, the test device sequentially stores the defect information and the difference FDIF to be transferred to the scan chain SCINC1 from the row FILNE0 to the row FLINE4. In addition, the test apparatus sequentially stores the defect information and the difference FDIF to be transferred to the scan chain SCINC2 from the row FILNE4 to the row FLINE0. As a result, defect information to be transferred to the two scan chains SCANC1 and SCANC2 can be stored in one program unit 30A.

  In the example shown in FIG. 10, the memories M1, M2, M6 and M8 have a defect. The defect information of the memories M1, M2, and M6 connected to the scan chain SCANC1 is stored in lines FLINE2, FLINE1, and FLINE0, respectively, as in FIG. On the other hand, the defect information of the memory M8 connected to the scan chain SCINC2 is stored in the last line FLINE4. At this time, since there is a defect in only one memory M8 corresponding to scan chain SCARC2, “6” is subtracted from memory number MN (= “8”) of memory M8 in the area of difference FDIF of row FLINE4. Value ("2") is stored. That is, a value obtained by subtracting “6” from memory number MN as a difference with respect to the smallest memory number MN among memory numbers MN indicating a memory M having a defect connected to scan chain SCINC2 corresponds to difference FDIF of row FLINE 4. It is stored in the area. Here, “6” is used to determine the position of the memory M having a defect from the upstream side when the memory M having a defect is one in the memories M7 to M10.

  Since the defect information is stored in the program unit 30A from both the first line FLINE0 and the last line FLINE4, the program unit 30A can determine whether the defect information corresponds to any of the scan chains SCINC1 and SCINC2. Stored. For example, one or more blank lines FLINE are provided between the area storing the defect information of the memories M1 to M6 and the area storing the defect information of the memories M7 to M10. Thus, the transfer control unit 20A can determine the defect information to be transferred to the scan chain SCINC1 and the defect information to be transferred to the scan chain SCINC2.

  In the example shown in FIG. 10, when there is a defect in the memory M connected to one of the scan chains SCINC1 and SCINC2, defect information of up to five memories M can be stored in five lines FLINE0 to FLINE4. On the other hand, when there is a defect in the memories M connected to each of the scan chains SCANC1 and SCANCE2, defect information of up to four memories M can be stored in five lines FLINE0 to FLINE4.

  The setting of the defect information to the scan chain SCANC1 is realized by the transfer control unit 20A executing the same processing as in FIG. 6 and FIG. On the other hand, setting of defect information to scan chain SCINC2 is realized by changing the processing shown in FIGS. 6 and 7 as follows. In step S102 shown in FIG. 6, the value of the counter FLINE is initialized to "5". In step S122 shown in FIG. 7, the counter FLINE is decremented by "1". In step S124 shown in FIG. 7, when the value of counter FLINE is "1" or more, the process proceeds to step S106 shown in FIG. 6, and when the value of counter FLINE is "0", the process proceeds to step S126. Ru. The probability that a defect does not exist in the memories M1 to M6 and a defect exists in the memories M7 to M10 is extremely low (almost "0"). For this reason, in the setting operation of the defect information to the scan chain SCINC2, the determination in step S124 may be omitted, and after the process of step S122, the process may always shift to the process of step S106.

  By the transfer operation of information to the scan chains SCINC1 and SCINC2 by the transfer control unit 20A, the same information as the information shown in FIG. 8K is set in the shift registers SR1 to SR10. When there is no defect in the memory M8, transfer of defect information to the scan chain SCINC2 can be omitted. The probability that a defect occurs in the memories M7 to M10 connected to the scan chain SCINC2 is lower than the probability that a defect occurs to the memories M1 to M6 connected to the scan chain SCANCE1. For this reason, the frequency at which the transfer of defect information to the scan chain SCANC2 is omitted is higher than that in the case where the memory M is connected to one of the scan chains SCINC1 and SCINC2 without considering the probability that a defect will occur. When the defect information is not transferred to scan chain SCINC2, shift registers SR7-SR10 do not receive scan clock signal SCLK2, and the transfer operation of scan chain SCARC2 is not performed. Therefore, power consumption of the semiconductor memory device MEM3 can be reduced as compared with the case where defect information is transferred by operating all the shift registers SR1 to SR10.

  As described above, also in the embodiments shown in FIGS. 9 to 10, similarly to the embodiments shown in FIGS. 1 to 8, the time for setting defect information in the shift register SR without increasing the circuit size of the semiconductor device SEM3. It can be shortened.

  Further, in the embodiments shown in FIGS. 9 to 10, in each of scan chains SCINC1 and SCNC2, shift register SR is connected to transfer control unit 20A in the order corresponding to memory M having a high probability of using redundant memory cell unit RMC. . The setting of the defect information in the memories M1 to M6 is performed using the scan chain SCINC1, and the setting of the defect information in the memories M7 to M10 is performed using the scan chain SCANCE2. The probability that a defect occurs in the memories M1 to M6 connected to the scan chain SCANC1 is higher than the probability that a defect occurs to the memories M7 to M10 connected to the scan chain SCANCE2. As a result, it is possible to lower the frequency of setting the defect information in the shift registers SR7 to SR10 by operating the scan chain SCANC2, and to reduce the power consumption of the semiconductor memory device MEM3.

  Further, when defect information is transferred in parallel to both scan chains SCINC1 and SCINC2, the time until defect information is set in each shift register SR can be shortened compared to the prior art. As a result, the start-up time until the operation of the semiconductor device SEM3 becomes possible can be shortened compared to the prior art.

  FIG. 11 shows another embodiment of the semiconductor device and the control method of the semiconductor device. Elements that are the same as or similar to the elements described in the embodiment illustrated in FIGS. 2 to 10 are given the same reference numerals, and detailed descriptions thereof will be omitted.

  The semiconductor device SEM4 of this embodiment has a program unit 30B instead of the program unit 30 shown in FIG. An example of the program unit 30B is shown in FIG. Further, each shift register SR1-SR10 of scan chain SCINC has, for example, four flip-flop circuits connected in series to hold 4-bit information. In each shift register SR1-SR10, a speed code SPDC for adjusting the operation timing of the control circuit in each of the memories M1-M10 is stored. An example of a control circuit is shown in FIG.

  For example, the control circuit is a sense amplifier which is disposed between the memory cell array ARY and the redundancy switching switch RSW shown in FIG. 4 and amplifies the signal amount of data read from the memory cell. Alternatively, the control circuit is a word line drive circuit that activates a word line WL (FIG. 4) that selects a memory cell in a read operation or a write operation of the memory M.

  Similar to the transfer control unit 20 shown in FIG. 2, the transfer control unit 20 generates a reset signal RST based on the start signal PON, and then generates a scan clock signal SCLK of a predetermined number of pulses. Then, the transfer control unit 20 executes an operation of transferring the data DT read from the program unit 30B to the scan chain SCINC. However, the data DT transferred to the scan chain SCANC is not defect information for relieving a defect in the memory but includes a speed code SPDC for changing the operation timing of the control circuit in the memory M from the initial state (default state).

  In the memories M1 to M10 illustrated in FIG. 11, the memory M having a smaller number has a smaller (stricken) timing margin than the memory M having a large number. The shift registers SR1 to SR10 are connected to the transfer control unit 20 in the order corresponding to the memories M1 to M10 having the smaller timing margin.

  A memory M having a small timing margin has a high probability of being determined as a failure in a test by a test apparatus as compared to a memory M having a large timing margin. The memory M determined to be defective may be able to relieve the defect without using a relief circuit for relieving the defect by changing the operation timing of the control circuit. That is, the memory M having a small timing margin has a high probability (probability) of changing the operation timing of the control circuit from the standard value, as compared with the memory M having a large timing margin. Whether or not to change the operation timing of the control circuit is determined based on the test result by a test device that tests the memory M.

  The area of each memory M1-M10 may be different from the area of each memory M1-M10 shown in FIG. For example, the area of the memory M1 may be smaller than the area of the memory M2. However, signal wiring in the memory M tends to be longer as the area of the memory M is larger, and as a result, the timing margin of the memory M tends to be smaller as the area of the memory M is larger.

  When the timing margin of the memory M becomes smaller as the area of the memory M becomes larger, the scan chain SCANC shown in FIG. 11 may be merged with the scan chain SCANC shown in FIG. That is, the speed code SPDC for changing the operation timing of the control circuit in the memory M and the defect information for relieving the defect in the memory M may be transferred to each shift register SR1-SR10 of the scan chain SCINC. In this case, as shown in FIG. 4, each memory M1-M10 has a redundant memory cell unit RMC for repairing a defective memory cell unit MC. Program unit 30B has a plurality of lines FLINE including an area for storing speed code SPDC and defect information. The transfer control unit 20 transfers the speed code SPDC read from the program unit 30B and the defect information to the scan chain SCANC.

  Further, as shown in FIG. 9, the scan chain SCINC may be divided into two scan chains SCINC1 and SCINC2.

  FIG. 12 shows an example of the adjustment circuit ADJ1 mounted in each memory M shown in FIG. 11 and adjusting the operation timing of the control circuit in each memory M. The adjustment circuit ADJ1 includes a plurality of delay circuits DLY (DLY1 to DLY7) that receive a control signal CNT for operating a control circuit (a sense amplifier, a word line drive circuit or the like), and a selection unit SEL. The propagation delay times of the delay circuits DLY1 to DLY7 are different from each other. In FIG. 12, the amount of propagation delay time is indicated by the lateral length of the delay circuits DLY1 to DLY7. That is, of the delay circuits DLY1 to DLY7, the propagation delay time of the delay circuit DLY1 is the shortest, and the propagation delay time of the delay circuit DLY7 is the longest. The delay circuits DLY1-DLY7 are examples of internal circuits included in each of the memories M1-M10.

  The selection unit SEL selects one of the delay signals obtained by delaying the control signal CNT by the delay circuits DLY1 to DLY7 based on the speed code SPDC, and outputs the selected delay signal as the adjustment control signal ACNT to the control circuit. That is, the selection unit SEL selects one of the delay circuits DLY1 to DLY7 that outputs the delay signal based on the speed code SPDC.

  The "high-speed 3", "high-speed 2", "high-speed 1", "standard", "low-speed 1", "low-speed 2" and "low-speed 3" attached to the outputs of delay circuits DLY1-DLY7 The operation timing of the control circuit in the memory M when the output of DLY 7 is selected by the selection unit SEL is shown. "High speed 3", "high speed 2", and "high speed 1" indicate that the operation timing of the control circuit is earlier than "standard". The "high speed 3" operation timing is earlier than the "high speed 2" operation timing, and the "high speed 2" operation timing is earlier than the "high speed 1" operation timing. “Slow 1”, “Slow 2” and “Slow 3” indicate that the operation timing of the control circuit is later than “Standard”. The "low speed 3" operation timing is later than the "low speed 2" operation timing, and the "low speed 2" operation timing is later than the "low speed 1" operation timing.

  FIG. 13 shows an example of operation timings of control circuits in the memories M1 to M10 shown in FIG. 11 and information programmed in the program unit 30B. Elements that are the same as or similar to those in FIG. 5 are given the same reference numerals as in FIG. 5, and detailed descriptions thereof will be omitted.

  The test apparatus for testing the semiconductor device SEM4 tests the timing margin of each of the memories M1 to M10, and determines a memory M for changing the operation timing of the control circuit with respect to a standard value (default value). For example, when the threshold voltage of the transistor included in semiconductor device SEM4 is lower than the standard value due to the fluctuation of the semiconductor manufacturing process for manufacturing semiconductor device SEM4, the operating speed of memories M1-M10 is higher than the operating speed corresponding to the standard value. Become. The test apparatus decides to delay the operation timing of the control circuit of the memory M in which the timing margin becomes smaller than the predetermined value due to the increase of the operation speed ("low speed 1", "low speed 2", "low speed 3 shown in FIG. "One of the As a result, the timing margin of the memory M can be kept within a predetermined margin, and the semiconductor device SEM 4 can be prevented from becoming defective. In this embodiment, the operation timing of the control circuit can be lowered to three levels with respect to the standard value.

  On the other hand, when the threshold voltage of the transistor included in the semiconductor device SEM4 is higher than the standard value, the operating speed of the memories M1-M10 is lower than the operating speed corresponding to the standard value. The test apparatus decides to accelerate the operation timing of the control circuit of the memory M in which the timing margin becomes smaller than the predetermined value due to the drop of the operation speed ("high speed 1", "high speed 2", "high speed 3 shown in FIG. "One of the As a result, the timing margin of the memory M can be kept within a predetermined margin, and the semiconductor device SEM 4 can be prevented from becoming defective. In this embodiment, the operation timing of the control circuit can be raised up to three levels with respect to the standard value.

  In the example shown in FIG. 13, the test apparatus determines that the operation mode SPD indicating the operation timing of the control circuit of the memories M1 and M2 whose timing margin is smaller than the predetermined value is set to "low speed 2". In addition, the test apparatus determines to set the operation mode SPD of the memory M6 having a timing margin smaller than a predetermined value to “low speed 1”. Furthermore, the test apparatus decides to set the operation mode SPD of the memories M3-M5 and M7-M10 whose timing margin is larger than the predetermined value to "standard" (default value).

  Program unit 30B changes the operation mode SPD to "standard". A plurality of lines including an area for storing difference FDIF of memory number MN of memory M and an area for storing speed code SPDC indicating operation mode SPD. Has FLINE. The area for storing the speed code SPDC has 2 bits for changing the operation mode SPD to the low speed side by 3 levels and 2 bits for changing the operation mode SPD to the high speed side (4 bits in total). In order to set the speed code SPDC in each shift register SR, the code bit number NCB which is the maximum value set in the counter ICB shown in FIG. 11 is “3”.

  The test apparatus programs, in the program unit 30B, the speed code SPDC indicating the operation mode SPD of the memory M for changing the operation timing of the control circuit based on the test result of the timing margin of the memories M1-M10. The method of programming the speed code SPDC to the program unit 30B is the same as that shown in FIG.

  For example, among the memory numbers MN indicating the memory M for changing the operation mode SPD to "standard", the test apparatus has the largest memory number MN (= 6) and the second largest memory number MN (= 2). Calculate the difference ("4") of Then, the test apparatus stores the calculated difference in the area of the difference FDIF in the first line FLINE0. The test device stores a value (“0100” in binary notation; low speed 1) indicating the operation mode SPD of the memory M6 corresponding to the largest memory number MN in the area of the speed code SPDC in the line FLINE0.

  Next, the test device selects the second largest memory number MN (= 2) and the third largest memory number MN (==) of the memory numbers MN indicating the memory M changing the operation mode SPD to "standard". Calculate the difference ("1") from 1). Then, the test apparatus stores the calculated difference in the area of the difference FDIF in the second line FLINE1. The test device stores a value ("1000" in binary; low speed 2) indicating the operation mode SPD of the memory M2 corresponding to the second largest memory number MN in the area of the speed code SPDC in the line FLINE1.

  The test apparatus sets the same value as the memory number MN as the difference with respect to the smallest memory number MN (= 1) among the memory numbers MN indicating the memory M for changing the operation mode SPD to “standard”. Store in the area of FDIF. The test device stores a value ("1000" in binary; low speed 2) indicating the operation mode SPD of the memory M1 corresponding to the smallest memory number MN in the area of the speed code SPDC in the line FLINE2. Thus, the value of the difference FDIF and the speed code SPDC are sequentially stored in the row FLINE in the descending order of the memory number MN. Then, the program of the program unit 30B by the test apparatus is completed. In the program unit 30B, an area not to be programmed indicates "0".

  Similarly to FIG. 5, since program unit 30B has five lines FLINE0 to FLINE5, when changing the operation timing of the control circuit of memory M exceeding five, the area for storing speed code SPDC in program unit 30B is Run short. In this case, the test apparatus treats the semiconductor device SEM 4 as a defective product. The number of memories M for changing the operation timing of the control circuit can be increased by increasing the number of rows FILNE provided in the program unit 30B. The line FLINE of the program unit 30B may be 2 or more and less than the number of memories M (= 10).

  The process of transferring the speed code SPDC to the scan chain SCINC by the transfer control unit 20 is realized by replacing the defect code CD and the redundancy enable bit REN with the speed code SPDC in steps S106 and S112 of FIGS. However, the value of the code bit number NCB in steps S112 and S120 is set to "3". The operation of transferring the speed code SPDC to the scan chain SCINC by the transfer control unit 20 is realized by replacing the defective code CD and the redundancy enable bit REN in FIG. 8 with the speed code SPDC.

  In the example shown in FIG. 13, the speed code SPDC is not transferred to the shift register SR7-SR10 corresponding to the memory M7-M10 in which the speed code SPDC is set to "standard" as in the example shown in FIG. As a result, at the time of activation of the semiconductor memory M1-M10, the time until setting the speed code SPDC in the shift register SR can be shortened compared to the prior art.

  Note that the value (default value) of the speed code SPDC set in each shift register SR corresponding to “standard” may be other than “0”. For example, in FIG. 13, the speed code SPDC indicating "high speed 3"-"high speed 1", "standard", "low speed 1"-"low speed 3" is binary "000"-"010", "011" , "100"-"110" ("standard" is "011"). In this case, the flip-flop circuit of each shift register SR has a set terminal for setting the held value to logic 1 and a reset terminal for resetting the held value to logic 0. Then, the reset signal RST is supplied to the set terminal or reset terminal of each flip-flop flop circuit according to the default value held by each shift register SR. Further, in step S120 shown in FIG. 7, the logic indicating the default value instead of “0” is transferred to the scan chain SCANC. This allows the default value to be assigned to a value other than "0".

  As described above, also in the embodiments shown in FIGS. 11 to 13, similarly to the embodiments shown in FIGS. 1 to 10, the time for setting the speed code SPDC in the shift register SR without increasing the circuit size of the semiconductor device SEM4. Can be shortened.

  Furthermore, in the embodiment shown in FIGS. 11 to 13, the shift register SR is connected to the transfer control unit 20 in the order corresponding to the memory M having a small timing margin and having a high probability of being judged as a failure in a test by a test apparatus. . As a result, the time until the speed code SPDC for adjusting the timing margin of the memory M is set in the shift register SR can be shortened compared to the conventional case, and the startup time until the operation of the semiconductor device SEM4 becomes possible It can be shortened compared to

  FIG. 14 shows another embodiment of the semiconductor device and the control method of the semiconductor device. Elements that are the same as or similar to the elements described in the embodiment illustrated in FIGS. 2 to 13 are given the same reference numerals, and detailed descriptions thereof will be omitted.

  The semiconductor device SEM5 of this embodiment has a transfer control unit 20C and a program unit 30C instead of the transfer control unit 20 and the program unit 30B shown in FIG. An example of the program unit 30C is shown in FIG. Also, each shift register SR1-SR10 of scan chain SCINC has two flip-flop circuits connected in series to hold 2-bit information. In each shift register SR1-SR10, a part of the speed code SPDC (speed level SLVL shown in FIG. 15) for adjusting the operation speed of each memory M1-M10 is stored. Each memory M1-M10 has an adjustment circuit similar to the adjustment circuit ADJ1 shown in FIG.

  The transfer control unit 20C includes a counter FLINE, an IRAM, an ICB, a reset generation unit RSTGEN1, and a clock generation unit CLKGEN3. The clock generation unit CLKGEN3 has a function of fixing the logic of the scan clock signal SCLK to the high level or the low level after transferring the speed level SLVL which is a part of the speed code SPDC to the scan chain SCINC. An example of the clock generation unit CLKGEN3 is shown in FIG. The clock generation unit CLKGEN3 may be disposed outside the transfer control unit 20C. Examples of the operation of the transfer control unit 20C are shown in FIGS. 20 to 22.

  The memories M1-M10 are the same as the memories M1-M10 shown in FIG. 11 except that the number of bits of the received speed code SPDC is different. However, in the semiconductor device SEM5, the logic of the scan clock signal SCLK is used for one bit (the mode bit MD shown in FIG. 15) of the speed code SPDC supplied to each of the memories M1-M10. Therefore, the clock signal line for transmitting the scan clock signal SCLK is connected to the memories M1 to M10 in order to supply one bit of the speed code SPDC to the selection unit SEL shown in FIG.

  Thereby, the number of flip flop circuits of each shift register SR1-SR10 can be reduced compared to the case where all bits of the speed code SPDC are supplied to the memories M1-M10 via the shift register SR1-SR10. As a result, the setting time of the speed code SPDC to the scan chain SCINC can be shortened compared to the conventional case, and the startup time of the semiconductor device SEM5 can be shortened compared to the conventional case.

  If the timing margin of the memory M becomes smaller as the area of the memory M becomes larger, the scan chain SCANC shown in FIG. 14 and the scan chain SCARC shown in FIG. 2 may be merged. That is, the speed code SPDC for changing the operation timing of the control circuit in the memory M and the defect information for relieving the defect in the memory M may be transferred to each shift register SR1-SR10 of the scan chain SCINC. In this case, as shown in FIG. 4, each memory M1-M10 has a redundant memory cell unit RMC for repairing a defective memory cell unit MC. Program unit 30C has a plurality of lines FLINE including an area for storing speed code SPDC and defect information. The transfer control unit 20C transfers the speed code SPDC read from the program unit 30C and the defect information to the scan chain SCANC.

  Further, as shown in FIG. 9, the scan chain SCINC may be divided into two scan chains SCINC1 and SCINC2.

  FIG. 15 shows an example of the operation timing of the control circuit in the memory M1-M10 shown in FIG. 14 and information programmed in the program unit. The elements that are the same as or similar to those in FIGS. 5 and 13 are assigned the same reference numerals as those in FIGS. 5 and 13, and detailed descriptions thereof will be omitted.

  The test apparatus for testing the semiconductor device SEM5 tests the timing margin of each memory M1-M10 as in FIG. 13, and sets the operation timing of the control circuit such as the sense amplifier or the word line drive circuit to the standard value (default value). The memory M to be changed is determined. The operation timing can be as high as three steps with respect to the standard value as in FIG. 13 (high speed 1, high speed 2, high speed 3) or as low as three steps with respect to the standard value. It is possible (low speed 1, low speed 2, low speed 3).

  In the example shown in FIG. 15, the test apparatus determines that the operation mode SPD indicating the operation timing of the control circuit of the memories M1 and M2 whose timing margin is smaller than the predetermined value is set to high speed 2. In addition, the test apparatus determines to set the operation mode SPD of the memory M6 having a timing margin smaller than a predetermined value to high speed 1. Furthermore, the test apparatus determines to set the operation mode SPD of the memories M3-M5 and M7-M10 whose timing margin is larger than a predetermined value to a standard value (default value).

  Similar to the program unit 30B shown in FIG. 13, the program unit 30C changes the operation mode SPD to "standard" and stores an area for storing the difference FDIF of the memory number MN of the memory M and an area for storing the speed code SPDC. With multiple lines FLINE containing However, the area for storing the speed code SPDC includes an area for storing the mode bit MD (1 bit) and an area for storing the speed level SLVL (2 bit). As described in FIG. 22, the speed level SLVL is transferred to the scan chain SCINC, but the mode bit MD is not transferred. In order to set the speed level SLVL in each shift register SR, the code bit number NCB which is the maximum value set in the counter ICB shown in FIG. 14 is “1”.

  The mode bit MD is set to “0” indicating the low speed mode when the speed level SLVL is set to “low 1”, “low 2”, or “low 3”. The mode bit MD is set to "1" which indicates the high speed mode when the speed level SLVL is set to any one of "high speed 1", "high speed 2" and "high speed 3". The mode bit MD is an example of second selection information commonly supplied to the selection unit SEL (FIG. 12) of the memories M1 to M10. Then, the selection unit SEL shown in FIG. 12 receives the value of the mode bit MD and the value of the speed level SLVL as the speed code SPDC, and converts any one of the delay signals output from the delay circuits DLY1 to DLY7 into the speed code SPDC. Select based on.

  The low speed mode is set when the timing margin of the memory M is smaller than a predetermined margin due to the threshold voltage of the transistor included in the semiconductor device SEM5 being lower than the standard value. The high-speed mode is set when the timing margin of the memory M is smaller than a predetermined margin due to the threshold voltage of the transistor included in the semiconductor device SEM5 being higher than the standard value. Since the tendency of fluctuation of the threshold voltage is the same in all circuits in the semiconductor device SEM5, "low speed" and "high speed" are not mixed and programmed in the program unit 30C.

  The speed level SLVL is set to one of “standard”, “low speed 1”, “low speed 2”, and “low speed 3” according to the logical value of 2 bits when the mode bit MD indicates the low speed mode. In addition, the speed level SLVL is set to one of "standard", "high speed 1", "high speed 2", and "high speed 3" according to the logical value of 2 bits when the mode bit MD indicates the high speed mode. Ru. The speed level SLVL is an example of first selection information individually supplied to the selection unit SEL (FIG. 12).

  The test apparatus programs the program code 30C with a speed code SPDC (MB, SLVL) indicating the operation mode SPD of the memory M for changing the operation timing of the control circuit based on the test result of the timing margin of the memories M1-M10. The method of programming the speed code SPDC to the program unit 30C is the same as that shown in FIGS.

  For example, among the memory numbers MN indicating the memory M for changing the operation mode SPD to "standard", the test apparatus has the largest memory number MN (= 6) and the second largest memory number MN (= 2). Calculate the difference ("4") of Then, the test apparatus stores the calculated difference in the area of the difference FDIF in the first line FLINE0. The test apparatus stores a value ("101" in binary; high speed 1) indicating the operation mode SPD of the memory M6 corresponding to the largest memory number MN in the area of the speed code SPDC in the line FLINE0.

  Next, the test apparatus selects the second largest memory number MN (= 2) and the third largest memory number MN (= 1) among the memory numbers MN indicating the memory M for changing the operation mode SPD with respect to the default value. Calculate the difference (“1”) with. Then, the test apparatus stores the calculated difference in the area of the difference FDIF in the second line FLINE1. The test device stores a value ("110" in binary; high speed 2) indicating the operation mode SPD of the memory M2 corresponding to the second largest memory number MN in the area of the speed code SPDC in the line FLINE1.

  The test apparatus sets the same value as the memory number MN as the difference with respect to the smallest memory number MN (= 1) among the memory numbers MN indicating the memory M for changing the operation mode SPD to “standard”. Store in the area of FDIF. The test device stores a value ("110" in binary; high speed 2) indicating the operation mode SPD of the memory M1 corresponding to the smallest memory number MN in the area of the speed code SPDC in the line FLINE2.

  FIG. 16 shows an example of the clock generation unit CLKGEN3 shown in FIG. The clock generation unit CLKGEN3 includes a counter COUNT, an enable generation circuit ENBGEN, and a clock counter CLKC. The clock counter CLKC has a flip flop circuit FF and an inverter IV.

  The counter COUNT maintains the counter value CV in the reset state (“0”) until it receives the activation level of the start signal PON at the reset terminal RESET. The counter COUNT cancels the reset state in response to the change of the power on signal PON to the activation level, and executes the counting operation in synchronization with the scan clock signal SCLK received at the clock terminal CK. "Increment by one.

  The enable generation circuit ENBGEN has a comparator CMP. The enable generation circuit ENBGEN sets the enable signal ENB to the activation level in response to the change to the activation level of the power on signal PON received at the reset terminal RESET, and starts the operation of the comparator CMP. The comparator CMP compares the counter value CV with the shift number NSFT, and outputs a coincidence signal CON when the counter value CV matches the shift number NSFT. Here, the shift number NSFT is the number of pulses of the scan clock signal SCLK (the shift number of the scan chain SCINC) generated to transfer all the speed levels SLVL programmed in the program unit 30C to the scan chain SCANC.

  When the mode bit MD of the last speed code SPDC from the program unit 30C is “1”, the enable generation circuit ENBGEN generates the enable signal ENB when the scan clock signal SCLK goes high based on the match signal CON. Deactivate. The enable generation circuit ENBGEN deactivates the enable signal ENB while the scan clock signal SCLK is at low level based on the match signal CON when the mode bit MD of the last speed code SPDC from the program unit 30C is "0". Set to level.

  The flip-flop circuit FF of the clock counter CLKC receives the start signal PON at the reset terminal RESET, receives the clock signal CLK at the clock terminal CK, and receives the enable signal ENB at the enable terminal ENB. The clock signal CLK may be a system clock signal supplied to the semiconductor device SEM 5 or may be another clock signal generated based on the system clock signal. The flip-flop circuit FF receives a signal obtained by inverting the logic of the scan clock signal SCLK at the data input terminal D through the inverter IV, and outputs the scan clock signal SCLK from the data output terminal Q.

  Then, flip-flop circuit FF generates scan clock signal SCLK from data output terminal Q in synchronization with clock signal CLK received at clock terminal CK when activation signal PON and enable signal ENB are at the activation level. Further, the flip-flop circuit FF fixes the scan clock signal SCLK to low level while the activation signal PON is at the inactivation level, and stops generation of the scan clock signal SCLK while the enable signal ENB is at the inactivation level.

  The clock generation unit CLKGEN3 sets the logic of the scan clock signal SCLK to the logic of the mode bit MD when the number of pulses of the scan clock signal SCLK matches the shift number NSFT after the activation signal PON changes to the activation level. . An example of the operation of the clock generation unit CLKGEN3 is shown in FIG.

  FIG. 17 shows an example of the operation of the clock generation unit CLKGEN3 shown in FIG. The example illustrated in FIG. 17 illustrates the operation of the clock generation unit CLKGEN3 in the case of sequentially transferring 2-bit information indicating the speed level SLVL to the shift registers SR1-SR6 corresponding to the memories M1-M6. The number of shifts NSFT calculated by the transfer control unit 20C is “12” in order to sequentially transfer information including the speed level SLVL programmed in the program unit 30C to the six shift registers SR1 to SR6. The operation when the mode bit MD is “1” (= high speed mode) shows the case where the information shown in FIG. 15 is programmed in the program section 30C.

  First, the enable generation circuit ENBGEN changes the enable signal ENB to the activation level in response to the change of the activation signal PON to the activation level (FIGS. 17A and 17B). The clock counter CLKC inverts the logic of the scan clock signal SCLK in synchronization with the rising edge of the clock signal CLK during the activation period of the enable signal ENB (FIGS. 17 (c), (d)). The counter COUNT counts the number of clocks of the scan clock signal SCLK and outputs a counter value CV (FIG. 17 (e)).

  If the counter value CV matches the shift number NSFT, the comparator CMP outputs a coincidence signal CON (FIG. 17 (f)). Then, when the mode bit MD is “1”, the enable generation circuit ENBGEN sets the enable signal ENB to the inactivation level after the scan clock signal SCLK changes to the high level “H” based on the output of the match signal CON. The change is made (FIG. 17 (g)). Thus, the scan clock signal SCLK is fixed to the high level "H" (FIG. 17 (h)).

  On the other hand, when the mode bit MD is “0”, the enable generation circuit ENBGEN changes the enable signal ENB to the inactivation level while the scan clock signal SCLK is low level “L” based on the output of the coincidence signal CON ( 17 (i), the scan clock signal SCLK is fixed at the low level "L" (FIG. 17 (j)).

  FIG. 18 shows an example of the shift register SR1 shown in FIG. The other shift register SR2-SR10 has the same circuit configuration as that of FIG. 18 except that the received data and the connected memory M are different.

  The shift register SR1 has two master-slave flip-flop circuits MSFF1 and MSFF2 connected in series. Master-slave flip-flop circuit MSFF1 has master latch circuit MLT1 and slave latch circuit SLT1, and master-slave flip-flop circuit MSFF2 has master latch circuit MLT2 and slave latch circuit SLT2. Master latch circuits MLT1 and MLT2 and slave latch circuits SLT1 and SLT2 are the same circuit, and each have a data input terminal D, a data output terminal Q, a reset terminal RST, and a clock terminal CK.

  The master latch circuits MLT1 and MLT2 and the slave latch circuits SLT1 and SLT2 are reset when the reset signal RST is at the activation level at the reset terminal RST, and output "0" from the data output terminal Q. When the reset signal RST is at the inactivation level, the master latch circuits MLT1 and MLT2 operate in synchronization with the scan clock signal SCLK. When the reset signal RST is at the inactive level, the slave latch circuits SLT1 and SLT2 operate in synchronization with a signal obtained by inverting the logic of the scan clock signal SCLK by the inverter IV.

  Each of the master latch circuits MLT1 and MLT2 latches the logic of the data DT received at the data input terminal D in synchronization with the rising edge of the scan clock signal SCLK, and outputs the latched logic from the data output terminal Q. Each slave latch circuit SLT1 and SLT2 latches the logic of data received at data input terminal D in synchronization with the falling edge of scan clock signal SCLK, and outputs the latched logic from data output terminal Q. The logic output from slave latch circuit SLT1 is supplied to memory M1 and master slave flip flop circuit MSFF2, and the logic output from slave latch circuit SLT2 is supplied to memory M1 and shift register SR2 of the next stage.

  FIG. 19 shows an example of the operation of the shift register SR1 shown in FIG. The other shift registers SR2-SR10 operate similarly to FIG. In the example shown in FIG. 19, master-slave flip-flop circuit MSFF1 sequentially latches data D1, D2, D3, D4, D5 in synchronization with scan clock signal SCLK, and sequentially outputs latched data D1-D5. . Master-slave flip-flop circuit MSFF2 sequentially latches data D1, D2, D3, and D4 in synchronization with scan clock signal SCLK, and sequentially outputs latched data D1-D4.

  The data output from each slave latch circuit SLT1 and SLT2 does not change between the low level period of one clock cycle of the scan clock signal SCLK and the high level period of the next clock cycle. For example, the slave latch circuit SLT1 outputs data D5 and the slave latch circuit SLT2 outputs data D4 in the low level period "L" of the fifth clock cycle and the high level period "H" of the sixth clock cycle. Therefore, as shown in FIG. 17, the logic held in shift register SR does not change even if the logic of scan clock signal SCLK is changed according to the logic of mode bit MD. As a result, even if the logic of the scan clock signal SCLK is changed according to the logic of the mode bit MD, it is possible to prevent the erroneous speed level SLVL from being set in the memory M. Furthermore, by using the logic of the scan clock signal SCLK after transferring the speed level SLVL to the scan chain SCINC, the logic of the mode bit MD can be set in the memory M without using the scan chain SCINC. As a result, the number of flip flop circuits FF (FIG. 3) included in each shift register SR1 to SR10 can be reduced compared to FIG. 11, and the circuit scale of the semiconductor device SEM5 can be reduced to the semiconductor device SEM4 shown in FIG. It can be made smaller than that.

  FIG. 20 shows an example of an operation flow for setting defect information in the scan chain SCANC shown in FIG. The process shown in FIG. 20 shows a control method of the semiconductor device SEM 5 and is executed by the transfer control unit 20C shown in FIG. Processes that are the same as or similar to those in FIG. 6 are assigned the same reference numerals as those in FIG. The transfer control unit 20C executes the process of step S106C instead of the process of step S106 shown in FIG. The process except step S106C is the same as that of FIG.

  In step S106C, the transfer control unit 20C reads out the difference FDIF and the speed code SPDC (mode bit MD and speed level SLVL) stored in the row FLINE of the program unit 30C indicated by the value of the counter FLINE.

  FIG. 21 shows an example (continuation of FIG. 20) of an operation flow for setting defect information in the scan chain SCINC shown in FIG. The process shown in FIG. 21 shows a control method of the semiconductor device SEM 5 and is executed by the transfer control unit 20C shown in FIG. Processes that are the same as or similar to those in FIG. 7 are assigned the same reference numerals as in FIG. The transfer control unit 20C executes the processes of steps S112C and S120C instead of the processes of steps S112 and S120 shown in FIG. Also, the transfer control unit 20C executes the process of step S125C between step S124 and step S126. The other processes are the same as in FIG.

  In step S112C, the transfer control unit 20C transfers the logic of the speed level SLVL to the scan chain SCINC while incrementing the counter ICB until the value of the counter ICB reaches the shift number NCB (= "1"). That is, the transfer control unit 20C performs an operation of sequentially transferring the logic of the speed level SLVL to the scan chain SCINC and an operation of incrementing the counter ICB by “1” until the value of the counter ICB becomes the code bit number NCB. repeat.

  In step S120C, the transfer control unit 20C transfers “0” to the scan chain SCINC while incrementing the counter ICB until the value of the counter ICB reaches the shift number NCB (= “1”). That is, the transfer control unit 20C repeats the operation of sequentially transferring "0" to the scan chain SCINC and the operation of incrementing the counter ICB by "1" until the value of the counter ICB reaches the code bit number NCB. Then, the processes of steps S114, S116, and S120C are repeated until the value of the counter IRAM becomes "0". Thereby, the shift register SR corresponding to the memory (such as the memory M3-M5 in FIG. 13) which does not change the operation mode SPD between the pair of memories (M2, M6 in FIG. 13) changing the operation mode SPD A value indicating “is set.

  In step S125C, as shown in FIG. 17, the transfer control unit 20C sets the scan clock signal SCLK to the high level “H” or the low level “L” based on the logic of the mode bit MD.

  FIG. 22 shows an example of an operation of setting defect information in the scan chain SCINC shown in FIG. FIG. 22 shows the operation of the transfer control unit 20C and the scan chain SCANC in the case of transferring the speed level SLVL stored in the program unit 30C shown in FIG. 15 to the scan chain SCANC. A detailed description of the same or similar operation as FIG. 8 is omitted. As in FIG. 8, the underlined numbers indicate that the values have changed, and the value of the speed level SLVL set in the shift registers SR1 to SR10 is indicated by a bold frame.

  The operation of the transfer control unit 20C is shown in the figure except that the speed level SLVL is transferred to the scan chain SCINC instead of the defect information, and that the logic of the scan clock signal SCLK is fixed to the logic of the mode bit MB after transfer. It is similar to the operation shown in FIG.

  The transfer control unit 20C determines the completion of transfer of the speed level SLVL to the scan chain SCINC based on the fact that the difference FDIF read from the program unit 30C indicates "0" (Fig. 22 (a)). Then, the transfer control unit 20C fixes the logic of the scan clock signal SCLK to the logic of the mode bit MD included in the valid speed code SPDC read last from the program unit 30C (FIG. 22 (b)). In the example shown in FIG. 22, since the logic of the effective mode bit MD read last is “1”, the scan clock signal SCLK is fixed to the high level “H”.

  As described above, also in the embodiments shown in FIGS. 14 to 22, similarly to the embodiments shown in FIGS. 1 to 13, the time for setting the speed level SLVL in the shift register SR without increasing the circuit size of the semiconductor device SEM5. Can be shortened.

  Furthermore, in the embodiment shown in FIGS. 14 to 22, the logic of the mode bit MD is supplied to the memory M using the logic of the scan clock signal SCLK without passing through the shift register SR. Therefore, the number of flip flop circuits of each shift register SR can be reduced, and the setting time of the speed code SPDC to the scan chain SCNC can be shortened as compared with the semiconductor device SEM4 shown in FIG. As a result, the start-up time of the semiconductor device SEM5 can be shortened compared to the semiconductor device SEM4 shown in FIG. 11 without increasing the circuit size of the semiconductor device SEM5.

  In the embodiment shown in FIG. 11 to FIG. 22, the operation timing of the control circuit in each memory M is adjusted based on the test result of each memory M. However, the control circuit in each memory M is described The operating voltage of V may be adjusted based on the test result of each memory M. That is, the operation timing of the control circuit may be adjusted based on the operating voltage. Alternatively, the internal power supply voltage supplied to the control circuit in each memory M may be adjusted based on the test result (margin of the internal power supply voltage) of each memory M.

  When the operating voltage or the internal power supply voltage of the control circuit is adjusted, shift registers SR1-SR10 are connected to the transfer control unit in the order corresponding to memory M having a small voltage margin. The shift registers SR1 to SR10 hold selection information for selecting any of the plurality of voltages generated in each memory M. For example, in the memories M1 to M10 illustrated in FIG. 11, the memory M having a smaller number has a smaller (more severe) voltage margin than the memory M having a large number.

  Furthermore, in the embodiments shown in FIG. 2 to FIG. 22, the example in which the defect of the memory M1-M10 is relieved or the example in which the operation timing of the control circuit in the memory M1-M10 is adjusted have been described. However, the embodiments shown in FIG. 2 to FIG. 22 may be used to relieve a defect in a circuit block such as a peripheral circuit other than the memory M mounted on the semiconductor device, or the operation timing of the circuit block (or It may be used to adjust the operating voltage).

  FIG. 23 shows an example of the adjustment circuit ADJ2 mounted on each circuit block in the semiconductor device and adjusting the voltage used in the circuit block. Adjustment circuit ADJ2 includes a plurality of voltage generation circuits VGEN (VGEN1, VGEN2, VGEN3, VGEN4, VGEN5) for generating internal voltages VI (VI1, VI2, VI3, VI4, VI5) for operating the control circuit, and a selection unit SEL Have. The internal voltages VI1, VI2, VI3, VI4, and VI5 gradually increase in the order of VI1, VI2, VI3, VI4, and VI5 (VI1 <VI2 <VI3 <VI4 <VI5). For example, the internal voltage VI3 is a standard value (default value). For example, the circuit block is a memory M1-M10 shown in FIG. 11 or the like, and a circuit including voltage generation circuits VGEN1-VGEN5 is an example of an internal circuit included in each of the memories M1-M10. Internal voltage VI is used for the voltage at the activation level of word line WL shown in FIG. 4, or internal voltage VI is used for the substrate voltage of memory cell array ARY shown in FIG.

  The selection unit SEL selects one of the internal voltages VI1 to VI5 based on the voltage code VC indicating the operation specification of the control circuit, and sets the substrate voltage to the substrate of the word line drive circuit or the memory cell array ARY as the selected internal voltage VI. Output to a control circuit such as a supply circuit. That is, the selection unit SEL selects one of the voltage generation circuits VGEN1 to VGEN5 outputting the internal voltages VI1 to VI5 based on the voltage code VC. In the program unit 30B and the like shown in FIG. 11, a voltage code VC for setting the internal voltage VI in the memory M to be changed from the standard internal voltage VI3 and a difference FDIF are programmed. The shift registers SR <b> 1 to SR <b> 10 are connected to the transfer control unit 20 in the order corresponding to the memories M <b> 1 to M <b> 10 having a small voltage margin.

  The features and advantages of the embodiments will be apparent from the foregoing detailed description. This is intended to cover the features and advantages of the embodiments as described above without departing from the spirit and scope of the claims. Also, all modifications and variations should be readily apparent to those skilled in the art. Accordingly, there is no intention to limit the scope of the embodiments having the invention to those described above, and it is also possible to rely on appropriate modifications and equivalents included in the scope disclosed in the embodiments.

  10 Operation control unit 12 Power supply control unit 20, 20A, 20C Transfer control unit 30, 30A, 30B, 30C Program unit ACNT Adjustment control signal ADEC Address decoder ADJ1, ADJ2 Adjustment circuit ; ARY: memory cell array; CBLK (CBLK1 to CBLK4): circuit block: CD: defective code: CLKC: clock counter: CLKGEN1, CLKGEN2, CLKGEN3: clock generation unit: CMP: comparator: CNT: control signal: CNTL: control unit ; COUNT ... counter; DLY (DLY1-DLY7) ... delay circuit; DT ... data; ENB ... enable signal; ENB GEN ... enable generation circuit; FDIF ... difference; FF ... flip flop circuit; FLINE, FLINE 1, FLINE 2 ... counter; (HLD1-HLD4) ··· Holding section: IC (IC1, IC2) ··· Internal circuit: ICB, ICB1, ICB2 ··· Counter, IO (IO0-IO63) · · · Data input / output terminal; ; IVDD: power supply voltage; M (M1 to M10): memory; MC (MC0 to MC63): memory cell unit; MD: mode bit; MEM: storage unit; MLT1, MLT2: master latch circuit; MSFF1, MSFF2: master slave flip flop NCB: code bit number; NSFT: shift number; OPE: operation enable signal; PGM: program signal; PON: start signal; REN: redundant enable bit; RMC: redundant memory cell portion; RST: reset signal; RSTGEN2 ... reset Generation unit: RSW: redundant switching switch; SCINC, SCINC1, SCINC2: scan chain; SCLK: scan clock signal; SEL (SEL1, SEL2, SEL3, SEL4): selection unit: SEM1, SEM2, SEM3, SEM4, SEM5: semiconductor device ; SI1, SI2 ... selection information; SINIT ... selection information; SLT1, SLT2 ... slave latch circuit; SLVL ... speed level; SPD ... operation mode; SPDC ... speed code; SR (SR1-SR10) ... shift register; VC ... voltage code VI1, VI2, VI3, VI4, VI5: Internal voltage; VGEN (VGEN1 to VGEN5): Voltage generation circuit; WL (WL0 to WL4): Word line

Claims (10)

A plurality of circuit blocks each including a plurality of internal circuits and a selection unit which selects an internal circuit to be used among the plurality of internal circuits based on selection information;
A storage unit that stores selection information supplied to the selection unit of the circuit modification block, which is a circuit block that changes a selection state of the plurality of internal circuits from an initial state among the plurality of circuit blocks;
The selection information is provided corresponding to each of the plurality of circuit blocks, connected in the order corresponding to the circuit block having a high probability of changing the selection state from the initial state, and the selection information to be supplied to the selection unit of the plurality of circuit blocks A plurality of holding parts to hold,
The holding unit corresponding to the change circuit block among the plurality of holding units includes: a control unit that sequentially transfers selection information stored in the storage unit ;
The storage unit is
A plurality of first storage areas each storing selection information supplied to the selection unit of the change circuit block;
And a plurality of second storage areas each storing interval information indicating an interval between two holding units corresponding to two of the plurality of holding units and corresponding to the changed circuit block.
Have
The control unit, while sequentially transferring selection information stored in the two first storage areas to the plurality of holding units based on the interval information, selects the selection information corresponding to the initial state. A semiconductor device characterized by transferring data to a plurality of holding units. A plurality of circuit blocks each including a plurality of internal circuits and a selection unit which selects an internal circuit to be used among the plurality of internal circuits based on selection information;
A storage unit that stores selection information supplied to the selection unit of the circuit modification block, which is a circuit block that changes a selection state of the plurality of internal circuits from an initial state among the plurality of circuit blocks;
The selection information is provided corresponding to each of the plurality of circuit blocks, connected in the order corresponding to the circuit block having a high probability of changing the selection state from the initial state, and the selection information to be supplied to the selection unit of the plurality of circuit blocks A plurality of holding parts to hold,
And a control unit sequentially transferring selection information stored in the storage unit to a holding unit corresponding to the change circuit block among the plurality of holding units.
Equipped with
The plurality of holding units are respectively connected in series corresponding to a first circuit block group and a second circuit block group among the plurality of circuit blocks,
A holding unit corresponding to each circuit block of the first circuit block group among the plurality of holding units is connected to the control unit in an order corresponding to a circuit block having a high probability of changing the selected state from the initial state ,
A holding unit corresponding to each circuit block of the second circuit block group among the plurality of holding units is connected to the control unit in an order corresponding to a circuit block having a high probability of changing the selected state from the initial state ,
The probability of changing the selection state in each circuit block of the first circuit block group from the initial state is higher than the probability of changing the selection state in each circuit block of the second circuit block group from the initial state
Semiconductor device characterized by A plurality of circuit blocks each including a plurality of internal circuits and a selection unit which selects an internal circuit to be used among the plurality of internal circuits based on selection information;
A storage unit that stores selection information supplied to the selection unit of the circuit modification block, which is a circuit block that changes a selection state of the plurality of internal circuits from an initial state among the plurality of circuit blocks;
The selection information is provided corresponding to each of the plurality of circuit blocks, connected in the order corresponding to the circuit block having a high probability of changing the selection state from the initial state, and the selection information to be supplied to the selection unit of the plurality of circuit blocks A plurality of holding parts to hold,
And a control unit sequentially transferring selection information stored in the storage unit to a holding unit corresponding to the change circuit block among the plurality of holding units.
Equipped with
The selection information stored in the storage unit is a first selection information individually supplied to the selection unit of the change circuit block, and a second selection information commonly supplied to the selection unit of the plurality of circuit blocks. Including selection information,
The control unit generates a clock signal for operating the plurality of holding units, and transmits the first selection information to the holding unit corresponding to the change circuit block, based on the second selection information. A clock generation unit for fixing the clock signal to either high level or low level;
A clock signal line for transmitting the clock signal is connected to the plurality of circuit blocks,
The selection unit receives, as the second selection information, the level of the clock signal fixed after transfer of the first selection information to the holding unit corresponding to the change circuit block.
Semiconductor device characterized by Each of the plurality of holders has a plurality of master-slave flip-flop circuits connected in series.
The semiconductor device according to claim 3, characterized in that The control unit has a reset generation unit that generates a reset signal before transferring selection information to a holding unit corresponding to the change circuit block.
The plurality of holding units are reset to a state of holding selection information corresponding to the initial state based on the reset signal.
The semiconductor device according to any one of claims 1 to 4, characterized in that The power supply control unit controls a power supply voltage supplied to a circuit area including the plurality of circuit blocks and the plurality of holding units, and generates a start signal based on the supply of the power supply voltage to the circuit area.
The control unit may start transfer of selection information stored in the storage unit after generating the reset signal based on the start signal.
The semiconductor device according to claim 5, characterized in that The plurality of internal circuits included in each of the plurality of circuit blocks are either a memory cell unit including a plurality of memory cells or a redundant memory cell unit including a redundant memory cell for repairing a defective memory cell unit. Including
The selection unit included in each of the plurality of circuit blocks selects the redundant memory cell unit instead of the memory cell unit having a defect based on selection information.
The plurality of holding units are connected to the control unit in the order corresponding to the circuit block having a large area.
The semiconductor device according to claim 1, characterized in that Each of the plurality of internal circuits included in each of the plurality of circuit blocks includes a plurality of delay circuits having different propagation delay times.
The selection unit included in each of the plurality of circuit blocks selects one of the signals generated by the plurality of delay circuits based on selection information;
The plurality of holding units are connected to the control unit in an order corresponding to a circuit block having a small timing margin.
The semiconductor device according to claim 1, characterized in that Each of the plurality of internal circuits included in each of the plurality of circuit blocks includes a plurality of voltage generation circuits generating different voltages, respectively.
The selection unit included in each of the plurality of circuit blocks selects one of the voltages generated by the plurality of voltage generation circuits based on selection information;
The plurality of holding units are connected to the control unit in an order corresponding to a circuit block having a small voltage margin.
The semiconductor device according to claim 1, characterized in that A plurality of circuit blocks respectively including a plurality of internal circuits and a selection unit for selecting an internal circuit to be used among the plurality of internal circuits based on selection information, and provided corresponding to the plurality of circuit blocks, A plurality of holding units connected in the order corresponding to the circuit block having a high probability of changing the selection state of the plurality of internal circuits from the initial state, and holding selection information to be supplied to the selection unit of the plurality of circuit blocks ; Among the plurality of circuit blocks, a plurality of first storage areas respectively storing selection information supplied to the selection unit of the change circuit block that is a circuit block that changes the selection state of the plurality of internal circuits from the initial state And a plurality of interval information indicating intervals between two holding units corresponding to the two changed circuit blocks among the plurality of holding units. A control method of a semiconductor device having a storage unit and a second storage area,
Reading out, from the storage unit, selection information supplied to the selection unit of the change circuit block that is a circuit block that changes the selection state of the plurality of internal circuits from the initial state among the plurality of circuit blocks;
The read selection information is sequentially transferred to a holding unit corresponding to the change circuit block among the plurality of holding units ,
The selection information corresponding to the initial state is transmitted to the plurality of holding units while the selection information stored in the two first storage areas is sequentially transferred to the plurality of holding units based on the interval information. A control method of a semiconductor device characterized by transferring .

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