JP6540607B2 - Method of manufacturing bonded wafer and bonded wafer - Google Patents

Description

  The present invention relates to a method of manufacturing a bonded wafer and a bonded wafer.

  In a semiconductor wafer manufacturing process or a device formation process, if heavy metals are mixed into a semiconductor wafer which is a substrate of the device, the device characteristics such as a pause time failure, retention failure, junction leak failure, and oxide film dielectric breakdown are significantly adversely affected. Therefore, in order to suppress the diffusion of heavy metals into the device formation region, which is a region for forming devices, on the surface of a silicon wafer which is a typical substrate, gettering capability has been conventionally provided by the gettering method.

  As the gettering method, an intrinsic gettering method (IG method) in which oxygen is precipitated inside a silicon wafer and the formed oxygen precipitates are used as gettering sites, and on the back surface of the silicon wafer, There is an extrinsic gettering method (EG method) in which mechanical strain is applied using a sand blast method or the like, or a polycrystalline silicon film or the like is formed to form a gettering site.

  However, in recent years, due to the reduction in temperature of the device formation process and the increase in diameter of the silicon wafer, there is a problem that the gettering ability can not be sufficiently provided to the silicon wafer. That is, in the IG method, it is difficult to form an oxygen precipitate inside the silicon wafer due to the lowering of the manufacturing process temperature.

  In addition, with regard to the EG method, it is customary to mirror-finish not only the main surface but also the back surface of a silicon wafer having a diameter of 300 mm or more, and mechanical distortion is caused on the back surface of the silicon wafer. In the situation where it is impossible to form a polycrystalline silicon film or the like.

  If the silicon wafer can not be provided with sufficient gettering ability, if the metal with a very low diffusion rate such as titanium (Ti), molybdenum (Mo), or tungsten (W) adheres to the wafer surface, the temperature of the device formation process is lowered. In the case of a solid-state imaging device, for example, a white defect may occur. Therefore, it is necessary to form a gettering layer immediately below the device formation region so as to capture such slow diffusion metal.

  For example, as an extrinsic gettering method, Patent Document 1 discloses a straining method of a single crystal silicon wafer in which a strained layer is formed on the back surface by polishing the back surface of the single crystal silicon wafer with abrasive grains and a polishing cloth. It is done.

  Further, in Patent Document 2 proposed by the present applicant, the cluster ions are introduced into the semiconductor wafer in a state where the accelerating voltage per atom is reduced by irradiating the surface of the semiconductor wafer with cluster ions. A semiconductor epitaxial wafer is disclosed in which a modified layer is formed and an epitaxial layer is formed on the surface of the modified layer. According to the technique described in Patent Document 2, a gettering layer having strong gettering ability can be formed in the vicinity immediately below an epitaxial layer which is to be a device formation region.

Japanese Patent Application Publication No. 07-321119 International Publication No. 2012/157162

  However, in the straining method as described in Patent Document 1, the position of the strained layer is limited to the back surface of the silicon wafer. If a gettering layer is formed at a position relatively far from the device formation region, the low temperature of recent device formation processes can not allow heavy metals with slow diffusion rates to leave the device formation region and can not capture heavy metals in the gettering layer I have a concern.

  In addition, although a gettering layer having a strong gettering ability can be formed by the method disclosed in Patent Document 2, the formation of an epitaxial layer is a premise, so a bulk silicon wafer without an epitaxial layer can be formed. Not applicable

  The inventor examined as a new subject the introduction of a gettering site at the interface of a bonded wafer obtained by bonding a wafer for active layer and a wafer for support substrate using the vacuum room-temperature bonding technology which has been attracting attention in recent years. . By grinding and polishing the active layer wafer of this bonded wafer, gettering sites can be formed at any depth from the device active layer region.

  Therefore, in the bonding wafer using the vacuum room-temperature bonding technique, the inventor once recalls that the strained layer as disclosed in Patent Document 1 is the bonding interface, and the bonding interface is the gettering site. It was investigated. However, such strained layers can not be joined.

  Then, this invention aims at the manufacturing method of a joining wafer which can form a gettering site in arbitrary depth positions, and provision of a joining wafer.

  The present inventors diligently studied how to solve the above-mentioned problems. Then, the inventors of the present invention perform bonding so that misfit dislocations are formed at the interface between the wafer for active layer and the wafer for support substrate in the bonding step, instead of forming gettering sites in advance. They recalled and found that the interface was an effective gettering site, and completed the present invention.

That is, the gist configuration of the present invention is as follows.
(1) A method for producing a bonded wafer in which a bonding surface of an active layer wafer made of silicon and a bonding surface of a support substrate wafer made of silicon are directly bonded, which is characterized by the above-mentioned activity under vacuum normal temperature. An activation treatment step of activating the bonding surface of the layer wafer and the bonding surface of the support substrate wafer, and subsequently to the activation treatment step, bonding the active layer wafer under vacuum normal temperature And a bonding step of bonding the wafer for active layer and the wafer for support substrate by bringing the bonding surface and the bonding surface of the wafer for support substrate into contact with each other, and in the bonding step, the activation step A method of manufacturing a bonded wafer, wherein the bonding is performed such that misfit dislocations are formed at the interface between the layer wafer and the support substrate wafer.

  Hereinafter, in the present specification, the laminating method according to the activation treatment step and the subsequent laminating step is referred to as “vacuum room temperature bonding method”.

(2) The wafer for active layer and the wafer for support substrate each have a notch indicating the crystal axis direction, and in the bonding step, the notch of the wafer for active layer is the support substrate The method for producing a bonded wafer according to (1), wherein the bonding is performed in a state where the bonding wafer is rotated in the circumferential direction from the cutout portion.

(3) The method for producing a bonded wafer according to (2), wherein the notch is a notch or an orientation flat.

(4) The method for producing a bonded wafer according to (1), wherein the surface orientations of the bonding surface of the active layer wafer and the bonding surface of the support substrate wafer are different from each other.

(5) The active layer wafer includes a silicon wafer and an epitaxial silicon layer provided on the surface of the silicon wafer, and the bonding surface of the active layer wafer is the surface of the epitaxial silicon layer. The manufacturing method of the joining wafer in any one of said (1)-(4).

(6) The bonded wafer according to (5), further including the step of grinding and polishing the active layer wafer from the opposite side of the epitaxial silicon layer of the active layer wafer to expose the epitaxial silicon layer. Manufacturing method.

(7) The method for producing a bonded wafer according to (6), wherein the grinding and polishing include grinding and polishing of the epitaxial silicon layer.

(8) The method for producing a bonded wafer according to any one of (1) to (7), wherein the activation treatment is a treatment in which an ionized neutral element is caused to collide with the bonding surface to perform sputtering. .

(9) The method for producing a bonded wafer according to (8), wherein the neutral element is at least one selected from the group consisting of argon, neon, xenon, hydrogen, helium and silicon.

(10) The method for producing a bonded wafer according to any one of (1) to (7), wherein the activation process is a plasma etching process.

(11) The method for producing a bonded wafer according to any one of (1) to (10), wherein the activation treatment is performed such that the thickness of the amorphous layer formed on the both bonding surfaces is 2 nm or more.

(12) The method for producing a bonded wafer according to any one of (1) to (10), wherein the activation treatment is performed such that the thickness of the amorphous layer formed on the bonding surfaces is 10 nm or more.

(13) A wafer for supporting substrate made of silicon, and a wafer for active layer made of silicon provided on the surface of the wafer for supporting substrate, and the wafer for active layer and the wafer for supporting substrate A bonded wafer characterized by the presence of misfit dislocations at an interface.

(14) The wafer for active layer and the wafer for support substrate each have a notch indicating the crystal axis direction, and the notch of the wafer for active layer is the notch of the wafer for support substrate The bonded wafer according to (13), wherein the bonded wafer is rotated in the circumferential direction from the part.

(15) The bonded wafer according to (14), wherein the notch is a notch or an orientation flat.

(16) The surface orientation of the surface of the support substrate wafer on the side of the active layer wafer and the surface orientation of the surface of the support substrate wafer of the active layer wafer are different from each other in (13). Bonding wafer.

(17) The bonded wafer according to any one of (13) to (16), wherein the active layer wafer comprises an epitaxial silicon layer.

  According to the present invention, it is possible to provide a method of manufacturing a bonded wafer and a bonded wafer capable of forming gettering sites at any depth position.

It is a flowchart explaining the manufacturing method of bonded wafer 100 concerning a 1st embodiment of the present invention. In one Embodiment of this invention, it is a schematic cross section of the apparatus used when performing vacuum normal temperature bonding. (A) is a schematic diagram explaining the notch of the wafer in the preferred embodiment of the present invention, and (A) is a schematic diagram explaining the orientation flat of the wafer in the preferred embodiment of the present invention. It is a flowchart explaining the manufacturing method of bonded wafer 200 concerning a 2nd embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS It is a graph which shows the oxygen concentration profile in evaluation 1 of an Example, (A) is an oxygen concentration profile of (A) of invention example 1, (B) of conventional example 1, and (C) of comparative example 1. It is a graph which shows the oxygen concentration profile in evaluation 2 of an Example, (A) is an oxygen concentration profile of comparative example 1 of (B) of conventional example 1, (C) of comparative example 1. It is an optical microscope photograph of the epitaxial layer surface in evaluation 3 of an example, (A) is an invention example 1, (B) is an invention example 2, (C) is a conventional example 1, (D) is a comparative example 1. Is a photomicrograph of It is a cross-sectional TEM photograph of the joining area | region of the epitaxial wafer produced using the vacuum room-temperature bonding method in a reference experiment example, (A) is a reference example 1, (B) is a reference example 2, (C) is a reference. 7 is a cross-sectional TEM image of Example 3.

First Embodiment
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a flowchart of a method of manufacturing a bonded wafer 100 according to a first embodiment of the present invention. In the method of manufacturing a bonded wafer 100 according to the present embodiment, a bonded wafer 100 in which a bonding surface 10A of an active layer wafer 10 made of silicon and a bonding surface 20A of a support substrate wafer 20 made of silicon are directly bonded. It is a manufacturing method. In the present embodiment, first, an activation processing step of performing activation processing of the bonding surface 10A of the active layer wafer 10 and the bonding surface 20A of the support substrate wafer 20 under vacuum normal temperature is performed (FIG. ), (B)). Subsequently to the activation treatment step, the bonding surface 10A of the active layer wafer 10 and the bonding surface 20A of the support substrate wafer 20 are brought into contact with each other under vacuum normal temperature, thereby the active layer wafer 10 and the support are supported. A bonding step of bonding the substrate wafer 20 is performed (FIG. 1 (C)).

  First, the bonding method by the vacuum room temperature bonding method will be specifically described below. As shown to FIG. 1 (A)-(C), in this embodiment, the wafer 10 for active layers and the wafer 20 for support substrates are bonded in the environment of vacuum and normal temperature. As pretreatment therefor, the bonding surface is activated on each of the bonding surface 10A of the wafer 10 for the active layer and the bonding surface 20A of the wafer 20 for the support substrate in a vacuum and normal temperature environment. An activation process is performed (FIG. 1 (A)).

  By the above activation treatment, as shown in FIG. 1B, the amorphous layers 12 and 22 are formed on the bonding surfaces 10A and 20A, respectively, and the elements constituting the amorphous layers 12 and 22 are formed on the surfaces thereof (ie, Dangling bonds of silicon) are formed. Since this dangling bond is energetically unstable, when the two bonding surfaces are brought into contact in the subsequent treatment, the bonding force acts between the wafers so as to eliminate the dangling bond on both surfaces, and the treatment such as heat treatment is performed. Without being applied, the wafer for active layer 10 and the wafer for support substrate 20 can be strongly bonded together without non-bonding areas (voids).

  In the activation treatment of the bonding surface, the ionized neutral element accelerated by the ion beam device is caused to collide with the bonding surface to sputter the surface, or the ionized neutral element is accelerated in the plasma atmosphere to the wafer surface. The etching can be performed by performing plasma etching processing.

  FIG. 2 shows an example of a vacuum room-temperature bonding apparatus in which two wafers are bonded after the bonding surface is activated by plasma etching. The apparatus 50 includes a plasma chamber 51, a gas inlet 52, a vacuum pump 53, a pulse voltage application device 54, and wafer fixing bases 55A and 55B.

  First, the wafer 10 for the active layer and the wafer 20 for the support substrate are mounted and fixed on the wafer fixing tables 55A and 55B in the plasma chamber 51, respectively. Next, after the inside of the plasma chamber 51 is depressurized by the vacuum pump 53, the source gas is introduced into the plasma chamber 51 from the gas inlet 52. Subsequently, a negative voltage is applied in a pulsed manner to the wafer fixing bases 55A and 55B (the active layer wafer 10 and the support substrate wafer 20) by the pulse voltage application device 54. As a result, the plasma of the source gas is generated, and ions of the source gas contained in the generated plasma are accelerated and irradiated toward the bonding surfaces of the active layer wafer 10 and the supporting substrate wafer 20, respectively. An amorphous layer can be formed on the surface, and dangling bonds of elements constituting the amorphous layer can be formed on the irradiated surface.

  The neutral element to be irradiated is preferably at least one selected from the group consisting of argon (Ar), neon (Ne), xenon (Xe), hydrogen (H), helium (He) and silicon (Si). .

The pressure (degree of vacuum) in the plasma chamber 51 is preferably 1 × 10 ⁻⁵ Pa or less. Thus, the re-adhesion of the element sputtered to the wafer surface can be suppressed, and the activation process can be performed without reducing the formation rate of the dangling bond.

  The pulse voltage applied to the active layer wafer 10 and the support substrate wafer 20 is set so that the acceleration energy of the irradiation element to the wafer surface is 100 eV or more and 10 keV or less. When the acceleration energy is less than 100 eV, the irradiated neutral element is deposited on the wafer surface, and no dangling bond can be formed on the wafer surface. On the other hand, when the acceleration energy exceeds 10 keV, the irradiated element is implanted into the inside of the wafer, and also in this case, no dangling bond can be formed on the wafer surface.

  The frequency of the pulse voltage determines the number of times the ions are irradiated to the active layer wafer 10 and the support substrate wafer 20. The frequency of the pulse voltage is preferably 10 Hz to 10 kHz. Here, by setting the frequency to 10 Hz or more, variations in ion irradiation can be absorbed, and the ion irradiation amount is stabilized. Further, by setting the frequency to 10 kHz or less, plasma formation by glow discharge is stabilized.

  The pulse width of the pulse voltage determines the time during which ions are irradiated to the active layer wafer 10 and the support substrate wafer 20. The pulse width is preferably in the range of 1 μs to 10 ms. Ions can be stably emitted to the active layer wafer 10 and the supporting substrate wafer 20 by setting the time to 1 μsec or more. Further, by setting the time to 10 msec or less, plasma formation by glow discharge is stabilized.

  In the above process, since the wafer 10 for the active layer and the wafer 20 for the support substrate are not heated, the temperature is normal temperature (usually 30 ° C. to 90 ° C.).

  No misfit dislocation is usually formed at the interface between the active layer wafer 10 made of silicon and the bonded substrate wafer 20 made of silicon bonded by vacuum room temperature bonding. This is generally to bond the same kind of silicon wafers having the same plane orientation so that the notches indicating the crystal axis direction are aligned. However, in the present embodiment, in the bonding step, bonding is performed so that misfit dislocations are formed at the interface between the active layer wafer 10 and the support substrate wafer 20.

  In order to form such misfit dislocations at the interface, for example, the wafer for active layer 10 and the wafer for support substrate 20 each have a notch indicating the crystal axis direction, and in the bonding step, the active layer The bonding is preferably performed in a state where the notch of the wafer 10 is rotated in the circumferential direction from the notch of the supporting substrate wafer 20. The rotation angle is not particularly limited, but if it is rotated by 2 ° or more, misfit dislocations can be sufficiently formed, and it is preferable to rotate by 5 ° or more. The upper limit of the rotation angle is not particularly limited, but may be 358 °. Such a shift of the rotation angle may be adjusted before the activation process, but in consideration of the stability of the activation process, it is preferable to adjust the rotation angle just before bonding after the activation process.

  The notches described above can be notches or orientation flats (sometimes referred to as "ori-flats") that are commonly provided on silicon wafers. 3A schematically shows the notch 16 of the active layer wafer 10, and FIG. 3B schematically shows the orientation flat 18 of the active layer wafer 10. As shown in FIG. Notches may be formed on both the active layer wafer 10 and the support substrate wafer 20, or orientation flats may be formed on both the active layer wafer 10 and the support substrate wafer 20. Further, a notch may be formed on the active layer wafer 10, and an orientation flat may be formed on the support substrate wafer 20, or vice versa.

  A shift in crystal orientation is caused by shifting and joining the notches of the active layer wafer 10 and the notches of the support substrate wafer 20 in the circumferential direction, so that the active layer wafer 10 and the support substrate Misfit dislocations will be formed at the interface with the wafer 20.

  In addition, if the plane orientations of the bonding surface 10A of the active layer wafer 10 and the bonding surface 20A of the support substrate wafer 20 are different from each other, misfit dislocations can be formed at the interface. For example, when the surface orientation of the bonding surface 10A is (111) and the surface orientation of the bonding surface 20A is (100), misfit dislocations can be formed at the interface. Of course, the reverse combination may be used, and the combination of plane orientations is not limited to the above example and may be a (110) plane. When the plane orientations are different from each other, the notch of the active layer wafer 10 and the notch of the support substrate wafer 20 may be aligned and bonded.

  The inventor of the present invention functions as an effective gettering site for the formed misfit dislocation in any of the bonded wafer in which the above-mentioned notched portions are shifted and bonded, and in the bonded wafer in which wafers of different surface orientations are bonded. That was confirmed experimentally. Here, even when the wafer for active layer 10 and the wafer for support substrate 20 are bonded by a method other than the vacuum room temperature bonding method, as described above, the notch portion is shifted and bonded or different. Misfit dislocations can be formed in the vicinity of the interface by bonding wafers of plane orientation. However, when bonding is performed using a method other than vacuum room temperature bonding, a natural oxide film of about several nm is inevitably generated on the silicon surface, and such natural oxide films do not transmit heavy metals and misfit dislocations Can not function as an effective gettering site. On the other hand, in the case of the present embodiment, since the bonding is performed by the vacuum room temperature bonding method, the inventor thinks that the formed misfit dislocation effectively functions as a gettering site.

Second Embodiment
The present invention is also applicable to epitaxial silicon wafers. As shown in FIG. 4A, the active layer wafer 10 includes a silicon wafer 10B and an epitaxial silicon layer 10E provided on the surface of the silicon wafer 10B, and the bonding surface of the active layer wafer 10 Preferably, 10A is the surface of the epitaxial silicon layer 10E. The epitaxial silicon layer 10E can be formed by epitaxially growing a silicon wafer 10B as a support substrate. For example, a source gas such as dichlorosilane (H ₂ Cl ₂ Si) or trichlorosilane (HCl ₃ Si) is introduced into the chamber using hydrogen (H) as a carrier gas, and the growth temperature also varies depending on the source gas used. The epitaxial silicon layer 10E can be epitaxially grown on the silicon wafer 10B by a chemical vapor deposition (CVD) method at a temperature in a temperature range of approximately 1000 to 1200 ° C. The thickness of the epitaxial silicon layer 10E is not particularly limited, and may be appropriately set based on the specification of the device formation region.

  Then, after the manufacturing method according to the first embodiment bonds the wafer for active layer 10 and the wafer for support substrate 20 by vacuum room-temperature bonding (FIG. 4 (B)), epitaxial silicon for the wafer for active layer 10 is obtained. Bonded wafer 200 can be obtained by further including the step of grinding and polishing active layer wafer 10 from the opposite side 10R of layer 10E to expose epitaxial silicon layer 10E (FIG. 4C). The bonding wafer 200 can be used as an epitaxial silicon wafer because the epitaxial silicon layer 10E is exposed. Therefore, it can be called a "junction epitaxial wafer" unlike what forms an epitaxial layer directly on the conventional wafer for support substrates.

  In the bonded wafer 200 obtained according to the second embodiment, as in the bonded wafer 100 of the first embodiment, misfit dislocations are formed at the interface between the active layer wafer 10 and the support substrate wafer 20. The bonding surface 10A side of the epitaxial silicon layer 10E serves as a gettering site, which enables proximity gettering. As described above, according to the second embodiment, an epitaxial silicon wafer having gettering capability can be manufactured at low cost.

  Here, in the second embodiment, the grinding and polishing in the step of FIG. 4C preferably include grinding and polishing of the epitaxial silicon layer 10E (FIG. 4D). Here, in the portion on the silicon wafer 10B side of the epitaxial silicon layer 10E, an impurity may be diffused from the silicon wafer 10B at the time of epitaxial growth. However, by partially grinding and polishing the epitaxial silicon layer 10E as shown in FIG. 4D, the above-described influence of diffusion can be suppressed.

  Hereafter, the suitable aspect according to the manufacturing method of this invention is demonstrated. The active layer wafer 10 is used as a device formation region, and a single crystal silicon wafer made of silicon single crystal can be used. The active layer wafer 10 can also be an epitaxial silicon wafer having a silicon wafer 10B made of silicon single crystal and an epitaxial silicon layer 10E provided on the surface of the silicon wafer 10B.

  As a single crystal silicon wafer, a single crystal silicon ingot grown by a known method such as Czochralski (Czochralski, CZ) method or floating zone (FZ) method is sliced by a wire saw or the like. can do. Further, any impurity can be added to make it n-type or p-type, and the concentration of the impurity can be adjusted to adjust the resistivity, the oxygen concentration, and the like.

  The supporting substrate wafer 20 is a wafer for supporting the active layer wafer 10. As the supporting substrate wafer 20, it is desirable to use a single crystal silicon wafer made of silicon single crystal, as in the case of the active layer wafer 10. Further, any impurity can be added to make it n-type or p-type, and the concentration of the impurity can be adjusted to adjust the resistivity, the oxygen concentration, and the like.

  In the first embodiment, either or both of the active layer wafer 10 and the support substrate wafer 20 may be ground and polished from the surface opposite to the bonding surfaces 10A and 10B. Similarly, in the second embodiment, in addition to grinding and polishing of the active layer wafer 10, grinding and polishing of the supporting substrate wafer may be performed.

  Moreover, it is preferable to perform an activation process so that the thickness of the amorphous layers 12 and 22 may be 2 nm or more. Such amorphous layers 12 and 22 can function as a block layer that suppresses the thermal diffusion of impurities in the active layer wafer 10 and the support substrate wafer 20. The thickness of the amorphous layer can be adjusted by adjusting the acceleration voltage of ions.

  Furthermore, the activation treatment is preferably performed so that the thickness of the amorphous layers 12 and 22 is 10 nm or more. Thus, the amorphous layers 12 and 22 can function as a block layer that suppresses the thermal diffusion of interstitial oxygen in the active layer wafer 10 and the support substrate wafer 20.

  The dopant concentrations of the active layer wafer 10 and the support substrate wafer 20 can be appropriately set based on the specifications. When the active layer wafer 10 has the epitaxial silicon layer 10E, the dopant concentrations of the silicon wafer 10B and the epitaxial silicon layer 10E as the support substrate can be appropriately set based on the specifications.

(Bonded wafer)
Next, bonded wafers 100 and 200 according to the present invention will be described. The bonding wafer 100 includes a supporting substrate wafer 20 made of silicon, and an active layer wafer 10 made of silicon provided on the surface of the supporting substrate wafer 20, and the active layer wafer 10 and the supporting substrate Misfit dislocations are present at the interface with the wafer 20. Misfit dislocations present at the interface can function as effective gettering sites.

  The active layer wafer 10 and the support substrate wafer 20 each have a cutaway portion indicating the crystal axis direction, and the cutaway portion of the active layer wafer 10 extends circumferentially from the cutaway portion of the support substrate wafer 20. Preferably it is in a rotated position. And these notches can be notches or orientation flats.

  It is also preferable that the plane orientation of the surface 20A on the active layer wafer side of the support substrate wafer 20 and the plane orientation of the surface 10A on the support substrate wafer side of the active layer wafer 10 be different from each other.

  Then, as shown in FIGS. 4C and 4D, in the bonded wafer 200, it is preferable that the wafer for active layer be composed of epitaxial silicon layers 10E and 10E '. In this case, the bonded wafer 200 can be an epitaxial silicon wafer. And, as described above, the gettering site is formed immediately below the epitaxial silicon layer.

  The bonded wafers 100 and 200 can be manufactured by the embodiment of the manufacturing method described above. Since the bonded wafers 100 and 200 are bonded by vacuum room temperature bonding, the interface to be a bonded part is an amorphous region immediately after preparation, and the amorphous region can be confirmed by observing a cross-sectional TEM photograph. . Further, when the bonded wafers 100 and 200 undergo heat treatment, the amorphous layers of the active layer wafer 10 and the supporting substrate wafer 20 recrystallize by heat treatment, so that only misfit dislocations are observed in the cross-sectional TEM photograph. For example, when heat treatment is performed at 800 ° C. or more for 30 minutes or more in a nitrogen atmosphere, recrystallization of the amorphous layer is confirmed.

  Hereinafter, the present invention will be described in more detail using examples, but the present invention is not limited to the following examples.

(Invention Example 1)
According to the flow chart shown in FIGS. 1 and 4, a bonded wafer (hereinafter, particularly referred to as “epitaxial wafer” in the present embodiment) according to Inventive Example 1 was manufactured. First, a silicon wafer (oxygen concentration: 0.5 × 10 ¹⁸ atoms / cm ³ , dopant: phosphorus, dopant concentration: as a wafer for active layer, plane orientation (100) of main surface, diameter: 200 mm, thickness: 725 μm) 4.4 × 10 ¹⁴ atoms / cm ³ , target resistivity: 10 Ω · cm) were prepared. In addition, as a wafer for support substrate, a silicon wafer with a main surface (100) plane orientation, a diameter of 200 mm and a thickness of 725 μm (oxygen concentration: 0.7 × 10 ¹⁷ atoms / cm ³ , dopant: phosphorus, dopant concentration: 1.4 × 10 ¹⁴ atoms / cm ³ , target resistivity: 30 Ω · cm) were prepared. Both wafers are provided with notches.

Then, an epitaxial layer of silicon (thickness: 8 μm, dopant: phosphorus, 4.4 × 10 ¹⁴ atoms / cm ^{3) is formed} on the wafer for active layer by a CVD method at 1150 ° C. using hydrogen as a carrier gas and dichlorosilane as a source gas. , Target resistivity: 10 Ω · cm).

Subsequently, the wafer for active layer and the wafer for support substrate were bonded in an environment of vacuum and normal temperature. Specifically, after introducing the wafer for active layer and the wafer for supporting substrate into the vacuum room-temperature bonding apparatus shown in FIG. 2 and setting the pressure in the chamber to 5.0 × 10 ⁻⁵ Pa, Ar ions are accelerated. Implantation is performed on the surface of the epitaxial layer of the wafer for active layer and the surface of the wafer for support substrate under the conditions of voltage: 1.0 keV, frequency: 140 Hz, pulse width: 55 × 10 ⁻⁶ seconds, and activation treatment is performed. Amorphous layers were formed on both surfaces. Thereafter, in the chamber, the wafer for active layer and the wafer for support substrate were pasted together through the amorphous layer on both surfaces. At the time of bonding, bonding was performed with the notch position of the wafer for active layer and the wafer for support substrate shifted in the circumferential direction by 5 °.

  Finally, the surface of the wafer for the active layer opposite to the surface of the epitaxial layer is ground and polished to remove the wafer for the active layer, and the epitaxial layer is thinned to have a thickness of 4 μm. An epitaxial wafer according to 1 was obtained.

(Invention Example 2)
An epitaxial wafer according to Inventive Example 2 was obtained under the same conditions as Inventive Example 1, except that (111) wafers having different plane orientations were used as the supporting substrate and the notch position deviation was 0 °.

(Conventional example 1)
An epitaxial silicon layer (thickness: 4 μm, dopant: phosphorus, 4.4 × 10 ¹⁴ atoms) is formed on the surface of the same supporting wafer as in the invention example 1 by CVD using hydrogen as a carrier gas and dichlorosilane as a source gas at 1150 ° C. / Cm ³ , target resistivity: 10 Ω · cm) were formed, and an epitaxial wafer according to Conventional Example 1 was obtained.

(Comparative example 1)
An epitaxial wafer according to Comparative Example 1 was obtained under the same conditions as Inventive Example 1, except that the shift in notch position was 0 °.

<Evaluation 1: Oxygen concentration profile immediately after preparation>
With respect to the epitaxial wafers produced in Inventive Example 1, Conventional Example 1 and Comparative Example 1, SIMS measurement was performed in a state immediately after production (that is, no heat treatment was performed after production) to obtain an oxygen concentration profile. 5 (A) shows the oxygen concentration profile of the invention example 1, FIG. 5 (B) shows the oxygen concentration profile of the prior art example 1, and FIG. 5 (C) shows the oxygen concentration profile of the comparative example 1. In FIG. 5, the depth of the surface of the epitaxial layer is 0 μm, and the same applies to FIG. 6 described later.

  From FIGS. 5A and 5C, in the epitaxial wafers manufactured in Inventive Example 1 and Comparative Example 1, a stepwise oxygen concentration fluctuation occurs at the interface between the epitaxial layer and the wafer for support substrate. It is confirmed. On the other hand, it is confirmed from FIG. 5B that in the epitaxial wafer according to Conventional Example 1, the oxygen concentration decreases from the wafer for support substrate toward the surface of the epitaxial layer due to the influence of thermal diffusion at the time of epitaxial layer formation. .

<Evaluation 2: Oxygen concentration profile after heat treatment>
Heat treatment at device formation is simulated for the epitaxial wafers produced in Inventive Example 1, Conventional Example 1 and Comparative Example 1, and heat treatment (heat treatment temperature: 1100 ° C., heat treatment time: 2 hours) is performed in a nitrogen atmosphere, SIMS measurements were taken to obtain an oxygen concentration profile. 6 (A) shows the oxygen concentration profile of the invention example 1, FIG. 6 (B) shows the oxygen concentration profile of the conventional example 1, and FIG. 6 (C) shows the oxygen concentration profile of the comparative example 1.

  From FIG. 6A, it is confirmed that oxygen is captured at a high concentration at the interface between the epitaxial layer and the wafer for support substrate in the invention example 1. Therefore, in the invention example 1, it is confirmed that the interface functions effectively as a gettering site. On the other hand, it is confirmed from FIGS. 6 (B) and 6 (C) that in the conventional example 1 and the comparative example 1, the oxygen concentration decreases from the wafer for support substrate toward the surface of the epitaxial layer after the heat treatment. Therefore, the gettering ability to capture oxygen was not recognized in Conventional Example 1 and Comparative Example 1.

<Evaluation 3: Gettering ability evaluation>
The surfaces of the epitaxial layers of the epitaxial wafers of Inventive Examples 1 and 2 and Conventional Example 1 and Comparative Example 1 are intentionally contaminated by a spin coat contamination method using Ni contamination liquid (1.0 × 10 ¹³ atoms / cm ² ). Then, heat treatment was performed at 900 ° C. for 30 minutes in a nitrogen atmosphere. Next, after soaking in a light solution for 3 minutes, the surface of the epitaxial layer after intentional contamination is observed with an optical microscope to investigate the presence of pits (surface pits due to nickel silicide: Ni pits) observed on the surface of the epitaxial layer. did. 7A is a photomicrograph of the invention example 1, FIG. 7B is a photomicrograph of the invention example 2, FIG. 7C is a photomicrograph of the prior art example 1, and FIG.

  From FIGS. 7A and 7B, Ni silicide was not observed in invention examples 1 and 2 according to the present invention. Thus, it was confirmed that the gettering ability for Ni could be imparted. On the other hand, since Ni silicide was observed in Comparative Example 1 and Comparative Example 1 from FIGS. 7 (C) and 7 (D), it was confirmed that there is no gettering ability to Ni.

  From the above results, in Inventive Examples 1 and 2 according to the present invention, misfit dislocations formed at the interface at the time of bonding by vacuum room temperature bonding method are formed, and this misfit dislocation effectively functions as a gettering site confirmed.

(Reference experiment example)
An epitaxial wafer according to Reference Example 1 was produced under the same conditions as in Inventive Example 1. Further, an epitaxial wafer was produced under the same conditions as in Inventive Example 1, and heat treatment (heat treatment temperature: 800 ° C., heat treatment time: 30 minutes) was further performed in a nitrogen atmosphere to produce an epitaxial wafer according to Reference Example 2. In addition, an epitaxial wafer according to Reference Example 3 was produced under the same conditions as Reference Example 2 except that the heat treatment temperature was changed to 900 ° C.

  Cross-sectional TEM photographs of the vicinity of the bonding interface (bonding region) in Reference Examples 1 to 3 were obtained. FIG. 8A shows a cross-sectional TEM photograph of Reference Example 1, FIG. 8B shows Reference Example 2, and FIG. 8C shows Reference Example 3 of FIG. An amorphous region was observed in FIG. 8 (A), and misfit dislocations were observed in FIGS. 8 (B) and 8 (C).

  The present invention is useful in the semiconductor industry because it can provide a method of manufacturing a bonded wafer and a bonded wafer capable of forming gettering sites at any depth position.

100, 200 Bonding wafer 10 Wafer for active layer 10A Bonding surface 10B for wafer for active layer Silicon wafer 10E Epitaxial silicon layer 20 Wafer for support substrate 20A Bonding surface for wafer for support substrate 12, 22 Amorphous layer 50 Vacuum room temperature bonding apparatus 51 Plasma chamber 52 Gas inlet 53 Vacuum pump 54 Pulse voltage application device 55A, 55B Wafer fixing table

Claims (17)

A method for producing a bonded wafer, in which a bonding surface of a silicon active layer wafer and a bonding surface of a silicon support substrate wafer are directly bonded.
An activation treatment step of activating the bonding surface of the wafer for active layer and the bonding surface of the wafer for support substrate at room temperature under vacuum;
Subsequently to the activation treatment step, the bonding surface of the wafer for active layer and the bonding surface of the wafer for support substrate are brought into contact with each other under vacuum normal temperature, and the wafer for the active layer, and for the support substrate And a bonding step of bonding the wafer
In the bonding step, the bonding is performed such that a misfit dislocation is formed at the interface between the wafer for active layer and the wafer for support substrate. The wafer for active layer and the wafer for support substrate each have a notch that indicates the crystal axis direction,
In the bonding step, the bonding is performed in a state in which the cutaway portion of the wafer for active layer is rotated in the circumferential direction from the cutaway portion of the wafer for support substrate. The manufacturing method of the joining wafer as described in ,.   The method for manufacturing a bonded wafer according to claim 2, wherein the notch is a notch or an orientation flat.   The method for manufacturing a bonded wafer according to claim 1, wherein the surface orientations of the bonding surface of the active layer wafer and the bonding surface of the support substrate wafer are different from each other. The active layer wafer includes a silicon wafer and an epitaxial silicon layer provided on the surface of the silicon wafer.
The method for manufacturing a bonded wafer according to any one of claims 1 to 4, wherein the bonding surface of the active layer wafer is a surface of the epitaxial silicon layer.   The method for manufacturing a bonded wafer according to claim 5, further comprising the step of grinding and polishing the active layer wafer from the opposite side of the epitaxial silicon layer of the active layer wafer to expose the epitaxial silicon layer.   The method for manufacturing a bonded wafer according to claim 6, wherein the grinding and polishing include grinding and polishing of the epitaxial silicon layer.   The method for producing a bonded wafer according to any one of claims 1 to 7, wherein the activation treatment is a treatment in which the ionized neutral element is caused to collide with the bonding surface to perform sputtering.   The method for producing a bonded wafer according to claim 8, wherein the neutral element is at least one selected from the group consisting of argon, neon, xenon, hydrogen, helium and silicon.   The method for manufacturing a bonded wafer according to any one of claims 1 to 7, wherein the activation process is a plasma etching process.   The method for producing a bonded wafer according to any one of claims 1 to 10, wherein the activation treatment is performed such that the thickness of the amorphous layer formed on both the bonding surfaces is 2 nm or more.   The method for producing a bonded wafer according to any one of claims 1 to 10, wherein the activation treatment is performed such that the thickness of the amorphous layer formed on both the bonding surfaces is 10 nm or more. A supporting substrate wafer made of silicon,
And an active layer wafer made of silicon provided on the surface of the support substrate wafer.
Bonded wafer misfit dislocations at the interface between the support substrate wafer and the wafer for the active layer is present, and characterized that you have an amorphous region is formed in the interface. The wafer for active layer and the wafer for support substrate each have a notch that indicates the crystal axis direction,
The bonded wafer according to claim 13, wherein the cut-out portion of the wafer for active layer is located at a position circumferentially rotated from the cut-out portion of the wafer for support substrate.   15. The bonded wafer of claim 14, wherein the notches are notches or orientation flats.   The bonded wafer according to claim 13, wherein a plane orientation of a surface of the support substrate wafer on the active layer wafer side and a plane orientation of the surface of the support substrate wafer of the active layer wafer are different from each other. The bonded wafer according to any one of claims 13 to 16, wherein the active layer wafer comprises an epitaxial silicon layer.