JP6544317B2 - Transistor drive circuit - Google Patents

Description

  The present invention relates to a drive circuit to be driven by connecting a bipolar transistor and a MOSFET in parallel.

  Although RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) which is 1 type of a bipolar type | mold transistor is a high voltage | pressure-resistant power element, there exists a problem that ON resistance is high. Therefore, conventionally, a low loss MOSFET using, for example, a wide gap semiconductor such as SiC is connected in parallel to the RC-IGBT, and the loss is reduced by simultaneously turning them on. Hereinafter, such parallel driving of the IGBT and the FET may be referred to as “DC assist”.

JP-A-4-354156

  When performing parallel driving in this manner, the low level voltage applied at the time of off may be set to a negative potential as shown in FIG. 3 in order to reliably maintain the off state of the MOSFET. Then, since the potential difference with the high level voltage applied at the time of ON becomes large, driving loss will increase.

  The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to provide a transistor drive circuit capable of reducing a drive loss when driving a bipolar transistor and a MOSFET in parallel.

  According to the transistor drive circuit of the present invention, when the bipolar transistor and the MOSFET are connected in parallel to drive the MOSFET, the voltage applied to the gate of the bipolar transistor is high because the MOSFET is turned on and off. While changing between the level and the low level of the negative polarity, a period is provided to apply an intermediate level between the two levels as the voltage.

  According to this structure, the off state of the MOSFET can be reliably maintained by basically applying a low level voltage of negative polarity to the gate. Then, when turning on the MOSFET, the voltage applied to the gate is changed to the high level of the positive polarity after the period of maintaining the intermediate level. Also, when turning off the MOSFET, it is changed from the high level of the positive polarity to the low level of the negative polarity through a period in which the intermediate level is maintained. As a result, the driving loss can be reduced by the amount by which the potential difference between the intermediate level and the high level is relatively small.

Further, according to the transistor drive circuit according to claim 1, the rising edge of the input signal, a falling edge, a rising edge detection circuit, respectively, edges detected by the falling edge detection circuit. The rising timer and the falling timer count a predetermined time from the time when the rising edge and the falling edge are detected, respectively. The bipolar transistor drive control section applies a turn-on level voltage to the gate of the bipolar transistor by the bipolar transistor drive circuit from the time when the rising edge is detected, and is timed by the falling timer from the time when the falling edge is detected. Turn-off level voltage is applied.

The low level application circuit, the intermediate level application circuit, and the high level application circuit constituting the MOS drive circuit are respectively controlled by the first, second and third MOS drive control units. Then, the first MOS drive control unit applies a low level voltage to the gate of the MOSFET while the bipolar transistor drive circuit applies a turn-off level voltage. The second MOS drive control unit is a first period from the time when the rising edge is detected to the elapse of a predetermined time counted by the rising timer, and the time measured by the falling timer from the time when the falling edge is detected. An intermediate level voltage is applied in the second period until time elapses. The third MOS drive control unit applies a high level voltage between the first period and the second period.

  According to this structure, the first and second periods in which the MOS drive circuit applies the intermediate level voltage to the gate of the MOSFET are within the period when the bipolar transistor starts to turn on and within the period when the turn off starts. It can be set to Therefore, even if it is possible to turn on the MOSFET by applying the intermediate level voltage, there is no problem at all.

A functional block diagram showing the configuration of a drive IC, which is an embodiment Timing chart showing operation of drive IC Timing chart explaining conventional common parallel drive system

  As shown in FIG. 1, the collector and the emitter of the RC-IGBT 1 and the drain and the source of the SiC-MOSFET 2 are connected in common. The collector of the IGBT 1 and the drain of the FET 2 are connected, for example, to an element on the upper arm side (not shown) which is also constituted by elements connected in parallel, and the emitter and source are connected to the ground.

  The IGBT 1 is provided with a detection element for dividing and detecting the collector current, but only the emitter terminal 4E is shown in the figure. The emitter terminal 4E is connected to the ground via the resistor 5. A signal for driving and controlling the IGBT 1 is input to the drive IC 6 from a control circuit (not shown). The input signal is input to the rising edge detection circuit 7 and the falling edge detection circuit 8. The rising edge detection circuit 7 detects a rising edge of the input signal and outputs a trigger signal, and the falling edge detection circuit 8 detects a falling edge of the input signal and outputs a trigger signal.

  The output signal of the rising edge detection circuit 7 is input as an on command to the third MOS drive control unit 11 and the second MOS drive control unit 13 via the IGBT drive control unit 9, the rise timer 10. The output signal is input as an off command to the first MOS drive control unit 12 and the second MOS drive control unit 13 via the rising timer 14.

  On the other hand, the output signal of the falling edge detection circuit 8 is sent to the IGBT drive control unit 9 through the falling timer 15, the third MOS drive control unit 11, and the second MOS drive control unit 13 through the falling timer 16. On the other hand, they are input as an off command. The output signal is input as an ON command to the first MOS drive control unit 12 via the second MOS drive control unit 13 and the falling timer 15.

  The IGBT drive control unit 9 inputs a drive control signal to the IGBT drive circuit 17 according to the on command and off command inputted. The IGBT drive circuit 17 is formed of, for example, a series circuit of two MOSFETs 17P and 17N, and outputs 15V as a high level drive voltage, that is, a turn on level voltage to the gate of the IGBT 1, and a low level drive voltage, that is, a turn off level voltage For example, 0 V is output to the gate of IGBT1.

  On the other hand, the MOS drive circuit 18 is constituted of, for example, a series circuit of two MOSFETs 18P and 18N_L, and a MOSFET 18_0 connected between the common connection point thereof and the ground. The FETs 18P and 18N_L are driven by the third MOS drive control unit 11 and the first MOS drive control unit 12, respectively, and the FET 18_0 is driven by the second MOS drive control unit 13. The MOS drive circuit 18 outputs a high level drive voltage of, for example, 20 V and a low level drive voltage of, for example, -5 V to the gate of FET2 by a series circuit of FETs 18P and 18N_L, and an FET 18_0 for example of 0 V as an intermediate level drive voltage. Output to the gate of The series circuit of the FETs 18P and 18N_L corresponds to a high level application circuit and a low level application circuit, and the FET 18_0 corresponds to an intermediate level application circuit.

  The IGBT drive control unit 9 outputs a high level drive voltage to the gate of the IGBT 1 by turning on the FET 17P and turning off the FET 17N when the on command is input, and holds the state until the next off command is input. maintain. When the third MOS drive control unit 11, the first MOS drive control unit 12, and the second MOS drive control unit 13 receive the on command, the respective drive target elements constituting the MOS drive circuit 18, the FETs 18P, 18N_L, 18_0 are selected. Output the drive voltage to turn on. Then, the state is maintained until the off command is input next.

Next, the operation of the present embodiment will be described. In addition, "RC-IGBT" shown in FIG. 2 means IGBT1, and "MOS" means FET2. In an initial state in which the input signal is at a low level, the IGBT drive control unit 9, the third MOS drive control unit 11, the first MOS drive control unit 12, and the second MOS drive control unit 13 receive input signals The on command and off command are given as follows after the previous falling timing.
IGBT drive control unit 9 off command third MOS drive control unit 11 off command first MOS drive control unit 12 on command second MOS drive control unit 13 off command Thus, 0 V of low level drive voltage is applied to the gate of IGBT 1 The low level drive voltage of -5 V is also applied to the gate of the FET2.

  From this state, when the level of the input signal changes from low to high at time (1), an ON command is input to the IGBT drive control unit 9 at the rise timing. Therefore, IGBT 1 immediately starts to turn on.

  On the other hand, on the FET 2 side, the off command is input to the first MOS drive control unit 12 at the rise timing described above, and the on command is input to the second MOS drive control unit 13. As a result, the FET 18N_L is turned off and the FET 18N_0 is turned on, and the gate drive voltage of the FET 2 starts to rise from -5V to 0V. Then, at time (2), the gate drive voltage reaches 0 V, which is an intermediate level drive voltage.

  Also, the timers 10 and 14 start clocking at the above rising timing. As long as the fixed time which both perform time measurement to the same time (3), the on command is input to the third MOS drive control unit 11 and the off command is input to the second MOS drive control unit 13 there. Thereby, the gate drive voltage of the FET 2 starts to rise from 0V to 20V.

Thereafter, when the level of the input signal changes to low at time point (4) after the turn-on of both IGBT1 and FET2 is completed, the off command is input to the third MOS drive control unit 11, and the second MOS drive control unit 13 is The on command is input. As a result, FET2 starts to turn off first, and the gate drive voltage of FET2 decreases from 20V to 0V. Then, at time (5), the gate drive voltage reaches 0 V, which is an intermediate level drive voltage.

  Further, the timers 15 and 16 start clocking at the above-mentioned falling timing. If the fixed time which both do clocking up to the same time (6), the off command is input to the IGBT drive control unit 9 there, and the IGBT 1 starts to turn off. At the same time, the off command is input to the second MOS drive control unit 13, and the on command is input to the first MOS drive control unit 12. As a result, the gate drive voltage of the FET 2 starts to decrease from 0 V to -5 V, and reaches -5 V of the low level drive voltage at time (7). Then, the initial state before time point (1) is reached. The periods in which the second MOS drive control unit 13 turns on the FET 18N_0 while the timers 14 and 16 are counting time correspond to the first period and the second period, respectively.

  As described above, according to the present embodiment, when the IGBT 1 and the FET 2 are driven in parallel, the FET 2 is turned on and turned off. Therefore, the voltage applied to the gate is a high level of positive polarity: 20 V and a low level of negative polarity: While changing to -5 V, a period is provided to apply an intermediate level 0 V, which is intermediate between the two levels.

  With this configuration, when the FET 2 is turned on, the voltage applied to the gate is changed to 20 V through a fixed period from -5 V to 0 V, and when turned off, the voltage is fixed from 20 V to 0 V Change to -5 V over a period of That is, the driving loss can be reduced by the amount by which the potential difference between the intermediate level and the high level is relatively small.

  In this case, the rising edge detection circuit 7 and the falling edge detection circuit 8 respectively detect the rising edge and the falling edge of the input signal. Rising timers 10 and 14 and falling timers 15 and 16 respectively measure a fixed time from the time when the rising edge and the falling edge are detected. The IGBT drive control unit 9 causes the IGBT drive circuit 17 to apply a high level drive voltage to the gate of the IGBT 1 from the time when the rising edge of the input signal is detected, and is timed by the timer 15 from the time when the falling edge is detected. The low level drive voltage is applied after a predetermined time has elapsed.

  The first MOS drive control unit 12 applies a low level voltage of −5 V to the gate of the FET 2 with the FET 18 _L while the IGBT drive circuit 17 applies a low level voltage. The second MOS drive control unit 13 is clocked by the falling timer 16 from the time when the falling edge is detected and the first period from the time when the rising edge is detected to the elapse of a fixed time counted by the timer 14. An intermediate level voltage of 0 V is applied by the FET 18_0 in a second period until a predetermined time elapses. Further, the third MOS drive control unit 11 applies a high level voltage by the FET 18P between the first period and the second period.

  According to this structure, the first period and the second period in which MOS drive circuit 18 applies the intermediate level voltage to the gate of FET 2 are within the period when IGBT 1 starts to turn on and the period when it starts to turn off. It can be set. Therefore, even if it is possible to turn on the FET 2 by applying the intermediate level voltage, there is no problem at all.

  In addition, since the falling timer 15 referenced by the IGBT drive circuit 17 and the falling timer 16 referenced by the MOS drive circuit 18 are separately provided, the timing at which the IGBT 1 starts to turn off and the FET 2 turns off The timing to start can be set individually.

(Other embodiments)
The drive voltages of the IGBT 1 and the FET 2 may be appropriately changed according to the individual design. Also, the intermediate level voltage is not limited to 0 V, and any voltage that can turn off the FET 2 may be used at an intermediate voltage between the high level drive voltage and the low level drive voltage. Also, even if the FET 2 is a voltage that may malfunction and turn on, there is no problem if it is set to start the turn-on of the IGBT 1 first as described above.
The falling timers 15 and 16 may be shared.
The bipolar transistor is not limited to the RC-IGBT. Also, the MOSFET is not limited to the SiC-MOSFET.

  Although the present disclosure has been described based on the examples, it is understood that the present disclosure is not limited to the examples and structures. The present disclosure also includes various modifications and variations within the equivalent range. In addition, various combinations and forms, and further, other combinations and forms including only one element, or more or less than these elements are also within the scope and the scope of the present disclosure.

  DESCRIPTION OF SYMBOLS 1 RC-IGBT, 2 SiC-MOSFET, 5 resistance, 6 drive IC, 7 rising edge detection circuit, 8 falling edge detection circuit, 9 IGBT drive control part, 10 rise timer, 11 3rd MOS drive control part, 12 1st MOS Drive control unit, 13 second MOS drive control unit, 14 rise timer, 15, 16 fall timer, 17 IGBT drive circuit, 18 MOS drive circuit.

Claims (2)

The driving target is one in which a bipolar transistor (1) and a MOSFET (2) are connected in parallel,
While changing the voltage applied to the gate of the MOSFET between the high level of positive polarity and the low level of negative polarity to turn on and off the MOSFET, an intermediate level between the two levels is applied as the voltage. order to provide a period in which,
A bipolar transistor drive circuit (17) for applying a turn-on level voltage and a turn-off level voltage to the gate of the bipolar transistor in response to a level change of an input signal;
Low level application circuit (18P, 18N_L) for applying low level voltage to the gate of the MOSFET according to level change of the input signal, high level application circuit (18P, 18N_L) for applying high level voltage, and intermediate level voltage A MOS drive circuit (18) comprising an intermediate level application circuit (18N_0) for applying
A rising edge detection circuit (7) for detecting a rising edge of the input signal;
A falling edge detection circuit (8) for detecting a falling edge of the input signal;
A rising timer (10, 14) for counting a fixed time from the time when the rising edge is detected;
A falling timer (15, 16) for counting a fixed time from the time when the falling edge is detected;
The turn-on level voltage is applied by the bipolar transistor drive circuit from the time when the rising edge is detected, and the fixed time measured by the falling timer from the time when the falling edge is detected. A bipolar transistor drive control unit (9) for applying the turn-off level voltage by a transistor drive circuit;
A first MOS drive control unit (12) for applying the low level voltage to the low level application circuit while the bipolar transistor drive circuit applies the turn-off level voltage;
A first period from the time when the rising edge is detected to the elapse of a fixed time counted by the rising timer, and the fixed time measured by the falling timer from the time when the falling edge is detected A second MOS drive control unit (13) for applying the intermediate level voltage to the intermediate level application circuit in a second period until
A transistor drive circuit comprising: a third MOS drive control unit (11) for applying the high level voltage by the high level application circuit between the first period and the second period . The falling timer (15, 16), said bipolar transistor drive circuit and the MOS driver circuit and the transistor drive circuit according to claim 1, wherein those which refer respectively are provided separately.

Images