JP6544799B2 - Circuit board and signal analysis system - Google Patents

Description

  The present invention relates to a circuit board and a signal analysis system.

In various devices, control is performed using a control circuit such as a CPU (Central Processing Unit). When control is performed using a control circuit such as a CPU, the processing content in the control is determined by the program. Therefore, when developing a device that performs control using a control circuit such as a CPU, an operation generally called “debug” is performed to search for and remove program errors.
Patent Document 1 describes a technique related to debugging in a handy terminal as a related technique.

Unexamined-Japanese-Patent No. 4-304534

By the way, in game machines such as a pachinko machine and a torso type game machine, effects such as giving the user a feeling of expectation of a big hit at the time of lottery are performed. Such effects in gaming machines are becoming more and more complicated year by year, and control performed by the CPU is also complicated. Therefore, in order to prevent delays in the effects in the gaming machine, a plurality of CPUs may be used to control the effects so that the amount of data processed by each of the CPUs is designed not to exceed the predetermined amount of data. is there.
When each of the CPUs performing such control is mounted on a separate circuit board, debug the program by monitoring each signal of the CPU at each connection unit where the circuit boards are connected to each other. Can. However, when a plurality of CPUs are mounted on the same circuit board, it is necessary to take out the signals from the circuit board in order to monitor each signal of the CPU. Therefore, when debugging a program, it is possible to modify the circuit board so that the signal in the circuit board can be monitored. However, in gaming machines such as flippers and roll-to-roll type gaming machines, the board once passed the test. Since it is necessary to retest if you remodel, it is necessary to debug the program on the circuit board in the state of being subjected to the test.
Therefore, there has been a demand for a game machine capable of debugging a program by monitoring a signal in a circuit board without modifying the circuit board.

  Then, this invention aims at providing the circuit board which can solve said subject, and a signal-analysis system.

In order to achieve the above object, the present invention is a first circuit connecting an output of a first CPU and an input of a second CPU mounted on the same substrate, the first circuit comprising: A first circuit pattern connected to an output, a second circuit pattern connected to an input of the second CPU, and a first circuit connecting the first circuit pattern and the second circuit pattern A second circuit connecting a first circuit having a resistor, an output of the second CPU and an input of the first CPU, the second circuit being connected to the input of the first CPU A third circuit pattern, a fourth circuit pattern connected to the output of the second CPU, and a second resistor connecting the third circuit pattern and the fourth circuit pattern; and 2 of the circuit, a first terminal connected to said first circuit pattern, A second terminal connected to the second circuit pattern, a third terminal connected to the third circuit pattern, and a fourth terminal connected to the fourth circuit pattern And a connection terminal .

  Moreover, this invention is a signal-analysis system provided with the above-mentioned circuit board and the signal-analysis apparatus which analyzes the signal acquired from the said connection terminal with which the said circuit board is provided.

  According to the circuit board of the present invention, it is possible to monitor a signal in the circuit board and debug a program in the gaming machine without remodeling the circuit board.

It is a figure which shows the minimum structure of the circuit board of this invention. It is a figure showing composition of a circuit board by a first embodiment of the present invention. It is a figure showing composition of a signal analysis system by this embodiment. It is a figure for demonstrating the design of the signal-analysis system by this embodiment. It is a figure which shows the structure of the signal-analysis system by 2nd embodiment of this invention. It is a figure for demonstrating the design of the signal-analysis system by this embodiment.

Hereinafter, embodiments will be described in detail with reference to the drawings.
First, the circuit board 10 of the minimum configuration of the present invention will be described.
As shown in FIG. 1, the circuit board 10 of the present invention includes at least a first circuit (hereinafter referred to as “first circuit”) 100 and a second circuit (hereinafter referred to as “second circuit”) 200. And the connection terminal 300.
The first circuit 100 connects the output of the first CPU and the input of the second CPU mounted on the same substrate.
The second circuit 200 connects the output of the second CPU and the input of the first CPU.
The connection terminal 300 is connected to the middle of the first circuit 100 and the second circuit 200 via a resistor circuit.

First Embodiment
First, the configuration of the circuit board 10 according to the first embodiment of the present invention will be described.
As shown in FIG. 2, the circuit board 10 according to the present embodiment includes a first circuit 100, a second circuit 200, a connection terminal 300, a first terminal circuit 401, a second terminal circuit 402, and a second terminal circuit 402. A buffer 501, a second buffer 502, a third buffer 503, and a fourth buffer 504.

The first circuit 100 includes a first circuit pattern (hereinafter referred to as "first circuit pattern") 101, a second circuit pattern (hereinafter referred to as "second circuit pattern") 102, and a first resistor. (Hereinafter referred to as "first resistance") 103.
The first circuit pattern 101 is connected to the output of the first CPU via a first buffer (hereinafter referred to as “first buffer”) 501.
The second circuit pattern 102 is connected to the input of the second CPU via a second buffer (hereinafter referred to as “second buffer”) 502.
The first resistor 103 connects the first circuit pattern 101 and the second circuit pattern 102.

The second circuit 200 includes a third circuit pattern (hereinafter referred to as "third circuit pattern") 201, a fourth circuit pattern (hereinafter referred to as "fourth circuit pattern") 202, and a second resistor. (Hereinafter referred to as "second resistance") 203.
The third circuit pattern 201 is connected to the input of the first CPU via a third buffer (hereinafter, referred to as “third buffer”) 503.
The fourth circuit pattern 202 is connected to the output of the second CPU via a fourth buffer (hereinafter, referred to as “fourth buffer”) 504.
The second resistor 203 connects the third circuit pattern 201 and the fourth circuit pattern 202.

The connection terminal 300 includes a first terminal (hereinafter referred to as “first terminal”) 301, a second terminal (hereinafter referred to as “second terminal”) 302, and a third terminal (hereinafter referred to as “third terminal”). And a fourth terminal (hereinafter, referred to as "fourth terminal").
The first terminal 301 is connected to the first circuit pattern 101.
The second terminal 302 is connected to the second circuit pattern 102.
The third terminal 303 is connected to the third circuit pattern 201.
The fourth terminal 304 is connected to the fourth circuit pattern 202.

The circuit board 10 shown in FIG. 2 includes the connection terminal 300 at the end of the board. When the circuit board 10 includes the connection terminal 300 at the end of the board, the first terminal circuit (hereinafter referred to as "first terminal circuit") 401 (401a and 401b) and the second terminal circuit (hereinafter referred to as "first terminal circuit") Hereinafter, the “second terminal circuit” 402 (402a, 402b) is provided.
The first terminal circuit 401 extends from the first circuit 100 to the connection terminal 300. Specifically, the first terminal circuit 401 a extends from the first circuit pattern 101 to the first terminal 301. The first terminal circuit 401 b extends from the second circuit pattern 102 to the second terminal 302.
The second terminal circuit 402 extends from the second circuit 200 to the connection terminal 300. Specifically, the second terminal circuit 402 a extends from the third circuit pattern 201 to the third terminal 303. The second terminal circuit 402 b extends from the fourth circuit pattern 202 to the fourth terminal 304.
Thus, in the circuit board 10, the positions of the first circuit 100 and the second circuit 200 are fixed. The first terminal circuit 401 extends from the first circuit 100 to the connection terminal 300 and the second terminal circuit 402 extends from the second circuit 200 to the connection terminal 300 in accordance with the position of the connection terminal 300 in the circuit board 10.
However, the position of the connection terminal 300 in the circuit board 10 may be a position directly connected to the first circuit 100 and the second circuit 200. In that case, the first terminal circuit 401 and the second terminal circuit 402 are unnecessary.

The first buffer 501 has an input connected to the first CPU and an output connected to the first circuit pattern 101.
The second buffer 502 has an input connected to the second circuit pattern 102 and an output connected to the second CPU.
An output of the third buffer 503 is connected to the first CPU, and an input is connected to the third circuit pattern 201.
The fourth buffer 504 has an output connected to the fourth circuit pattern 202 and an input connected to the second CPU.
However, the circuit board 10 shown in FIG. 2 includes the first buffer 501, the second buffer 502, the third buffer 503, and the fourth buffer 504, but the first buffer 501, the second buffer 502, and the third buffer Each of 503 and the fourth buffer 504 may exist outside the circuit board 10.

  The circuit board 10 transmits the signal received by the first buffer 501 to the second buffer 502 through the first circuit 100 when the program debugging is not performed, that is, when the connection terminal 300 is in the open state. . Further, when debugging of a program is not performed, the circuit board 10 transmits a signal received by the fourth buffer 504 to the third buffer 503 via the second circuit 200.

Next, the configuration of the signal analysis system 1 including the circuit board 10 according to the present embodiment will be described.
As shown in FIG. 3, the signal analysis system 1 according to the present embodiment includes a circuit board 10, computers (signal analysis devices) 20 (20a and 20b), and interfaces 30 (30a and 30b). Note that FIG. 3 shows a first CPU (hereinafter referred to as “first CPU”) 40 and a second CPU (hereinafter referred to as “second CPU”) 50.

  The computer 20 includes a computer 20a and a computer 20b. The computer 20 analyzes the signal acquired from the connection terminal 300 via the interface 30. Specifically, the computer 20a acquires the signal s1 output from the first CPU 40 from the first terminal 301 via the fifth buffer 31 described later and analyzes it. In addition, the computer 20b acquires a signal s2 output from the second CPU 50 from the fourth terminal 304 via an eighth buffer 34 described later and analyzes it.

  The interface 30 includes a fifth buffer (hereinafter referred to as "fifth buffer") 31, a sixth buffer (hereinafter referred to as "sixth buffer") 32, and a seventh buffer (hereinafter referred to as "seventh And a eighth buffer (hereinafter, referred to as an “eighth buffer”) 34. The interface 30 connects the circuit board 10 and the computer 20. Specifically, the fifth buffer 31 connects the first terminal 301 and the computer 20a. The sixth buffer 32 also connects the second terminal 302 to the computer 20b. The seventh buffer 33 also connects the third terminal 303 to the computer 20a. The eighth buffer 34 also connects the fourth terminal 304 to the computer 20 b.

Next, transmission and reception of signals in the signal analysis system 1 according to the present embodiment will be described.
Here, in the signal analysis system 1, a first program executed by the first CPU 40 (hereinafter referred to as “first program”) and a second program executed by the second CPU 50 (hereinafter referred to as “second program”) Signal transmission and reception in the case where each debugging of the above is performed separately will be described.
It is assumed that the computer 20a outputs the signal s3 used for debugging the first program executed by the first CPU 40 to the seventh buffer 33. In addition, it is assumed that the computer 20 b outputs, to the sixth buffer 32, the signal s 4 used for debugging the second program executed by the second CPU 50.
Further, each of the first buffer 501, the second buffer 502, the third buffer 503, the fourth buffer 504, the fifth buffer 31, the sixth buffer 32, the seventh buffer 33, and the eighth buffer 34 has infinite input impedance. Let the output impedance be zero and the current sink / source capability at the output be an infinite ideal buffer.

The computer 20 a outputs the signal s 3 to the seventh buffer 33.
The seventh buffer 33 receives the signal s3 from the computer 20a. Since the seventh buffer 33 is an ideal buffer, the signal s3 is output to the third terminal 303 when the load of the seventh buffer 33 is other than zero ohms. At this time, since each of the second terminal circuit 402 a and the third circuit pattern 201 is at the same node as the third terminal 303, it has the same potential as the third terminal 303.

  The third buffer 503 receives the signal s3. Since the third buffer 503 is an ideal buffer, the signal s3 is output to the input terminal in1 of the first CPU 40 when the load of the third buffer 503 is other than zero ohms.

  The first CPU 40 receives the signal s3 from the third buffer 503. The first CPU 40 outputs a signal s1 corresponding to the input signal s3 from the output terminal out1 to the first buffer 501 based on the first program.

  Since the first buffer 501 is an ideal buffer, the signal s1 is output to the first circuit pattern 101 when the load on the first buffer 501 is other than zero ohms. At this time, since each of the first terminal circuit 401 a and the first terminal 301 is at the same node as the first circuit pattern 101, it has the same potential as the first circuit pattern 101.

  The fifth buffer 31 receives the signal s1. Since the fifth buffer 31 is an ideal buffer, the signal s1 is output to the computer 20a when the load of the fifth buffer 31 is other than zero ohms.

  The computer 20a receives the signal s1 from the fifth buffer 31. The computer 20a debugs the first program based on whether the input signal s1 is a signal corresponding to the signal s3 output to the seventh buffer 33. Specifically, when the computer 20a determines that the input signal s1 is a signal corresponding to the signal s3 output to the seventh buffer 33, it determines that the first program is correct. If the computer 20a determines that the input signal s1 is not a signal corresponding to the signal s3 output to the seventh buffer 33, it determines that the first program is incorrect. If it is determined that the first program is incorrect, the computer 20a may control display, sound, vibration and the like to notify the user that the first program is incorrect.

Similarly, the computer 20 b outputs the signal s 4 to the sixth buffer 32.
The sixth buffer 32 receives the signal s4 from the computer 20b. Since the sixth buffer 32 is an ideal buffer, the signal s 4 is output to the second terminal 302 when the load of the sixth buffer 32 is other than zero ohms. At this time, since each of the first terminal circuit 401 b and the second circuit pattern 102 is at the same node as the second terminal 302, it has the same potential as the second terminal 302.

  The second buffer 502 receives the signal s4. Since the second buffer 502 is an ideal buffer, the signal s4 is output to the input terminal in2 of the second CPU 50 when the load of the second buffer 502 is other than zero ohms.

  The second CPU 50 receives the signal s 4 from the second buffer 502. The second CPU 50 outputs a signal s2 corresponding to the input signal s4 from the output terminal out2 to the fourth buffer 504 based on the second program.

  Since the fourth buffer 504 is an ideal buffer, it outputs the signal s 2 to the fourth circuit pattern 202 when the load of the fourth buffer 504 is other than zero ohms. At this time, since each of the second terminal circuit 402 b and the fourth terminal 304 is at the same node as the fourth circuit pattern 202, the second terminal circuit 402 b and the fourth terminal 304 have the same potential as the fourth circuit pattern 202.

The eighth buffer 34 receives the signal s2. Since the eighth buffer 34 is an ideal buffer, it outputs the signal s2 to the computer 20b when the load of the eighth buffer 34 is other than zero ohms.
The computer 20 b receives the signal s 2 from the eighth buffer 34. The computer 20 b debugs the first program based on whether the input signal s 2 is a signal corresponding to the signal s 4 output to the sixth buffer 32. Specifically, when the computer 20b determines that the input signal s2 is a signal corresponding to the signal s4 output to the sixth buffer 32, it determines that the first program is correct. When the computer 20b determines that the input signal s2 is not a signal corresponding to the signal s4 output to the sixth buffer 32, it determines that the second program is incorrect. If it is determined that the second program is incorrect, the computer 20b may control display, sound, vibration and the like to notify the user that the second program is incorrect.

Since the first buffer 501, the second buffer 502, the fifth buffer 31, and the sixth buffer 32 are ideal buffers, the potential at one end of the first resistor 103 is determined by the output of the first buffer 501. The potential of the other end of the resistor 103 is determined by the output of the sixth buffer 32. Since the input impedances of the second buffer 502 and the fifth buffer 31 are infinite, no current flows in the respective inputs of the second buffer 502 and the fifth buffer 31.
Therefore, when each of the first buffer 501, the second buffer 502, the fifth buffer 31, and the sixth buffer 32 is an ideal buffer, the potential difference between both ends of the first resistor 103 is set to the resistance value of the first resistor 103 at each moment. The current calculated by dividing by 流 れ る flows only from the output of the first buffer 501 to the output of the sixth buffer 32, or from the output of the sixth buffer 32 to the output of the first buffer 501. In this case, the signal s1 output from the first buffer 501 is not transmitted to the second circuit pattern 102.

Similarly, since the third buffer 503, the fourth buffer 504, the seventh buffer 33, and the eighth buffer 34 are ideal buffers, the potential at one end of the second resistor 203 is determined by the output of the fourth buffer 504, The potential of the other end of the second resistor 203 is determined by the output of the seventh buffer 33. Since the input impedance of each of the third buffer 503 and the eighth buffer 34 is infinite, no current flows in each input of the third buffer 503 and the eighth buffer 34.
Therefore, when each of the third buffer 503, the fourth buffer 504, the seventh buffer 33, and the eighth buffer 34 is an ideal buffer, the potential difference between both ends of the second resistor 203 is set to the resistance value of the second resistor 203 at each moment. The current calculated by dividing by 4 flows only from the output of the fourth buffer 504 to the output of the seventh buffer 33 or from the output of the seventh buffer 33 to the output of the fourth buffer 504. In this case, the signal s2 output from the fourth buffer 504 is not transmitted to the third circuit pattern 201.

Each of the first buffer 501, the second buffer 502, the third buffer 503, the fourth buffer 504, the fifth buffer 31, the sixth buffer 32, the seventh buffer 33, and the eighth buffer 34 in the present embodiment is ideal. Although the actual buffer has been described as a conventional buffer, it has a finite input impedance, a non-zero output impedance, and a finite current sink / source capability at the output. If the buffer's output impedance is not zero, the signal transmitted from the buffer to the load is attenuated to a signal determined by the buffer's output impedance and load division ratio, but the negative feedback technique and buffer size should be properly determined, etc. With proper design, characteristics such as buffer input impedance, output impedance, current sink / source capability at the output can be made closer to an ideal buffer, and can be regarded as an ideal buffer. In addition, by making the first resistance 103 and the second resistance 203 in the circuit board 10 larger than the output impedance of the buffer, the finite output impedance of the buffer is relative to the first resistance 103 and the second resistance 203. The signal s1 output from the first buffer 501 can not be transmitted to the second circuit pattern 102. In addition, by making the first resistance 103 and the second resistance 203 in the circuit board 10 larger than the output impedance of the buffer, the finite output impedance of the buffer is relative to the first resistance 103 and the second resistance 203. The signal s2 output from the fourth buffer 504 can not be transmitted to the third circuit pattern 201. More detailed design of the circuit board 10 and the signal analysis system 1 may be performed based on circuit simulation, experiments, and the like.
Further, in the actual design of the circuit board 10 and the signal analysis system 1, there may be a case where the power supply voltage, the signal amplitude, the high level and the low level in the logic circuit, and the noise margin are limited. Also, in the actual design of the circuit board 10 and the signal analysis system 1, it can not be regarded as an ideal buffer because the input impedance and output impedance of the buffer can not be ignored and the current sink / source capacity at the output tends to be insufficient. There is a case. In such a case, for example, as shown in FIG. 4, the voltage division ratio is set by changing the resistance value of each of the first circuit pattern 101, the second circuit pattern 102, the third circuit pattern 201, and the fourth circuit pattern 202. It is possible to change and adjust the operation of the logic circuit to be appropriate.

The signal analysis system 1 according to the first embodiment of the present invention has been described above. In the signal analysis system 1 described above, the first circuit 100 connects the output of the first CPU 40 mounted on the same substrate and the input of the second CPU 50. The second circuit 200 connects the output of the second CPU 50 and the input of the first CPU 40. The connection terminal 300 is connected to the middle of the first circuit 100 and the second circuit 200 via a resistor circuit.
In this way, in the gaming machine, it is possible to monitor the signal in the circuit board and debug the program without modifying the circuit board.

Second Embodiment
The configuration of the circuit board 10 according to the second embodiment of the present invention will be described.
Similar to the circuit board 10 according to the first embodiment shown in FIG. 2, the circuit board 10 according to the present embodiment includes the first circuit 100, the second circuit 200, the connection terminal 300, and the first terminal circuit 401. , A second terminal circuit 402, a first buffer 501, a second buffer 502, a third buffer 503, and a fourth buffer 504.

Next, the configuration of the signal analysis system 1 including the circuit board 10 according to the present embodiment will be described.
The signal analysis system 1 according to the present embodiment is, as shown in FIG. 5, similar to the signal analysis system 1 according to the first embodiment, the circuit board 10, the computers 20 (20a, 20b), and the interfaces 30 (30a, 30b). And.
However, the seventh buffer 33 included in the interface 30 a is not connected to the third terminal 303. Also, the sixth buffer 32 included in the interface 30 b is not connected to the second terminal 302.

Next, transmission and reception of signals in the signal analysis system 1 according to the present embodiment will be described.
Here, in the signal analysis system 1, the first CPU 40 and the second CPU 50 operate in conjunction with each other, and debugging of the first program executed by the first CPU 40 and the second program executed by the second CPU 50 is performed in parallel. The transmission and reception of the signal of
Each of the first buffer 501, the second buffer 502, the third buffer 503, the fourth buffer 504, the fifth buffer 31, the sixth buffer 32, the seventh buffer 33, and the eighth buffer 34 has infinite input impedance. Let the output impedance be zero and the current sink / source capability at the output be an infinite ideal buffer.
Further, it is assumed that the signal s1 output from the output terminal out1 by the first CPU 40 is determined when the signal analysis system 1 is started.

  The first CPU 40 outputs the signal s1 from the output terminal out1 to the first buffer 501 based on the first program when the signal analysis system 1 is activated.

  Since the first buffer 501 is an ideal buffer, the signal s1 is output to the first circuit pattern 101 when the load on the first buffer 501 is other than zero ohms. Since the input impedance of the second buffer 502 is infinite, no current flows in the first resistor 103. Therefore, at this time, each of the first terminal circuit 401a, the first terminal 301, the first resistor 103, the second circuit pattern 102, the first terminal circuit 401b, and the second terminal 302 is at the same potential as the first circuit pattern 101. is there.

  The fifth buffer 31 receives the signal s1. Since the fifth buffer 31 is an ideal buffer, the signal s1 is output to the computer 20a when the load of the fifth buffer 31 is other than zero ohms.

  The computer 20a receives the signal s1 from the fifth buffer 31. The computer 20a records the input signal s1. The computer 20a debugs the first program based on whether the recorded signal s1 is an appropriate signal. Specifically, the computer 20a determines that the first program is correct when the recorded signal s1 matches a predetermined signal from the time of activation of the signal analysis system 1 determined in advance. When the recorded signal s1 does not match the predetermined signal from the start of the signal analysis system 1 determined in advance, the computer 20a determines that the first program is incorrect. If it is determined that the first program is incorrect, the computer 20a may control display, sound, vibration and the like to notify the user that the first program is incorrect.

  The second buffer 502 also receives the signal s1. Since the second buffer 502 is an ideal buffer, the signal s1 is output to the input terminal in2 of the second CPU 50 when the load of the second buffer 502 is other than zero ohms.

  The second CPU 50 receives the signal s 1 from the second buffer 502. The second CPU 50 performs processing in accordance with the input signal s1 based on the second program. Alternatively, based on the second program, the second CPU 50 outputs a signal s2 corresponding to the input signal s1 from the output terminal out2 to the fourth buffer 504.

  Since the fourth buffer 504 is an ideal buffer, it outputs the signal s 2 to the fourth circuit pattern 202 when the load of the fourth buffer 504 is other than zero ohms. Since the input impedance of the third buffer 503 is infinite, no current flows in the second resistor 203. Therefore, at this time, each of the second terminal circuit 402b, the fourth terminal 304, the second resistor 203, the third circuit pattern 201, the second terminal circuit 402a, and the third terminal 303 is at the same potential as the fourth circuit pattern 202. is there.

  The eighth buffer 34 receives the signal s2. Since the eighth buffer 34 is an ideal buffer, it outputs the signal s2 to the computer 20b when the load of the eighth buffer 34 is other than zero ohms.

  The computer 20 b receives the signal s 2 from the eighth buffer 34. The computer 20b records the input signal s2. The computer 20b debugs the second program based on whether or not the recorded signal s2 is an appropriate signal. Specifically, the computer 20b determines that the second program is correct when the recorded signal s2 matches a predetermined signal from the start of the signal analysis system 1 determined in advance. If the recorded signal s2 does not match the predetermined signal from the start of the signal analysis system 1 determined in advance, the computer 20b determines that the second program is incorrect. If it is determined that the second program is incorrect, the computer 20b may control display, sound, vibration and the like to notify the user that the second program is incorrect.

  The third buffer 503 also receives the signal s2. Since the third buffer 503 is an ideal buffer, the signal s2 is output to the input terminal in1 of the first CPU 40 when the load of the third buffer 503 is other than zero ohms.

  The first CPU 40 receives the signal s 2 from the third buffer 503. The first CPU 40 performs processing according to the input signal s2 based on the first program. Alternatively, the first CPU 40 outputs the signal s1 corresponding to the input signal s2 from the output terminal out1 to the first buffer 501 based on the first program. Thereafter, the above-described operation similar to that after activation is repeated in the signal analysis system 1.

Each of the first buffer 501, the second buffer 502, the third buffer 503, the fourth buffer 504, the fifth buffer 31, the sixth buffer 32, the seventh buffer 33, and the eighth buffer 34 in the present embodiment is ideal. Although the actual buffer has been described as a conventional buffer, it has a finite input impedance, a non-zero output impedance, and a finite current sink / source capability at the output. If the buffer's output impedance is not zero, the signal transmitted from the buffer to the load is attenuated to a signal determined by the buffer's output impedance and load division ratio, but the negative feedback technique and buffer size should be properly determined, etc. With proper design, characteristics such as buffer input impedance, output impedance, current sink / source capability at the output can be made closer to an ideal buffer. The detailed design of the circuit board 10 and the signal analysis system 1 may be performed based on circuit simulation, experiments, and the like.
Further, in the detailed design of the actual circuit board 10 and the signal analysis system 1, there may be a case where there are limitations on the power supply voltage, the signal amplitude, the high level, the low level, the noise margin and the like in the logic circuit. In such a case, for example, as shown in FIG. 6, the voltage division ratio is set by changing the resistance value of each of the first circuit pattern 101, the second circuit pattern 102, the third circuit pattern 201, and the fourth circuit pattern 202. It is possible to change and adjust the operation of the logic circuit to be appropriate.

The signal analysis system 1 according to the second embodiment of the present invention has been described above. In the signal analysis system 1 described above, the first circuit 100 connects the output of the first CPU 40 mounted on the same substrate and the input of the second CPU 50. The second circuit 200 connects the output of the second CPU 50 and the input of the first CPU 40. The connection terminal 300 is connected to the middle of the first circuit 100 and the second circuit 200 via a resistor circuit.
In this way, in the gaming machine, it is possible to monitor the signal in the circuit board and debug the program without modifying the circuit board.

  Note that the storage unit in the embodiment of the present invention may be provided anywhere as long as appropriate transmission and reception of information is performed. In addition, a plurality of storage units and memories may exist in a range where appropriate transmission and reception of information is performed, and data may be distributed and stored.

  Note that the processes in the embodiment of the present invention may be performed in parallel, or the order of the processes may be changed as long as appropriate processes are performed.

  Although the embodiment of the present invention has been described, the above-described signal analysis system 1 internally has a computer system. The process of the process described above is stored in the form of a program in a computer-readable storage unit, and the process is performed by the computer reading and executing the program. Here, the computer-readable storage unit refers to a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, and the like. Alternatively, the computer program may be distributed to a computer through a communication line, and the computer that has received the distribution may execute the program.

  Further, the program may be for realizing a part of the functions described above. Furthermore, it may be a so-called difference file (difference program) that can realize the above-described functions in combination with a program already recorded in the computer system.

  While several embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. In addition, various omissions, replacements and changes can be made without departing from the scope of the invention.

10: circuit board 20, 20a, 20b: computer 30, 30a, 30b: interface 31: fifth buffer 32: sixth buffer 33: seventh buffer 34 · · Eighth buffer 40 ... first CPU
50: Second CPU
100 ... first circuit 101 ... first circuit pattern 102 ... second circuit pattern 103 ... first resistor 200 ... second circuit 201 ... third circuit Pattern 202 ... fourth circuit pattern 203 ... second resistor 300 ... connection terminal 301 ... first terminal 302 ... second terminal 303 ... third terminal 304 ... · · · Fourth terminal 401, 401a, 401b · · · first terminal circuit 402, 402a, 402b · · · second terminal circuit 501 · · · first buffer 502 · · · second buffer 503 · · · · · Third buffer 504 ··· Fourth buffer

Claims (4)

A first circuit connecting an output of a first CPU and an input of a second CPU mounted on the same substrate, the first circuit pattern connected to the output of the first CPU; A first circuit having a second circuit pattern connected to the input of the second CPU, and a first resistor connecting the first circuit pattern and the second circuit pattern ;
A second circuit connecting an output of the second CPU and an input of the first CPU, the third circuit pattern connected to the input of the first CPU, and the second CPU A second circuit having a fourth circuit pattern connected to the output of the second circuit, and a second resistor connecting the third circuit pattern and the fourth circuit pattern ;
A first terminal connected to the first circuit pattern, a second terminal connected to the second circuit pattern, a third terminal connected to the third circuit pattern, and A connection terminal having a fourth terminal connected to the four circuit patterns;
A circuit board comprising: A first buffer is provided between the first circuit pattern and the output of the first CPU,
A second buffer between the second circuit pattern and the input of the second CPU;
A third buffer provided between the third circuit pattern and the input of the first CPU;
A fourth buffer is provided between the fourth circuit pattern and the output of the second CPU.
The circuit board according to claim 1 . When the connection terminal is provided at the end of the substrate,
A first terminal circuit extending from the first circuit to the connection terminal;
A second terminal circuit extending from the second circuit to the connection terminal;
The circuit board according to claim 1 or claim 2 comprising a. A circuit board according to any one of claims 1 to 3 ;
A signal analysis device that analyzes a signal acquired from the connection terminal provided in the circuit board;
Signal analysis system comprising:

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