JP6546131B2 - Controller of current source power converter - Google Patents

Description

  The present invention relates to a controller of a current source power converter, and more particularly, to control of a current source power converter for reducing distortion of a voltage waveform and current ripple caused by providing an overlap time to a PWM (Pulse Width Modulation) signal. It relates to the device.

  There is known a power converter that mutually converts three-phase AC power and DC power using a bridge circuit. In this type of power conversion device, a PWM signal generated based on a command value synchronized with three-phase AC power and a predetermined carrier signal (periodic signal) for a plurality of switching elements forming a bridge circuit is used. Supplied. As a result of each switching element repeatedly turning on and off at a high speed according to the PWM signal, generation of DC power from three-phase AC power (powering) or generation of three-phase AC power from DC power (regeneration) is performed .

  Patent Document 1 and Non-Patent Document 1 describe types of the power conversion devices referred to as current type. The power conversion device of the current type is configured such that the current flowing to the direct current side becomes constant within a predetermined time by providing the inductor on the direct current side, and operates as a constant current source. The feature is that it enables both powering and regeneration without changing the direction of the direct current, and is often used in relatively large devices such as elevators. On the other hand, a voltage-type power converter having a capacitor instead of an inductor on the DC side is also known.

JP 2001-008458 A

  By the way, switching of the switching element by the PWM signal is basically performed by instantaneous switching of the switching element in which one switching element is turned off and the other switching element is turned on. However, since it is practically impossible to turn on and off the switching element without delay, in fact, both the period in which both the switching element to be turned off and the switching element to be turned on are off or vice versa There can occur periods of time that are on.

  Here, since an inductive component such as a reactor is generally connected to the DC side of the current source power converter, assuming that the bridge circuit is in an open state (the terminals on the DC side are isolated), A large voltage is generated in the circuit in the current source power converter and causes a failure. Therefore, although it is strictly prohibited to open the bridge circuit, as described above, the bridge circuit is just open during the period when both the switching element to be turned off and the switching element to be turned off are turned off. Period of time

  Therefore, in the current source power conversion device, processing is performed to delay the timing at which the switching element is turned off. Specifically, the timing at which the switching element is turned off is delayed by delaying the falling of the PWM signal for a predetermined time. According to this delay processing, a period in which both the switching element to be turned off and the switching element to be turned on are turned on is intentionally created. The period created in this way is usually referred to as "overlap time".

  The provision of the overlap time can prevent the bridge circuit from being open. However, by providing the overlap time, the voltage and current output to the DC side deviate from the intended state. Specifically, this deviation appears as distortion of the voltage waveform or ripple of the current.

  Therefore, an object of the present invention is to provide a control apparatus and control method of a current source power converter capable of reducing distortion of a voltage waveform and current ripple caused by providing an overlap time.

  A control device of a current source power converter according to the present invention comprises: first to third AC side nodes respectively corresponding to first to third phases of three-phase AC; first and second DC side nodes; First to third switching elements respectively connected between the first to third alternating current side nodes and the first direct current side node; and the first to third alternating current side nodes and the first to third switching elements respectively A control device of a current source power converter comprising: fourth to sixth switching elements connected between two DC side nodes, the first to the third corresponding to the first to third phases, respectively. Command value generation units generating first to third command values having the same phase as each of the AC voltages of 3; and the first to third command values received from the command value generation unit; The first to third of the first to third command values A command value changing unit that outputs the first to third command values after changing at least one command value selected for each of a plurality of spaces determined according to the phase of the AC voltage, and the command value First to sixth controls for controlling on / off of the first to sixth switching elements based on the first to third command values output from the changer and a given carrier signal And a PWM signal generator configured to generate a PWM signal composed of a signal.

  According to the present invention, since the rising position or the falling position of the PWM signal can be adjusted by changing the command value, even if the overlap time is provided, the same voltage waveform as in the case where the overlap time is not provided is obtained. Becomes possible. Therefore, it is possible to reduce the distortion of the voltage waveform and the ripple of the current caused by providing the overlap time.

  In the control device, the command value changing unit may select, for each of the plurality of spaces, the largest one of at least the first to third command values as a change target. According to this, when generating the PWM signal based on the time length calculated based on the largest one and the smallest one of the first to third command values, this is caused by providing the overlap time. It becomes possible to reduce the distortion of the voltage waveform and the ripple of the current.

  In each of the control devices, the command value changing unit may select, for each of the plurality of spaces, an intermediate value among at least the first to third command values as a change target. According to this, when the PWM signal is generated based on the time length calculated based on the intermediate value and the minimum value among the first to third command values, the overlap time is provided. It is possible to reduce the distortion of the voltage waveform and the ripple of the current caused by

  In each control device, the command value changing unit determines whether to perform the powering operation or the regeneration operation based on the voltage across the load connected between the first and second DC side nodes, When it is determined that the power running operation is to be performed, the at least one command value may be decreased, and when it is determined to perform the regenerative operation, the at least one command value may be increased. According to this, it is possible to reduce the distortion of the voltage waveform and the ripple of the current caused by providing the overlap time in both the case of performing the power running operation and the case of performing the regeneration operation.

  Each of the control devices may further include a delay application unit that delays the falling positions of the first to sixth control signals generated by the PWM signal generation unit. According to this, it is possible to provide an overlap time to the PWM signal.

  In the control device, the command value changing unit may change the at least one command by a change amount according to a time length of a delay given by the delay giving unit and a time length and an amplitude of one cycle of the carrier signal. The value may be changed. Further, the change amount may be equal to a value obtained by dividing the product of the delay time length given by the delay giving unit and the amplitude of the carrier signal by the time length of one period of the carrier signal. . According to these, it is possible to properly determine the amount of change.

  In the control device, the command value changing unit is configured to operate the time length of the delay provided by the delay giving unit, the time length and the amplitude of one cycle of the carrier signal, and the operations of the first to sixth switching elements. The at least one command value may be changed by a change amount according to the delay time length caused by the delay. Further, the change amount is obtained by multiplying the sum of the time length of the delay given by the delay giving unit and the time length of the delay caused by the operation delay of the first to sixth switching elements by the amplitude of the carrier signal. May be equal to a value obtained by dividing the time length of one period of the carrier signal. According to this, in addition to the distortion of the voltage waveform and the ripple of the current caused by providing the overlap time, the command value is changed also for the distortion and the ripple of the voltage waveform caused by the operation delay of the first to sixth switching elements. It is possible to reduce by the processing of the part.

  According to the present invention, since the rising position or the falling position of the PWM signal can be adjusted by changing the command value, even if the overlap time is provided, the same voltage waveform as in the case where the overlap time is not provided is obtained. Becomes possible. Therefore, it is possible to reduce the distortion of the voltage waveform and the ripple of the current caused by providing the overlap time.

It is a figure which shows the current source power converter device 11 by its preferable embodiment of this invention, and its control apparatus 10. As shown in FIG. It is a signal waveform diagram which shows the waveform at the time of the power running of each signal relevant to the PWM control which the control apparatus 10 shown in FIG. 1 performs. It is a figure explaining the production | generation method of the PWM signal by the control apparatus 10 shown in FIG. It is a schematic block diagram which shows the functional block of the control apparatus 10 shown in FIG. (A) is a basic signal waveform diagram at the time of the power running in space III shown in FIG. 2, (b) is a signal waveform diagram which shows the case where overlap time is installed in (a). FIG. 5B is a signal waveform diagram showing a case where the command value is further changed in FIG. It is a figure explaining the determination method of the change amount of the command value by the command value change part 21 shown in FIG. (A) is a basic signal waveform diagram at the time of the regeneration in the space III shown in FIG. 2, (b) is a signal waveform diagram which shows the case where overlap time is installed in (a). FIG. 8B is a signal waveform diagram showing a case where the command value is further changed in FIG. It is a signal waveform diagram which shows a change of each command value at the time of performing change of the command value by the command value change part 21 shown in FIG. 4, (a) shows the case of power running, (b) shows the case of regeneration. ing.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

  FIG. 1 is a diagram showing a current source power conversion device 11 according to the present embodiment and a control device 10 thereof.

  As shown in FIG. 1, the current source power conversion device 11 includes six switching elements Up, Vp, Wp, Un, Vn, Wn, six diodes Upd, Vpd, Wpd, Und, Vnd, Wnd, and three inductors. An AC reactor ACL, an input capacitor C composed of three capacitors, a DC reactor DCL composed of one inductor, and five terminals U, V, W, P, N are configured. The current source power conversion device 11 can be used in any of applications for converting three-phase AC power to DC power (powering) and applications for converting DC power to three-phase AC power (regeneration).

  The switching elements Up, Vp, Wp, Un, Vn, and Wn are each formed of an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor) or a MOS transistor. In FIG. 1, the diodes connected in parallel with the switching elements Up, Vp, Wp, Un, Vn, and Wn are illustrated, but these are diodes that occur structurally.

  One end of the switching element Up is connected to an AC side node Nu provided in the current source power conversion device 11, and the other end is connected to the anode of the diode Upd. Further, one end of the switching element Vp is connected to an AC side node Nv provided in the current source power conversion device 11, and the other end is connected to the anode of the diode Vpd. Furthermore, one end of the switching element Wp is connected to an AC side node Nw provided in the current source power conversion device 11, and the other end is connected to the anode of the diode Wpd. The cathodes of the diodes Upd, Vpd, and Wpd are commonly connected to a DC side node Np provided in the current source power conversion device 11. The direct current side node Np is connected to the terminal P via the direct current reactor DCL.

  Similarly, one end of the switching element Un is connected to the AC side node Nu, and the other end is connected to the cathode of the diode Und. Further, one end of the switching element Vn is connected to the AC node Nv, and the other end is connected to the cathode of the diode Vnd. Furthermore, one end of the switching element Wn is connected to the AC node Nw, and the other end is connected to the cathode of the diode Wnd. The anodes of the diodes Und, Vnd, and Wnd are commonly connected to a DC side node Nn provided in the current source power conversion device 11. The DC side node Nn is directly connected to the terminal N.

  The three inductors constituting the AC reactor ACL have one end connected to the terminal U and the other end connected to the AC side node Nu, one end connected to the terminal V, and the other end connected to the AC side node Nv And an inductor whose one end is connected to the terminal W and whose other end is connected to the AC side node Nw. The three capacitors constituting the input capacitor C are delta-connected, and the three connection points are respectively connected to the AC side nodes Nu, Nv and Nw. AC reactor ACL and input capacitor C constitute an AC filter.

  AC voltages Vu, Vv and Vw (first to third AC voltages) are supplied from the system power supply 12 to the terminals U, V and W, respectively. AC voltages Vu, Vv, and Vw are voltages corresponding to the U-phase, V-phase, and W-phase of three-phase AC, respectively. On the other hand, a load 13 is connected between the terminals P and N. The output voltage Vdc of the current source power conversion device 11 is represented by the potential difference between the DC side nodes Np and Nn. A current Idc due to the output voltage Vdc flows through the load 13.

  The load 13 is, for example, a power converter for driving a motor of a hybrid car, and operates on the basis of direct current power supplied from the current source power converter 11 (power running) and conversely to the current source power converter 11. However, there are cases where power is supplied (regeneration). Although described later in detail, when the potential difference Vout between both ends of the load 13 is positive, that is, when the load 13 performs powering operation and when the potential difference Vout is negative, that is, when the load 13 performs regeneration operation. And change the method of generating the PWM signal. As a result, the current source power conversion device 11 can perform both the powering operation of driving the load 13 by the power supplied from the system power supply 12 and the regeneration operation of returning the power supplied from the load 13 to the system power supply 12. Configured The output voltage Vdc takes a positive value when the current source power conversion device 11 performs the power running operation, and takes a negative value when performing the regenerative operation.

  Control device 10 generates PWM signals Sup, Svp, Swp, Sun, Svn, Swn (first to sixth control signals) synchronized with AC voltages Vu, Vv, Vw, and generates switching elements Up, Vp, This is a device that performs PWM control of the current source power conversion device 11 by supplying Wp, Un, Vn, and Wn to the gates.

  FIG. 2 is a signal waveform diagram showing waveforms during powering of each signal related to PWM control performed by the control device 10. As shown in FIG. Note that, in the drawing, there is shown a waveform in a state in which the setting of the overlap time described above and the operation characteristic of the present invention (change of the command value described later) are not performed. Hereinafter, the basic operation of the control device 10 will be described with reference to FIG.

As shown in FIG. 2, the AC voltages Vu, Vv and Vw are respectively sine wave signals shifted in phase by 2π / 3. The control device 10 generates a command value | du ^* | represented by an absolute value of a sine wave signal having the same phase as the AC voltage Vu based on the AC voltage Vu, and generates the AC voltage Vv based on the AC voltage Vv. command value represented by the absolute value of the sine wave signal having the same phase as | dv * ^| generates a command based on the AC voltage Vw, is represented by the absolute value of the sine wave signal having the same phase as the AC voltage Vw Generate the value | dw ^* |

The carrier signal Ca shown in FIG. 2 is a periodic signal having the same frequency as the on / off control frequency of the switching elements Up, Vp, Wp, Un, Vn, Wn, and is not shown in the control device 10. It is generated synchronously. Although the frequency of the carrier signal Ca is set to 36 times the frequency of the three-phase alternating current in FIG. 2 for convenience of illustration, the actual carrier signal Ca has a frequency several dozen times to several thousand times the frequency of the three-phase alternating current It becomes a high frequency signal. Therefore, during one cycle of the carrier signal Ca, the values of the command values | du ^* |, | dv ^* |, | dw ^* | can be regarded as constant, and the operation of the control device 10 described below Are all executed on the basis of the value considered to be constant. The carrier signal Ca is a so-called sawtooth wave, and its value becomes a predetermined minimum value at the start point of each cycle, a predetermined maximum value at the end point, and changes so as to linearly increase at a constant rate during that period. It is also possible to configure the carrier signal Ca by a triangular wave.

  One cycle of the three-phase AC can be divided into 12 spaces I to XII as shown in FIG. 2 according to the phases of the AC voltages Vu, Vv and Vw. In the present embodiment, a region in which the phase of AC voltage Vu is 0 or more and less than π / 6 is space I, and a region in which π / 6 or more and less than π / 3 is space II, is π / 3 or more and less than π / 2 Region III, space III, region π / 2 or more and less than 2π / 3 Space IV, region 2π / 3 or more and less than 5π / 6 Space V, region 5π / 6 or more but less than π, space VI, π or more A region that is less than 7π / 6 is a space VII, a region that is greater than 7π / 6 and less than 4π / 3 is a space VIII, and a region that is greater than 4π / 3 and less than 3π / 2 is a space IX that is greater than 3π / 2 and less than 5π / 3 A region having a space X, a region of 5π / 3 to less than 11π / 6 is defined as a space XI, and a region having a range of 11π / 6 to less than 2π is a space XII.

The controller 10 is configured to generate the PWM signals Sup, Svp, Swp, Sun, Svn, Swn based on the command values | du ^* |, | dv ^* |, | dw ^* | and the carrier signal Ca.

FIG. 3 is a diagram for explaining a method of generating a PWM signal by the control device 10. In the figure, taking the space III as an example, the carrier signal Ca for one period and the command values | du ^* |, | dv ^* |, | dw ^* | are shown. Although the following description focuses on the space III, the same applies to other spaces. Also, in the same drawing, the command values | du ^* |, | dv ^* |, | dw ^* | are drawn by a constant value not based on time (that is, by a horizontal straight line). The reason is that the values of the command values | du ^* |, | dv ^* |, | dw ^* | can be regarded as unchanged during one cycle of the carrier signal Ca.

Control device 10 takes a minimum value among command values | du ^* |, | dv ^* |, | dw ^* | at the beginning of one cycle of carrier signal Ca, and command values | dw ^* | du ^* |, dv ^* |, | dw ^* | For each of the command values | du ^* | that take the maximum value, obtain a specific value. Then, the time length T1 required for the carrier signal Ca to become equal to the command value | dw ^* | and the time length T2 required for the carrier signal Ca to become equal to the command value | du ^* | are calculated.

The method of calculating the time lengths T1 and T2 will be described in detail. As apparent from FIG. 3, the time lengths T1 and T2 satisfy the following equation (1). However, T is the time length of one cycle of the carrier signal Ca, and H is the amplitude of the carrier signal Ca.
T1: | dw ^* | = T1 + T2: | du ^* | = T: H (1)

Each of T1 and T1 + T2 is calculated | required from following Formula (2) (3) from Formula (1). The control device 10 calculates the time lengths T1 and T2 by substituting specific values of the acquired command values | du ^* | and | dw ^* | into the equations (2) and (3).
T1 = (T · | dw ^* |) / H (2)
T1 + T2 = (T · | du ^* |) / H (3)

  The control device 10 generates a PWM signal according to Table 1 below based on the calculated time lengths T1 and T2.

In Table 1, PWM signals Sup, Svp, the Swp is constant value, the command value ^{| du * |, | dv *} |, | dw * | command value takes a maximum value among | du ^* This corresponds to the fact that the AC voltage Vu corresponding to | is positive. When the AC voltage corresponding to the command value which takes the maximum value among the command values | du ^* |, | dv ^* |, | dw ^* | is negative, the PWM signals Sun, Svn, and Swn have constant values. Become. Also, among the three PWM signals that become constant values, the one that becomes high is the PWM corresponding to the command value that takes the largest value among the command values | du ^* |, | dv ^* |, | dw ^* | It becomes a signal (PWM signal Sup in space III). Furthermore, in Table 1, the levels of these signals are determined to be high in the order of the PWM signals Swn, Svn, and Sun, but in this order, the command values | du ^* |, | dv ^* |, | It corresponds to the reverse order of the size of dw ^* | (in space III, | dw ^* | <| dv ^* | <| du ^* |).

An example of a method of generating a PWM signal for a space other than the space III is as follows. That is, in the equations (4) and (5) and Table 2, the space IV (| dv ^* | <| dw ^* | <| du ^* |, and the AC voltage Vu corresponding to the maximum command value | du ^* | is positive. (6) (7) and Table 3 show the space V (| dv ^* | <| du ^* | <| dw ^* |, and the maximum command value | dw ^* | Shows a method of generating the PWM signal at the AC voltage Vw corresponding to

T1 = (T · | dv ^* |) / H (4)
T1 + T2 = (T · | du ^* |) / H (5)

T1 = (T · | dv ^* |) / H (6)
T1 + T2 = (T · | dw ^* |) / H (7)

As described above, the control device 10 first obtains the values of the maximum and the minimum of the command values | du ^* |, | dv ^* |, | dw ^* | for each cycle of the carrier signal Ca. The time lengths T1 and T2 are calculated based on them, and the PWM signals are generated according to the rules based on the above-mentioned tables.

The equation (3) can be rewritten as the following equation (8) (the same applies to the equations (5) and (7)). Since the phases of the command values | du ^* |, | dv ^* |, | dw ^* | are shifted by 2π / 3, the command values | du ^* | have three command values | du ^* |, | dv ^* In space III which takes the largest value among |, | dw ^* |, it is because | du ^* | = | dv ^* | + | dw ^* | holds.
T1 + T2 = {T. (| dv ^* | + | dw ^* |)} / H (8)

When calculating the time lengths T1 and T2 using the equations (2) and (3), the control device 10 needs to obtain the command values | du ^* | and | dw ^* | at the beginning of one cycle of the carrier signal Ca. is there. On the other hand, when the time lengths T1 and T2 are calculated by using the equations (2) and (8), the control device 10 determines the command value | dv ^* |, | dw ^{* at} the beginning of one cycle of the carrier signal Ca. Need to get | Either of these may be used, but this point affects the determination of the command value to be changed by the command value changing unit 21 (FIG. 4) described later.

  The above is the processing of the control device 10 in the case of performing the power running operation, but the processing of the control device 10 in the case of performing the regenerative operation is the processing in which the p side and the n side are switched in the above processing.

Specifically describing the space III as an example, the control device 10 first determines which of the power running operation and the regeneration operation is to be performed, based on the potential difference Vout between both ends of the load 13. When it is determined that the power running operation is to be performed, the operation as described above with reference to Table 1 is performed. On the other hand, when it is determined that the regeneration operation is to be performed, the AC voltage Vu corresponding to the command value | du ^* | that takes the largest value among the command values | du ^* |, | dv ^* |, | dw ^* | Corresponding to being positive, the PWM signals Sun, Svn, Swn are set to fixed values. In the space where the AC voltage corresponding to the command value taking the maximum value among the command values | du ^* |, | dv ^* |, | dw ^* | is negative, the PWM signals Sup, Svp, Swp are constant. It will be a value. Further, among these three PWM signals having constant values, the PWM signal corresponding to the command value taking the largest value among the command values | du ^* |, | dv ^* |, | dw ^* | (PWM in space III The signal Sun) is high and the other two are low. Furthermore, in response to the reverse order of the magnitudes of the command values | du ^* |, | dv ^* |, | dw ^* | (in the space III | dw ^* | <| dv ^* | <| du ^* |), the PWM signal Swp , Svp, and Sup, and the levels of these signals are determined to be high.

  Hereinafter, with reference to the functional blocks of the control device 10, regarding setting of overlap times for the PWM signals Sup, Svp, Swp, Sun, Svn, and Swn, and the operation of the control device 10 characteristic of the present invention (change of command value). While explaining in detail.

  First, FIG. 4 is a schematic block diagram showing functional blocks of the control device 10. As shown in FIG. As shown in the figure, the control device 10 is configured to include a command value generation unit 20, a command value change unit 21, a PWM signal generation unit 22, and a delay application unit 23.

Command value generation unit 20 generates command values | du ^* |, | dv ^* |, | dw ^* | having the same phase as AC voltages Vu, Vv, Vw, based on AC voltages Vu, Vv, Vw. It is a functional unit. The details of the command values | du ^* |, | dv ^* |, | dw ^* | are as described above.

Command value changing unit 21, the command value from the command value generating section ^{20 | du * |, | dv} * |, | dw * | receives the received command value ^{| du * |, | dv *} |, | dw * | After changing at least one command value selected for each of the plurality of spaces, the command values | du ^* |, | dv ^* |, | dw ^* | are output.

As a command value to be changed by the command value changing unit 21, at least the largest command value | du ^* |, | dv ^* |, | dw ^* | is selected for each of the plurality of spaces. . However, this is based on the command values | du ^* |, | dv ^* |, | dw ^* | as in the equations (2) and (3) described above, and the time length T1, In the case of calculating T2, as in the above-mentioned equations (2) and (8), the command values | du ^* |, | dv ^* |, | dw ^* | When calculating the time lengths T1 and T2 based on the above, at least the intermediate value among the command values | du ^* |, | dv ^* |, | dw ^* | is selected for each of the plurality of spaces. .

  Further, the direction (rising or lowering) of the change of the command value by the command value changing unit 21 differs between the case of power running and the case of regeneration. Specifically, the command value changing unit 21 determines which of the power running operation and the regenerative operation is to be performed based on the potential difference Vout at both ends of the load 13, and when it is determined that the power running operation is performed, the command value is When it is determined that the regeneration operation is to be performed, the command value is increased.

  Furthermore, the change amount of the command value by the command value change unit 21 is a value corresponding to the time length of the delay (described later) provided by the delay giving unit 23 and the time length and amplitude of one cycle of the carrier signal Ca. . This point will be described in more detail later with reference to FIG.

The PWM signal generation unit 22 generates the PWM signals Sup, Svp, Swp based on the command values | du ^* |, | dv ^* |, | dw ^* | output from the command value change unit 21 and the above-described carrier signal Ca. , Sun, Svn, Swn are generated. Further, the PWM signal generation unit 22 determines which of the power running operation and the regeneration operation is to be performed based on the potential difference Vout at both ends of the load 13, and according to the result, the PWM signals Sup, Svp, Swp, Sun, Svn, Change the generation method of Swn. The details of this generation are as described above with reference to Tables 1 to 3 and Formulas (1) to (8).

  The delay application unit 23 is a functional unit that delays the falling position of the PWM signals Sup, Svp, Swp, Sun, Svn, and Swn generated by the PWM signal generation unit 22 for a predetermined time. The processing of the delay application unit 23 realizes the overlap time. The PWM signals Sup, Svp, Swp, Sun, Svn, Swn after being processed by the delay application unit 23 are supplied to the gates of the switching elements Up, Vp, Wp, Un, Vn, Wn shown in FIG. Ru.

  Hereinafter, the process performed by each unit of the control device 10 will be described in more detail with reference to FIGS. 5 to 10. Although the following description focuses on the space III, the same applies to other spaces.

  First, the powering operation will be described with reference to FIGS. 5 and 6.

  FIG. 5A is a basic signal waveform diagram at the time of power running in the region of one period of the carrier signal Ca in the space III. "Basic" means that the command value changing unit 21 and the delay applying unit 23 are both skipped, that is, the overlap time is not set and the command value is not changed. In the space III, as also shown in Table 1, the PWM signal Sup is fixed to high, and the PWM signals Svp and Swp are fixed to low. On the other hand, PWM signal Swn is high from the beginning of one cycle of carrier signal Ca for a period of time length T1 and thereafter low, and PWM signal Svn is for a period of time length T2 from the timing when PWM signal Swn turns off. In the high period and other periods, it is low, and the PWM signal Sun is low until the timing when the PWM signal Svn is off, and is high thereafter.

  Due to the above change of the PWM signals Sup, Svp, Swp, Sun, Svn, Swn, the value of the output voltage Vdc becomes Vwu over the time length T1 from the beginning of one cycle of the carrier signal Ca as shown in FIG. It becomes Vvu over the time length T2 after that, and becomes 0 after that. However, it is Vwu = Vu-Vw, and it is Vvu = Vu-Vv. As apparent from the magnitude relationship between the AC voltages Vu, Vv, and Vw shown in FIG. 2, in the space III, Vvu> Vwu.

  The current source power conversion device 11 does not generate distortion of the waveform of the output voltage Vdc or ripple of the current Idc by the output voltage Vdc becoming Vwu over the time length T1 and becoming Vvu over the subsequent time length T2 as described above. It is designed to be optimal. Therefore, if the duration of the voltage Vwu or the duration of the voltage Vvu changes, distortion occurs in the waveform of the output voltage Vdc and ripples occur in the current Idc.

  FIG. 5B is a signal waveform diagram showing the case where the overlap time is set in FIG. 5A (when the delay applying unit 23 is operated). Here, the time length of the delay given by the delay giving unit 23 (= the time length of the overlap time) is Tolt. In this case, the falling positions of the PWM signals Sun, Svn, and Swn are delayed by Tolt as compared with the example of FIG. 5A (circled numbers 1 to 3 in the figure).

  In the falling delay portion (circled number 1 shown) of the PWM signal Sun, both the PWM signal Sun and the PWM signal Swn are in the high state. Therefore, switching elements Un and Wn shown in FIG. 1 are simultaneously turned on, but since AC voltage Vw is lower than AC voltage Vu in space III (see FIG. 2), current is supplied only to switching element Wn. And no current flows in the switching element Un. Therefore, substantially the same state as when only the switching element Wn is turned on is obtained, and as shown in FIG. 5B, the value of the output voltage Vdc is the same as Vwu in the example of FIG. 5A. Become.

  The hatching in the PWM signal in FIG. 5B indicates a period during which the switching element corresponding to the PWM signal is substantially on. For example, hatching attached to the PWM signal Swn indicates a period during which the switching element Wn corresponding to the PWM signal Swn is substantially on. This notation is the same as in FIG. 6, FIG. 8 (b) and FIG. 9 described later.

  At the falling delay portion of the PWM signal Swn (circled number 2 shown in the drawing), both the PWM signal Svn and the PWM signal Swn are in the high state. Therefore, switching elements Vn and Wn shown in FIG. 1 are simultaneously turned on, but since AC voltage Vv is lower than AC voltage Vw in space III (see FIG. 2), current is supplied only to switching element Vn. And no current flows in the switching element Wn. Therefore, substantially the same state as when only the switching element Vn is turned on is obtained, and as shown in FIG. 5B, the value of the output voltage Vdc is the same as Vvu as in the example of FIG. 5A. Become.

  At the falling delay portion (circled number 3 in the figure) of the PWM signal Svn, both the PWM signal Sun and the PWM signal Svn are in the high state. Therefore, switching elements Un and Vn shown in FIG. 1 are simultaneously turned on, but since AC voltage Vv is lower than AC voltage Vu in space III (see FIG. 2), current is supplied only to switching element Vn. And no current flows in the switching element Un. Therefore, substantially the same state as when only the switching element Vn is turned on is obtained, and the value of the output voltage Vdc becomes Vvu as shown in FIG. 5 (b). In the example of FIG. 5A, since the value of the output voltage Vdc in this period is 0, it is increased by Vvu.

  As described above, the value of the output voltage Vdc increases from 0 to Vvu at the falling delay portion (circled number 3 in the figure) of the PWM signal Svn. Therefore, in the example of FIG. The period in which the value of the output voltage Vdc is Vvu is longer than that in the example of FIG. 5A. That is, since the period in which the value of the output voltage Vdc is Vvu continues for a time length T2 + Tolt longer than the time length T2, distortion occurs in the waveform of the output voltage Vdc, and ripples occur in the current Idc.

  FIG. 6 is a signal waveform diagram showing a case where the command value is further changed in FIG. 5B (when the command value changing unit 21 is operated).

The command value changing unit 21 lowers at least one of the maximum and intermediate values among the command values | du ^* |, | dv ^* |, | dw ^* |. In the example of FIG. 6, the command value | du ^* | is the maximum value, and the command value | dv ^* | is an intermediate value. Therefore, the command value changing unit 21 outputs the command value | du ^* |, | Lower at least one of dv ^* |. Specifically, the time length T1 is determined based on the maximum and the minimum among the command values | du ^* |, | dv ^* |, | dw ^* | as shown in the equations (2) and (3) described above. , when calculating the T2 has at least the command value ^{| du * |, | dv *} |, | dw * | largest of the is instruction value among | du ^* | is descending. Also, as in the above-mentioned equations (2) and (8), the time length T1, based on the intermediate value and the minimum value among the command values | du ^* |, | dv ^* |, | dw ^* | to calculate the T2 has at least the command value ^{| du * |, | dv *} |, | dw * | command value is intended to take an intermediate value in the | dv ^* | is descending.

  The specific amount by which the command value changing unit 21 decreases the command value is determined so that the falling position of the PWM signal Svn moved by the setting of the overlap time will return to the position when the overlap time is not set. (Circled number 4 shown). Hereinafter, the method of calculating the lowering amount will be specifically described.

FIG. 7 is an explanatory diagram of a method of calculating the amount of decrease of the command value by the command value changing unit 21. As shown in FIG. The figure shows the command value | du ^* | before and after the change and the carrier signal Ca. Hereinafter, although the case where the command value | du ^* | is lowered is described as an example, the same applies to the case where the command value | dv ^* | is lowered. Further, in the same figure, as in FIG. 3, assuming that the time length of one cycle of the carrier signal Ca is T, the amplitude of the carrier signal Ca is H, and the command value | du ^* | is a constant value independent of time ( In other words, it is illustrated as a horizontal straight line).

In order to return the falling position of the PWM signal Svn to the position where the overlap time is not set, it is necessary to move the falling position of the PWM signal Svn to the left on the drawing by the time length Tolt. For that purpose, it is necessary to move the intersection of the command value | du ^* | and the carrier signal Ca to the left, which can be realized by decreasing the command value | du ^* |.

Assuming that the amount of decrease of the command value | du ^* | necessary for setting the movement amount on the time axis at the intersection of the command value | du ^* | and the carrier signal Ca is X, as is apparent from FIG. The following equation (9) holds.
X: Tolt = H: T (9)

If equation (9) is solved for X, then X = (H · Tolt) / T. Therefore, if the command value | du ^* | is lowered by (H · Tolt) / T, it can be said that the falling position of the PWM signal Svn can be returned to the position where the overlap time is not set. The change unit 21 changes the product of the command value | du ^* | to (H · Tolt) / T (ie, the time length Tolt of the delay provided by the delay application unit 23 and the amplitude H of the carrier signal Ca) of the carrier signal Ca. It is configured to be lowered by a value obtained by dividing by the time length T of one cycle. Since H is usually 1, the amount of decrease of the command value by the command value changing unit 21 is Tolt / T.

Thus, by lowering the command value | du ^* | (or the command value | dv ^* |) by (H · Tolt) / T, as shown in FIG. 6, not only the falling position of the PWM signal Svn but The rising position of the PWM signal Sun also moves in the same manner. Thus, while maintaining the overlap time as in the example of FIG. 5 (b), the duration of Vvu increased by the setting of the overlap time is the same as the time length T2 of FIG. 5 (a) without the overlap time. It is possible to return to Therefore, it is realized to reduce the distortion of the voltage waveform and the ripple of the current caused by providing the overlap time.

  Next, the operation at the time of regeneration will be described with reference to FIGS. 8 and 9.

  FIG. 8A is a basic signal waveform diagram at the time of regeneration in a region corresponding to one period of the carrier signal Ca in the space III. In this case, the PWM signal Sun is fixed high, and the PWM signals Svn and Swn are fixed low. Also, the PWM signal Swp is high from the beginning of one cycle of the carrier signal Ca for a period of time length T1 and then low, and the PWM signal Svp is for a period of time length T2 from the timing when the PWM signal Swp is off. In the high period and other periods, it is low, and the PWM signal Sup is low until the timing when the PWM signal Svp is turned off, and then high. The change of each of these PWM signals is obtained by replacing the p side and the n side in Table 1.

  Due to the above change of the PWM signals Sup, Svp, Swp, Sun, Svn, Swn, the value of the output voltage Vdc is from the beginning of one cycle of the carrier signal Ca to the time length T1 as shown in FIG. It becomes Vwu, it becomes -Vvu over the time length T2 after that, and it becomes 0 after that. However, it is Vwu = Vu-Vw, and it is Vvu = Vu-Vv.

  In the current source power conversion device 11, the output voltage Vdc becomes -Vwu over the time length T1 and then becomes -Vvu over the subsequent time length T2, thereby causing distortion of the waveform of the output voltage Vdc or ripple of the current Idc. It is optimally designed not to occur. Therefore, if the duration of the voltage -Vwu or the duration of the voltage -Vvu changes, the waveform of the output voltage Vdc is distorted as in the case of the power running, and a ripple occurs in the current Idc.

  FIG. 8B is a signal waveform diagram showing the case where the overlap time is set in FIG. 8A (when the delay applying unit 23 is operated). Here, the time length of the delay given by the delay giving unit 23 is Tolt. In this case, the falling positions of the PWM signals Sup, Svp, Swp are delayed by Tolt as compared with the example of FIG. 8A (circled numbers 1 to 3 in the figure).

  At the falling delay portion (circled number 1 shown in the figure) of the PWM signal Sup, both the PWM signal Sup and the PWM signal Swp are in the high state. Therefore, switching elements Up and Wp shown in FIG. 1 are simultaneously turned on, but since AC voltage Vu is higher than AC voltage Vw in space III (see FIG. 2), current is supplied only to switching element Up. And no current flows in the switching element Wp. Therefore, the state is substantially the same as when only the switching element Up is turned on, and the value of the output voltage Vdc becomes 0, as shown in FIG. 8B. In the example of FIG. 8A, since the value of the output voltage Vdc in this period is -Vwu, it is increased by Vwu.

  At the falling delay portion of the PWM signal Swp (circled number 2 shown in the drawing), both the PWM signal Svp and the PWM signal Swp are in the high state. Therefore, switching elements Vp and Wp shown in FIG. 1 are simultaneously turned on, but since AC voltage Vw is higher than AC voltage Vv in space III (see FIG. 2), current is supplied only to switching element Wp. And no current flows in the switching element Vp. Therefore, the state is substantially the same as when only the switching element Wp is turned on, and the value of the output voltage Vdc becomes -Vwu, as shown in FIG. 8B. In the example of FIG. 8A, since the value of the output voltage Vdc in this period is -Vvu, it is increased by Vvu-Vwu.

  In the falling delay portion (circled number 3 in the figure) of the PWM signal Svp, both the PWM signal Sup and the PWM signal Svp are turned on. Therefore, switching elements Up and Vp shown in FIG. 1 are simultaneously turned on, but since AC voltage Vu is higher than AC voltage Vv in space III (see FIG. 2), current is supplied only to switching element Un And no current flows in the switching element Vn. Therefore, the state is substantially the same as when only the switching element Un is turned on, and the value of the output voltage Vdc becomes zero, as shown in FIG. 8 (b). In the example of FIG. 8A, since the value of the output voltage Vdc in this period is -Vvu, it is increased by Vvu.

  As described above, at the time of regeneration, the value of the output voltage Vdc changes in the fall delay portion for any of the PWM signals Sup, Swp, and Svp. However, viewed as a whole, it can be said that the output voltage Vdc is −Vwu over the time length T1 and is further −Vvu over the subsequent time length T2-Tolt. Therefore, it can be said that the difference from FIG. 8A is that the duration of −Vvu is shortened by the time length Tolt, and the waveform of the output voltage Vdc in the example of FIG. And distortion occurs in the current Idc. In the example of FIG. 8B, the timing at which the output voltage Vdc changes from 0 to −Vwu is delayed by the time length Tolt as compared to the example of FIG. 8A, but the effect of the delay is Can be ignored.

  FIG. 9 is a signal waveform diagram showing a case where the command value is further changed in FIG. 8B (when the command value changing unit 21 is operated).

The command value changing unit 21 at the time of regeneration raises at least one of the maximum value and the intermediate value among the command values | du ^* |, | dv ^* |, | dw ^* |. In the example of FIG. 9, the command value | du ^* | is the largest value, and the command value | dv ^* | is an intermediate value. Therefore, the command value changing unit 21 outputs the command value | du ^* |, | raise at least one of dv ^* | Specifically, the time length T1 is determined based on the maximum and the minimum among the command values | du ^* |, | dv ^* |, | dw ^* | as shown in the equations (2) and (3) described above. , when calculating the T2 has at least the command value ^{| du * |, | dv *} |, | dw * | largest of the is instruction value among | du ^* | raise. Also, as in the above-mentioned equations (2) and (8), the time length T1, based on the intermediate value and the minimum value among the command values | du ^* |, | dv ^* |, | dw ^* | to calculate the T2 has at least the command value ^{| du * |, | dv *} |, | dw * | command value is intended to take an intermediate value in the | dv ^* | raise.

  A specific amount by which the command value changing unit 21 increases the command value is that the falling position of the PWM signal Svn moved by the setting of the overlap time further moves in the same direction by the overlap time (time length Tolt) Determined (circled number 4 shown). Specifically, (H · Tolt) / T is the increase amount of the command value, as in the case of the decrease amount described with reference to FIG.

Thus, by raising the command value | du ^* | (or the command value | dv ^* |) by (H · Tolt) / T, as shown in FIG. 9, the falling position of the PWM signal Svp is, of course, The rising position of the PWM signal Sup also moves in the same manner. As a result, while maintaining the overlap time as in the example of FIG. 8 (b), the duration of -Vvu shortened by the setting of the overlap time is the same as the time length as FIG. 8 (a) without the overlap time. It is possible to return to T2. Therefore, it is realized to reduce the distortion of the voltage waveform and the ripple of the current caused by providing the overlap time.

  In the above, the process which each part of the control apparatus 10 performs was demonstrated in detail about each at the time of power running and regeneration. Finally, an overview of changes in each command value will be described below.

FIG. 10 is a signal waveform diagram showing the change of each command value when the command value change unit 21 changes the command value, where (a) shows the case of powering and (b) shows the case of regeneration. There is. In the same figure, the command values | du ^* |, | dv ^* |, | dw ^* | as in the example of FIG. An example is shown. At the time of power running, as shown in FIG. 10A, as a result of processing by the command value changing unit 21, in each of the spaces I to XII, among the command values | du ^* |, | dv ^* |, | dw ^* | The ones with the largest and the middle ones fall. On the other hand, during regeneration, as shown in FIG. 10 (b), in each of the spaces I to XII, the maximum and middle values among the command values | du ^* |, | dv ^* |, | dw ^* | What you take will rise. As a result, it is possible to reduce the distortion of the voltage waveform and the ripple of the current caused by providing the overlap time in each of the spaces I to XII in both of the power running and the regeneration.

  Table 4 below summarizes the command values to be changed by the command value changing unit 21 for each space. The command value changing unit 21 raises or lowers the command value shown in Table 4 for each space.

  As described above, according to the control device 10 of the current source power conversion device 11 according to the present embodiment, the rising position or the falling position of the PWM signal can be adjusted by changing the command value. Even if provided, it becomes possible to obtain the same voltage waveform as in the case where the overlap time is not provided. Therefore, it is possible to reduce the distortion of the voltage waveform and the ripple of the current caused by providing the overlap time.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to these embodiments in any way, and the present invention can be implemented in various aspects without departing from the scope of the present invention. Of course.

  For example, although the above embodiment has been described on the premise that each switching element turns on and off momentarily according to a change in the corresponding PWM signal, in actuality, after the PWM signal changes, the corresponding switching element There may be a non-negligible delay before the on / off state switches. And generally speaking, the magnitude of the delay when the switching element is switched from off to on and the magnitude of the delay when the switching element is switched from on to off are not the same, and the latter becomes larger. The delay also causes an overlap time. Then, the total time length of the overlap time is a time length Tolt + Toff obtained by adding the time length Toff of the overlap time generated by this delay to the time length Tolt of the overlap time realized by the delay application unit 23 shown in FIG.

  Based on the above, the change amount of the command value by the command value change unit 21 when the time length Toff can not be ignored is the delay time length (= Tolt) given by the delay giving unit 23 and one cycle of the carrier signal Ca. It is preferable to set the value according to the time length Toff of the delay caused by the operation delay of the switching element, in addition to the value according to the time length and the amplitude of. Specifically, {H · (Tolt + Toff)} / T (that is, the sum of the delay time Tolt provided by the delay application unit 23 and the delay time Toff caused by the operation delay of the switching element is set to the carrier signal Ca. It is preferable to set the value obtained by multiplying the amplitude H of H.sub.2 by the time length T of one cycle of the carrier signal Ca). By doing this, in addition to distortion of the voltage waveform and ripple of the current caused by providing the overlap time, distortion of the voltage waveform and ripple of the current caused by the operation delay of the switching element are also reduced by the processing of the command value changing unit 21. It will be possible to

DESCRIPTION OF SYMBOLS 10 control apparatus 11 current source power converter 12 system power supply 13 load 20 command value generation part 21 command value change part 22 signal generation part 23 delay provision part ACL AC reactor C input capacitor Ca carrier signal DCL DC reactor H carrier signal Ca amplitude I to XII Space Idc Currents U, V, W, P, N flowing through the load 13 Terminals Np, Nn of the current source power converter 11 DC side nodes Nu, Nv, Nw AC side nodes Sup, Svp, Swp, Sun, Svn , Swn PWM signal T Carrier signal Ca One cycle time length T1 In a state where the command value changing unit 21 does not change the command value, the carrier signal Ca has a command value | du ^* |, | dv ^* |, | The time length T2 required to be equal to the smallest one of dw ^* | The change of the command value by the command value change unit 21 is performed The length of time required for the carrier signal Ca to become equal to the largest one among the command values | du ^* |, | dv ^* |, | dw ^* | , Un, Vn, Wn Switching elements Upd, Vpd, Wpd, Und, Vnd, Wnd Diode Vdc Output voltage Vout of current source power conversion device 11 Potential difference between both ends of load 13

Claims (7)

First to third AC side nodes respectively corresponding to the first to third phases of three-phase AC;
First and second DC side nodes;
First to third switching elements respectively connected between the first to third AC side nodes and the first DC side node;
A control device of a current source power conversion device, comprising: fourth to sixth switching elements respectively connected between the first to third alternating current side nodes and the second direct current side node;
A command value generation unit that generates first to third command values having the same phase as the first to third AC voltages respectively corresponding to the first to third phases;
Among the first to third command values received from the command value generation unit, the plurality of command values determined according to the phases of the first to third AC voltages. A command value changing unit that outputs the first to third command values after changing at least one command value selected for each space of
First to sixth for controlling on / off of each of the first to sixth switching elements based on the first to third command values output from the command value changing unit and a given carrier signal A PWM signal generation unit that generates a PWM signal including six control signals ;
And a delay application unit for delaying a falling position of the first to sixth control signals generated by the PWM signal generation unit ,
The command value changing unit, time and length of the delay applied by the delay imparting section, at the changing amount corresponding to the time length and amplitude of one cycle of the carrier signal, to change said at least one command value A control device characterized by The control device according to claim 1, wherein the command value changing unit selects, for each of the plurality of spaces, the largest one of at least the first to third command values as a change target. . 3. The apparatus according to claim 1, wherein the command value changing unit selects, for each of the plurality of spaces, an intermediate value among at least the first to third command values as a change target. Control device as described. The command value change unit is
Power running is performed such that the PWM signal is generated such that the DC-side output voltage of the current source power converter becomes positive based on the voltage across the load connected between the first and second DC-side nodes whether to perform the operation at the time, it determines whether to perform the operation at the time of regeneration of the output voltage is the PWM signal such that the negative is produced,
If it is determined that performing the operation during power running, the lowers the at least one command value,
The control device according to any one of claims 1 to 3, wherein, when it is determined that the operation at the time of regeneration is performed, the at least one command value is increased. The change amount is equal to a value obtained by dividing the product of the delay time length given by the delay giving unit and the amplitude of the carrier signal by the time length of one period of the carrier signal. The control apparatus of claim 1 . The command value changing unit includes a delay time length given by the delay giving unit, a time length and amplitude of one period of the carrier signal, and a delay caused by an operation delay of the first to sixth switching elements. at the changing amount corresponding to the time length, the control device according to claim 1, characterized in that to change the at least one command value. The amount of change is a value obtained by multiplying the sum of the time length of the delay given by the delay giving unit and the time length of the delay caused by the operation delay of the first to sixth switching elements by the amplitude of the carrier signal. The control device according to claim 6 , wherein the control signal is equal to a value obtained by dividing the time length of one period of the carrier signal.

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