JP6548688B2 - Semiconductor device - Google Patents

Description

The disclosed invention relates to a semiconductor device using an oxide semiconductor.

Note that, in the present specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor in this specification is a semiconductor device, and an electro-optical device, a semiconductor circuit, and an electronic device including the transistor are all included in the semiconductor device.

A transistor used in many flat panel displays represented by a liquid crystal display device and a light emitting display device is formed of a silicon semiconductor such as amorphous silicon, single crystal silicon or polycrystalline silicon formed on a glass substrate. . In addition, transistors using the silicon semiconductor are also used in integrated circuits (ICs) and the like.

In place of the silicon semiconductor, a technique using a metal oxide exhibiting semiconductor characteristics for a transistor has attracted attention. Note that in the present specification, a metal oxide exhibiting semiconductor characteristics is referred to as an "oxide semiconductor".

For example, a technology in which a transistor is manufactured using a Zn-O-based metal oxide or an In-Ga-Zn-O-based metal oxide as an oxide semiconductor and used for a switching element of a pixel of a display device Are disclosed (see Patent Document 1 and Patent Document 2).

In a transistor using an oxide semiconductor, a source region and a drain region,
A technique for reducing the contact resistance between an oxide semiconductor and a source electrode and a drain electrode is disclosed by providing a highly conductive oxide semiconductor containing nitrogen as a buffer layer between the source electrode and the drain electrode. (See Patent Document 3).

Further, in a top gate transistor including an oxide semiconductor, a technique for forming a channel formation region, a source region, and a drain region in a self-aligned manner is disclosed (see Non-Patent Document 1).

Unexamined-Japanese-Patent No. 2007-123861 JP 2007-96055 A JP, 2010-135774, A

Jae Chul Park et al. “High performance amorphous oxide thin film transistors with self-aligned top-gate structure” IEDM 2009, pp 191-194

In order to increase the degree of integration of integrated circuits using transistors, it is necessary to miniaturize the transistors.

Generally, in miniaturization of a transistor using a silicon semiconductor, a transistor whose channel length is extremely shortened causes variation in electrical characteristics such as a threshold voltage variation in the negative direction. Suppression of this phenomenon is one of the problems in miniaturization of a transistor using a silicon semiconductor.

In addition, a transistor using an oxide semiconductor is known to have a small off-state current at room temperature as compared to a transistor using silicon, which has few carriers generated by thermal excitation, that is, has a small carrier density. it is conceivable that. Then, even in a transistor using a material with a low carrier density, fluctuation in threshold voltage or the like appears by shortening the channel length.

Therefore, an object of one embodiment of the present invention is to provide a semiconductor device in which fluctuation in electrical characteristics due to miniaturization is less likely to occur.

In a transistor using an oxide semiconductor, in order to suppress variation in electrical characteristics due to miniaturization of the transistor, a region including a dopant is provided in an oxide semiconductor film including a channel formation region. Specifically, the oxide semiconductor film is provided with a pair of regions containing a dopant and a channel formation region. By doing this, it occurs in the drain region,
In addition, in order to reduce the electric field applied to the channel formation region, it is possible to reduce the influence of shortening the channel length, such as the fluctuation of the threshold voltage. Note that in this specification, a dopant is a generic term for an element and an impurity which are added to an oxide semiconductor film including a channel formation region.

In addition, the oxide semiconductor film is non-single-crystal, and in detail, viewed in a direction perpendicular to the ab plane of the non-single-crystal, the atomic arrangement of a triangle, a hexagon, an equilateral triangle, or an equilateral hexagon And a crystal part in which the metal atoms are layered or the metal atoms and the oxygen atoms are arranged in layers when viewed in the direction perpendicular to the c-axis. In this specification, an oxide semiconductor having the crystal part is referred to as a CAA.
C-OS (C Axis Aligned Crystalline Oxide Se
I will call it "miconductor". In addition, the channel formation region is referred to as a CAAC-O.
By using S, variation in the electrical characteristics of the transistor due to irradiation of visible light or ultraviolet light, heat, a bias, or the like can be suppressed, and the reliability of the semiconductor device can be improved.

Further, the region containing the above-described dopant is formed of an oxide semiconductor region having a plurality of crystal parts mainly made of polycrystal. Thus, also in the region including the above-described dopant, variation in electrical characteristics of the transistor can be suppressed by using the oxide semiconductor region having a plurality of crystal parts.

That is, one embodiment of the present invention is an oxide semiconductor film including a first region and a pair of second regions facing each other with the first region interposed therebetween, and a gate insulating film provided over the oxide semiconductor film. A non-single-crystal oxide having a film and a first electrode provided over a gate insulating film and overlapping a first region, the first region having a c-axis oriented crystal part The semiconductor device is a semiconductor region, and the pair of second regions is a semiconductor device which is an oxide semiconductor region including a dopant and having a plurality of crystal parts.

In the region containing a dopant, a non-single-crystal oxide semiconductor region having a c-axis aligned crystal part may be provided over an oxide semiconductor region having a plurality of crystal parts.

The oxide semiconductor film is preferably an oxide semiconductor film containing two or more elements selected from In, Ga, Sn, and Zn.

Further, the semiconductor device has a second electrode and a third electrode electrically connected to the pair of second regions.

The pair of second regions can be formed in a self-aligned manner by using the first electrode as a mask and passing the gate insulating film to add a dopant. The pair of second regions functions as at least a source region and a drain region, and an electric field applied to the first region is provided by providing a pair of second regions containing a dopant at both ends of the first region which is a channel formation region. It is possible to reduce the influence of shortening the channel length, such as fluctuation of the threshold voltage of the transistor.

Further, a sidewall insulating film is provided on the side surface of the first electrode, and the first electrode is used as a mask.
By passing the sidewall insulating film and adding the dopant, a pair of third regions having a lower dopant concentration than the pair of second regions can be formed in a self-aligned manner.

That is, the pair of third regions is formed between the first region functioning as a channel formation region and the pair of second regions. The pair of second regions having a higher dopant concentration than the pair of third regions functions as a source region and a drain region. The pair of third regions, which has a lower dopant concentration than the pair of second regions, functions as a region that relaxes an electric field applied to the channel formation region, that is, an electric field relaxation region. By providing the electric field relaxation region in this manner, the influence of shortening the channel length, such as fluctuation of the threshold voltage of the transistor, can be reduced. Further, the pair of second regions and the pair of third regions are each formed of an oxide semiconductor region having a plurality of crystal parts.

Therefore, according to another aspect of the present invention, there is provided a first region and a pair of second regions facing each other via the first region.
An oxide semiconductor film including the first region and a pair of third regions provided between the first region and the pair of second regions; and a gate insulating film provided over the oxide semiconductor film. And a first electrode provided over the gate insulating film and overlapping the first region, and the first region includes a c-axis-oriented crystal portion and a non-single-crystal oxide semiconductor region The pair of second regions and the pair of third regions are an oxide semiconductor region including a dopant and having a plurality of crystal parts, and the dopant concentration of the pair of second regions is a pair of second regions and a pair of third regions. The semiconductor device is higher than the dopant concentration in the third region.

In each of the pair of second regions and the pair of third regions, a non-single-crystal oxide semiconductor region having c-axis aligned crystal parts is provided over the oxide semiconductor region having a plurality of crystal parts. May be

For example, the dopant added to the pair of second regions and the pair of third regions is a Group 15 element or boron. For example, the dopant is one or more elements selected from phosphorus, arsenic, and antimony and boron, and the dopant concentration included in the pair of second regions and the pair of third regions is 5 × 10 ¹⁸ cm ^{− 3} or more and 1 * 10 < ²² > cm < ^-3 > or less are preferable. Furthermore, the dopant concentration of the pair of second regions is 5 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²
And ² cm ^-3 or less, the dopant concentration of the pair of third regions is 5 × ¹⁰ 18 ^{cm -3} or more 5
It is more preferable to set it as less than * 10 < ²¹ > cm < ^-3 >.

In addition, the transistor of one embodiment of the present invention is a top gate transistor, and the top contact structure in which the second electrode and the third electrode are in contact with the top surfaces of the pair of second regions may be employed. The bottom contact structure may be in contact with the lower surface of the two regions.

In the above, when the dopant is added to the oxide semiconductor film including the channel formation region, the first
The dopant may be added without passing through the gate insulating film, using the electrode of (1) as a mask. For example, the range in which the gate insulating film is formed may be set only on the first region.

In the case where the gate insulating film is formed of an oxide insulating film and the sidewall insulating film is formed of a nitride insulating film, the etching rates of the nitride insulating film and the oxide insulating film may be different.
The gate insulating film (the oxide insulating film) functions as an etching stopper when the sidewall insulating film (the nitride insulating film) is formed, and the oxide semiconductor film in contact with the lower surface of the gate insulating film is formed. Excessive etching can be suppressed. As a result, the gate insulating film is left over the first region, the pair of second regions, and the pair of third regions.

Further, when both the sidewall insulating film and the gate insulating film are oxide insulating films, the pair of second regions and the pair of second regions and the pair of insulating films can be formed by utilizing the difference in etching rates of the oxide insulating film and the first electrode. The gate insulating film provided over the third region can be etched.
As a result, the gate insulating film is left on the first region.

According to one embodiment of the present invention, a semiconductor device in which fluctuation in electrical characteristics due to miniaturization is less likely to occur can be provided.

7A and 7B are a top view and a cross-sectional view illustrating an example of a semiconductor device which is an embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 7A and 7B are a top view and a cross-sectional view illustrating an example of a semiconductor device which is an embodiment of the present invention. 7A and 7B are a top view and a cross-sectional view illustrating an example of a semiconductor device which is an embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating an example of a semiconductor device which is an embodiment of the present invention. 7A and 7B are a top view and a cross-sectional view illustrating an example of a semiconductor device which is an embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 7A and 7B are a top view and a cross-sectional view illustrating an example of a semiconductor device which is an embodiment of the present invention. 7A and 7B are a top view and a cross-sectional view illustrating an example of a semiconductor device which is an embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating an example of a semiconductor device which is an embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating an example of a semiconductor device which is an embodiment of the present invention. FIG. 18 is a cross-sectional view illustrating an example of a semiconductor device which is an embodiment of the present invention. The figure which shows the structure of the oxide semiconductor after adding a dopant. FIG. 16 shows electronic states of an oxide semiconductor before and after addition of a dopant. FIG. 18 shows a cross-sectional TEM image of the oxide semiconductor after the addition of the dopant. FIG. 7 illustrates an example of a circuit diagram of a semiconductor device which is an embodiment of the present invention. FIG. 7 illustrates an example of a circuit diagram of a semiconductor device which is an embodiment of the present invention. FIG. 7 illustrates an example of a circuit diagram of a semiconductor device which is an embodiment of the present invention. FIG. 7 illustrates an example of a circuit diagram of a semiconductor device which is an embodiment of the present invention. The block diagram which shows the specific example of CPU, and the figure which shows the circuit diagram of the one part.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that various changes can be made in the form and details thereof without departing from the spirit of the present invention and the scope thereof. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated.

It should be noted that in the figures described herein, the size of each component, the thickness of the film, or the area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale.

Further, the terms first, second, third and the like used in the present specification are given to avoid confusion of components, and are not limited numerically. Therefore, for example, "first"
The description can be appropriately replaced with the second "or" or the like.

In the present specification, the term "film" is formed on the entire surface of the surface to be formed by CVD (including plasma CVD) or sputtering, etc. Are used for the semiconductor device after the process related to the manufacturing process of the semiconductor device is performed.

The functions of “source” and “drain” may be switched when adopting transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in the present specification, the terms "source" and "drain" can be used interchangeably.

Embodiment 1
In this embodiment mode, a structure and a manufacturing method of a transistor which is one embodiment of the present invention
This will be described using FIGS. 1 to 8.

<Structure and Features of Transistor 100>
FIG. 1A is a top view of the transistor 100. FIG. Note that in FIG. 1A, the base insulating film 102, the gate insulating film 111, and the interlayer insulating film 117 are not shown for convenience.

As illustrated in FIG. 1A, the first electrode 113 is provided over the oxide semiconductor film 103 including a first region 105 (not shown) and a pair of second regions 123a and 123b. And the second
The electrode 119a is provided in contact with 123a of the pair of second regions 123a and 123b via the opening 116a, and the third electrode 119b is provided in contact with 123b via the opening 116b. In addition, since the second electrode 119a and the third electrode 119b are in contact with the top surfaces of the pair of second regions 123a and 123b, the transistor 100 has a top gate structure and a top contact structure.

FIG. 1B is a cross-sectional view taken along line AB in the transistor 100. FIG. From Figure 1 (B),
The base insulating film 102 is provided over the substrate 101, and the oxide semiconductor film 103 including the first region 105 and the pair of second regions 123a and 123b is provided over the base insulating film 102. . The pair of second regions 123 a and 123 b are provided opposite to each other via the first region 105.

The gate insulating film 111 is provided over the oxide semiconductor film 103. A first electrode 113 overlapping with the first region 105 is provided over the gate insulating film 111.

An interlayer insulating film 117 is provided over the gate insulating film 111 and the first electrode 113.

As illustrated in FIG. 1B, the second electrode 119a and the third electrode 119b are a pair of second regions with openings 116a and 116b provided in the gate insulating film 111 and the interlayer insulating film 117, respectively. It is provided in contact with 123a and 123b. The gate insulating film 111 is
It is provided in contact with the first region 105 and the pair of second regions 123a and 123b.

Oxide semiconductor film 1 including a first region 105 and a pair of second regions 123a and 123b
03 is a metal oxide containing two or more elements selected from In, Ga, Sn and Zn. Note that the metal oxide has a band gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. Thus, by using a metal oxide with a wide band gap, the off-state current of the transistor 100 can be reduced.

In the transistor 100, the first region 105 functions as a channel formation region.

The first region 105 is the CAAC-OS described above. As mentioned above, CAAC-
OS is a non-single crystal, viewed from a direction perpendicular to the ab plane of the non-single crystal, having an atomic arrangement of a triangle or a hexagon, or an equilateral triangle or a regular hexagon, and from a direction perpendicular to the c axis In this case, it refers to an oxide semiconductor including a crystal part in which metal atoms are layered or metal atoms and oxygen atoms are arranged in layers.

In addition, although the CAAC-OS is not a single crystal, it is not formed only from amorphous. In addition, although the CAAC-OS includes a crystal part, in some cases the boundary between one crystal part and another crystal part can not be clearly distinguished.

Some of the oxygen constituting the CAAC-OS may be replaced by nitrogen. In addition, CAAC-OS
The c-axes of the individual crystal parts constituting the may be aligned in a predetermined direction (for example, a direction perpendicular to the surface of the substrate on which the CAAC-OS is formed, the surface of the CAAC-OS, the film surface, the interface, or the like). Alternatively, the normals of the ab planes of the individual crystal parts constituting the CAAC-OS are in a predetermined direction (eg, CAA
The substrate may be oriented in a direction perpendicular to the substrate surface where the C-OS is formed, the surface or the film surface of the CAAC-OS, the interface, or the like.

The CAAC-OS is a conductor, a semiconductor, or an insulator depending on its composition or the like. In addition, depending on the composition etc., it is transparent or opaque to visible light.

In addition, the hydrogen concentration in the first region 105 is less than 5 × 10 ¹⁸ cm ⁻³ , preferably 1 × 10 10
¹⁸ cm ⁻³ or less, more preferably 5 × 10 ¹⁷ cm ⁻³ or less, still more preferably 1 × 1
It is 0 ¹⁶ cm ^-3 or less. The first region 105 which is a channel formation region is a CAAC-OS.
And the hydrogen concentration is reduced, the transistor 100 before and after light irradiation and BT.
(Gate and thermal bias) Before and after a stress test, it can be said that the transistor has stable electrical characteristics and a high reliability because the fluctuation of the threshold voltage is small.

The pair of second regions 123a and 123b is an oxide semiconductor region containing a dopant and having a plurality of crystal parts. The pair of second regions 123a and 123b is doped with one or more elements selected from phosphorus, arsenic, antimony, and boron as a dopant.

Since the pair of second regions 123a and 123b is an oxide semiconductor region containing a dopant and having a plurality of crystal parts, the pair of second regions 123a and 123b are temporarily separated from the first region 105. Similarly, in the case of a CAAC-OS which does not contain a dopant (when all of the oxide semiconductor film 103 is a CAAC-OS which does not contain a dopant),
The conductivity is high. That is, the resistance component in the channel direction of the oxide semiconductor film 103 can be reduced, and the on-state current of the transistor 100 can be increased.

Therefore, the pair of second regions 123a and 123b has a conductivity of 0.1 S / cm or more and 1000 or more.
S / cm or less, preferably 10 S / cm or more and 1000 S / cm or less. However, when the conductivity is too low, the on-state current of the transistor 100 is reduced. When the dopant concentration is increased to increase the conductivity of the pair of second regions 123a and 123b,
Although the carrier density can be increased, if the dopant concentration is increased too much, the conductivity of the pair of second regions 123a and 123b may be reduced.

Therefore, the dopant concentration of the pair of second regions 123a, 123b is 5 × 10 ¹⁸ cm ⁻
It is preferable that it is ^three or more and 1 * 10 < ²² > cm < ^-3 > or less. In addition, in the step of adding a dopant in the manufacturing process of the transistor 100, the first electrode 113 functions as a mask,
The first region 105 and the pair of second regions 123a and 123b are formed in a self-aligned manner.

The pair of second regions 123 a and 123 b functions as at least a source region and a drain region in the transistor 100. By providing the pair of second regions 123 a and 123 b at both ends of the first region 105 in the channel formation region, the electric field applied to the first region 105 which is the channel formation region can be relaxed.

Specifically, the pair of second regions 123a and 123b is used as a first region 105 of the channel formation region.
By providing at the both ends, the effect of reducing the bending of the band edge in the channel formed in the first region 105 is shown. Therefore, in the transistor 100, the influence of shortening the channel length, such as the threshold voltage fluctuating in the negative direction, can be reduced.

Further, since the contact resistance between the pair of second regions 123a and 123b with the second electrode 119a and the third electrode 119b is reduced, the on-state current of the transistor 100 can be increased.

<Method for Manufacturing Transistor 100>
Next, a method for manufacturing the transistor 100 is described with reference to FIGS.

The substrate 101 is not particularly limited in material and the like, but needs to have at least heat resistance enough to withstand heat treatment to be performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate,
A sapphire substrate or the like may be used as the substrate 101. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element is provided on these substrates May be used as the substrate 101.

Alternatively, a flexible substrate may be used as the substrate 101. In the case of providing a transistor on a flexible substrate, the transistor may be manufactured directly on the flexible substrate, or after manufacturing the transistor on another substrate, this is peeled off and transferred to the flexible substrate. You may Note that in order to separate the transistor and transfer it to a flexible substrate, a region in which separation is easy is preferably provided between the other substrate and the transistor.

First, the base insulating film 102 is formed over the substrate 101. The base insulating film 102 is formed as a single layer structure or a stacked structure using the following materials.

As a material of the base insulating film 102, an oxide insulating film such as silicon oxide, gallium oxide, or aluminum oxide, a nitride insulating film such as silicon nitride or aluminum nitride, silicon oxynitride, or aluminum oxynitride Alternatively, an insulating film selected from silicon nitride oxide can be used. Note that the base insulating film 102 preferably contains oxygen in a portion in contact with the oxide semiconductor film 103 which is to be formed later. Note that "silicon nitride oxide" refers to a composition having a nitrogen content greater than oxygen as the composition, and "silicon oxynitride" refers to a composition having an oxygen content greater than nitrogen as the composition. Say.

An aluminum nitride film, an aluminum nitride oxide film, and a silicon nitride film have high thermal conductivity; thus, by using the base insulating film 102, the heat dissipation of the transistor 100 can be favorable.

Further, in manufacturing the transistor 100, the content of an alkali metal such as Li or Na is preferably reduced because it is an impurity. In the case where a glass substrate containing an impurity such as an alkali metal is used for the substrate 101, the nitride insulating film is preferably formed as the base insulating film 102 in order to prevent the penetration of the alkali metal.

The base insulating film 102 can be formed by a sputtering method, a CVD method, a coating method, or the like. Although the thickness of the base insulating film 102 is not limited, the thickness of the base insulating film 102 is preferably 50 nm or more. This is because the base insulating film 102 contains impurities (eg, L
This is because it is used to prevent the substrate 101 from being etched by the etching step in the manufacturing process of the transistor 100, in addition to the diffusion of alkali metals such as i and Na).

Since the base insulating film 102 preferably contains oxygen in a portion in contact with the oxide semiconductor film 103 to be formed later, a film from which oxygen is released by heating may be used as the base insulating film 102. Note that “oxygen is released by heating” means TDS (Thermal
In desorption spectroscopy (heated temperature desorption gas spectroscopy) analysis,
The amount of released oxygen converted to oxygen atoms is 1.0 × 10 ¹⁸ cm ⁻³ or more, preferably 3.0 ×
It means that it is 10 ²⁰ cm ^-3 or more.

Hereinafter, a method of quantifying the released amount of oxygen by converting it into an oxygen atom by TDS analysis will be described.

The amount of gas released upon TDS analysis is proportional to the integral value of the spectrum. Therefore, the amount of released gas can be calculated by using the integral value of the spectrum of the insulating film and the reference value of the standard sample. The reference value of the standard sample is the ratio of the density of atoms to the integral value of the spectrum of a sample containing a predetermined atom.

For example, from the results of TDS analysis of a silicon wafer containing hydrogen of a predetermined density, which is a standard sample, and the TDS analysis result of an insulating film, the amount of released oxygen molecules (N _O2 ) of the insulating film can be obtained by Equation 1. . Here, it is assumed that all of the spectra detected with a mass number of 32 obtained by TDS analysis are derived from molecular oxygen. There is CH ₃ OH as mass number 32 but it is not considered here as being unlikely to be present. Further, oxygen molecules containing an oxygen atom having a mass number of 17 and an oxygen atom having a mass number of 18, which are isotopes of oxygen atoms, are not considered because the abundance ratio in the natural world is extremely small.

N _H2 is a value obtained by converting the density of hydrogen molecules desorbed from the standard sample. S _H2 is an integral value of a spectrum when TDS analysis of a standard sample is performed. Here, the reference value of the standard sample is N
_{It is set to H2} / S _H2 . _SO2 is an integral value of the spectrum when TDS analysis of the insulating film is performed. α is a coefficient that affects the spectral intensity in TDS analysis. Japanese Patent Laid-Open No. 6-275697 can be referred to for the details of Formula 1. The numerical value of the amount of released oxygen mentioned above is a silicon wafer containing hydrogen atoms of 1 × 10 ¹⁶ cm ⁻³ as a standard sample, using a temperature rising desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. It is the numerical value measured using it.

In TDS analysis, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. In addition, since the above-mentioned alpha contains the ionization rate of an oxygen molecule, it can estimate also about the emitted amount of an oxygen atom by evaluating the emitted amount of an oxygen molecule.

Here, _NO2 is the amount of released oxygen molecules. In the insulating film, the amount of released oxygen when converted to oxygen atoms is twice the amount of released oxygen molecules.

As an example of a film which releases oxygen by heating, silicon oxide (SiO _x (x>
2) There is. The oxygen-excess silicon oxide (SiO _x (x> 2)) contains oxygen atoms per unit volume which is more than twice the number of silicon atoms. The number of silicon atoms and the number of oxygen atoms per unit volume are values measured by the Rutherford backscattering method.

With the use of a film from which oxygen is released by heating for the base insulating film 102, oxygen is supplied to the oxide semiconductor film 103 to be formed later, whereby interface states of the base insulating film 102 and the oxide semiconductor film 103 can be reduced. Therefore, charge that may be generated due to the operation of the transistor 100 can be prevented from being captured at the interface between the base insulating film 102 and the oxide semiconductor film 103, and the transistor 100 can be a transistor with less deterioration in electrical characteristics. Can.

Next, the oxide semiconductor film 130 which is a CAAC-OS is formed over the base insulating film 102 in all regions.

As a method for forming the oxide semiconductor film 130 which is a CAAC-OS in all the regions, there are, for example, the following two types of methods. (1) One method is a method in which the step of forming the oxide semiconductor film is performed once while heating the substrate, and (2) another method is twice the step of forming the oxide semiconductor film In each of the methods, heat treatment is performed after the oxide semiconductor film is formed.

First, the case where the oxide semiconductor film 130 is formed by the method (1) will be described.

The oxide semiconductor film 130 is formed over the base insulating film 102 while heating the substrate 101 (see FIG. 2A). Note that the oxide semiconductor film 130 may be formed by a sputtering method, a molecular beam epitaxy method, an atomic layer deposition method, or a pulsed laser deposition method. The thickness of the oxide semiconductor film 130 may be 10 nm to 100 nm, preferably 10 nm to 30 nm.

For the oxide semiconductor film 130, a metal oxide material containing two or more kinds selected from In, Ga, Zn, and Sn may be used. For example, In-Sn-Ga-Zn- which is a quaternary metal oxide
O-based materials, In-Ga-Zn-O-based materials that are ternary metal oxides, In-Sn-Z
n-O-based material, In-Al-Zn-O-based material, Sn-Ga-Zn-O-based material, Al
-Ga-Zn-O-based material, Sn-Al-Zn-O-based material, In-Zn-O-based material which is binary metal oxide, Sn-Zn-O-based material, Al- Zn-O based material, Zn-M
A g-O-based material, a Sn-Mg-O-based material, an In-Mg-O-based material, an In-Ga-O-based material, indium oxide, tin oxide, zinc oxide, or the like may be used. Here, for example,
In-Ga-Zn-O-based materials include indium (In), gallium (Ga), zinc (Z
It means an oxide having n), and the composition ratio thereof is not particularly limited. Also, In and Ga
And elements other than Zn may be contained. At this time, relative to the stoichiometry ratio of the oxide semiconductor film,
An excess of O is preferred. By making O excessively, generation of carriers due to oxygen vacancies in the oxide semiconductor film can be suppressed.

In the case of using an In-Ga-Zn-O-based material as the oxide semiconductor film 130, In, Ga,
And In ₂ O ₃ : Ga ₂ O ₃ : ZnO as an example of a metal oxide target containing Zn and Zn
Some have a composition ratio of 1: 1: 1 [molar ratio]. Furthermore, In ₂ O ₃ : Ga ₂
A target having a composition ratio of O ₃ : ZnO = 1: 1: 2 [molar ratio], In ₂ O ₃ : G
A target having a composition ratio of a ₂ O ₃ : ZnO = 1: 1: 4 [molar ratio], or In
A target having a composition ratio of ₂ O ₃ : Ga ₂ O ₃ : ZnO = 2: 1: 8 [molar ratio] can also be used.

Note that as an example, in the case of using an In-Zn-O-based material as the oxide semiconductor film 130,
In atomic ratio, In / Zn = 0.5 or more and 50 or less, preferably In / Zn = 1 or more and 20 or less, more preferably In / Zn = 1.5 or more and 15 or less. When the atomic ratio of In and Zn is in the above range, field-effect mobility of the transistor 100 can be improved. Here, when the atomic ratio of the compounds is In: Zn: O = X: Y: Z, it is preferable to set Z> 1.5X + Y.

As the oxide semiconductor film, a material represented by a chemical formula InMO ₃ (ZnO) _m (m> 0) may be used. Here, M represents one or more metal elements selected from Ga, Al, Mn and Co. For example, Ga, Ga and Al, Ga and Mn or Ga and Co may be used as M.

The temperature for heating the substrate 101 may be 150 ° C. or more and 450 ° C. or less, preferably 200 ° C. or more and 350 ° C. or less. Note that by raising the temperature at which the substrate 101 is heated at the time of formation of the oxide semiconductor film 130, CAAC-OS in which the ratio of the crystal part to the amorphous part is high can be obtained.

Next, the case where the oxide semiconductor film 130 is formed by the method (2) will be described.

A first oxide semiconductor film is formed over the base insulating film 102 while maintaining the substrate temperature at 200 ° C. to 400 ° C., and an atmosphere of nitrogen, oxygen, a rare gas, or dry air is used. Heat treatment is performed at 550 ° C. or more and less than the substrate strain point. By this heat treatment, c-axis-oriented crystals (including plate-like crystals) are formed in a region including the surface of the first oxide semiconductor film. Then, the second oxide semiconductor film is formed to be thicker than the first oxide semiconductor film. After that, heat treatment is performed again at 550 ° C. or more and the substrate strain point or less, and crystal growth is performed on the first oxide semiconductor film in which c-axis oriented crystals (including plate crystals) are formed in the region including the surface. Crystal growth of the second oxide semiconductor film upward as a seed of Note that for the first oxide semiconductor film and the second oxide semiconductor film, a metal oxide material that can be applied to the above-described oxide semiconductor film 130 may be used. Note that the first oxide semiconductor film is preferably formed to have a thickness of 1 nm to 10 nm.

The oxide semiconductor film 130 is formed by a sputtering method and either method (1) or method (2).
It is preferable to reduce the concentration of hydrogen contained in the oxide semiconductor film 130 as much as possible. In order to reduce the hydrogen concentration, high-purity rare gas (typically, argon), oxygen, or the like from which impurities such as hydrogen, water, hydroxyl, or hydride are removed as an atmosphere gas supplied into the processing chamber of the sputtering apparatus. And a mixed gas of a rare gas and oxygen as appropriate. Furthermore, the exhaust of the treatment chamber may be used in combination with a cryopump having a high water evacuation capacity and a sputter ion pump having a high hydrogen evacuation capacity.

By the above method, the oxide semiconductor film 130 in which the mixing of hydrogen is reduced can be formed. Note that even when using the above-described sputtering apparatus, the oxide semiconductor film 130 is formed to contain a large amount of nitrogen. For example, secondary ion mass spectrometry (SIMS: Seconda)
Oxide semiconductor film 13 measured by ry Ion Mass Spectrometry
The nitrogen concentration of 0 is less than 5 × 10 ¹⁸ cm ⁻³ .

The base insulating film 102 and the oxide semiconductor film 130 may be formed successively under vacuum. For example, after the impurity including hydrogen attached to the surface of the substrate 101 is removed by heat treatment or plasma treatment, the base insulating film 102 is formed without exposure to the air, and the oxide semiconductor is continuously exposed to the air. The film 130 may be formed. By doing this, the substrate 1
Reduce impurities containing hydrogen attached to the surface of the substrate 01, and the substrate 101 and the base insulating film 102.
Further, adhesion of atmospheric components to the interface between the base insulating film 102 and the oxide semiconductor film 130 can be suppressed. As a result, the transistor 100 with favorable electrical characteristics and high reliability can be manufactured.

When or after the oxide semiconductor film 130 is formed, charge may be generated due to oxygen vacancies in the oxide semiconductor film 130. In general, part of an oxygen vacancy in an oxide semiconductor serves as a donor to generate an electron which is a carrier. In other words, transistor 10
Even in 0, part of oxygen vacancies in the oxide semiconductor film 130 serves as donors, and electrons which are carriers are generated, whereby the threshold voltage of the transistor 100 is shifted in the negative direction. In the oxide semiconductor film 130, the generation of the electrons is remarkable in the oxygen vacancies generated in the vicinity of the interface between the oxide semiconductor film 130 and the base insulating film 102.

Therefore, after the oxide semiconductor film 130 is formed, first heat treatment is performed to form the oxide semiconductor film 13.
Form 1 (see FIG. 2 (B)).

The first heat treatment is performed using hydrogen from the oxide semiconductor film 130 (including water, a hydroxyl group, or a hydride).
In addition, part of oxygen contained in the base insulating film 102 is released, and oxygen is diffused in the oxide semiconductor film 130 and in the vicinity of the interface between the base insulating film 102 and the oxide semiconductor film 130. That is, the first heat treatment reduces the interface state between the base insulating film 102 and the oxide semiconductor film 130 and oxygen vacancies in the oxide semiconductor film 130, whereby the transistor 100 is completed.
The influence of carrier capture at the interface between the oxide semiconductor film 103 and the base insulating film 102 can be reduced. Thus, the first heat treatment can suppress variation in the threshold voltage of the transistor 100 in the negative direction.

Further, not only part of oxygen vacancies in the oxide semiconductor film 130 but also hydrogen in the oxide semiconductor film 130 also serves as a donor to generate electrons as carriers. By the first heat treatment, the hydrogen concentration in the oxide semiconductor film 130 is reduced, so that the oxide semiconductor film 131 is highly purified. The hydrogen concentration of the oxide semiconductor film 131 is less than 5 × 10 ¹⁸ cm ⁻³ , preferably 1 × 10 3.
¹⁸ cm ⁻³ or less, more preferably 5 × 10 ¹⁷ cm ⁻³ or less, still more preferably 1 × 1
It is 0 ¹⁶ cm ^-3 or less. Note that the concentration of hydrogen in the oxide semiconductor film 131 is determined by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometr).
y) is measured.

By using the oxide semiconductor film 131 in which the hydrogen concentration is sufficiently reduced and highly purified by the first heat treatment and sufficient oxygen is supplied to reduce defect levels due to oxygen vacancies, The off current of the transistor 100 can be reduced. Specifically, room temperature (25
Off current (in this case, the value per unit channel width (1 μm)) is 100 zA (1
zA (zept ampere) is 1 × 10 ⁻²¹ A) or less, preferably 10 zA or less. Note that since an alkali metal such as Li or Na is an impurity, the content is preferably reduced, and the content is 2 × 10 ¹⁶ cm ⁻³ or less, preferably 1 × 10 ¹⁵ or less in the oxide semiconductor film 131.
It is preferable to set it as the density ^| concentration of cm < ^-3 > or less. Furthermore, since the alkaline earth metal is also an impurity, it is preferable to reduce the content.

The temperature of the first heat treatment is 150 ° C. or more and less than the substrate strain point temperature, preferably 250 ° C. or more.
The heating is performed at 50 ° C. or less, more preferably 300 ° C. to 450 ° C., in an oxidizing atmosphere or an inert atmosphere. Here, the oxidizing atmosphere refers to an atmosphere containing 10 ppm or more of an oxidizing gas such as oxygen, ozone, or nitrogen oxide. In addition, the inert atmosphere is an atmosphere containing less than 10 ppm of the aforementioned oxidizing gas, and additionally filled with nitrogen or a rare gas. Treatment time is 3 minutes to 24 hours. Heat treatment for more than 24 hours is not preferable because it causes a decrease in productivity.

There is no particular limitation on the heating device used for the first heat treatment, and a device for heating the object by heat conduction or heat radiation from a heating element such as a resistance heating element may be provided. For example, electric furnace, GRTA (Gas Rapid Thermal Anneal) apparatus, LRTA
RTA (rapid rapid thermal annealing) equipment
Thermal Anneal) equipment can be used. The LRTA device is based on the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps and high pressure mercury lamps.
It is an apparatus for heating an object to be treated. The GRTA apparatus is an apparatus that performs heat treatment using a high temperature gas.

Next, a resist mask is formed over the oxide semiconductor film 131 by a photolithography step, and the oxide semiconductor film 131 is etched into a desired shape using the resist mask to form an island-shaped oxide semiconductor film 132. (See FIG. 2C). Note that as the resist mask, an inkjet method, a printing method, or the like can be used as appropriate in addition to the photolithography step. The etching is preferably performed so that an end portion of the island-shaped oxide semiconductor film 132 has a tapered shape. By forming the end portion of the island-shaped oxide semiconductor film 132 into a tapered shape, coverage with a film to be formed can be improved in manufacturing the transistor 100 in and after this step, and breakage of the film can be prevented. can do. The tapered shape can be formed by etching while retracting the resist mask.

The etching process in this step can be performed by dry etching or wet etching, and these may be performed in combination. As an etching solution for wet etching, a mixed solution of phosphoric acid, acetic acid and nitric acid, ammonia peroxide (31 wt% hydrogen peroxide solution: 2)
8% by weight ammonia water: water = 5: 2: 2 (volume ratio) or the like can be used. Also,
You may use ITO07N (made by Kanto Chemical Co., Ltd.).

As an etching gas used for dry etching, a gas containing chlorine (chlorinated gas such as chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), carbon tetrachloride (
CCl ₄ ) and the like are preferred.

In addition, a gas containing fluorine (fluorinated gas such as carbon tetrafluoride (CF ₄ ), sulfur hexafluoride (S
F ₆ ), nitrogen trifluoride (NF ₃ ), trifluoromethane (CHF ₃ ), etc., hydrogen bromide (H
It is possible to use Br), oxygen (O ₂ ), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, or the like.

As dry etching, parallel plate type RIE (Reactive Ion Etchi) is used.
and the ICP (Inductively Coupled Plasma) etching method can be used. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the substrate-side electrode,
Adjust the electrode temperature etc. of the substrate side appropriately.

Next, the gate insulating film 111 is formed over the oxide semiconductor film 132. Gate insulating film 111
A single layer structure or a stacked structure is formed using a material that can be applied to the base insulating film 102. In addition, the thickness of the gate insulating film 111 is 1 nm or more and 300 nm or less, more preferably 5
The thickness is preferably in the range of nm to 50 nm.

In addition, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x
> 0, y> 0)), nitrogen-doped hafnium silicate (HfSi _x O _y N _z (x>
0, y> 0, z> 0)), hafnium aluminate (HfAl _x O _y (x> 0, y> 0)
, Etc. can be used. Since the high-k material has a high dielectric constant, for example, the physical thickness of the gate insulating film can be increased while having the same gate insulating film capacitance as when using a silicon oxide film as the gate insulating film. it can. Therefore, the gate leak current can be reduced. Note that the high-k material may be used as the gate insulating film 111 as a single-layer structure, or may be stacked with a material applicable to the base insulating film 102.

Note that since oxygen is preferably contained in a portion in contact with the oxide semiconductor film 132, the gate insulating film 111 is preferably an oxide insulating film or a film which releases oxygen by heating.

After the gate insulating film 111 is formed, second heat treatment is performed to form an island-shaped oxide semiconductor film 140.
(See FIG. 2D). The second heat treatment is performed using hydrogen from the oxide semiconductor film 132 (
Water, a hydroxyl group, or a hydride) and a part of oxygen contained in the base insulating film 102 and the gate insulating film 111, and the base insulating film 10 in the oxide semiconductor film 132.
In the vicinity of the interface between the oxide semiconductor film 132 and the oxide semiconductor film 132 and the oxide semiconductor film 132 and the gate insulating film 1
Oxygen can be diffused in the vicinity of the interface with the element 11. That is, in the second heat treatment, oxygen vacancies in the oxide semiconductor film 132, an interface state between the base insulating film 102 and the oxide semiconductor film 132, and an interface state between the oxide semiconductor film 132 and the gate insulating film 111 Can be reduced.

The conditions and apparatus for the second heat treatment may be conditions and apparatuses applicable to the first heat treatment as appropriate.

Note that the second heat treatment may be performed concurrently with the first heat treatment, but by performing both the first heat treatment and the second heat treatment, the interface state and the oxygen deficiency are efficiently performed. Can be reduced.

Next, a conductive film 112 is formed over the gate insulating film 111 using a conductive material applicable to the first electrode 113 (see FIG. 3A). The thickness of the conductive film 112 can be determined as appropriate in consideration of the electrical resistance of the following conductive material and the time taken for the manufacturing process. For example, 10 nm
It may be formed to be 500 nm or less.

Conductive materials applicable to the first electrode 113 include aluminum, titanium, chromium, nickel,
A single metal consisting of copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing this as a main component. The conductive film 112 is formed as a single layer structure or a stacked structure using the conductive material. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a tungsten film, a copper film on a copper-magnesium-aluminum alloy film There is a two-layer structure to be stacked, a titanium film, and a three-layer structure in which an aluminum film is stacked on the titanium film and a titanium film is formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

Next, a resist mask is formed over the conductive film 112 by a photolithography step, and the conductive film 112 is etched into a desired shape using the resist mask to form a first electrode 113 (FIG. 3B). reference). The first electrode 113 functions at least as a gate electrode,
The gate wiring may also function. Note that as the resist mask, an inkjet method, a printing method, or the like can be used as appropriate in addition to the photolithography step, and the same dry etching or wet etching as in processing the oxide semiconductor film 130 can be used as appropriate for the etching. Can.

The conductive film to be the gate insulating film 111 and the first electrode 113 is preferably formed in succession without exposure to the air.

In addition, In—Ga—Zn— containing nitrogen is provided between the first electrode 113 and the gate insulating film 111.
O film, In-Sn-O film containing nitrogen, In-Ga-O film containing nitrogen, I containing nitrogen
n-Zn-O film, Sn-O film containing nitrogen, In-O film containing nitrogen, metal nitride film (I
It is preferable to provide nN, ZnN, etc.). These films are 5 eV or more, preferably 5.
The transistor 100 can have a work function of 5 eV or more, can have a positive threshold voltage in the electrical characteristics of the transistor 100, and can be a so-called normally-off transistor. For example, in the case of using an In—Ga—Zn—O film containing nitrogen, a nitrogen concentration higher than at least the oxide semiconductor film 140, specifically, an In—Ga—Zn— film having a concentration of 7 atomic% or more
Use an O membrane.

Next, treatment is performed to add the dopant 150 to the oxide semiconductor film 140 (see FIG. 3C).

The dopant 150 to be added is a Group 15 element or boron, specifically one or more selected from any of phosphorus, arsenic, and antimony and boron. Further, as a method for adding the dopant 150 to the oxide semiconductor film 140, an ion doping method or an ion implantation method can be used.

Dopant 1 by using ion doping or ion implantation
The addition depth (addition area) of 50 can be easily controlled, and the dopant semiconductor
It is possible to add 0 precisely. In addition, when adding the dopant 150 by an ion doping method or an ion implantation method, the heating may be performed while heating the substrate 101.

Note that the process of adding the dopant 150 to the oxide semiconductor film 140 may be performed plural times. In the case where the oxide semiconductor film 140 is subjected to the process of adding the dopant 150 a plurality of times, the dopant 150 may be the same element in all the plurality of times, or may be changed for each process.

When the dopant 150 is added to the oxide semiconductor film 140, the first electrode 113 functions as a mask, and the dopant 150 is not added to the oxide semiconductor film 140 in a region overlapping with the first electrode 113; The first region 105 is formed.

Further, in the region to which the dopant 150 is added, the crystallinity is reduced by the damage of the addition of the dopant 150, and the region becomes an amorphous region. By adjusting the amount of addition of the dopant 150 or the like, the amount of damage can be reduced and the semiconductor layer can be formed so as not to be a complete amorphous region. That is, the region to which the dopant 150 is added is a region in which the proportion of amorphous regions is higher than at least the first region 105. It is preferable not to form a completely amorphous region because crystallization by the third heat treatment to be performed next is easily performed.

Next, after the dopant 150 is added, third heat treatment is performed. By performing the third heat treatment, the region to which the dopant 150 is added can be a pair of second regions 123 a and 123 b which are oxide semiconductor regions each including a dopant and having a plurality of crystal parts. Yes (see FIG. 3 (D)).

The pair of second regions 123a and 123b function as a source region and a drain region. Further, an oxide semiconductor region having a plurality of crystal parts which is a pair of second regions 123 a and 123 b is different from the CAAC-OS which is the first region 105. Note that the crystallinity of the CAAC-OS that is the first region 105 may be improved by the third heat treatment.

The temperature of the third heat treatment is higher than or equal to 450 ° C. and lower than the substrate strain point temperature, preferably higher than or equal to 650 ° C. and lower than the substrate strain point temperature. Here, the oxidizing atmosphere refers to an atmosphere containing 10 ppm or more of an oxidizing gas such as oxygen, ozone, or nitrogen oxide. In addition, the inert atmosphere is an atmosphere containing less than 10 ppm of the aforementioned oxidizing gas, and additionally filled with nitrogen or a rare gas. The treatment time is 1 hour to 24 hours. Heat treatment for more than 24 hours is not preferable because it causes a decrease in productivity.

As a heating device used for the third heat treatment, an apparatus applicable to the first heat treatment and the second heat treatment can be used.

Thus, the dopant 150 is used as the oxide semiconductor film 14 with the first electrode 113 as a mask.
The first region 105 serving as a channel formation region and the pair of second regions 123a and 123b serving as a source region and a drain region are self-aligned by addition to 0 and subsequent third heat treatment. It can be formed into

Next, an insulating film to be the interlayer insulating film 117 is formed over the gate insulating film 111 and the first electrode 113, and a resist mask is formed over the insulating film to be the interlayer insulating film 117 by photolithography. Etching is performed using a resist mask to form openings 116a and 116b.
(See FIG. 4A). Note that as the resist mask, an inkjet method, a printing method, or the like can be used as appropriate in addition to the photolithography step, and the same dry etching or wet etching as in processing the oxide semiconductor film 130 can be used as appropriate for the etching. Can.

The interlayer insulating film 117 may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or a silicon nitride film by a sputtering method, a CVD method, or the like. At this time, as the interlayer insulating film 117, a film which hardly releases oxygen by heating is preferably used. This is to prevent the conductivity of the pair of second regions 123a and 123b from being reduced. Specifically, a film may be formed by mixing silane gas as a main material and a suitable source gas from nitrogen oxide gas, nitrogen gas, hydrogen gas and a rare gas by a CVD method. Further, the substrate temperature may be 300 ° C. or more and 550 ° C. or less. By using the CVD method, the film can be hardly released of oxygen by heating.

Next, a conductive film is formed to be in contact with the pair of second regions 123a and 123b through the openings 116a and 116b, a resist mask is formed over the conductive film by a photolithography step, and the resist mask is formed. The conductive film is etched to form the second electrode 119a and the third electrode 119b (see FIG. 4B). Note that the second electrode 119 a and the third electrode 119 b can be formed in the same manner as the first electrode 113.

The second electrode 119a and the third electrode 119b function at least as a source electrode and a drain electrode, respectively, and also function as a source wiring and a drain wiring.

Thus, the transistor 100 can be manufactured.

<Variation 1 of Transistor 100>
In addition, by performing the third heat treatment at a temperature higher than or equal to 550 ° C. and lower than the strain point temperature of the substrate and in an oxidizing atmosphere, the dopant 150 is included in the pair of second regions 123 a and 123 b and a plurality of crystal parts The non-single-crystal oxide semiconductor regions 107a and 107b can be formed over the oxide semiconductor regions 109a and 109b, respectively, which include the dopant 150 and a c-axis aligned crystal part.

A top view of the transistor 160 completed in this case is illustrated in FIG. Furthermore, a cross-sectional view taken along line A-B in FIG. 5A is shown in FIG.

A pair of second regions 123a and 123b of the transistor 160 includes the dopant 150 and is a non-single-crystal oxide semiconductor region 107a and 107b having a c-axis aligned crystal part.
And the dopant 150, and the oxide semiconductor region 109a having a plurality of crystal parts
, 109b (see FIG. 5B). Note that the oxide semiconductor region 107a,
The dopant concentrations of 107 b and the oxide semiconductor regions 109 a and 109 b are the same.

The second electrode 119a and the third electrode 119b are in contact with the oxide semiconductor regions 107a and 107b through the openings 116a and 116b. The other configuration of the transistor 160 is similar to that of the transistor 100.

In addition, when the third heat treatment is performed for one hour under the above conditions, the oxide semiconductor region 107a,
107 b is a pair of second regions 123 a and 123 b from the top surface of the pair of second regions 123 a
, 123b in the direction of the lower surface, at least 2 nm. Further, the oxide semiconductor regions 107a and 107b can be formed thicker by lengthening the time of the third heat treatment performed under the above conditions.

In the transistor 100 and the transistor 160, the pair of second regions 123a,
The configuration of the transistor 100 is different from that of the transistor
The same applies to 0.

The transistor 160 also has an effect of reducing bending of the band edge in the channel formed in the first region 105, and the transistor 160 is generated by shortening the channel length, such as the threshold voltage fluctuating in the negative direction. The impact can be reduced. Further, in the pair of second regions 123a and 123b, the contact resistance with the second electrode 119a and the third electrode 119b and the resistance component in the channel direction of the pair of second regions 123a and 123b are reduced. Thus, the on-state current of the transistor 160 can be increased.

In the transistor 160, since the pair of second regions 123a and 123b is the oxide semiconductor regions 107a and 107b and the oxide semiconductor regions 109a and 109b, the pair of second regions 123a and 123b is temporarily amorphous. It is considered that the fluctuation of the threshold voltage before and after light irradiation and before and after the BT (gate and thermal bias) stress test is smaller than in the case of the above region, and the transistor is highly reliable.

<Modification 2 of Transistor 100>
When the first electrode 113 in the method for manufacturing the transistor 100 is formed, the gate insulating film 111 is formed.
At the same time, the gate insulating film 121 can be provided only on the first region 105 of the oxide semiconductor film 103 by etching.

A top view of the transistor 170 completed in this case is illustrated in FIG. Further, a cross-sectional view taken along a line AB in FIG. 6A is shown in FIG. The top surface structure of the transistor 170 is similar to that of the transistor 100 and is a top gate and top contact transistor.

Further, only the shape of the gate insulating film 111 is different between the transistor 100 and the transistor 170, and the description of the transistor 100 is also applied to the transistor 170.

The transistor 170 also has an effect of reducing the bending of the band edge in the channel formed in the first region 105, and the transistor 170 is generated by shortening the channel length, such as the threshold voltage fluctuating in the negative direction. The impact can be reduced. Further, in the pair of second regions 123a and 123b, the contact resistance with the second electrode 119a and the third electrode 119b and the resistance component in the channel direction of the pair of second regions 123a and 123b are reduced. Thus, the on-state current of the transistor 170 can be increased.

In the case where the pair of second regions 123a and 123b is an amorphous region, the transistor 170 is an oxide semiconductor region in which the pair of second regions 123a and 123b is a plurality of crystal parts. In this transistor, the fluctuation of the threshold voltage before and after light irradiation and before and after the BT (gate and thermal bias) stress test is considered to be small, and the transistor is highly reliable.

A method for manufacturing the transistor 170 is described with reference to FIGS. 3, 7, and 8. The transistor 170 is similar to the transistor 100 up to the step of forming the conductive film 112 (see FIG. 3A).

After the conductive film 112 is formed, etching is performed on the conductive film 112 and the gate insulating film 111 so that the conductive film 112 is overlapped only over the first region 105 of the first electrode 113 and the oxide semiconductor film 103 to be formed later. The gate insulating film 121 can be formed (see FIG. 7A).

In addition, since the gate insulating film 121 is in contact with only the first region 105, the oxide semiconductor film 1 can be formed.
It is not provided along the 40 shapes (steps). In other words, the gate insulating film 121 has no portion which passes over the step of the oxide semiconductor film 140. Therefore, also in the completed transistor 170, the gate insulating film 121 does not have a portion which passes over the steps of the oxide semiconductor film 103; therefore, leakage current due to disconnection or the like of the gate insulating film 121 is reduced. The withstand voltage of the insulating film 121 can be increased. Therefore, the gate insulating film 121
Alternatively, the transistor 170 can be operated even when it is thinned to about 5 nm. Note that by thinning the gate insulating film 121, an influence caused by shortening the channel length can be reduced and the operation speed of the transistor can be increased.

Further, in the transistor 170, since there is no portion where the gate insulating film 121 passes over the step, there is almost no parasitic capacitance generated between the first electrode 113 and the pair of second regions 123a and 123b. Therefore, even if the transistor 170 reduces the channel length,
Variations in threshold voltage can be reduced.

After that, the transistor 170 can be formed by performing a process similar to that of the transistor 100. Note that the process in which the dopant 150 is added in the transistor 170 is different from that in the transistor 100, and the oxide semiconductor film 14 is formed using the first electrode 113 as a mask
It will be added in a state where a part of 0 is exposed (see FIG. 7 (B)).

When the dopant 150 is added in a state where part of the oxide semiconductor film 140 is exposed as in the transistor 170, a method other than the ion doping method or the ion implantation method can be used as a method of adding the dopant 150 . For example, plasma is generated in a gas atmosphere containing an element to be added, and an additive (here, the oxide semiconductor film 1
40) plasma treatment for irradiating the plasma. As an apparatus for generating the plasma, a dry etching apparatus, a plasma CVD apparatus, a high density plasma CVD apparatus, or the like can be used. Further, the plasma treatment may be performed while heating the substrate 101.

In the transistor 170, the third heat treatment performed after the addition of the dopant 150 is performed at a temperature higher than or equal to 550 ° C. and lower than the strain point temperature of the substrate and in an oxidizing atmosphere; A pair of second regions 123a and 123b in which non-single-crystal oxide semiconductor regions 107a and 107b including a dopant portion 150 and a c-axis-oriented crystal portion are provided over the oxide semiconductor regions 109a and 109b. Can be formed (see FIG. 8). Note that each reference numeral in FIG. 8 indicates the transistor 100 (see FIG. 1),
This corresponds to the reference numerals of the transistor 160 (see FIG. 5) and the transistor 170 (see FIG. 6).

As described above, one embodiment of the disclosed invention can solve the problems associated with miniaturization, and as a result, the transistor size can be sufficiently reduced. By sufficiently reducing the size of the transistor, the area occupied by the semiconductor device can be reduced, and the number of semiconductor devices can be increased. Thereby, the manufacturing cost per semiconductor device is suppressed. In addition, since the semiconductor device is miniaturized while maintaining the same function, when the size is made to be the same, it is possible to realize a semiconductor device with a further enhanced function. In addition, effects such as speeding up of operation and reduction of power consumption can be obtained by reducing the channel length. That is, according to one embodiment of the disclosed invention, miniaturization of a transistor including an oxide semiconductor can be achieved, and thus various effects can be obtained. Note that this embodiment can be combined with any of the other embodiments and examples as appropriate.

Second Embodiment
In this embodiment, a structure and a manufacturing method of the transistor 200 which is another embodiment of the present invention will be described with reference to FIGS. In the transistor 200, compared with the transistor 100 described in Embodiment 1, the sidewall insulating film 215 is provided on the end face of the first electrode 113, and the first region 105 and the pair of the oxide semiconductor film 103 are formed. A difference is that a pair of third regions 223a and 223b is provided between the second regions 123a and 123b.

Further, since the transistor 200 is another embodiment of the present invention, the contents described in Embodiment 1 are also applied to this embodiment.

<Structure and Features of Transistor 200>
FIG. 9A is a top view of the transistor 200. FIG. Note that in FIG. 9A, the base insulating film 102, the gate insulating film 111, and the interlayer insulating film 117 are not shown for convenience.

From FIG. 9A, the first electrode 113 includes a first region 105 (not shown), a pair of second regions 123a and 123b, and a pair of third regions 223a and 223b (not shown). And the oxide semiconductor film 103 including the A sidewall insulating film 215 is provided on the side surface of the first electrode 113. The second electrode 119a and the third electrode 119b are provided over the pair of second regions 123a and 123b via the openings 116a and 116b. In addition, the second electrode 119 a and the third electrode 119 b are a pair of second regions 12.
It is in contact with the upper surfaces of 3a and 123b. The transistor 200 is a top gate structure and a top contact structure transistor.

FIG. 9B is a cross-sectional view taken along line AB in the transistor 200. FIG. From FIG. 9 (B),
The base insulating film 102 is provided over the substrate 101, and the first region 105, the pair of second regions 123 a and 123 b, and the pair of third regions 223 a and 22 are provided over the base insulating film 102.
An oxide semiconductor film 103 including 3b is provided. A pair of second regions 123a, 123
b is provided opposite to each other via the first area 105. A pair of third regions 223a, 2
The 23 b is provided between the first region 105 and the pair of second regions 123 a and 123 b.

The gate insulating film 111 is provided over the oxide semiconductor film 103. A first electrode 113 overlapping with the first region 105 is provided over the gate insulating film 111. First electrode 11
Sidewall insulating films 215 are provided in contact with both side surfaces of 3.

An interlayer insulating film 117 is provided over the gate insulating film 111, the first electrode 113, and the sidewall insulating film 215.

The second electrode 119 a and the third electrode 119 b are provided in contact with the pair of second regions 123 a and 123 b through the openings 116 a and 116 b provided in the interlayer insulating film 117. Note that the gate insulating film 111 includes the first region 105 and the pair of second regions 123 a and 12.
It is in contact with 3 b and the pair of third regions 223 a, 223 b.

The ends of the second electrode 119a and the third electrode 119b may be tapered, but
The end of the first electrode 113 preferably has a vertical shape. The sidewall insulating film 215 is formed by forming an end portion of the first electrode 113 in a vertical shape, forming an insulating film to be the sidewall insulating film 215 over the first electrode 113, and performing etching with high anisotropy. It is because it can form.

Further, although the details will be described later, according to FIGS. 9A and 9B, the pair of third regions 223a is described.
223 b correspond to a region where the oxide semiconductor film 103 overlaps with the sidewall insulating film 215. The sidewall insulating film 215 has a curved shape at least in part except the side surface of the first electrode 113 and the region in contact with the gate insulating film 111.

The oxide semiconductor film 103 is a metal oxide containing two or more elements selected from In, Ga, Sn, and Zn as in Embodiment 1, and a transistor with a wide band gap can be used as a transistor. The off current of 200 can be reduced.

In the transistor 200, the first region 105 functions as a channel formation region, is a CAAC-OS, and has a reduced concentration of hydrogen. Therefore, the transistor 200 has stable electric characteristics and can be said to be a highly reliable transistor before and after light irradiation and before and after a BT (gate and thermal bias) stress test because the variation of the threshold voltage is small.

A pair of second regions 123a and 123b is the same as that in Embodiment 1, and a pair of second regions 123a and 123b does not contain a dopant similarly to the first region 105.
—OS (when the oxide semiconductor film 103 does not contain any dopant;
The conductivity is higher than in the case of OS). In addition, the pair of third regions 223a and 223b
Also in the second embodiment, a dopant is contained similarly to the pair of second regions 123a and 123b, and the conductivity is high. That is, the resistance component in the channel direction of the oxide semiconductor film 103 is reduced, and the on-state current of the transistor 200 can be increased.

In the transistor 200, the conductivity and the dopant concentration of the pair of second regions 123a and 123b and the pair of third regions 223a and 223b are in the same range as in Embodiment 1, and the dopant concentration is excessively increased. As a result, the on-state current of the transistor 200 is reduced.

Thus, a pair of second regions 123a, 123b and a pair of third regions 223a, 223
The dopant concentration of b is preferably 5 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. Furthermore, the dopant concentration of the pair of second regions 123a and 123b is higher than the dopant concentration of the pair of third regions 223a and 223b. Specifically, the dopant concentration of the pair of second regions 123a and 123b is 5 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²² cm 2
And ^-3, a pair of third regions 223a, the dopant concentration of 223b is, 5 × ^{10 18}
preferably less than cm ^-3 to 5 × ¹⁰ 21 ^{cm -3.} In addition, the difference between the dopant concentrations can be obtained because the sidewall insulating film 215 is provided in the transistor 200.
It is self-aligned in the step of adding the dopant.

The transistor 200 is a second region 123 of the pair of second regions 123a and 123b.
The third region 22 of the pair of third regions 223a and 223b between a and the first region 105
By providing the third region 223 b between the second region 123 b and the first region 105, the electric field applied to the first region 105 can be relaxed. The pair of second regions 123a and 123b function as a source region and a drain region. In addition, the pair of third regions 223a and 223b function as an electric field relaxation region.

Specifically, of the pair of second regions 123a and 123b, the third region 223a of the pair of third regions 223a and 223b is interposed between the second region 123a and the first region 105;
By providing the third region 223b between the first region 123b and the first region 105,
There is almost no band edge bending in the channel formed in the first region 105.
Thus, the transistor 200 can reduce the influence of shortening the channel length, such as the threshold voltage fluctuating in the negative direction.

Further, since the contact resistance between the pair of second regions 123a and 123b with the second electrode 119a and the third electrode 119b is reduced, the on-state current of the transistor 200 can be increased.

<Method for Manufacturing Transistor 200>
Next, a method for manufacturing the transistor 200 will be described with reference to FIGS.

In the method for manufacturing the transistor 200, the step of forming the oxide semiconductor film 140 in which oxygen is diffused and the hydrogen concentration is sufficiently reduced, and the gate insulating film 111 (step corresponding to FIG. 2D) The steps up to the step of forming the conductive film 112 using the conductive material applicable to the first electrode 113 over the oxide semiconductor film 140 (the step corresponding to FIG. 3A) are the same as the transistor 100; Can be referred to.

Next, a photolithography step is performed to form a resist mask over the conductive film 112 and etching is performed using the resist mask to form a first electrode 113 (see FIG. 10A). The etching is preferably performed with high anisotropy so that the end of the first electrode 113 has a vertical shape as described above. As etching conditions with high anisotropy, it is preferable that the selectivity of the conductive film 112 with respect to the resist mask be extremely high.

Next, treatment for adding the dopant 150 (first dopant addition treatment) is performed on the oxide semiconductor film 140 (see FIG. 10B). In the first dopant addition process, the type of the dopant 150 (element to be added) and the method of adding the dopant 150 are the same as in the first embodiment.

In the first dopant addition treatment, the first electrode 113 functions as a mask, and the dopant 150 passes through the gate insulating film 111 and is added to the oxide semiconductor film 140. Thus, the oxide semiconductor regions 214a and 214b to which the dopant 150 is added are formed.
Further, since the oxide semiconductor film 140 is not added to a region overlapping with the first electrode 113, the first region 105 is formed.

Next, sidewall insulating films 215 are formed. The sidewall insulating film 215 is formed of any of the insulating films described in the base insulating film 102 and the gate insulating film 111.

The gate insulating film 111 is provided in contact with the transistor 200 in any of the first region 105, the pair of second regions 123a and 123b, and the pair of third regions 223a and 223b. In order to form such a structure, the gate insulating film 111 and the sidewall insulating film 215 may be insulating films having different etching rates. In this manner, the gate insulating film 111 can function as an etching stopper when the sidewall insulating film 215 is formed. By using the gate insulating film 111 as an etching stopper, excessive etching of the oxide semiconductor film 140 can be suppressed. Furthermore, the end point (end point) of etching when forming the sidewall insulating film 215 can be easily detected. In addition, by causing the gate insulating film 111 to function as an etching stopper, the width of the sidewall insulating film 215 (the sidewall insulating film 2 in FIG.
Control of the width of the portion where 15 is in contact with the gate insulating film 111 is facilitated. The range of the pair of third regions 223 a and 223 b is determined corresponding to the width of the sidewall insulating film 215. By increasing the range of the pair of third regions 223a and 223b, the electric field applied to the first region 105 which is the channel formation region can be reduced accordingly.

First, the insulating film 114 to be the sidewall insulating film 215 is formed over the gate insulating film 111 and the first electrode 113 (see FIG. 10C). The insulating film 114 is a base insulating film 102.
Alternatively, the gate insulating film 111 can be formed in a manner similar to that of the gate insulating film 111 and is preferably any of the nitride insulating films described in Embodiment 1. The thickness of the insulating film 114 is not particularly limited, but may be appropriately selected in consideration of the coverage with the shape of the first electrode 113.

By etching the insulating film 114, a sidewall insulating film 215 is formed. The etching is etching with high anisotropy, and the sidewall insulating film 215 is an insulating film 1.
By performing an etching process with high anisotropy to 14, it is possible to form self-alignment. Here, dry etching is preferable as etching with high anisotropy. For example, trifluoromethane (CHF ₃ ) or octafluorocyclobutane (CHF ₃ ) is used as an etching gas.
A gas containing fluorine such as C ₄ F ₈ ) or tetrafluoromethane (CF ₄ ) can be used, and a rare gas such as helium (He) or argon (Ar) or hydrogen (H ₂ ) may be added. . Furthermore, it is preferable to use a reactive ion etching method (RIE method) which applies a high frequency voltage to the substrate as dry etching.

Further, since the dopant concentration of the pair of third regions 223a and 223b formed later corresponds to the thickness of the sidewall insulating film 215, the pair of third regions 223a and 223b is formed.
The thickness of the sidewall insulating film 215, and further, the thickness of the first electrode 113 may be determined so that the dopant concentration of the above becomes the above-mentioned value. The side wall insulating film 21 here
The thickness 5 means from the surface in contact with the gate insulating film 111 to the top of the surface in contact with the first electrode 113 in the sidewall insulating film 215.

The range of the pair of third regions 223 a and 223 b is determined corresponding to the width of the sidewall insulating film 215, and the width of the sidewall insulating film 215 also corresponds to the thickness of the first electrode 113. Thus, the thickness of the first electrode 113 may be determined so that the range of the pair of third regions 223a and 223b is a desired range.

Next, a treatment (second dopant addition treatment) of adding the dopant 150 to the oxide semiconductor regions 214a and 214b is performed (see FIG. 10D). Note that the type of the dopant 150 (element to be added) and the method of adding the dopant 150 are the same as in the first embodiment.

Also in the second dopant addition treatment, the first electrode 113 functions as a mask, and the dopant 150 passes through the gate insulating film 111 and the sidewall insulating film 215, and is added to the oxide semiconductor regions 214a and 214b. And the dopant 150 to be added is
The region added through the gate insulating film 111 and the sidewall insulating film 215 is smaller than the region added through only the gate insulating film 111. Therefore, the dopant concentration difference can be provided in self alignment in the oxide semiconductor regions 214a and 214b.

Also in this embodiment, the region to which the dopant 150 is added is reduced in crystallinity by damage due to the addition of the dopant 150 and becomes an amorphous region. By adjusting the amount of addition of the dopant 150 or the like, the amount of damage can be reduced and the semiconductor layer can be formed so as not to be a complete amorphous region. That is, the region to which the dopant 150 is added is a region in which the proportion of amorphous regions is higher than at least the first region 105. It is preferable not to form a completely amorphous region because crystallization by the third heat treatment to be performed next is easily performed.

Next, third heat treatment is performed in a similar manner to the manufacturing process of the transistor 100, and
A pair of second regions 123a and 123b and a pair of third regions 223a and 223 which are oxide semiconductor regions containing a dopant and having a plurality of crystal parts, in which 0 is added are included.
It can be b (see FIG. 10E). Note that the heating condition and the heating device of the third heat treatment are the same as those described in Embodiment 1.

Thus, the dopant 150 is used as the oxide semiconductor film 14 with the first electrode 113 as a mask.
After the third heat treatment is performed, a first region 105 which is to be a channel formation region, a pair of second regions 123a and 123b which are to be a source region and a drain region, and an electric field relaxation region are added. The pair of third regions 223a and 223b can be formed in a self-aligned manner.

Thereafter, the interlayer insulating film 117 is formed, and the openings 116 a and 116 b are formed in the gate insulating film 111 and the interlayer insulating film 117 in the same manner as the manufacturing process of the transistor 100.
and a second electrode 119a in contact with the pair of second regions 123a and 123b through 116b.
And the third electrode 119b. Interlayer insulating film 117 and openings 116a and 11
The steps of forming the 6b, the second electrode 119a, and the third electrode 119b are the same as those described in Embodiment 1.

Through the above steps, the transistor 200 can be manufactured (see FIG. 9).

Also, the above is a first dopant addition treatment and a second dopant addition treatment.
Two doping processes are performed. However, the sidewall insulating film 215 may be formed before the first dopant addition treatment, and then, the dopant addition treatment may be performed to achieve a desired dopant concentration, whereby the transistor 200 may be formed. Note that the desired dopant concentration is a dopant concentration in the pair of second regions 123 a and 123 b and the pair of third regions 223 a and 223 b of the transistor 200.

<Variation 1 of Transistor 200>
In addition, by performing the third heat treatment at a temperature higher than or equal to 550 ° C. and lower than the strain point temperature of the substrate and in an oxidizing atmosphere, the dopant 150 is included in the pair of second regions 123 a and 123 b and a plurality of crystal parts A non-single-crystal oxide semiconductor region 107a or 107b which includes a dopant 150 and has a c-axis-oriented crystal portion can be formed over the oxide semiconductor regions 109a and 109b. Also in the regions 223a and 223b, the dopant 150 is
A non-single-crystal oxide semiconductor region 207a including a dopant 150 on the oxide semiconductor regions 209a and 209b including a plurality of crystal parts and having a c-axis aligned crystal part
, 207b can be formed.

A top view of the transistor 260 completed in this case is illustrated in FIG. further,
FIG. 11B is a cross-sectional view taken along line A-B in FIG.

A pair of second regions 123a and 123b of the transistor 260 includes the dopant 150 and is a non-single-crystal oxide semiconductor region 107a and 107b having a c-axis aligned crystal part.
And the dopant 150, and the oxide semiconductor region 109a having a plurality of crystal parts
, 109b (see FIG. 11B). Note that the oxide semiconductor region 107a
And 107b and the oxide semiconductor regions 109a and 109b have the same dopant concentration.

In addition, the pair of third regions 223 a and 223 b of the transistor 260 is a dopant 150.
A non-single crystal oxide semiconductor region 207a, 20 having a crystal part containing c and having c axis orientation.
7b and the dopant 150, and the oxide semiconductor region 2 having a plurality of crystal parts
It is comprised by 09a and 209b (refer FIG. 11 (B)).

As described above, the pair of third regions 223a, 223b is a pair of second regions 123a,
Since the dopant concentration is lower than that of 123b, the oxide semiconductor regions 207a and 207b and the oxide semiconductor regions 209a and 209b have a dopant concentration lower than that of the oxide semiconductor regions 107a and 107b and the oxide semiconductor regions 109a and 109b. Note that the dopant concentrations of the oxide semiconductor regions 207a and 207b and the oxide semiconductor regions 209a and 209b are the same.

The second electrode 119a and the third electrode 119b are in contact with the oxide semiconductor regions 107a and 107b through the openings 116a and 116b. The other configuration of the transistor 260 is similar to that of the transistor 160.

In addition, when the third heat treatment is performed for one hour under the above conditions, the oxide semiconductor region 107a,
107 b is a pair of second regions 123 a and 123 b from the top surface of the pair of second regions 123 a
, 123b in the direction of the lower surface, at least 2 nm. Further, the oxide semiconductor regions 107a and 107b can be formed thicker by lengthening the time of the third heat treatment performed under the above conditions.

In the transistor 200 and the transistor 260, the pair of second regions 123a,
The description of the transistor 200 is also applied to the transistor 260, with the only difference being the configuration of 123b and the pair of third regions 223a and 223b.

The transistor 260 also has an effect of reducing the bending of the band edge in the channel formed in the first region 105, and the transistor 260 is generated by shortening the channel length, such as the threshold voltage fluctuating in the negative direction. The impact can be reduced. Furthermore, the contact resistance between the second electrode 119a and the third electrode 119b and the pair of second regions 123a and 123b can be reduced, and the on-state current of the transistor 260 can be increased.

In the transistor 260, the pair of second regions 123a and 123b is the oxide semiconductor regions 107a and 107b and the oxide semiconductor regions 109a and 109b, so the pair of second regions 123a and 123b is temporarily amorphous. It is considered that the fluctuation of the threshold voltage before and after light irradiation and before and after the BT (gate and thermal bias) stress test is smaller than in the case of the above region, and the transistor is highly reliable.

<Variation 2 of Transistor 200>
When the first electrode 113 in the method for manufacturing the transistor 200 is formed, the gate insulating film 111 is formed.
At the same time, the gate insulating film 121 can be provided only on the first region 105 of the oxide semiconductor film 103 by etching.

A top view of the transistor 270 completed in this case is illustrated in FIG. further,
A cross-sectional view taken along line A-B in FIG. 12A is shown in FIG. The top surface structure of the transistor 270 is similar to that of the transistor 200, and is a top gate and top contact transistor.

The transistor 200 and the transistor 270 are different only in the shape of the gate insulating film, and the description of the transistor 200 is also applied to the transistor 270.

Therefore, also in the transistor 270, the effect of reducing the band edge bending in the channel formed in the first region 105 is exhibited, and in the transistor 270, the channel length is shortened, for example, the threshold voltage fluctuates in the negative direction. You can reduce the impact of Furthermore, the second electrode 119a and the third electrode 119b and the pair of second regions 123a and 123
The contact resistance with b can be reduced, and the on current of the transistor 270 can be increased.

In the case where the pair of second regions 123a and 123b is an amorphous region, the transistor 270 is an oxide semiconductor region in which the pair of second regions 123a and 123b is a plurality of crystal parts. In this transistor, the fluctuation of the threshold voltage before and after light irradiation and before and after the BT (gate and thermal bias) stress test is considered to be small, and the transistor is highly reliable.

A method for manufacturing the transistor 270 is described with reference to FIGS. 3, 13 and 14.
The transistor 270 is similar to the transistor 100 up to the step of forming the conductive film 112 (see FIG. 3A).

After the conductive film 112 is formed, the conductive film 112 and the gate insulating film 111 are etched to form the first electrode 113 and the first region 105 of the oxide semiconductor film 103 which is to be formed later.
A gate insulating film 121 which overlaps only on the top can be formed (see FIG. 13A).

In addition, since the gate insulating film 121 is in contact with only the first region 105, the oxide semiconductor film 1 can be formed.
It is not provided along the 40 shapes (steps). In other words, the gate insulating film 121 has no portion which passes over the step of the oxide semiconductor film 140. Therefore, in the completed transistor 270 as well, since there is no portion in the gate insulating film 121 which passes over the step of the oxide semiconductor film 103, leakage current due to disconnection or the like of the gate insulating film 121 is reduced. The withstand voltage of the insulating film 121 can be increased. Therefore, the gate insulating film 121
Alternatively, the transistor 270 can be operated even when used as a thin film to about 5 nm. Note that by thinning the gate insulating film 121, an influence caused by shortening the channel length can be reduced and the operation speed of the transistor can be increased.

Further, since the transistor 270 has no portion where the gate insulating film 121 passes over the step, the first electrode 113, the pair of second regions 123a and 123b, and the pair of third regions 2
There is almost no parasitic capacitance generated between 23a and 223b. Therefore, transistor 27
Even when the channel length is reduced, the variation of the threshold voltage can be reduced.

Next, a first dopant addition process is performed (see FIG. 13B). The first dopant addition treatment may be performed in a manner similar to that of the transistor 200. By the first doping process, oxide semiconductor regions 214a and 214b to which the dopant 150 is added are formed.

Next, the insulating film 114 to be the sidewall insulating film 215 is formed (see FIG. 13C).
. The insulating film 114 can be formed in a similar manner to the base insulating film 102 or the gate insulating film 111, and is either the oxide insulating film or the nitride insulating film described in Embodiment 1.
The thickness of the insulating film 114 is not particularly limited, but may be appropriately selected in consideration of the coverage with the shape of the first electrode 113.

Similarly to the transistor 200, the insulating film 114 is etched to form a sidewall insulating film 215. The details of the etching can be referred to the above.

In addition, the thickness of the sidewall insulating film 215 is the first electrode 1 from the surface in contact with the oxide semiconductor film 140 which is to be the oxide semiconductor film 103 later in the sidewall insulating film 215.
It says to the top of the face in contact with 13. And, a pair of third regions 22 formed later
Since the dopant concentration of 3 a and 223 b corresponds to the thickness of the sidewall insulating film 215, the sidewall insulating film 215 has sidewall insulating properties such that the dopant concentration of the pair of second regions 123 a and 123 b becomes the value described for the transistor 200. The thickness of the membrane 215 and further the first electrode 11
The thickness of 3 should be decided.

Further, the width of the pair of second regions 123 a and 123 b is the width of the sidewall insulating film 215 (for example, the width of a portion where the sidewall insulating film 215 in FIG. 12B is in contact with the oxide semiconductor film 103) Determined in response to By increasing the range of the pair of second regions 123a and 123b, the electric field applied to the first region 105 can be relaxed accordingly.

The width of the sidewall insulating film 215 also corresponds to the thickness of the first electrode 113, so that the range of the pair of second regions 123a and 123b is within the desired range.
The thickness of 3 should be decided.

Next, a second dopant addition process is performed. Note that the process in which the dopant 150 is added in the transistor 270 is different from the process of the transistor 200, in which the first electrode 113 is used as a mask and a region added through the sidewall insulating film 215;
There is a region to be added in a state in which a part of L is exposed (see FIG. 13 (D)).

In the case where the dopant 150 is added in a state where part of the oxide semiconductor film 140 is exposed as in the transistor 270, a method other than ion doping or ion implantation can be used as a method of adding the dopant 150. . For example, plasma is generated in a gas atmosphere containing an element to be added, and an additive (here, the oxide semiconductor film 1
40) plasma treatment for irradiating the plasma. As an apparatus for generating the plasma, a dry etching apparatus, a plasma CVD apparatus, a high density plasma CVD apparatus, or the like can be used. Further, the plasma treatment may be performed while heating the substrate 101.

After that, the transistor 270 can be manufactured by performing the same process as the transistor 200 (see FIG. 12).

Note that the sidewall insulating film 215 is formed before the first dopant addition treatment is performed similarly to the transistor 200, and then, the dopant addition treatment is performed to achieve a desired dopant concentration, whereby the transistor 270 is formed. It is also good.

In the transistor 270, the third heat treatment performed after the addition of the dopant 150 is performed at a temperature higher than or equal to 550 ° C. and lower than the strain point temperature of the substrate and in an oxidizing atmosphere; A pair of second regions 123a and 123b in which non-single-crystal oxide semiconductor regions 107a and 107b including a dopant portion 150 and a c-axis-oriented crystal portion are provided over the oxide semiconductor regions 109a and 109b. (See FIG. 14). Each reference numeral in FIG. 14 corresponds to each reference numeral of the transistor 200, the transistor 260, and the transistor 270.

As described above, one embodiment of the disclosed invention can solve the problems associated with miniaturization, and as a result, the transistor size can be sufficiently reduced. By sufficiently reducing the size of the transistor, the area occupied by the semiconductor device can be reduced, and the number of semiconductor devices can be increased. Thereby, the manufacturing cost per semiconductor device is suppressed. In addition, since the semiconductor device is miniaturized while maintaining the same function, when the size is made to be the same, it is possible to realize a semiconductor device with a further enhanced function. In addition, effects such as speeding up of operation and reduction of power consumption can be obtained by reducing the channel length. In other words, by achieving miniaturization of a transistor using an oxide semiconductor according to one embodiment of the disclosed invention, various effects associated with this can be obtained. Note that this embodiment can be combined with any of the other embodiments and examples as appropriate.

Third Embodiment
In this embodiment, a structure and a manufacturing method of a transistor which is another embodiment of the present invention will be described with reference to FIGS.

In the transistor described in this embodiment, the second electrode 119 a and the third electrode 119 b correspond to the pair of second regions 123 a of the oxide semiconductor film in comparison with the transistor 100 described in Embodiment 1. It is different that it is in contact with the lower surface of 123b. That is, the transistor described in this embodiment is a top gate and bottom contact transistor. A cross-sectional view of the top-gate and bottom-contact transistor is illustrated in FIG.

Further, all the transistors described in Embodiment 1 and Embodiment 2 can also be top-gate and bottom-contact transistors. For example, each of the transistor 160 and the transistor 170 can also have a top gate structure and a bottom contact structure. FIG. 15B shows a cross-sectional view of a transistor in which the transistor 160 has a top gate structure and a bottom contact structure, and FIG. 15C shows a cross-sectional view of a transistor in which the transistor 170 has a top gate structure and a bottom contact structure.

Furthermore, FIG. 16A shows a cross-sectional view of a transistor in which the transistor 200 has a top gate structure and a bottom contact structure, and FIG. 16B shows a cross-sectional view of a transistor in which the transistor 260 has a top gate structure and a bottom contact structure. A cross-sectional view of a transistor in which the transistor 270 has a top gate structure and a bottom contact structure is illustrated in FIG.

In FIGS. 15A to 15C and FIGS. 16A to 16C, reference numerals indicate the respective symbols of the transistor 100, the transistor 160 and the transistor 170, and the respective symbols of the transistor 200, the transistor 260 and the transistor 270. Because of the correspondence, the description of each of the reference numerals can be appropriately referred to the description of Embodiment 1 and Embodiment 2. In addition to the reference numerals, what has been described in Embodiment 1 and Embodiment 2 is also applied to this embodiment.

Further, as a method for manufacturing the transistors illustrated in FIGS. 15A to 15C and FIGS. 16A to 16C, the order of manufacturing steps of the corresponding transistors may be changed. For example, in the process of forming the second electrode 119a and the third electrode 119b,
Subsequent to the step of forming the base insulating film 102, the transistor 100, the transistor 160 and the transistor 170, and the transistor 200 and the transistor 260 are performed.
And the second electrode 119 a and the third electrode 11 in the manufacturing process of the transistor 270.
Steps other than the step of forming 9b may be sequentially performed.

Note that in the transistors illustrated in FIGS. 15C and 16C, the oxide semiconductor film 1 is
As shown in FIG. 15 (B) and FIG. 16 (B), the pair of second regions 123a and 123 is used.
b, the dopant 150, and an oxide semiconductor region 109a having a plurality of crystal parts
And 109b, a non-single-crystal oxide semiconductor region 107a and 107b including a dopant 150 and having a c-axis aligned crystal part, or a pair of third regions 223a and 2b.
An oxide semiconductor region 20 including a dopant 150 and having a plurality of crystal parts.
A non-single-crystal oxide semiconductor region 207a or 207b which contains a dopant 150 and has a c-axis aligned crystal part may be provided over 9a or 209b. The cross-sectional view of the transistor of this configuration is not shown.

As described above, one embodiment of the disclosed invention can solve the problems associated with miniaturization, and as a result, the transistor size can be sufficiently reduced. By sufficiently reducing the size of the transistor, the area occupied by the semiconductor device can be reduced, and the number of semiconductor devices can be increased. Thereby, the manufacturing cost per semiconductor device is suppressed. In addition, since the semiconductor device is miniaturized while maintaining the same function, when the size is made to be the same, it is possible to realize a semiconductor device with a further enhanced function. In addition, effects such as speeding up of operation and reduction of power consumption can be obtained by reducing the channel length. In other words, by achieving miniaturization of a transistor using an oxide semiconductor according to one embodiment of the disclosed invention, various effects associated with this can be obtained. Note that this embodiment can be combined with any of the other embodiments as appropriate.

Embodiment 4
In this embodiment, in a region to which a dopant is added which functions as a source region and a drain region and a field relaxation region of the transistor described in Embodiments 1 to 3, the bonding state of the dopant, and the dopant The electronic states of the oxide semiconductor forming the region to which H is added are described with reference to FIGS.

For example, in the transistor 100, the pair of second regions 123a and 123b which are regions containing a dopant has higher conductivity than the first region 105 which does not include a dopant.

This increase in conductivity can be expected to be due to the generation of carriers in the oxide semiconductor by the addition of the dopant to the oxide semiconductor forming the pair of second regions 123a and 123b.

Thus, in this embodiment, a first principle molecular dynamics (First-Principles Molecular Dynamic) is used in an oxide semiconductor having a structure to which a dopant is added.
The bonding state and electronic state of the oxide semiconductor by s: FPMD calculation and structure optimization calculation are described. Note that the oxide semiconductor is an In-Ga-Zn-O-based metal oxide,
In order to simplify the above calculation, it is assumed that the In-Ga-Zn-O-based metal oxide is amorphous (hereinafter referred to as a-IGZO). Furthermore, the dopant is a phosphorus (P) atom.

The above calculation is performed on a-IGZO in which 1 atom of phosphorus is disposed (added). Specifically, a-IGZO has 84 atoms per unit cell, and the composition ratio is In: Ga: Zn:
O = 1: 1: 1: 4 (atomic number ratio), density is 5.9 g cm ⁻³ , lattice constant is a
It is assumed that = b = c = 1.02 nm and α = β = γ = 90 °.

Moreover, in performing the said calculation, the calculation program used CASTEP which is a first principle quantum mechanics program made from Accelrys. The functional used GGA-PBE, and the pseudopotential used Ultrasoft. The cutoff energy is 260 eV (DO
In the S calculation, 380 eV), and the number of k points is 1 × 1 × 1. The FPMD calculation was performed with the NVT ensemble at a temperature of 1500K. Total calculation time is 0.3 ps and time step size is 1.0 fs
It is.

The initial structure in the above calculation and the final structure after the above calculation are shown in FIG. Figure 17 (A)
FIG. 17 shows the initial structure, and FIG. 17 (B) shows the final structure. The initial structure is
It corresponds to a structure in which a phosphorus atom is disposed at an arbitrary position with respect to a-IGZO. The final structure corresponds to the structure after the above calculation, that is, the structure after structure optimization. Further, the final structure subjected to the structure optimization corresponds to the structure of the oxide semiconductor region containing a dopant in the transistors described in Embodiments 1 to 3.

As shown in FIG. 17A, phosphorus atoms in the initial structure are arranged (added) between the elements constituting a-IGZO. In FIG. 17, black circles represent oxygen atoms, white circles represent metal atoms (In atoms, Zn atoms or Ga atoms), and gray circles represent phosphorus atoms.

As a result of the above calculation, the phosphorus atom in the final structure forms "a bond with one Zn atom", a "two oxygen atom with a single bond", and a "double bond with an oxygen atom". That is, the phosphorus atom is coordinated to the Zn atom in a state of being bonded to the oxygen atom (see FIG. 17B).

The fact that the metal atom to which the phosphorus atom is bonded is a Zn atom can be explained from the viewpoint of bonding energy.

The bond energy between Zn atom and oxygen atom is lower than the bond energy between other metal atoms (In and Ga atoms) and oxygen atom, so the bond between Zn atom and oxygen atom is lower than that of other bonds. It can be said that the bond is susceptible to cleavage. Therefore, after structural optimization, it is believed that the phosphorus atom coordinates the surrounding oxygen atom to the Zn atom. However, this indicates that the possibility of bonding between the phosphorus atom and the Zn atom is the highest, and the metal atom to which the phosphorus atom is bonded is not limited to the Zn atom, and other metals constituting a-IGZO It may be a metal atom.

Next, FIG. 18 shows a state density diagram of the structure after structure optimization. FIG. 18A is a state density diagram in a-IGZO in which no phosphorus atom is disposed (added). Also, FIG. 18 (B)
Is a state density diagram in a-IGZO (corresponding to FIG. 17 (B)) after arrangement (addition) of phosphorus atoms and structure optimization. The solid line in FIG. 18B arranges (adds) a phosphorus atom,
And the full state density of a-IGZO after structure optimization is represented, The broken line of FIG. 18 (B) represents the partial state density of the phosphorus atom in a-IGZO after this structure optimization. Figure 18 (A) and Figure 1
In both of 8 (B), the horizontal axis represents energy [eV], and the vertical axis represents the density of states [states / eV] in the structure after structure optimization. In both state density diagrams shown in FIGS. 18 (A) and 18 (B), the origin of energy is taken at the Fermi level.

As shown in FIG. 18A, in all density of states, the Fermi level of a-IGZO in which no phosphorus atom is disposed matches the upper end of the valence band, and the conduction band is formed on the band gap. .

From FIG. 18 (B), a-I after arranging phosphorus atoms in all density of states and after structure optimization
Since the Fermi level of GZO exists in the range of the conduction band, it can be said that carriers are generated in the a-IGZO. Furthermore, within the band gap of the a-IGZO,
It can be seen that the level of phosphorus atom is also generated.

From the above, it can be understood that carriers are generated in the oxide semiconductor by adding the dopant to the oxide semiconductor.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Fifth Embodiment
In this embodiment, an example of a semiconductor device using the transistor described in any of Embodiments 1 to 3 will be described.

FIG. 20A illustrates an example of a circuit diagram of a memory element (hereinafter, also referred to as a memory cell) included in a semiconductor device. The memory cell includes a transistor 1160 using a material other than an oxide semiconductor for a channel formation region and a transistor 1162 using an oxide semiconductor for the channel formation region.

The transistor 1162 using an oxide semiconductor for a channel formation region can be manufactured according to the above embodiment.

As shown in FIG. 20A, the gate electrode of the transistor 1160 and the transistor 116
One of the source electrode and the drain electrode of 2 is electrically connected. The first wiring (also referred to as a source line) and the source electrode of the transistor 1160 are electrically connected to each other, and a second wiring (also referred to as a bit line) and a drain electrode of the transistor 1160 are connected. Are electrically connected. And the third wiring (3rd
Line: Also referred to as a first signal line, and the other of the source electrode and the drain electrode of the transistor 1162 are electrically connected to each other, and a fourth wiring (also referred to as a second signal line) and a gate of the transistor 1162 The electrodes are electrically connected.

The transistor 1160 using a material other than an oxide semiconductor, for example, single crystal silicon, in the channel formation region can operate at sufficiently high speed.
It is possible to read stored contents at high speed. In addition, the transistor 1162 in which an oxide semiconductor is used for a channel formation region has a feature that off current is smaller than that of the transistor 1160. Therefore, by turning off the transistor 1162, the potential of the gate electrode of the transistor 1160 can be held for an extremely long time.

By utilizing the feature that the potential of the gate electrode of the transistor 1160 can be held, writing, holding, and reading of data can be performed as follows.

First, writing and holding of information will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 1162 is turned on, whereby the transistor 1162 is turned on. Thus, the potential of the third wiring is supplied to the gate electrode of the transistor 1160 (writing). After that, the potential of the gate electrode of the transistor 1160 is held (holding) by setting the potential of the fourth wiring to a potential at which the transistor 1162 is turned off and the transistor 1162 is turned off.

Since the off-state current of the transistor 1162 is smaller than that of the transistor 1160, the potential of the gate electrode of the transistor 1160 is held for a long time. For example, when the potential of the gate electrode of the transistor 1160 is a potential at which the transistor 1160 is turned on, the on state of the transistor 1160 is held for a long time. In addition, when the potential of the gate electrode of the transistor 1160 is a potential at which the transistor 1160 is turned off, the off state of the transistor 1160 is held for a long time.

Next, reading of information will be described. As described above, in the state where the on state or the off state of the transistor 1160 is held, when a predetermined potential (a low potential) is applied to the first wiring, the first wiring is selected depending on the on state or the off state of the transistor 1160. The potentials of the two wires have different values. For example, when the transistor 1160 is in the on state, the potential of the second wiring is lower than the potential of the first wiring. In addition, when the transistor 1160 is off, the potential of the second wiring does not change.

As described above, in the state where the information is held, the information can be read out by comparing the potential of the second wiring with a predetermined potential.

Next, rewriting of information will be described. Rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the fourth wiring is set to a potential at which the transistor 1162 is turned on, whereby the transistor 1162 is turned on. Thus, the potential of the third wiring (potential of new information) is supplied to the gate electrode of the transistor 1160. After that, the potential of the fourth wiring is set to a potential at which the transistor 1162 is turned off, and the transistor 1162 is turned off, whereby new information is held.

Thus, the memory cell according to the disclosed invention can directly rewrite information by writing information again. Therefore, the erase operation required in the flash memory or the like is not necessary, and it is possible to suppress the decrease in operation speed due to the erase operation.
That is, high speed operation of the semiconductor device having the memory cell is realized.

In addition, an example of a circuit diagram of a memory cell developed from the memory cell of FIG.
Shown in.

The memory cell 1100 illustrated in FIG. 20B includes a first wiring SL (source line), a second wiring BL (bit line), a third wiring S1 (first signal line), and a fourth wiring Wiring S2 (second signal line)
, Fifth wiring WL (word line), and transistor 1164 (first transistor),
A transistor 1161 (second transistor) and a transistor 1163 (third transistor) are included. The transistors 1164 and 1163 each use a material other than an oxide semiconductor for a channel formation region, and the transistor 1161 uses an oxide semiconductor for a channel formation region.

Here, the gate electrode of the transistor 1164 and one of the source electrode and the drain electrode of the transistor 1161 are electrically connected. The first wiring SL and the source electrode of the transistor 1164 are electrically connected, and the drain electrode of the transistor 1164 and the source electrode of the transistor 1163 are electrically connected. Then, the second wiring BL and the drain electrode of the transistor 1163 are electrically connected, and the third wiring S1 and the other of the source electrode or the drain electrode of the transistor 1161 are electrically connected; The wiring S2 of 4 and the gate electrode of the transistor 1161 are electrically connected, and the fifth wiring WL and the gate electrode of the transistor 1163 are electrically connected.

Next, the operation of the circuit will be specifically described.

When writing to the memory cell 1100, the first wiring SL is 0 V, the fifth wiring WL is 0 V, the second wiring BL is 0 V, and the fourth wiring S2 is 2 V. When writing data “1”, the third wiring S1 is 2 V, and when writing data “0”, the third wiring S1 is 0 V. At this time, the transistor 1163 is turned off and the transistor 1161 is turned on. Note that at the end of writing, the fourth wiring S2 is set to 0 V to turn off the transistor 1161 before the potential of the third wiring S1 changes.

As a result, after writing data "1", the potential of a node (hereinafter, node A) connected to the gate electrode of the transistor 1164 becomes about 2 V, and after writing data "0", the potential of the node A becomes about 0 V. Although charge corresponding to the potential of the third wiring S1 is stored in the node A, the off-state current of the transistor 1161 is smaller than that of a transistor in which single crystal silicon is used for a channel formation region and the gate electrode of the transistor 1164 The potential of is maintained for a long time.

Next, in the case of reading a memory cell, the first wiring SL is at 0 V and the fifth wiring WL is at 2
V, the fourth wiring S2 is 0 V, the third wiring S1 is 0 V, and the reading circuit connected to the second wiring BL is in an operation state. At this time, the transistor 1163 is on and the transistor 1161 is off.

If the data “0”, that is, the node A is at about 0 V, the transistor 1164 is in the off state, and the resistance between the second wiring BL and the first wiring SL is in a high state. On the other hand, when the data “1”, that is, the node A is in the state of about 2 V, the transistor 1164 is in the on state, so that the resistance between the second wiring BL and the first wiring SL is low. The reading circuit can read data "0" and "1" from the difference in resistance state of the memory cell. Although the second wiring BL at the time of writing is 0 V, it may be charged in a floating state or a potential of 0 V or more. Although the third wiring S1 at the time of reading is set to 0 V, it may be charged to a floating state or a potential of 0 V or more.

Data “1” and data “0” are definitions for convenience and may be reversed. Moreover, the operating voltage mentioned above is an example. The operating voltage is transistor 1 in the case of data "0".
164 is turned off, and the transistor 1164 is turned on in the case of data “1”, and the transistor 1161 is turned on at the time of writing, and turned off at times other than the time of writing. Should be selected to be on. In particular, power supply potential VDD of the peripheral logic circuit may be used instead of 2V.

In the present embodiment, the memory cell of the minimum storage unit (1 bit) is described for simplicity of understanding, but the configuration of the memory cell is not limited to this. A plurality of memory cells can be appropriately connected to construct a more advanced semiconductor device. For example, it is possible to configure a NAND type or NOR type semiconductor device by using a plurality of the memory cells. The configuration of the wiring is not limited to that in FIGS. 20A and 20B, and can be changed as appropriate.

FIG. 21 illustrates a block circuit diagram of a semiconductor device according to one embodiment of the present invention, which has a storage capacity of m × n bits.

The semiconductor device illustrated in FIG. 21 includes m fifth wirings WL (1) to WL (m) and m fourth wirings.
Wirings S2 (1) to S2 (m), n second wirings BL (1) to BL (n), n third wirings S1 (1) to S1 (n), and a plurality of Memory cells 1100 (1, 1) to 110
A memory cell array 1110 is arranged in a matrix of 0 (m, n) with m (rows) × n (columns) (m, n are natural numbers) in the vertical direction. In addition, the second wiring BL and the third wiring S1
And a driver circuit 1113 connected to the fourth wiring S2 and the fifth wiring WL, and a peripheral circuit such as a reading circuit 1112. A refresh circuit or the like may be provided as another peripheral circuit.

Memory cell 1100 (i, j) is considered as a representative of each memory cell. Here, the memory cell 1100 (i, j) (i is an integer of 1 or more and m or less, j is an integer of 1 or more and n or less) is a second wiring BL (j) and a third wiring S1 (j), Fifth wiring WL (i) and fourth wiring S2 (
i) and are connected to the first wiring respectively. The first wiring potential Vs is applied to the first wiring
Is given. In addition, second wires BL (1) to BL (n) and a third wire S1 (1
) To S1 (n) are connected to the driver circuit 1111 and the readout circuit 1112 using the fifth wiring WL (1).
The WL <b> 1 to WL (m) and the fourth wirings S <b> 2 (1) to S <b> 2 (m) are respectively connected to the drive circuit 1113.

The operation of the semiconductor device shown in FIG. 21 will be described. In this configuration, writing and reading are performed row by row.

When the memory cell 1100 (i, 1) to 1100 (i, n) in the i-th row is to be programmed, the first wiring potential Vs is 0 V, the fifth wiring WL (i) is 0 V, and the second wiring BL (1) to BL (
n) is 0V, and the fourth wiring S2 (i) is 2V. At this time, the transistor 1161 is turned on. The third wires S1 (1) to S1 (n) have 2 V in the column for writing data "1".
The column for writing data "0" is 0V. At the end of writing, before the potentials of the third wirings S1 (1) to S1 (n) change, the fourth wiring S2 (i) is set to 0V.
The transistor 1161 is turned off. Further, the non-selected fifth wiring WL is at 0 V, and the non-selected fourth wiring S2 is at 0 V.

As a result, the potential of a node (hereinafter, node A) connected to the gate electrode of transistor 1164 of the memory cell in which data "1" is written is approximately 2 V, and the node of the memory cell in which data "0" is written The potential of A becomes about 0 V (see FIG. 20 (B) and FIG. 21). Also,
The potential of node A of the non-selected memory cell does not change.

When reading the memory cell 1100 (i, 1) to 1 100 (i, n) of the i-th row,
The first wiring potential Vs is 0 V, the fifth wiring WL (i) is 2 V, and the fourth wiring S2 (i) is 0 V
The third wirings S1 (1) to S1 (n) are set to 0 V, and the readout circuit connected to the second wirings BL (1) to BL (n) is brought into an operating state. In the read circuit, for example, data “0” and “1” can be read from the difference in resistance state of the memory cell. In addition, the fifth not selected
The line WL is at 0V, and the non-selected fourth line S2 is at 0V. Although the second wiring BL at the time of writing is 0 V, it may be charged in a floating state or a potential of 0 V or more. Although the third wiring S1 at the time of reading is set to 0 V, it may be charged to a floating state or a potential of 0 V or more.

Data “1” and data “0” are definitions for convenience and may be reversed. Moreover, the operating voltage mentioned above is an example. The operating voltage is transistor 1 in the case of data "0".
164 is turned off, and the transistor 1164 is turned on in the case of data “1”, and the transistor 1161 is turned on at the time of writing, and turned off at times other than the time of writing. Should be selected to be on. In particular, power supply potential VDD of the peripheral logic circuit may be used instead of 2V.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Sixth Embodiment
In this embodiment, an example of a circuit diagram of a memory cell having a capacitor is shown. A memory cell 1170 illustrated in FIG. 22A includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, a fifth wiring WL, and a transistor 1171 (a first wiring And the transistor 1172 (second transistor), and the capacitor element 1173.
The transistor 1171 uses a material other than an oxide semiconductor for the channel formation region, and the transistor 1172 uses an oxide semiconductor for the channel formation region.

Here, the gate electrode of the transistor 1171, one of the source electrode or the drain electrode of the transistor 1172, and one electrode of the capacitor 1173 are electrically connected. In addition, the first wiring SL and the source electrode of the transistor 1171 are electrically connected, and the second wiring BL and the drain electrode of the transistor 1171 are electrically connected, and the third wiring S1 and the third wiring S1. The other of the source electrode and the drain electrode of the transistor 1172 is electrically connected, the fourth wiring S2 and the gate electrode of the transistor 1172 are electrically connected, a fifth wiring WL, and a capacitor The other electrode of 1173 is electrically connected.

Next, the operation of the circuit will be specifically described.

When writing to the memory cell 1170, the first wiring SL is 0 V, the fifth wiring WL is 0 V, the second wiring BL is 0 V, and the fourth wiring S2 is 2 V. When writing data “1”, the third wiring S1 is 2 V, and when writing data “0”, the third wiring S1 is 0 V. At this time, the transistor 1172 is turned on. Note that at the end of the writing, the fourth wiring WL is set to 0 V to turn off the transistor 1172 before the potential of the third wiring S1 changes.

As a result, the potential of a node (hereinafter, node A) connected to the gate electrode of the transistor 1171 after writing data "1" is about 2 V, and the potential of node A becomes about 0 V after writing data "0". .

When the memory cell 1170 is read, the first wiring SL is set to 0 V, the fifth wiring WL is set to 2 V, the fourth wiring S2 is set to 0 V, the third wiring S1 is set to 0 V, and the second wiring BL is connected. The read circuit in operation is put into operation. At this time, the transistor 1172 is turned off.

The state of the transistor 1171 in the case where the fifth wiring WL is 2 V will be described. The potential of the node A that determines the state of the transistor 1171 depends on the capacitance C1 between the fifth wiring WL and the node A and the capacitance C2 between the gate electrode and the source electrode of the transistor 1171 and the drain electrode.

Although the third wiring S1 at the time of reading is set to 0 V, it may be charged to a floating state or a potential of 0 V or more. Data "1" and data "0" are definitions for convenience, and may be reversed.

When the potential of the third wiring S1 at the time of writing is such that the transistor 1172 is turned off after writing and the potential of the fifth wiring WL is 0 V, the data “0”, It is sufficient to select the potential of 1 ′ ′. The potential of the fifth wiring WL at the time of reading may be selected so that the transistor 1171 is turned off in the case of data “0” and the transistor 1171 is turned on in the case of data “1”. Also, the transistor 11
The threshold voltage 71 is also an example. Any threshold may be used as long as the state of the transistor 1171 described above is not changed.

In addition, an example of a NOR-type semiconductor memory device using a memory cell including a selection transistor having a first gate electrode and a second gate electrode and a memory cell having a capacitor is described with reference to FIG.

The semiconductor device according to one embodiment of the present invention illustrated in FIG. 22B includes I rows (I is a natural number of 2 or more) J
A memory cell array comprising a plurality of memory cells arranged in a matrix in a column (J is a natural number) is provided.

In the memory cell array shown in FIG. 22B, a plurality of memory cells 1180 arranged in a matrix of i rows (i is a natural number of 3 or more) and j columns (j is a natural number of 3 or more) and i word lines W
L (word line WL_1 to word line WL_i), i capacitive line CL (capacitive line CL_1 to capacitive line CL_i), i gate line BGL (gate line BGL_1 to gate line BGL
_I), j bit lines BL (bit lines BL_1 to bit lines BL_j), and a source line SL.

Further, each of the plurality of memory cells 1180 (also referred to as a memory cell 1180 (M, N) (where N is a natural number of 1 or more and j or less and M is a natural number of 1 or more and i or less)) is a transistor 1181 (M, N ), A capacitive element 1183 (M, N), and a transistor 1182 (M, N).
And.

Note that in the semiconductor memory device, the capacitor element is formed of a first capacitor electrode, a second capacitor electrode, and a dielectric layer overlapping with the first capacitor electrode and the second capacitor electrode. The capacitive element stores charge in response to a voltage applied between the first capacitive electrode and the second capacitive electrode.

The transistor 1181 (M, N) is an n-channel transistor and includes a source electrode, a drain electrode, a first gate electrode, and a second gate electrode. Note that in the semiconductor memory device of this embodiment, the transistor 1181 may not necessarily be an n-channel transistor.

One of the source electrode and the drain electrode of transistor 1181 (M, N) is connected to bit line B.
The first gate electrode of the transistor 1181 (M, N) is connected to the word line W
The second gate electrode of the transistor 1181 (M, N) is connected to the gate line B
Connected to GL_M. When one of the source electrode and the drain electrode of the transistor 1181 (M, N) is connected to the bit line BL_N, data can be selectively read for each memory cell.

The transistor 1181 (M, N) functions as a selection transistor in the memory cell 1180 (M, N).

As the transistor 1181 (M, N), a transistor in which an oxide semiconductor is used for a channel formation region can be used.

The transistor 1182 (M, N) is a P-channel transistor. Note that in the semiconductor memory device of this embodiment, the transistor 1182 may not necessarily be a p-channel transistor.

One of the source and drain electrodes of the transistor 1182 (M, N) has a source line S
L, the other of the source and drain electrodes of the transistor 1182 (M, N) is connected to the bit line BL_N, and the gate electrode of the transistor 1182 (M, N) is the source of the transistor 1181 (M, N) It is connected to the other of the electrode and the drain electrode.

The transistor 1182 (M, N) functions as an output transistor in the memory cell 1180 (M, N). As the transistor 1182 (M, N), for example, a transistor in which single crystal silicon is used for a channel formation region can be used.

The first capacitance electrode of the capacitance element 1183 (M, N) is connected to the capacitance line CL_M, and the second capacitance electrode of the capacitance element 1183 (M, N) is the source electrode of the transistor 1181 (M, N) It is connected to the other of the drain electrodes. Note that the capacitor element 1183 (M, N) has a function as a storage capacitor.

The voltage of each of the word line WL_1 to the word line WL_i is controlled by a drive circuit using a decoder, for example.

The voltage of each of the bit lines BL_1 to BL_j is controlled by a driver circuit using, for example, a decoder.

The voltage of each of the capacitor lines CL_1 to CL_i is controlled by, for example, a driver circuit using a decoder.

The voltage of each of the gate lines BGL_1 to BGL_i is controlled using, for example, a gate line driving circuit.

The gate line drive circuit is formed of, for example, a circuit including a diode and a capacitive element in which the first capacitive electrode is electrically connected to the anode of the diode and the gate line BGL.

By adjusting the voltage of the second gate electrode of the transistor 1181, the transistor 1
The threshold voltage of 181 can be adjusted. Therefore, the threshold voltage of the transistor 1181 functioning as a selection transistor is adjusted, and the transistor 118 in the off state is adjusted.
The current flowing between the source electrode and the drain electrode can be minimized. Thus, the data retention period in the memory circuit can be extended. In addition, power consumption can be reduced because voltages required for writing and reading data can be made lower than those of conventional semiconductor devices.

According to this embodiment, the potential of a node connected to a transistor in which an oxide semiconductor is used for a channel formation region can be held for an extremely long time, data writing, holding, and reading can be performed with low power consumption. Can be manufactured.
In the memory cell array shown in FIG. 22B, instead of memory cell 1180,
The memory cell 1170 shown in FIG. 22A can be used. Note that at this time, wirings are provided as appropriate in accordance with the memory cell 1170.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Seventh Embodiment
In this embodiment, an example of a semiconductor device using the transistor described in the above embodiment will be described with reference to FIGS.

In FIG. 23A, so-called DRAM (Dynamic Random Access) is shown.
An example of a semiconductor device having a configuration corresponding to that of A memory cell array 1120 shown in FIG. 23A has a configuration in which a plurality of memory cells 1130 are arranged in a matrix. The memory cell array 1120 also has m first wires and n second wires. In the present embodiment, the first wiring is referred to as a bit line BL, and the second wiring is referred to as a word line WL.

The memory cell 1130 includes a transistor 1131 and a capacitor 1132. The gate electrode of the transistor 1131 is connected to the first wiring (word line WL). Further, one of the source electrode or the drain electrode of the transistor 1131 is connected to the second wiring (bit line BL), and the other of the source electrode or the drain electrode of the transistor 1131 is connected to one of the electrodes of the capacitor ing. In addition, the other of the electrodes of the capacitive element is connected to the capacitive line CL, and a constant potential is applied. The transistor described in the above embodiment is applied to the transistor 1131.

The transistor using an oxide semiconductor described in the above embodiment for the channel formation region has a feature that off current is smaller than a transistor using single crystal silicon for the channel formation region. Therefore, when the transistor is applied to the semiconductor device illustrated in FIG. 23A, which is recognized as a so-called DRAM, a substantially nonvolatile memory can be obtained.

In FIG. 23B, so-called SRAM (Static Random Access M) is shown.
1 shows an example of a semiconductor device having a configuration corresponding to "emory". The memory cell array 1140 shown in FIG. 23B can have a structure in which a plurality of memory cells 1150 are arranged in a matrix. In addition, the memory cell array 1140 includes the first wiring BL, the second wiring BLB
And a third wiring WL, a power supply line Vdd, and a ground potential line Vss.

The memory cell 1150 includes a first transistor 1151, a second transistor 1152, a third transistor 1153, a fourth transistor 1154, and a fifth transistor 1155.
, And a sixth transistor 1156. First transistor 1151 and second
The transistor 1152 functions as a selection transistor. In addition, one of the third transistor 1153 and the fourth transistor 1154 is an n-channel transistor (here, the fourth transistor 1154), and the other is a p-channel transistor (here, the third transistor 1153). ). That is, a CMOS circuit is formed by the third transistor 1153 and the fourth transistor 1154. Similarly, a fifth circuit 1155 and a sixth transistor 1156 form a CMOS circuit.

First transistor 1151, second transistor 1152, fourth transistor 115
The fourth and sixth transistors 1156 are n-channel transistors, to which the transistors described in the above embodiments can be applied. The third transistor 1153 and the fifth transistor 1155 are p-channel transistors, and a material other than an oxide semiconductor (eg, single crystal silicon or the like) is used for a channel formation region.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Eighth Embodiment
A CPU using at least part of a transistor including an oxide semiconductor in a channel formation region
(Central Processing Unit) can be configured.

FIG. 24A is a block diagram showing a specific configuration of the CPU. C shown in FIG.
The PU is an arithmetic circuit (ALU: Arithmetic logic u) on a substrate 1190.
nit) 1191, ALU controller 1192, instruction decoder 1193
, Interrupt controller 1194, timing controller 1195, register 11
96, register controller 1197, bus interface (Bus I / F) 119
8. Rewritable ROM 1199 and ROM interface (ROM I / F)
It has 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM I / F 1189 may be provided on different chips. Of course, the CPU shown in FIG. 24A is merely an example in which the configuration is simplified, and the actual CP
U has a wide variety of configurations depending on its application.

An instruction input to the CPU via the Bus I / F 1198 is input to the instruction decoder 1193 and decoded, and then the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 119.
It is input to 5.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instruction. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Further, the interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or the mask state while the program of the CPU is being executed. The register controller 1197 generates an address of the register 1196 and performs reading and writing of the register 1196 according to the state of the CPU.

The timing controller 1195 also includes an ALU 1191 and an ALU controller 119.
2. Generate a signal that controls the operation timing of the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on a reference clock signal CLK1, and supplies the clock signal CLK2 to the various circuits.

In the CPU illustrated in FIG. 24A, the register 1196 is provided with a memory element (memory cell). The memory element (memory cell) described in any of Embodiments 5 to 7 can be used for a memory element (memory cell) of the register 1196.

In the CPU shown in FIG. 24A, the register controller 1197 is an ALU 1191.
In accordance with the instruction from, the selection of the holding operation in the register 1196 is performed. That is, in the memory element included in the register 1196, the register controller 1197 selects whether data is held by the phase inverting element or data is held by the capacitor. If retention of data by the phase inverting element is selected, the storage element in the register 1196
Supply of power supply voltage is performed. When retention of data in the capacitor is selected, data rewriting to the capacitor is performed, and supply of the power supply voltage to the storage element in the register 1196 can be stopped.

With respect to power supply stop, as shown in FIG. 24B or 24C, a switching element is provided between the memory element group and a node to which the power supply potential VDD or the power supply potential VSS is applied. Can. The circuits in FIGS. 24B and 24C will be described below.

FIGS. 24B and 24C illustrate an example of a structure of a memory circuit including a transistor in which an oxide semiconductor is used for a channel formation region as a switching element for controlling supply of power supply potential to the memory element.

The memory device illustrated in FIG. 24B includes a switching element 1141 and a memory element group 1143 including a plurality of memory elements 1142. Specifically, as each memory element 1142, the memory element described in the above embodiment can be used. Each storage element 1142 of the storage element group 1143 has a high level power supply potential V via the switching element 1141.
DD is supplied. Furthermore, each storage element 1142 of the storage element group 1143 includes
The potential of the signal IN and the potential of the low level power supply potential VSS are given.

In FIG. 24B, a transistor including an oxide semiconductor in a channel formation region is used as the switching element 1141. The switching of the transistor is controlled by a signal SigA supplied to its gate electrode.

Note that FIG. 24B illustrates a structure in which the switching element 1141 includes only one transistor; however, without particular limitation, a plurality of transistors may be included. When the switching element 1141 includes a plurality of transistors functioning as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or a combination of series and parallel May be connected.

In FIG. 24B, the supply of the high-level power supply potential VDD to each storage element 1142 of the storage element group 1143 is controlled by the switching element 1141, but the switching element 1141 controls the low level. The supply of the power supply potential VSS may be controlled.

FIG. 24C illustrates an example of a memory device in which the low-level power supply potential VSS is supplied to each of the memory elements 1142 in the memory element group 1143 through the switching element 1141. The switching element 1141 can control supply of the low-level power supply potential VSS to each of the storage elements 1142 of the storage element group 1143.

A switching element is provided between the memory element group and a node supplied with the power supply potential VDD or the power supply potential VSS, and the operation of the CPU is temporarily stopped and data is retained even when the supply of the power supply voltage is stopped. It is possible to reduce power consumption. Specifically, for example, even while a user of a personal computer stops inputting information to an input device such as a keyboard, the operation of the CPU can be stopped, thereby reducing power consumption. it can.

Here, although the CPU has been described as an example, the DSP (Digital Signal P)
rocessor), custom LSI, FPGA (Field Programmabl)
The present invention is also applicable to an LSI such as e Gate Array).

In this embodiment, a cross-sectional structure of an oxide semiconductor film to which a dopant is added is described.

A method for manufacturing an oxide semiconductor film which is a dopant to be doped is described. First, a silicon oxide film was formed to a thickness of 300 nm on a glass substrate by a sputtering method.

Next, an oxide semiconductor film of an In—Ga—Zn—O-based material (hereinafter referred to as “IGZ”) is formed over a silicon oxide film.
O film was formed by sputtering. In this example, the composition ratio is In ₂ O ₃ :
Using a target of Ga ₂ O ₃ : ZnO = 1: 1: 2 [molar ratio], the flow rate of argon is 30 sccm, the flow rate of oxygen is 15 sccm, and the substrate temperature is 400 ° C .;
An IGZO film of 0 nm was formed. The IGZO film formed under these conditions is the CAAC-OS described in Embodiment Modes 1 to 3.

Next, in order to release hydrogen in the formed IGZO film, heat treatment was performed at a heating temperature of 450 ° C. for one hour in a nitrogen atmosphere.

Next, a dopant was added to the heated IGZO film by ion implantation. In this example, the dopant is phosphorus ion (31 P ⁺ ), the acceleration voltage is 20 kV, and the doping amount is 1 × 10 ¹⁶ cm ⁻² and added to the IGZO film.

Next, with respect to the IGZO film to which the dopant (phosphorus ion) was added, the heating temperature was set to 650 ° C., and heat treatment was performed for 1 hour. In this embodiment, in the heat treatment performed after the addition of the dopant, the IGZO film in the nitrogen atmosphere is sample 1, and the IGZO film in the oxygen atmosphere is sample 2.

Transmission electron microscope (Transmission Electron Microscop
e: TEM was used to carry out cross-sectional TEM observation of Sample 1 and Sample 2. As a comparative example, the cross section of the IGZO film not subjected to the heat treatment after the addition of the dopant was also observed using a TEM. FIG. 19 (A) shows a cross-sectional TEM image of a comparative example, and FIG. 19 (B).
Shows a cross-sectional TEM image of the sample 1, and FIG. 19 (C) shows a cross-sectional TEM image of the sample 2. 19A to 19C are cross-sectional TEM images observed at a magnification of 8,000,000.

A grating image is not observed in FIG. 19A, and an electron diffraction pattern (not shown) of the comparative example.
Was a hello pattern. From this, it was confirmed that the comparative example was amorphous.

Since the lattice image is confirmed in FIG. 19B, it is confirmed that the sample 1 has a crystal part. Moreover, the electron beam diffraction pattern (not shown) of the sample 1 had a diffraction pattern which is different depending on the position where the electron beam is irradiated. In particular, in FIG. 19 (B), the crystal orientations of the IGZO films were different at the places where the contrasts were different. Therefore, it was confirmed that sample 1 has a plurality of crystal parts.

Since the lattice image is confirmed in FIG. 19C, it is confirmed that the sample 2 has a crystal part. Also, from FIG. 19 (C) and an electron diffraction pattern (not shown) of sample 2, IG
It was confirmed that the region including the surface of the ZO film is a crystal part having c-axis orientation. Furthermore, since the crystal part having the c-axis orientation is non-single crystal, the region including the surface of the IGZO film is CA.
Although it is said that it is AC-OS, at least 2 nm was formed from the surface of the IGZO film. And it was confirmed that it has a plurality of crystal parts like sample 1 except a field including the surface of an IGZO film.

From the above, it was confirmed that an oxide semiconductor film having a plurality of crystal parts can be formed by performing heat treatment performed after adding a dopant to the oxide semiconductor film. Furthermore, non-single crystal is formed in a region including the surface of the oxide semiconductor film to be formed by an atmosphere of the heat treatment.
It has been confirmed that an oxide semiconductor (CAAC-OS) including a crystal part having an axial orientation can be formed.

100 transistor 101 substrate 102 base insulating film 103 oxide semiconductor film 105 first region 107 a oxide semiconductor region 107 b oxide semiconductor region 109 a oxide semiconductor region 109 b oxide semiconductor region 111 gate insulating film 112 conductive film 113 first electrode 116a Opening 116b Opening 117 Interlayer insulating film 119a Second electrode 119b Third electrode 121 Gate insulating film 123a Second region 123b Second region 130 Oxide semiconductor film 131 Oxide semiconductor film 132 Oxide semiconductor film 140 Oxide semiconductor film 150 Dopant 160 Transistor 170 Transistor 200 Transistor 207a Oxide semiconductor region 207b Oxide semiconductor region 209a Oxide semiconductor region 209b Oxide semiconductor region 214a Oxide semiconductor region 214b Oxide semiconductor Body region 215 sidewall insulating film 223a third region 223b third region 260 transistor 270 transistor 1100 memory cell 1110 memory cell array 1111 drive circuit 1112 read circuit 1113 drive circuit 1120 memory cell array 1130 memory cell 1131 transistor 1132 capacitive element 1140 memory cell array 1141 switching element 1142 storage element 1143 storage element group 1150 memory cell 1151 transistor 1152 transistor 1153 transistor 1154 transistor 1155 transistor 1156 transistor 1160 transistor 1161 transistor 1162 transistor 1163 transistor 1164 transistor 1170 memory cell 1171 transistor 1172 Register 1173 capacitive element 1180 memory cell 1181 transistors 1182 transistors 1183 capacitive element 1189 ROM interface 1190 substrate 1191 ALU
1192 ALU controller 1193 instruction decoder 1194 interrupt controller 1195 timing controller 1196 registers 1197 register controller 1198 bus interface 1199 ROM

Claims (2)

An oxide semiconductor film,
A gate insulating film above the oxide semiconductor film;
A gate electrode above the gate insulating film,
An insulating film above the gate electrode;
A source electrode,
And a drain electrode,
The source electrode is in contact with the gate insulating film and a first portion of the surface of the oxide semiconductor film exposed from the insulating film.
The drain electrode is in contact with the gate insulating film and a second portion of the surface of the oxide semiconductor film exposed from the insulating film.
The oxide semiconductor film has a first region overlapping with the gate electrode through the gate insulating film,
The oxide semiconductor film includes a second region having a region overlapping with the source electrode,
The oxide semiconductor film includes a third region having a region overlapping with the drain electrode,
The oxide semiconductor film includes In, Ga, and Zn.
Each of the first to third regions has a plurality of crystals,
Each of the plurality of crystals in the first region has c-axis orientation,
The plurality of crystals in the second region have different crystal structures on the surface side of the second region and the lower side of the second region,
The plurality of crystals in the third region have different crystal structures on the surface side of the third region and the lower side of the third region,
The second region comprises phosphorous, arsenic, antimony or boron,
The third region comprises phosphorous, arsenic, antimony or boron,
The surface of the second region has the first portion,
The surface of the said 3rd area | region has a said 2nd part, The semiconductor device characterized by the above-mentioned. An oxide semiconductor film,
A gate insulating film above the oxide semiconductor film;
A gate electrode above the gate insulating film,
An insulating film above the gate electrode;
A source electrode,
And a drain electrode,
The source electrode is in contact with the gate insulating film and a first portion of the surface of the oxide semiconductor film exposed from the insulating film.
The drain electrode is in contact with the gate insulating film and a second portion of the surface of the oxide semiconductor film exposed from the insulating film.
The oxide semiconductor film has a first region overlapping with the gate electrode through the gate insulating film,
The oxide semiconductor film includes a second region having a region overlapping with the source electrode,
The oxide semiconductor film includes a third region having a region overlapping with the drain electrode,
The oxide semiconductor film includes In, Ga, and Zn.
Each of the first to third regions has a plurality of crystals,
Each of the plurality of crystals in the first region has c-axis orientation,
Each of the plurality of crystals on the surface side of the second region has c-axis orientation,
The plurality of crystals below the second region are different in orientation from one another,
Each of the plurality of crystals on the surface side of the third region has c-axis orientation,
The plurality of crystals below the third region are different in orientation from one another,
The second region comprises phosphorous, arsenic, antimony or boron,
The third region comprises phosphorous, arsenic, antimony or boron,
The surface of the second region has the first portion,
The surface of the said 3rd area | region has a said 2nd part, The semiconductor device characterized by the above-mentioned.