JP6550465B2 - Information processing circuit - Google Patents

Description

  The present invention relates to an information processing circuit.

  In recent years, the problem of single event upset in which information in a bit of a semiconductor is inverted has become apparent. This is because the critical charge amount of the semiconductor is reduced due to the refinement of the process rule accompanying the advancement of the semiconductor manufacturing technology. The critical charge amount is a charge amount necessary to cause inversion of data, and for example, high energy neutron radiation collides with a semiconductor and reacts to exceed the critical charge amount. When the critical charge amount is exceeded, data (in-bit information) is inverted, and single event upset occurs. High reliability is required for embedded systems intended for industrial applications, and technology development is required to reduce the effects of single event upsets occurring on arithmetic circuits. Japanese Patent Application Laid-Open No. 5-308399 (Patent Document 1) discloses a technique in which two identical circuits are arranged in parallel and operated in parallel, and an error generated on the circuit is detected by comparing the outputs.

Unexamined-Japanese-Patent No. 5-308399

  In the technique disclosed in Patent Document 1, the error detection can prevent a failure in advance, and the reliability of the system is improved. However, in the technique disclosed in Patent Document 1, doubling the number of circuits requires twice the amount of circuitry, resulting in an increase in the cost of mounting hardware. An object of the present invention is to provide an information processing circuit capable of error detection with a smaller amount of circuit than doubling the circuit.

  The outline of typical ones of the inventions disclosed in the present application will be briefly described as follows.

  An information processing circuit according to an embodiment of the present invention includes an arithmetic circuit that receives an input signal and a verification circuit that receives the input signal. The arithmetic circuit also outputs a numerical solution calculated based on the input signal to the check circuit. In addition, the check calculation circuit restores the numerical solution received from the arithmetic circuit into an input signal after restoration, and determines the presence or absence of an error based on the restored input signal after restoration and the received input signal. Output the judgment result of the presence or absence.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  According to the representative embodiment of the present invention, it is possible to realize an information processing circuit capable of error detection with a smaller amount of circuit than doubling the circuit.

FIG. 1 is a diagram showing an outline of a configuration example of an information processing circuit in Embodiment 1. FIG. 2 is a diagram showing an outline of a configuration example of a simultaneous linear equation arithmetic circuit in Embodiment 1. FIG. 2 is a diagram showing an outline of a configuration example of a simultaneous linear equation check circuit in Embodiment 1. 5 is a timing chart of an information processing circuit in Embodiment 1; 5 is a timing chart of an information processing circuit in Embodiment 1; 5 is a timing chart of an information processing circuit in Embodiment 1; 5 is a timing chart of an information processing circuit in Embodiment 1; FIG. 5 is a state transition diagram showing an operation of the information processing circuit in the first embodiment. FIG. 7 is a state transition diagram showing the operation of the simultaneous linear equation check circuit in the first embodiment. 5 is a flowchart showing an outline of processing by an information processing circuit in Embodiment 1; FIG. 6 is a flowchart showing an outline of processing by a simultaneous linear equation computing circuit in Embodiment 1. FIG. 5 is a flowchart showing an outline of processing by a simultaneous linear equation check circuit in Embodiment 1. FIG. FIG. 16 is a diagram showing an outline of a configuration example of a simultaneous linear equation arithmetic circuit in Embodiment 2. FIG. 17 is a flowchart showing an outline of processing using a CG method by a standing linear equation arithmetic circuit in Embodiment 2. FIG. FIG. 18 is a diagram showing an outline of a configuration example of a simultaneous linear equation computing circuit in a third embodiment. FIG. 16 is a flowchart showing an outline of processing using the SOR method by the simultaneous linear equation arithmetic circuit in Embodiment 3. FIG. FIG. 18 is a diagram showing an outline of a configuration example of a simultaneous linear equation computing circuit according to a fourth embodiment. FIG. 25 is a diagram showing an outline of processing using LU decomposition by a simultaneous linear equation arithmetic circuit in Embodiment 4. FIG. 25 is a diagram showing an outline of a configuration example of an information processing circuit in a fifth embodiment. FIG. 18 is a diagram showing an outline of a configuration example of a non-linear equation arithmetic circuit according to a fifth embodiment. FIG. 18 is a diagram showing an outline of a configuration example of a non-linear equation check circuit in a fifth embodiment. FIG. 20 is a flowchart showing an outline of processing by an information processing circuit in Embodiment 5. FIG. FIG. 20 is a flowchart showing an outline of processing by a non-linear equation arithmetic circuit in Embodiment 5. FIG. FIG. 20 is a flowchart showing an outline of processing by a non-linear equation check circuit in Embodiment 5. FIG. FIG. 25 is a diagram showing an outline of a configuration example of an information processing circuit in a sixth embodiment. FIG. 25 is a diagram showing an outline of a configuration example of an information processing circuit in a sixth embodiment. FIG. 25 is a diagram showing an outline of a configuration example of an information processing circuit in a sixth embodiment. FIG. 25 is a diagram showing an outline of a configuration example of an information processing circuit in a seventh embodiment. FIG. 25 is a diagram showing an outline of a configuration example of an information processing circuit in a seventh embodiment.

Embodiment 1

Hereinafter, Embodiment 1 of the present invention will be described in detail with reference to FIGS. 1 to 12. Note that, in all the drawings for describing the embodiments, the same reference numeral is attached to the same part in principle, and the repetitive description thereof will be omitted.
<Overall configuration>

  FIG. 1 is a diagram showing an outline of a configuration example of the information processing circuit 100 according to the first embodiment. As shown in FIG. 1, the information processing circuit 100 includes an input line 101, an output line 102, a notification line 103, a simultaneous linear equation calculation circuit 104, and a simultaneous linear equation check circuit 105.

  The input line 101 includes a CLK for inputting a clock, an RST for inputting a reset signal, an IVLD for inputting an operation start signal, and an IDAT for inputting an input signal.

  The input line 101 is branched when entering the information processing circuit 100, and is connected to the simultaneous linear equation calculation circuit 104 and the simultaneous linear equation check circuit 105. That is, CLK and RST, IVLD and IDAT of the input line 101 are branched inside the information processing circuit 100 and connected to the simultaneous linear equation operation circuit 104 and the simultaneous linear equation analysis circuit 105.

  An output line 102 connected to the simultaneous linear equation arithmetic circuit 104 is composed of an OVLD and an ODAT. Further, the output line 102 is branched inside the information processing circuit 100, one is connected to the upper system of the information processing circuit 100, and the other is connected to the simultaneous linear equation check circuit 105. That is, each of the OVLD and the ODAT of the output line 102 is branched inside the information processing circuit 100, one is connected to the upper system of the information processing circuit 100, and the other is connected to the simultaneous linear equation check circuit 105.

The simultaneous linear equation operation circuit 104 outputs the coefficient matrix A of the simultaneous linear equation as the input signal and the right side vector b through the input line 101, and solves the following simultaneous linear equation (Equation (1)) Calculate the numerical solution x '.
Formula (1): Ax = b

  Then, the simultaneous linear equation calculation circuit 104 sends the numerical solution x ′ calculated based on the input signal as an output signal to the simultaneous linear equation check circuit 105 via the output line 102 (output line connected to the simultaneous linear equation check circuit 105). While outputting, the numerical solution x ′ is output to the upper system of the information processing circuit 100 via the output line 102 (output line connected to the upper system).

  The simultaneous linear equation check circuit 105 receives, via the input line 101, the coefficient matrix A of the simultaneous linear equation as the input signal and the right side vector b. Further, the simultaneous linear equation check circuit 105 receives the numerical solution x ′ calculated by the simultaneous linear equation calculation circuit 104 through the output line 102. The simultaneous linear equation check circuit 105 checks the simultaneous linear equations represented by the equation (2) using the input data, the coefficient matrix A, the right side vector b, and the numerical solution x '.

Formula (2): || b-Ax '| | <epsilon

  The simultaneous linear equation check circuit 105 restores the numerical solution x ′ received from the simultaneous linear equation operation circuit 104 into a right side vector b ′ which is an input signal after restoration, and the right side vector b ′ of the right side vector and the right side vector of the input signal By checking the simultaneous linear equations based on b and b, the presence or absence of an error is determined. Then, the simultaneous linear equation check circuit 105 outputs an error determination result indicating the determination result of the presence or absence of an error to the upper system via the notification line 103. For example, the simultaneous linear equation check circuit 105 restores the right-hand side vector b 'by performing a matrix-vector product of the coefficient matrix A and the numerical solution x', and restores the right-hand side vector b previously received as an input signal. Compare with the right-hand side vector b '. Further, in order to compare the right-hand side vector b 'obtained by the calculation and the received right-hand side vector b, the simultaneous linear equation check circuit 105 calculates the norm of the difference || b-b' || Compare the norm || b-b '|| with the tolerance error epsilon.

Here, the reason for introducing the tolerance error epsilon is that the real number operation is affected by the rounding error. The numerical solution x 'of real operations such as simultaneous linear equations is different from the true solution x, and the right side vector b' restored by the real operation is different from the original right side vector b. Therefore, by introducing the tolerance error epsilon, it is evaluated that the numerical solution x 'exists in the vicinity of the true solution x by the above-mentioned equation (2). The simultaneous linear equation check circuit 105 has no error in the numerical solution x ′ when the equation (2) holds (when || b−b ′ || is less than the tolerance error epsilon), therefore the simultaneous linear equation It is determined that the arithmetic circuit 104 has no error. On the contrary, when the equation (2) does not hold (when || b−b ′ || is equal to or larger than the tolerance error epsilon), the simultaneous linear equation check circuit 105 has an error in the numerical solution x ′. Therefore, it is determined that the simultaneous linear equation arithmetic circuit 104 has an error. The simultaneous linear equation check circuit 105 outputs an error determination result indicating the determination result of the presence or absence of an error to the upper system via the notification line 103.
<Detailed configuration>

  FIG. 2 is a diagram showing an outline of a configuration example of the simultaneous linear equation arithmetic circuit 104 in the first embodiment.

  As shown in FIG. 2, the simultaneous linear equation operation circuit 104 outputs an input line 101 for inputting the coefficient matrix A and the right side vector b of the simultaneous linear equation (Ax = b) and a numerical solution x ′. , The bus 110, the simultaneous linear equation operation control unit 111, the operation unit 112, and the operation data holding unit 113.

  The input line 101 and the output line 102 are connected to the bus 110. The simultaneous linear equation operation control unit 111, the operation unit 112, and the operation data holding unit 113 are connected to one another via a bus 110.

  Arithmetic unit 112 performs processing required to obtain numerical solution x ′ (processing of S142 to S144, processing of S147 and S148 described later), matrix vector product operation unit 114, scalar vector product operation unit 115 The vector product-sum operation unit 116, the vector inner product operation unit 117, the Givens rotation operation unit 118, and the backward substitution operation unit 119.

  The arithmetic data holding unit 113 has a storage area capable of storing primary data generated in the middle of GMRES method arithmetic, and includes a queue 125 of the same size as the arithmetic data holding unit 124 of the simultaneous linear equation check circuit 105. The calculation data holding unit 113 includes the queue 125 of the same size as the calculation data holding unit 124 of the simultaneous linear equation check circuit 105 because the throughputs of the simultaneous linear equation calculation circuit 104 and the simultaneous linear equation check circuit 105 are different. It is for equality.

  The simultaneous linear equation operation control unit 111 performs state transition shown in FIG. 8 described later according to the reset signal and the operation start signal, and inputs signals (coefficient matrix A and right side vector b) to the operation data holding unit 113. Temporarily save the

  In addition, the simultaneous linear equation operation control unit 111 calls the operation unit 112 according to the process (described later, FIG. 11) by the simultaneous linear equation operation circuit 104, and the operation data holding unit 113 of the data generated during the operation. Save and read out.

  Further, when the numerical solution x 'is calculated as a result of the calculation, the simultaneous linear equation calculation control unit 111 outputs the numerical solution x' as an output signal from the output line 102 together with the calculation end signal.

  FIG. 3 is a diagram showing an outline of a configuration example of the simultaneous linear equation check circuit 105 according to the first embodiment.

  As shown in FIG. 3, the simultaneous linear equation check circuit 105 outputs an input line 101 for inputting the coefficient matrix A and the right side vector b of the simultaneous linear equation (Ax = b), and an output of the simultaneous linear equation calculation circuit 104. An output line 102 for receiving a numerical solution x ′ of the simultaneous linear equations (Ax = b), a notification line 103 for notifying the upper system of an error determination result by the simultaneous linear equation check circuit 105, a bus 110, A simultaneous linear equation verification control unit 120, an arithmetic unit 123, and an arithmetic data holding unit 124 are included.

  The input line 101, the output line 102, and the notification line 103 are connected to the bus 110. Further, the simultaneous linear equation check control unit 120, the operation unit 123, and the operation data holding unit 124 are mutually connected via the bus 110. The simultaneous linear equation check control unit 120, the operation unit 123, and the operation data holding unit 124 mutually communicate operation data and input / output signals via the bus 110.

  Operation unit 123 performs matrix vector product operation unit 114, vector product-sum operation unit 116, and vector inner product operation for performing processing necessary for determining the presence or absence of an error (processing of S151 to be described later). And a unit 117.

  The operation data holding unit 124 functions as a storage area of intermediate data of operation, and includes a queue 125 for accumulating input signals (coefficient matrix A and right side vector b).

  The simultaneous linear equation verification control unit 120 includes a comparison unit 121, in which a tolerance error 122 is stored.

  The simultaneous linear equation check control unit 120 performs the state transition shown in FIG. 9 described later according to the reset signal 1, the operation start signal and the operation end signal, and also outputs an input signal and an output signal to the operation data holding unit 124 Temporarily save and read out.

  In addition, the simultaneous linear equation check control unit 120 calls the operation unit 123 according to the process (described later, FIG. 12) by the simultaneous linear equation check circuit 105, and the operation data holding unit 124 of the data generated in the middle of the operation. Save and read out.

  Further, the simultaneous linear equation check control unit 120 determines the presence or absence of an error in the information processing circuit 100 from the comparison result, and outputs the error determination result from the notification line 103.

  The circuit area of the information processing circuit 100 according to the first embodiment will be described below. Assuming that the circuit area of the simultaneous linear equation calculation circuit 104 in the first embodiment is Sm and the circuit area of the simultaneous linear equation check circuit 105 is Sv, the circuit area of the information processing circuit 100 is a value obtained by adding Sv to Sm (Sm + Sv). It is. In addition, the circuit area when the simultaneous linear equation arithmetic circuit 104 is doubled is twice as large as Sm (2.times.Sm).

  Assuming that the circuit area of simultaneous linear equation operation control unit 111, which is a component of simultaneous linear equation operation circuit 104, is Sm0, the circuit area of operation unit 112 is Sm1, and the circuit area of operation data holding unit is Sm2, the following equation (3) Is true.

Formula (3): Sm = Sm0 + Sm1 + Sm2

  Assuming that the circuit area of the simultaneous linear equation check control unit, which is a component of the simultaneous linear equation check circuit 105, is Sv0, the circuit area of the operation unit 123 is Sv1, and the circuit area of the operation data holding unit is Sv2, the following equation (4 ) Holds.

Formula (4): Sv = Sv0 + Sv1 + Sv2

By comparing the processing by the simultaneous linear equation calculation circuit 104 (described later with reference to FIG. 11) and the processing by the simultaneous linear equation checking circuit 105 (described with reference to FIG. 12), the simultaneous linear equation operation control unit It can be seen that 111 is performing complicated arithmetic control. Therefore, the following equation (5) holds.
Formula (5): Sm0> Sv0

Further, the arithmetic unit 112 of the simultaneous linear equation arithmetic circuit 104 performs an inner product arithmetic unit 117 of a plurality of vectors, a Givens rotation arithmetic unit 118, and a backward substitution arithmetic unit 119 with respect to the arithmetic unit 123 of the simultaneous linear equation check circuit 105. And. Therefore, the following equation (6) holds.
Formula (6): Sm1> Sv1

It is known that the GMRES method requires a storage area for storing k vectors in order to obtain a numerical solution x '. On the other hand, it is only necessary to store one vector of storage area necessary for the check calculation. Considering that the throughputs of the simultaneous linear equation calculation circuit and the simultaneous linear equation check circuit are equal and the sizes of the queues are equal, the following equation (7) holds.
Formula (7): Sm2> Sv2

Then, the following equation (8) is established from the equations (3), (4), (5), (6) and (7).
Formula (8): 2 × Sm> Sm + Sv

  Therefore, the circuit area of the information processing circuit 100 of the present invention is smaller than the circuit area obtained by doubling the simultaneous linear equation arithmetic circuit 104.

  Since the information processing circuit 100 of the present invention performs calculation of simultaneous linear equations after performing calculation of simultaneous linear equations, the time for error detection is more in comparison with duplexing. That is, there is a trade-off between execution time and circuit area, and it is necessary to design with that in mind.

  <Timing chart of information processing circuit>

  FIGS. 4, 5, 6, and 7 are timing charts of the information processing circuit 100 according to the first embodiment, showing the anteroposterior relationship of each signal. As shown in FIGS. 4 to 7, the clock 182 is input to the information processing circuit 100 through the CLK of the input line 101, and the upper system and the simultaneous linear equation calculation circuit 104 and the simultaneous linear equation check calculation are performed by the clock 182. The circuit 105 operates in synchronization.

  FIG. 4 shows the initialization of simultaneous linear equation arithmetic circuit 104 and simultaneous linear equation analysis circuit 105, which are internal circuits of information processing circuit 100, when reset signal 184 is input from the host system via RST of input line 101. It is a timing chart which shows the situation of. When receiving the reset signal 184, the simultaneous linear equation arithmetic circuit 104 performs storage area initialization 185. Also, upon receiving the reset signal 184, the simultaneous linear equation check circuit 105 performs initialization 186 of the internal storage area. As a result, the simultaneous linear equation calculation circuit 104 and the simultaneous linear equation check circuit 105 can be operated.

  FIG. 5 is a timing chart showing how the simultaneous linear equation computation circuit 104 starts computation when the computation start signal 187 is input from the host system via the IVLD of the input line 101. Upon receipt of the operation start signal 187, the simultaneous linear equation calculation circuit 104 starts the simultaneous linear equation calculation 189 and the input signal 188 via the IDAT of the input line 101, that is, the aforementioned simultaneous linear equations (Ax = b) And the right-hand side vector b.

  The simultaneous linear equation check circuit 105 enters the idle state 183 by receiving the operation start signal 187, and receives the input signal 188 (coefficient matrix A and right side vector b) through the IDAT.

  FIG. 6 is a timing chart showing how the simultaneous linear equation check circuit 105 starts the checkup operation when the operation end signal 190 is outputted from the simultaneous linear equation calculation circuit 104 via the OVLD of the output line 102. When the simultaneous linear equation calculation circuit 104 completes the calculation 189 of the simultaneous linear equations, the simultaneous linear equation calculation circuit 104 outputs an operation end signal 190 to the simultaneous linear equation check circuit 105. At this time, the simultaneous linear equation check circuit 105 ends the idle state 183 and starts the check 192 of the simultaneous linear equations.

  After outputting the operation end signal 190, the simultaneous linear equation calculation circuit 104 outputs the output signal 191, that is, the numerical solution x 'of the simultaneous linear equation to the simultaneous linear equation check circuit 105 via the ODAT of the output line 102. After receiving the output signal 191 (numerical solution x '), the simultaneous linear equation check circuit 105 performs a check 192 of the simultaneous linear equations.

FIG. 7 is a timing chart showing how the error judgment result 193 is output when the simultaneous linear equation check circuit 105 finishes the check 192 of the simultaneous linear equation. The simultaneous linear equation check circuit 105 outputs an error judgment result 193 to the upper system from the result of the check 192 of the simultaneous linear equations. The host system receives the error determination result 193 and determines whether to continue processing using the output signal 191 or not. The simultaneous linear equation check circuit 105 may output an error determination result 193 indicating that there is an error to the host system only when it determines that there is an error.
<State transition>

  FIG. 8 is a state transition diagram showing an operation of the information processing circuit 100 in the first embodiment.

  The state 170 is a so-called initial state in which the information processing circuit 100 has stopped operating.

  A state 171 is an initialization state in which the simultaneous linear equation calculation circuit 104 and the simultaneous linear equation check circuit 105 of the information processing circuit 100 initialize their internal storage areas.

  The state 172 is an idle state in which the information processing circuit 100 is waiting for the input of the operation start signal 187 and the input signal 188 (coefficient matrix A and right side vector b) from the upper system.

  A state 173 is a state in which the simultaneous linear equation computation circuit 104 of the information processing circuit 100 is performing the computation 189.

  A state 174 is a state in which the simultaneous linear equation check circuit 105 of the information processing circuit 100 is performing a check 192.

  In the state 175, since the upper system receives the error determination result 193 indicating that there is an error from the simultaneous linear equation check circuit 105, the operation of the information processing circuit 100 is stopped and processing by the alternative system is performed. is there. At this time, an error due to a single event upset has occurred in the information processing circuit 100.

  In the state 170 (initial state), the information processing circuit 100 receives a reset signal 184 from the host system, thereby performing state transition 280 from the state 170 (initial state) to the state 171 (initialization state).

  In the state 171 (initialization state), the simultaneous linear equation arithmetic operation circuit 104 and the simultaneous linear equation check circuit 105 of the information processing circuit 100 complete initialization of their storage areas, whereby the state 171 (initialization) is automatically performed. State transition 281 to state 172 (idle state).

  In state 172 (idle state), when the information processing circuit 100 receives the reset signal 184 from the host system, the state transition 282 is made from the state 172 (idle state) to the state 171 (initialization state).

  In state 172 (idle state), the information processing circuit 100 receives the operation start signal 187 and the coefficient matrix A which is the input signal 188 and the right-hand vector b from the upper system, and from state 172 (idle state) State transition 283).

  When the information processing circuit 100 receives the reset signal 184 from the host system in the state 173 (operation in progress), the state transition 284 is made from the state 173 (operation in operation) to the state 171 (initialization state).

  In the state 173 (state under calculation), the simultaneous linear equation calculation circuit 104 of the information processing circuit 100 ends the calculation 189, and the upper system and the simultaneous linear equation check circuit 105 the calculation end signal 190 and the output signal (numerical solution x ' The state transition 285 is made from the state 173 (operational state) to the state 174 (state under calculation) by outputting the) 191.

  When the information processing circuit 100 receives the reset signal 184 from the host system in the state 174 (state under calculation), the state transition 286 is made from the state 174 (state under calculation) to the state 171 (initialization state).

  In state 174 (state under check calculation), simultaneous linear equation check circuit 105 of information processing circuit 100 ends check calculation 192, and notifies upper level system of error judgment result 193 indicating no error, so that state 174 automatically. A state transition 287 is made from (state under calculation) to state 172 (idle state).

  In state 174 (state under checkup), simultaneous linear equation checkout circuit 105 of information processing circuit 100 ends checkout 192 and notifies the upper system of error judgment result 193 indicating that there is an error; A state transition 288 is made from the state under verification to the state 175 (fail safe state).

  FIG. 9 is a state transition diagram showing the operation of the simultaneous linear equation check circuit 105 in the first embodiment.

  The state 160 is a so-called initial state in which the simultaneous linear equation check circuit 105 does not operate and is stopped.

  A state 161 is an initialization state in which the simultaneous linear equation checking circuit 105 performs storage area initialization 185.

  The state 162 is an idle state (idle state A) in which the simultaneous linear equation check circuit 105 is waiting for the input of the operation start signal 187 and the input signal 188 from the host system. In state 162 (idle state A), simultaneous linear equation calculation circuit 104 and simultaneous linear equation check circuit 105 included in information processing circuit 100 receive calculation start signal 187 and input signal (coefficient matrix A and right side vector) from the upper system. b) Wait for the input of 188.

  The state 163 is an idle state (idle state B) in which the simultaneous linear equation check circuit 105 waits for the input of the operation end signal 190 and the output signal 191 from the simultaneous linear equation calculation circuit 104. In state 163 (idle state B), simultaneous linear equation calculation circuit 104 included in information processing circuit 100 calculates output signal (numerical solution x ') 191, and simultaneous linear equation check circuit 105 calculates simultaneous linear equations. Waiting for the input of the operation end signal 190 and the output signal 191 from the circuit 104.

  The state 164 is a state under check in which the simultaneous linear equation check circuit 105 performs check 192 and the determination of the above-mentioned equation (2) is performed.

  In the state 160 (initial state), the simultaneous linear equation check circuit 105 receives a reset signal 184 from the host system, and makes a state transition 290 from the state 160 (initial state) to the state 161 (initialization state).

  The state transition 291 from the state 161 (initialization state) to the state 162 (idle state A) is automatically performed by the simultaneous linear equation check circuit 105 ending the initialization 185 of the storage area in the state 161 (initialization state). Do.

  In the state 162 (idle state A), when the simultaneous linear equation check circuit 105 receives the reset signal 184 from the host system, the state transition 292 is made from the state 162 (idle state A) to the state 161 (initialization state).

  In state 162 (idle state A), simultaneous linear equation check circuit 105 receives coefficient start signal 187 and coefficient matrix A which is input signal 188 from the upper system, and state 162 (idle state A). State transition 293 to state 163 (idle state B). At this time, the simultaneous linear equation check circuit 105 stores the input signal 188 in the storage area queue.

  In state 162 (idle state A), the simultaneous linear equation check circuit 105 receives the operation end signal 190 and the numerical solution x ′ which is the output signal 191 from the simultaneous linear equation operation circuit 104, and thereby the state 162 (idle state A). State transition 294 to state 164 (state under calculation). At this time, the simultaneous linear equation check circuit 105 takes out the coefficient matrix A which is the input signal 188 and the right side vector b from the queue of the storage area and uses it for the calculation.

  In the state 163 (idle state B), the simultaneous linear equation check circuit 105 receives a reset signal 184 from the host system, and makes a state transition 295 from the state 163 (idle state B) to the state 161 (initialization state).

  In state 163 (idle state B), simultaneous linear equation check circuit 105 receives operation end signal 190 and output signal 191 from simultaneous linear equation operation circuit 104, and from state 163 (idle state B) to state 164 (under test calculation). State transition 296). At this time, the simultaneous linear equation check circuit 105 reads the input signal 188 from the storage area queue and uses it for calculation.

  In the state 163 (idle state B), when the simultaneous linear equation check circuit 105 receives the operation start signal 187 and the input signal 188 from the host system, the state 163 (idle state B) remains (state transition 297). At this time, the simultaneous linear equation check circuit 105 stores the input signal 188 in the storage area queue.

  In the state 164 (state under check), the simultaneous linear equations check circuit 105 receives a reset signal 184 from the host system, and makes a state transition 298 from the state 164 (state under check) to a state 161 (initialization state).

In state 164 (state under check), simultaneous linear equation check circuit 105 ends check 192 and notifies error judgment result 193 to the upper system, so that state 164 (state under check) is automatically changed to state 162 (idle). State transition 299 is made to state A).
<Flow chart>

  FIG. 10 is a flowchart showing an outline of processing by the information processing circuit 100 according to the first embodiment.

  First, at S130, the information processing circuit 100 receives the coefficient matrix A of the simultaneous linear equations and the right side vector b from the host system. Then, the simultaneous linear equation calculation circuit 104 and the simultaneous linear equation check circuit 105 of the information processing circuit 100 receive the number matrix A and the right side vector b via the input line 101.

  Next, in S131, processing (described later, FIG. 11) by the simultaneous linear equation arithmetic circuit 104 is executed. Then, the simultaneous linear equation calculation circuit 104 calculates the numerical solution x ′ of the simultaneous linear equation (Ax = b) based on the coefficient matrix A and the right side vector b.

  Next, in S132, the simultaneous linear equation calculation circuit 104 outputs the numerical solution x ′ of the simultaneous linear equation (Ax = b), which is the calculation result, to the upper system via the output line 102 and the simultaneous first order It outputs to the equation check circuit 105.

  Next, in S133, a process (described later, FIG. 12) by the simultaneous linear equation check circuit 105 is performed.

  Next, in S 134, the simultaneous linear equation check circuit 105 outputs the error determination result 193 to the upper system via the notification line 103.

  FIG. 11 is a flowchart showing an outline of processing (S131) by the simultaneous linear equation computing circuit 104 according to the first embodiment. In the first embodiment, the GMRES method is used as an algorithm for solving simultaneous linear equations. The GMRES method is an algorithm for efficiently searching for solutions of simultaneous linear equations (Ax = b) from the Krylov subspace while expanding the basis of the Krylov subspace by repeating matrix-vector product. That is, the processing by the simultaneous linear equation computing circuit 104 shown in FIG. 11 is based on the GMRES algorithm.

  First, in S140, the simultaneous linear equation arithmetic circuit 104 calculates the residual r0 = b−Ax0 from the appropriate initial solution x0, and generates a first basis vector q0 = r0 / | r0 ||. A random value is set to the initial solution x0.

  Next, in S141, the simultaneous linear equation computation circuit 104 initializes a loop variable i to one.

  Next, in S142, the simultaneous linear equation operation circuit 104 calculates the matrix vector product v = Aq (i-1) of the coefficient matrix A of the simultaneous linear equation and the (i-1) -th base vector q (i-1). Extend the basis of the Krylov subspace by doing.

  Next, in S143, the simultaneous linear equation computation circuit 104 performs the orthonormalization of the vector v and the orthonormal basis {q0,..., Q (i-1)} of the Krylov subspace to normalize the i-th line. Find an orthogonal basis vector qi. In this process, an inner product operation and a product-sum operation of a vector are required.

  Next, in S144, the simultaneous linear equation computation circuit 104 performs QR decomposition of the Hessenberg matrix by Givens rotation.

  Next, in S145, the simultaneous linear equation computation circuit 104 compares the maximum iteration number k with the loop variable i. Then, as a result of comparison by the simultaneous linear equation arithmetic circuit 104, if i is less than k (i <k), the process proceeds to step 146 to repeat the loop. On the other hand, if i is equal to or larger than k as a result of comparison by the simultaneous linear equation arithmetic circuit 104, the process proceeds to step 147.

  Next, at S146, the simultaneous linear equation computation circuit 104 increments the loop variable i (i = i + 1). After S146, the process returns to S142.

  When it is determined in S145 that i is equal to or greater than k, the simultaneous linear equation computation circuit 104 obtains the numerical solution x ′ of the simultaneous linear equation (Ax = b) by the linear combination of the generated orthonormal basis in S147. In order to determine the coefficients {y0,..., Yk} of each basis. For this purpose, the simultaneous linear equation arithmetic circuit 104 obtains a kth simultaneous linear equation by back substitution using the upper triangular matrix R obtained by QR decomposition of the Hessenberg matrix as a coefficient matrix.

  Next, in S148, the simultaneous linear equation calculation circuit 104 obtains a numerical solution x 'of the simultaneous linear equation (Ax = b) from the sum of the generated orthonormal base and the respective coefficients. For this purpose, the simultaneous linear equation operation circuit 104 needs to perform k-times product sum operation of vectors.

  FIG. 12 is a flowchart showing an outline of processing (S133) by the simultaneous linear equation check circuit 105 according to the first embodiment.

  First, in S150, the simultaneous linear equation check circuit 105 calculates the norm || b || of the right side vector b. The Euclidean norm is used as the norm, and the simultaneous linear equation check circuit 105 stores the square root of the calculation result of the inner product calculation of the vectors b and b as the norm || b ||. Further, the simultaneous linear equation check circuit 105 calculates the distance between the numerical solution x ′ output from the simultaneous linear equation calculation circuit 104 and the true solution x of the simultaneous linear equation by the residual norm || r ||. Note that the simultaneous linear equation check circuit 105 obtains a residual (r = b−Ax) by calculation of matrix-vector product and vector sum.

  Next, in S151, the operation unit 123 of the simultaneous linear equation check circuit 105 obtains the relative error || r || / || b || by dividing the floating point number of the scalar value, and the relative error || r | Compare | / || b || with tolerance epsilon. The floating point number used in the information processing circuit 100 is a double precision floating point number defined by IEEE754, and is set to a tolerance error of approximately 1.0e-8. If the relative error || r || / || b || satisfies the tolerance error epsilon (if the relative error is less than the tolerance), the process proceeds to step 152. On the other hand, if the relative error deviates from the allowable error (if the relative error is equal to or larger than the allowable error), the process proceeds to step 153.

  If the relative error is less than the allowable error, the simultaneous linear equation check circuit 105 determines in S152 that there is no error in the arithmetic unit.

On the other hand, if the relative error is equal to or greater than the allowable error, the simultaneous linear equation check circuit 105 determines in S153 that there is an error in the arithmetic unit.
<Effect of Embodiment 1>

According to the information processing circuit 100 in the first embodiment described above, the simultaneous linear equation check circuit 105, which is a check operation circuit, restores the numerical solution output from the simultaneous linear equation operation circuit 104, which is an operation circuit (right side By determining the presence or absence of an error based on the restored input signal after the restoration to the vector b ′) and the received input signal (right side vector b), error detection can be performed even if the circuit amount is reduced. For example, in comparison with the case where two simultaneous linear equation operation circuits 104 are provided, an inner product operation unit 117 of a plurality of vectors, a Givens rotation operation unit 118, and a back substitution operation unit are obtained from one simultaneous linear equation operation circuit 104. Even if 119 is excluded, error detection becomes possible.
Second Embodiment

  The simultaneous linear equations (Ax = b) need to select an appropriate solution according to the type of the coefficient matrix A. When the coefficient matrix A is a dense matrix, as a solution method, a direct method is used which makes it easy to find a solution by decomposing the matrix into a simple matrix product. When the coefficient matrix A is a sparse matrix, an iterative method is used as a solution method in which the numerical solution x 'is approximated to the true solution x by iteratively calculating a function mainly based on a matrix-vector product.

  The iterative method is roughly divided into two types, a stationary iterative method and a non-stationary iterative method. The nonstationary iterative method is widely used as a high-speed method to reach a solution with at most N iterations when the vector length is N. The nonstationary iterative method used when the coefficient matrix A is sparse and asymmetric is the GMRES method, and the nonstationary iterative method used when the coefficient matrix A is a sparse matrix and symmetric positive definite is the CG method is there.

In the first embodiment, the simultaneous linear equation operation circuit 104 obtains the solution of the simultaneous linear equation (Ax = b) by the GMRES method, whereas in the second embodiment, the solution of the simultaneous linear equation (Ax = b) is obtained. The difference is that CG method is used as an algorithm for obtaining. Hereinafter, the difference between the second embodiment of the present invention and the first embodiment will be mainly described with reference to FIG. 13 and FIG.
<Detailed configuration>

  FIG. 13 is a diagram showing an outline of a configuration example of the simultaneous linear equation arithmetic circuit 104 in the second embodiment.

  The simultaneous linear equation arithmetic circuit 104 shown in FIG. 13 has a circuit configuration that implements processing using the CG method (described later, FIG. 14).

  The operation unit 112 includes a matrix vector product operation unit 114, a vector product-sum operation unit 116, a vector inner product operation unit 117, and an incomplete LU decomposition pre-processing unit 206 in order to process an operation required by the CG method. Have.

As in the first embodiment, the equation (8): 2 × Sm> Sm + Sv described above also holds in the second embodiment. That is, even when compared with the circuit area of the information processing circuit 100 that solves the conventional CG method, the circuit area of the information processing circuit 100 of the second embodiment that solves the CG method is smaller.
<Flow chart>

  FIG. 14 is a flowchart showing an outline of processing using the CG method by the simultaneous linear equation computing circuit 104 according to the second embodiment.

First, in S200, the simultaneous linear equation arithmetic circuit 104 calculates the residual r0 = b−Ax0 from the appropriate initial solution x0, and generates a first orthogonal vector. Here, it is known that the number of iterations in the iterative method depends on the eigenvalue distribution of the coefficient matrix A, and by improving the eigenvalue distribution, the number of iterations is reduced, and it is possible to solve simultaneous linear equations at high speed. is there. Therefore, the general iterative method preprocesses the matrix. When pre-processing a matrix, the simultaneous linear equation operation circuit 104 solves the following equations (9) and (10).
Formula (9): AMy = b
Formula (10): My = x

  Degeneration of the eigenvalues of the matrix AM reduces the number of iterations. When performing matrix preprocessing, it is necessary to solve Mz (i) = r (i) in the algorithm. In this step, Mz0 = r0 is solved.

  Next, in S201, the simultaneous linear equation arithmetic circuit 104 initializes a loop variable i to one.

  Next, in S202, the simultaneous linear equation computing circuit 104 generates a gradient vector p by computing a matrix-vector product of the coefficient matrix A and the orthogonal vector r, and extends the Krylov subspace.

  Next, in S203, the simultaneous linear equation computing circuit 104 updates the orthogonal basis vector and the solution vector by an inner product operation of vectors and a product-sum operation of vectors.

  Next, in S204, the simultaneous linear equation computation circuit 104 performs preprocessing of the coefficient matrix A by solving Mz (i) = r (i) by the incomplete LU decomposition.

  Next, in S205, the simultaneous linear equation computing circuit 104 updates the gradient vector by the inner product operation of the vector and the product-sum operation of the vector.

  Next, in S206, the simultaneous linear equation computation circuit 104 performs convergence determination by confirming whether the value of the inner product obtained in S204 is smaller than the allowable error. When a rounding error is accumulated in the value of the inner product, the convergence determination is performed by determining the following equation (11) using the numerical solution x (i) of the ith iteration. If the simultaneous linear equation computation circuit 104 determines that convergence has occurred (S206-YES), the process ends. On the other hand, when the simultaneous linear equation arithmetic circuit 104 determines that the convergence has not occurred (S206-NO), the process proceeds to S207.

Formula (11): || b-Ax (i) || / || b || <epsilon

Next, in S207, the simultaneous linear equation computation circuit 104 increments the loop variable i (i = i + 1). After S207, the process returns to S202.
<Effect of Second Embodiment>

  According to the information processing circuit 100 in the second embodiment described above, the same effects as in the first embodiment can be obtained by the simultaneous linear equation calculation circuit 104 which is a calculation circuit solving the simultaneous linear equations using the iterative method. In addition, the time until an error is detected can be shortened.

In addition to the same effect as that of the first embodiment, the simultaneous linear equations operation circuit 104 uses the CG method, and even if the coefficient matrix A is a sparse matrix and a symmetric positive definite value, the simultaneous linear equations It becomes easy to solve.
Third Embodiment

In the first embodiment, the simultaneous linear equation operation circuit 104 obtains the solution of the simultaneous linear equation (Ax = b) by the GMRES method, whereas in the third embodiment, the solution of the simultaneous linear equation (Ax = b) is obtained. The difference is that the SOR method is used as an algorithm for obtaining. The SOR method is one of stationary iteration methods and is known to be easy to program although its speed is inferior to non-stationary iterative methods. The differences between the third embodiment of the present invention and the first embodiment will be mainly described below with reference to FIGS.
<Detailed configuration>

  FIG. 15 is a diagram showing an outline of a configuration example of the simultaneous linear equation arithmetic circuit 104 in the third embodiment. The simultaneous linear equation computing circuit 104 shown in FIG. 15 has a circuit configuration that implements processing using an SOR method (described later, FIG. 16). That is, the arithmetic unit 112 of the simultaneous linear equation arithmetic circuit 104 performs the operation equivalent to matrix vector multiplication, the operation equivalent to the product-sum operation of vectors, and the operation equivalent to the preprocessing of the matrix to obtain the update vector of the solution vector. A matrix pre-processing unit 213 for determining r is included.

As in the first embodiment, the equation (8): 2 × Sm> Sm + Sv also holds in the third embodiment. That is, the circuit area of the information processing circuit 100 according to the third embodiment for solving the CG method is smaller than that of the information processing circuit 100 for solving the conventional CG method.
<Flow chart>

  FIG. 16 is a flowchart showing an outline of processing using the SOR method by the simultaneous linear equation computation circuit 104 according to the third embodiment.

  First, at S210, the simultaneous linear equation arithmetic circuit 104 initializes a loop variable i to one.

  Next, at S211, the simultaneous linear equation arithmetic circuit 104 updates the solution vector by performing an operation equivalent to matrix-vector product, an operation equivalent to product-sum operation of vector, and an operation equivalent to preprocessing of matrix. Find the vector (residual) r.

  Next, in S212, the simultaneous linear equation arithmetic circuit 104 multiplies the acceleration parameter by the acceleration vector by the product-sum operation of the vector, and adds it to the solution vector.

  Next, in S213, the simultaneous linear equation computation circuit 104 determines convergence by determining the following equation (11) using the numerical solution x (i) of the ith iteration. If the simultaneous linear equation computation circuit 104 determines convergence (S213-YES), the process ends. On the other hand, when the simultaneous linear equation arithmetic circuit 104 determines that the convergence has not occurred (S213-NO), the process proceeds to S214.

Formula (11): || b-Ax (i) || / || b || <epsilon

Next, in S214, the simultaneous linear equation computation circuit 104 increments the loop variable i (i = i + 1). After S214, the process returns to S211.
<Effect of Embodiment 3>

According to the information processing circuit 100 in the third embodiment described above, the same effects as in the first embodiment can be obtained by using the SOR method to solve the simultaneous linear equations by the simultaneous linear equation calculation circuit 104, which is an arithmetic circuit. In addition, programming necessary to realize the information processing circuit 100 is facilitated.
Embodiment 4

In the first embodiment, the simultaneous linear equation operation circuit 104 obtains the solution of the simultaneous linear equation (Ax = b) by the GMRES method, while in the fourth embodiment, the simultaneous linear equation operation circuit 104 performs the LU decomposition. The difference is that the simultaneous linear equations (Ax = b) are solved. The LU factorization divides the coefficient matrix A into an upper triangular matrix L and a lower triangular matrix U. After decomposition, first solve a simple simultaneous linear equation of Ly = b by forward substitution, and then solve a simple simultaneous equation of Ux = y by backward substitution. The differences between the fourth embodiment of the present invention and the first embodiment will be mainly described below with reference to FIGS.
<Detailed configuration>

  FIG. 17 is a diagram showing an outline of a configuration example of the simultaneous linear equation calculation circuit 104 in the fourth embodiment. The simultaneous linear equation computing circuit 104 shown in FIG. 17 has a circuit configuration for realizing a process (described later, FIG. 18) using LU decomposition by the simultaneous linear equation computing circuit 104. That is, operation unit 112 of simultaneous linear equation operation circuit 104 performs scalar vector product operation unit 223 for performing processing of decomposing coefficient matrix A into upper triangular matrix L and lower triangular matrix U, and vector product operation unit 224 and a matrix sum operation unit 225. The arithmetic unit 112 of the simultaneous linear equation arithmetic circuit 104 includes a forward substitution operation unit 226 which solves a simple simultaneous linear equation of Ly = b by forward substitution. The arithmetic unit 112 of the simultaneous linear equation arithmetic circuit 104 includes a backward substitution operation unit 119 which solves a simple simultaneous linear equation of Ux = y by backward substitution.

As in the first embodiment, the equation (8): 2 × Sm> Sm + Sv also holds in the fourth embodiment. That is, the circuit area of the information processing circuit 100 according to the fourth embodiment for solving the CG method is smaller than the circuit area of the simultaneous linear equation calculation circuit 104 for solving the conventional CG method.
<Flow chart>

  FIG. 18 is a diagram showing an outline of processing using LU decomposition by the simultaneous linear equation computation circuit 104 according to the fourth embodiment.

  First, at S220, the simultaneous linear equation computing circuit 104 decomposes the coefficient matrix A into an upper triangular matrix L and a lower triangular matrix U by a known technique. At this time, the simultaneous linear equation arithmetic circuit 104 performs a scalar vector product operation, a vector vector product operation, and a matrix sum operation.

  Next, in S221, the simultaneous linear equation computation circuit 104 solves a simple (upper triangular matrix) simultaneous linear equation of Ly = b by forward substitution.

Next, in S222, the simultaneous linear equation computation circuit 104 solves a simple (lower triangular matrix) simultaneous linear equation of Ux = y by back substitution.
<Effect of Fourth Embodiment>

According to the information processing circuit 100 in the fourth embodiment described above, the simultaneous linear equations arithmetic circuit 104 which is an arithmetic circuit solves the simultaneous linear equations by LU decomposition to solve when the coefficient matrix A is a dense matrix. Make it easier to
Fifth Embodiment

In the first embodiment, the information processing circuit 100 solves a simultaneous linear equation (Ax = b) which is a linear equation, whereas in the fifth embodiment, the information processing circuit 100 has nonlinearity shown in the following equation (11). It differs in the point which solves the equation.
Formula (11): y = f (x)

In the equation (11) which is this non-linear equation, the left side vector y and the function form f are known and become the input of the information processing circuit 100. In the fifth embodiment, the solution vector x is obtained by solving the equation (11) which is a non-linear equation using the Newton method. Hereinafter, the difference between the fifth embodiment of the present invention and the first embodiment will be mainly described with reference to FIGS.
<Overall configuration>

  FIG. 19 is a diagram showing an outline of a configuration example of the information processing circuit 100 in the fifth embodiment. As shown in FIG. 19, the information processing circuit 100 includes an input line 101, an output line 102, a notification line 103, a non-linear equation calculation circuit 230, and a non-linear equation check circuit 231.

  The input line 101 is branched when entering the information processing circuit 100, and is connected to the non-linear equation calculation circuit 230 and the non-linear equation check circuit 231.

  An output line 102 connected to the non-linear equation arithmetic circuit 230 is branched inside the information processing circuit 100, one is connected to the upper system of the information processing circuit 100, and the other is connected to the non-linear equation analysis circuit 231.

  The non-linear equation check circuit 231 outputs an error determination from the notification line 103.

The timing chart and the state transition diagram of the information processing circuit 100 solving equation (11) which is a non-linear equation: y = f (x) are the same as the information processing circuit 100 solving the simultaneous linear equations (Ax = b). Then, the information processing circuit 100 can be realized simply by replacing the above-described simultaneous linear equation operation circuit 104 with the non-linear equation operation circuit 230 and replacing the above-described simultaneous linear equation check circuit 105 with the non-linear equation check circuit 231.
<Detailed configuration>

  FIG. 20 is a diagram showing an outline of a configuration example of the non-linear equation arithmetic circuit 230 according to the fifth embodiment. As shown in FIG. 20, the non-linear equation arithmetic circuit 230 includes an input line 101 for inputting parameters of the left side vector y of the non-linear equation (y = f (x)) and the function f of the non-linear equation; An output line 102 for receiving a numerical solution x ′ of the nonlinear equation (y = f (x)) output from the circuit 230, a bus 110, a nonlinear equation arithmetic control unit 247, an arithmetic unit 112, and an arithmetic data holding unit It has 113.

  The arithmetic unit 112 generates an Jacobian matrix Jg, which is a process of evaluating a newly introduced nonlinear equation and partially differentiating the function g (x) with x, and obtains an update vector r by solving equation (12) described later. Processing, processing of updating a solution vector by an operation of x (i + 1) = x (i) -r by product-sum operation of vectors, non-linear equation g (x (i + 1) with newly obtained solution vector To realize the processing of evaluating the norm) and calculating the norm, the nonlinear equation evaluation operation unit 243, the vector product-sum operation unit 116, the vector inner product operation unit 117, the Jacobian matrix generation unit 248 and the simultaneous linear equation operation unit 249 Have.

  FIG. 21 is a diagram showing an outline of a configuration example of the non-linear equation check circuit 231 in the fifth embodiment. As shown in FIG. 21, the non-linear equation check circuit 231 has an input line 101 for inputting parameters of the left side vector y of the non-linear equation (y = f (x)) and the function f of the non-linear equation, and non-linear equation calculation. An output line 102 for receiving a numerical solution x ′ of the nonlinear equation (y = f (x)) output from the circuit 230, and a notification line 103 for notifying the upper system of an error determination result by the nonlinear equation check circuit 231. , A non-linear equation check control unit 242, an operation unit 123, and an operation data holding unit 124.

The arithmetic unit 123 evaluates the nonlinear equation g (x (i + 1)) with the newly obtained solution vector, and performs calculation required to calculate the norm, the nonlinear equation evaluation operation unit 243 and the vector It has a product-sum operation unit 116 and an inner product operation unit 117 of a vector.
<Flow chart>

  FIG. 22 is a flowchart showing an outline of processing by the information processing circuit 100 according to the fifth embodiment. FIG. 22 shows an outline of a process of solving the equation (y = f (x)) which is a non-linear equation by using the Newton method in the process shown in the fifth embodiment.

  First, at S232, the information processing circuit 100 receives the parameters of the left side vector y of the non-linear equation and the function f of the non-linear equation from the IDAT of the input line 101.

  Next, in S233, processing (described later, FIG. 23) is executed by the non-linear equation arithmetic circuit 230.

  Next, in S234, the nonlinear equation arithmetic circuit 230 outputs the numerical solution x ′ of the nonlinear equation (y = f (x)), which is the arithmetic result, to the upper system via the output line 102, The result is output to the non-linear equation check circuit 231.

  Next, in S235, processing (described later, FIG. 24) by the non-linear equation check circuit 231 is executed.

  Next, at S 236, the non-linear equation check circuit 231 outputs the error determination result 193 to the upper system via the notification line 103.

  FIG. 23 is a flowchart showing an outline of processing (S233) by the non-linear equation arithmetic circuit 230 according to the fifth embodiment.

  First, at S240, the non-linear equation arithmetic circuit 230 initializes a loop variable i to one.

  Next, in S241, the non-linear equation arithmetic circuit 230 evaluates the newly introduced non-linear equation g (x (i)) = y−f (x (i)). The nonlinear equation (11) has a solution when g (x) = 0.

  Next, in S242, the non-linear equation arithmetic circuit 230 generates a Jacobian matrix Jg obtained by partially differentiating the function g (x) with x, and obtains the update vector r by solving the following equation (12).

g (x (i)) = Jgr ... (12)

  Next, in S243, the non-linear equation arithmetic circuit 230 updates the solution vector by the operation of x (i + 1) = x (i) -r by the product-sum operation of vectors.

  Next, in S244, the non-linear equation arithmetic circuit 230 evaluates the non-linear equation g (x (i + 1)) with the newly obtained solution vector and calculates the norm.

  Next, in S245, the non-linear equation arithmetic circuit 230 evaluates || g (x (i + 1)) || <epsilon. When it is determined that || g (x (i + 1)) || satisfies the allowable error (S245-YES), the processing is ended. On the other hand, when the non-linear equation arithmetic circuit 230 determines that the allowable error is not satisfied (S245-NO), the process proceeds to S246.

  Next, in S246, the non-linear equation calculation circuit 230 increments the loop variable i (i = i + 1). After S246, the process returns to S241.

  FIG. 24 is a flowchart showing an outline of processing (S131) by the non-linear equation check circuit 231 according to the fifth embodiment.

  First, at S 240, the non-linear equation check circuit 231 receives the numerical solution x ′ of the non-linear equation computation circuit 230, and g (x ′) = yf (x ′) by the non-linear equation evaluation computation and the vector sum operation. Perform the operation of Next, evaluation of the norm || g (x ') || is performed by an inner product operation of vectors.

  Next, in S241, the non-linear equation check circuit 231 compares the norm (|| g (x ') ||) with the tolerance error epsilon so that the norm (|| g (x') ||) is acceptable. It is determined whether the error is satisfied. If the non-linear equation check circuit 231 determines that the norm (|| g (x ') ||) satisfies the tolerance (if the norm is less than the tolerance) (S241-YES), the processing proceeds to S242. On the other hand, when the non-linear equation check circuit 231 determines that the norm (|| g (x ') ||) does not satisfy the tolerance (when the norm is greater than the tolerance) (S241-NO), the process proceeds to S243. .

  If the relative error is less than the allowable error, the nonlinear equation check circuit 231 determines in S242 that there is no error in the computing unit.

  On the other hand, if the relative error is equal to or greater than the allowable error, the nonlinear equation check circuit 231 determines in S243 that there is an error in the arithmetic unit.

Also in the fifth embodiment, as in the first embodiment, the circuit area of the non-linear equation check circuit 231 is smaller than the circuit area of the non-linear equation calculation circuit 230. Therefore, the circuit area of the information processing circuit 100 of the fifth embodiment is smaller than that of the information processing circuit in which the non-linear equation arithmetic circuit 230 is duplicated.
<Effect of Fifth Embodiment>

According to the information processing circuit 100 in the fifth embodiment described above, the non-linear equation arithmetic circuit 230 which is an arithmetic circuit solves the non-linear equation to calculate a numerical solution, and the non-linear equation check circuit 231 which is a verification circuit is restored. By performing the check of the non-linear equation based on the restored input signal and the received input signal, error detection can be performed even if the circuit amount is reduced as compared with the information processing circuit 100 provided with two non-linear equation calculation circuits 230.
Sixth Embodiment

  The sixth embodiment is different from the first embodiment in that the information processing circuit 100 of the sixth embodiment has a post-processing circuit 250. Hereinafter, a point of difference of the sixth embodiment of the present invention from the first embodiment will be mainly described using FIG.

  As shown in FIG. 25, the information processing circuit 100 includes an input line 101, an output line 102, a notification line 103, an output line 251, a simultaneous linear equation calculation circuit 104, and a simultaneous linear equation check circuit 105. And a post-processing circuit 250.

  The post-processing circuit 250 is provided at a position immediately before (or before) the output line 102 of the simultaneous linear equation arithmetic circuit 104 leaves the information processing circuit 100, and is connected to the simultaneous linear equation arithmetic circuit 104 via the output line 102.

  The simultaneous linear equation arithmetic circuit 104 outputs an output signal (numerical solution x ′) to the post-processing circuit 250.

  The post-processing circuit 250 performs post-processing which is an operation different from that of the simultaneous linear equation check circuit 105 (a calculation impossible with the simultaneous linear equation check circuit 105), and outputs the operation result through the output line 251. For example, the post-processing circuit 250 applies predetermined processing to the output signal (numerical solution x ′), and then outputs a signal that is the operation result via the output line 251.

  Note that, as shown in FIG. 26, the information processing circuit 100 may have a control line 252. In this case, the simultaneous linear equation check circuit 105 and the post-processing circuit 250 are connected via the control line 252. Further, the simultaneous linear equation check circuit 105 outputs an output signal (numerical solution x ′) to the post-processing circuit 250 via the control line 252 until the check of the simultaneous linear equation (or non-linear equation) is completed. As a result, for example, the post-processing circuit 250 latches the operation result of the simultaneous linear equation operation circuit 104 and can output the error judgment result of the notification line 103 simultaneously.

  Further, as shown in FIG. 27, the post-processing circuit 250 of the information processing circuit 100 may be provided between the simultaneous linear equation calculation circuit 104 and the simultaneous linear equation check circuit 105. In this case, the simultaneous linear equation arithmetic circuit 104 and the post-processing circuit 250 are connected via the output line 102.

  The simultaneous linear equation arithmetic circuit 104 outputs an output signal (numerical solution x ′) to the post-processing circuit 250.

If the numerical solution output from the simultaneous linear equation arithmetic circuit 104 is not data that can be processed by the simultaneous linear equation check circuit 105, the post-processing circuit 250 can process the simultaneous linear equation inspection circuit 105 based on the outputted numerical solution Data is generated, and the generated data is output to the simultaneous linear equation check circuit 105.
<Effect of Sixth Embodiment>

  According to the information processing circuit 100 in the sixth embodiment described above, the simultaneous linear equation calculation circuit 104 outputs a numerical solution to the post-processing circuit 250, and the post-processing circuit 250 performs an operation different from that of the simultaneous linear equation check circuit 105. By outputting the calculation result, the calculation result that can be processed by the simultaneous linear equation check circuit 105 is once outputted through the output line 102 and can not be processed by the simultaneous linear equation check circuit 105 (a calculation different from the simultaneous linear equation check circuit 105 ) Can be processed by the post-processing circuit 250.

Further, the simultaneous linear equation arithmetic circuit 104 outputs the numerical solution to the post-processing circuit 250, and the post-processing circuit 250 is outputted when the outputted numerical solution is not data that can be processed by the simultaneous linear equation check circuit 105. Based on the numerical solution, data that can be processed by the simultaneous linear equation check circuit 105 is generated, and the generated data is output to the simultaneous linear equation check circuit 105, whereby an output signal (numerical solution) output from the simultaneous linear equation calculation circuit 104 is generated. Even if x ′) is not data that can be processed by the simultaneous linear equation check circuit 105, the check can be performed by the simultaneous linear equation check circuit 105.
Seventh Embodiment

  The seventh embodiment is different from the first embodiment in that the information processing circuit 100 of the seventh embodiment has a post-processing circuit 250. Hereinafter, the seventh embodiment of the present invention will be described mainly with reference to FIG. 28 as to differences from the first embodiment.

  As shown in FIG. 28, the pre-processing circuit 254 is provided immediately before (or before) the input signal is input to the simultaneous linear equation check circuit 105. The preprocessing circuit 254 generates an input signal after preprocessing by performing preprocessing on the input signal input. Then, the pre-processing circuit 254 outputs the generated pre-processed input signal to the simultaneous linear equation check circuit 105.

  The simultaneous linear equation calculation circuit 104 outputs the numerical solution calculated based on the input signal to the simultaneous linear equation check circuit 105.

  The simultaneous linear equation check circuit 105 restores the numerical solution output from the simultaneous linear equation operation circuit 104 to the input signal after restoration, and based on the restored input signal and the received input signal after the pre-processing, the presence or absence of an error is It makes a judgment and outputs the judgment result of the presence or absence of an error.

  As shown in FIG. 29, the preprocessing circuit 254 may be provided immediately before (or before) the input signal is input to the simultaneous linear equation arithmetic circuit 104.

  Here, in order for the simultaneous linear equation calculation circuit 104 to calculate simultaneous linear equations using input data received via the input line 101, processing for improving the accuracy of the input data, etc. is necessary in the preprocessing circuit. May be On the other hand, the process for increasing the accuracy of the input data is not necessary in the simultaneous linear equation check circuit 105.

  For example, in the first embodiment, the process for increasing the accuracy of the input data is executed by both the simultaneous linear equation calculation circuit 104 and the simultaneous linear equation check circuit 105.

  The information processing circuit 100 shown in FIG. 29 performs preprocessing from the simultaneous linear equation check circuit 105 by providing the preprocessing circuit 254 that performs processing for increasing the accuracy of the input data in front of the simultaneous linear equation arithmetic circuit 104. Can be reduced, and the circuit size of the simultaneous linear equation check circuit 105 can be reduced.

  In this case, the preprocessing circuit 254 performs preprocessing on the input signal to generate an input signal after preprocessing, and outputs the generated input signal after preprocessing to the simultaneous linear equation arithmetic circuit 104.

  The simultaneous linear equation calculation circuit 104 outputs the numerical solution calculated based on the preprocessed input signal to the simultaneous linear equation check circuit 105.

The simultaneous linear equation check circuit 105 restores the numerical solution received through the simultaneous linear equation calculation circuit 104 into an input signal after restoration, and determines the presence or absence of an error based on the restored input signal and the received input signal. Output the judgment result of the presence or absence of an error.
<Effect of Seventh Embodiment>

  According to the information processing circuit 100 in the seventh embodiment described above, the pre-processing circuit 254 performs pre-processing on the input signal, and outputs the post-pre-processing input signal after the pre-processing to the simultaneous linear equation check circuit 105 By doing this, even if the input data is not data that can be processed by the simultaneous linear equation check circuit 105, the check can be performed by the simultaneous linear equation check circuit 105.

  Further, the preprocessing circuit 254 performs preprocessing on the input signal to generate an input signal after preprocessing, and outputs the generated input signal after preprocessing to the simultaneous linear equation arithmetic circuit 104, The number of units performing preprocessing from the simultaneous linear equation check circuit 105 can be reduced, and the circuit amount of the simultaneous linear equation check circuit 105 can be reduced.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and various modifications are included. For example, the above-described embodiments are described in detail to explain the present invention in an easy-to-understand manner, and are not necessarily limited to those having all the described configurations. Also, part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, with respect to a part of the configuration of each embodiment, it is possible to add, delete, and replace other configurations.

  Further, each configuration, function, etc. described above may be realized by software by the processor interpreting and executing a program that realizes each function. Information such as a program, a table, and a file for realizing each function can be placed in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

100 ... information processing circuit, 104 ... simultaneous linear equation calculation circuit, 105 ... simultaneous linear equation check circuit,
230 ... non-linear equation calculation circuit, 231 ... non-linear equation check circuit.

Claims (2)

An arithmetic circuit for receiving an input signal; and a check circuit for the input signal,
The arithmetic circuit outputs a numerical solution calculated based on the input signal to the check circuit.
The verification circuit restores the numerical solution received from the arithmetic circuit into an input signal after restoration, and determines the presence or absence of an error based on the restored input signal after restoration and the received input signal. and it outputs the judgment result,
And a post-processing circuit connected to the arithmetic circuit,
The arithmetic circuit outputs the numerical solution to the post-processing circuit,
The post-processing circuit generates data processable by the verification circuit based on the numerical solution when the output numerical solution is not data processable by the verification circuit, and the generated data is processed by the verification circuit Output to
Information processing circuit. An arithmetic circuit receiving an input signal; a pre-processing circuit receiving the input signal; and a check calculation circuit connected to the pre-processing circuit and the arithmetic circuit.
The arithmetic circuit outputs a numerical solution calculated based on the input signal to the check circuit.
The pre-processing circuit generates a post-pre-processing input signal by performing pre-processing on the received input signal, and outputs the generated pre-processing input signal to the check circuit.
The verification circuit restores the numerical solution received from the arithmetic circuit into an input signal after restoration, and determines the presence or absence of an error based on the restored input signal after restoration and the received input signal after preprocessing. Output the judgment result of the presence or absence of an error,
Information processing circuit.

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