JP6554643B2

JP6554643B2 - Electronic device and manufacturing method thereof

Info

Publication number: JP6554643B2
Application number: JP2015171314A
Authority: JP
Inventors: 崇博山下; 小林　健; 健小林; 浩尚岡田; 伊藤　寿浩; 寿浩伊藤
Original assignee: National Institute of Advanced Industrial Science and Technology AIST
Current assignee: National Institute of Advanced Industrial Science and Technology AIST
Priority date: 2015-08-31
Filing date: 2015-08-31
Publication date: 2019-08-07
Anticipated expiration: 2035-08-31
Also published as: JP2017050355A

Description

本発明は電子デバイス及びその製造方法に係り、特に機能性素子を搭載した電子デバイス及びその製造方法に関する。 The present invention relates to an electronic device and a manufacturing method thereof, and more particularly to an electronic device having a functional element and a manufacturing method thereof.

フレキシブルデバイスの実現には、有機半導体材料などの柔軟な材料を用いる方法や、シリコン化合物半導体など硬い材料を微細加工して構造自体に柔軟性をもたせる方法が採用されている。後者についてはＳＯＩ(Silicon On Insulator)ウェハ(シリコン基板上に酸化膜を介して薄いシリコン構造体が形成されたウェハ)を利用した犠牲層エッチングプロセスで、薄いシリコン構造体が浮いた構造をシリコン基板上に作製し、これをポリジメチルシロキサン(ＰＤＭＳ)などの柔軟材料に転写する方法がとられている(例えば、特許文献１、２、３参照)。 In order to realize a flexible device, a method using a flexible material such as an organic semiconductor material or a method of making a structure itself flexible by finely processing a hard material such as a silicon compound semiconductor is employed. The latter is a sacrificial layer etching process using an SOI (Silicon On Insulator) wafer (a wafer in which a thin silicon structure is formed on a silicon substrate through an oxide film), and the structure in which the thin silicon structure is floated is a silicon substrate. A method of producing the above and transferring it to a flexible material such as polydimethylsiloxane (PDMS) is used (for example, see Patent Documents 1, 2, and 3).

転写方法としては、層状構造形成時に特殊な剥離層を導入する方法(例えば、特許文献４参照)、多孔質半導体層を剥離層として導入する方法(例えば、特許文献５参照)、レーザー光を利用する方法(例えば、特許文献６参照)などがとられている。また、半導体歪みゲージの作製で、電気化学エッチングにおけるｐ型、ｎ型シリコンのエッチングレートの差を利用して、シリコンを薄くする方法も知られている(例えば、特許文献７参照)。 As a transfer method, a method of introducing a special release layer when forming a layered structure (see, for example, Patent Document 4), a method of introducing a porous semiconductor layer as a release layer (see, for example, Patent Document 5), or utilizing laser light (For example, refer to Patent Document 6). In addition, a method of thinning silicon by making use of a difference in etching rate between p-type and n-type silicon in electrochemical etching in manufacturing a semiconductor strain gauge is also known (see, for example, Patent Document 7).

特開２００７−２８１４０６号公報JP 2007-281406 A 特開２０１３−２３９７１６号公報JP 2013-239716 A 特開２０１４−０１７４９５号公報JP 2014-017495 A 特開２００１−０１５６８３号公報JP 2001-015683 A 特開２００５−１０１６３０号公報JP 2005-101630 A 特開２０１４−０９３５１０号公報JP 2014-093510 A 特開２００１−２６４１８８号公報JP 2001-264188 A

しかしながら、特許文献１〜３記載の方法は、犠牲層エッチングを用いるため、構造体サイズをそれほど大きくできないという制約がある。また、特許文献４〜７記載の方法では、剥離や薄化のために材料に特殊な処理をしており、これがデバイスの性能に影響を与えたり、プロセスが複雑になったりするという問題が懸念される。 However, since the methods described in Patent Documents 1 to 3 use sacrificial layer etching, there is a restriction that the structure size cannot be increased so much. In addition, in the methods described in Patent Documents 4 to 7, a special treatment is applied to the material for peeling or thinning, and this may affect the performance of the device or may complicate the process. Is done.

本発明は以上の点に鑑みなされたもので、犠牲層エッチングのためのサイズの制約や、特殊な材料の導入をすることなく、所定の機能を実現するための機能性素子と、機能性素子の入力信号又は出力信号用電極と、電極用の電極パッドとが積層された極薄の構造体の本体部分を回路基板上に簡便に転写できる電子デバイス及びその製造方法を提供することを目的とする。 The present invention has been made in view of the above points, and includes a functional element for realizing a predetermined function without limiting the size for sacrificial layer etching or introducing a special material, and a functional element. It is an object to provide an electronic device that can easily transfer a main body portion of an ultra-thin structure in which electrodes for input signals or output signals and electrode pads for electrodes are laminated onto a circuit board, and a method for manufacturing the same. To do.

上記の目的を達成するため、第１の発明の電子デバイスは、平面形状が四角枠状である基板と、所定の機能を実現するための機能性素子、前記機能性素子の入力信号又は出力信号用電極、及び前記電極用の電極パッドが積層された本体部分と、前記本体部分の周辺部に形成された複数の支持部とからなる構造体とを備え、前記支持部は前記構造体の長手方向と直交する幅の長さよりも短い部分からなる平面形状であり、前記基板の枠部にのみ前記支持部で前記構造体の本体部分を支持することで前記構造体を前記基板に架け渡した構造であることを特徴とする。 In order to achieve the above object, an electronic device according to a first aspect of the present invention includes a substrate whose planar shape is a square frame shape, a functional element for realizing a predetermined function, an input signal or an output signal of the functional element And a structure composed of a main body portion on which electrode pads for the electrodes are laminated, and a plurality of support portions formed on the periphery of the main body portion, and the support portion is a longitudinal length of the structure body. It is a planar shape consisting of a portion shorter than the length of the width orthogonal to the direction, and the structure is bridged on the substrate by supporting the main body portion of the structure with the support portion only on the frame portion of the substrate. It is a structure.

また、上記の目的を達成するため、第２の発明の電子デバイスは、第1の発明における前記基板が、シリコン基板と表面シリコン層との間に二酸化シリコン層が形成された扁平な直方体形状のＳＯＩ基板における前記シリコン基板であり、前記構造体が、前記ＳＯＩ基板中の前記表面シリコン層の上に下部電極、前記機能性素子及び上部電極が積層されると共に、前記下部電極上に下部電極用電極パッドが、前記上部電極上に上部電極用電極パッドがそれぞれ形成され、前記直方体形状の少なくとも前記表面シリコン層の周辺部に前記複数の支持部が間隔を空けて形成されていることを特徴とする。 In order to achieve the above object, the electronic device of the second invention is a flat rectangular parallelepiped shape in which the substrate in the first invention has a silicon dioxide layer formed between a silicon substrate and a surface silicon layer. The silicon substrate in an SOI substrate, wherein the structure includes a lower electrode, the functional element, and an upper electrode laminated on the surface silicon layer in the SOI substrate, and a lower electrode on the lower electrode. An electrode pad is formed with an electrode pad for an upper electrode formed on the upper electrode, respectively, and the plurality of supporting portions are formed at intervals around at least the surface silicon layer of the rectangular parallelepiped shape. To do.

また、上記の目的を達成するため、第３の発明の電子デバイスは、第１又は第２の発明における前記支持部が、平面形状が先端ほど細くなるテーパ形状であり、そのテーパ形状の先端部分付近が前記基板の枠部分又は前記構造体の本体部分に位置することを特徴とする。 In order to achieve the above object, according to a third aspect of the present invention, there is provided an electronic device according to the third or second aspect, wherein the support portion in the first or second aspect has a tapered shape in which a planar shape becomes narrower toward a distal end. The vicinity is located in the frame portion of the substrate or the main body portion of the structure.

また、上記の目的を達成するため、第４の発明の電子デバイスは、第１又は第２の発明における前記支持部が、平面形状が半円形状であり、その半円形状の先端の曲線部分付近が前記基板の枠部分又は前記構造体の本体部分に位置することを特徴とする。 In order to achieve the above object, according to a fourth aspect of the present invention, in the electronic device according to the first or second aspect, the planar shape of the support portion is a semicircular shape, and the curved portion of the semicircular tip is provided The vicinity is located in the frame portion of the substrate or the main body portion of the structure.

また、上記の目的を達成するため、第５の発明の電子デバイスの製造方法は、第１乃至第４の発明のいずれかの電子デバイスにおいて、前記支持部を除く前記構造体の本体部分を前記基板から剥離する剥離工程と、前記剥離工程で前記基板から剥離した前記構造体の本体部分を、所望の回路基板の所定領域に転写する転写工程とを含み、前記転写工程により、前記構造体の本体部分が前記所望の回路基板に転写された構造の新たな電子デバイスを製造することを特徴とする。 In order to achieve the above object, a method for manufacturing an electronic device according to a fifth invention is the electronic device according to any one of the first to fourth inventions, wherein the main body portion of the structure excluding the support portion is A peeling step for peeling from the substrate, and a transfer step for transferring the main body portion of the structure peeled from the substrate in the peeling step to a predetermined region of a desired circuit board. A new electronic device having a structure in which a main body portion is transferred to the desired circuit board is manufactured.

また、上記目的を達成するため、第６の発明の電子デバイスの製造方法は、第２乃至第４の発明のいずれかの電子デバイスにおいて、前記支持部を除く前記構造体の本体部分を前記基板から剥離する剥離工程と、前記剥離工程で前記基板から剥離した前記構造体の本体部分を、表面に第１及び第２の配線部が形成された所望の回路基板の前記第１及び第２の配線部を除いた所定領域に転写する転写工程と、前記下部電極及び前記上部電極が暴露された前記構造体の本体部分のうち、少なくとも前記上部電極の側面部分を絶縁性ペーストで被覆保護する第１の被覆工程と、前記絶縁性ペーストを被覆して前記上部電極の上面と前記所望の回路基板の前記第１の配線部との間を第１の導電性ペーストで電気的に接続するとともに、前記下部電極の上面と前記所望の回路基板の前記第２の配線部との間を第２の導電性ペーストで被覆して電気的に接続する第２の被覆工程とを含み、前記構造体の本体部分が前記所望の回路基板に転写された構造の新たな電子デバイスを製造することを特徴とする。 In order to achieve the above object, a method for manufacturing an electronic device according to a sixth invention is the electronic device according to any one of the second to fourth inventions, wherein the main body portion of the structure excluding the support portion is the substrate. The first and second of the desired circuit board on which the first and second wiring portions are formed on the surface of the main body portion of the structure peeled from the substrate in the peeling process. A transfer step of transferring to a predetermined area excluding the wiring portion; and a body portion of the structure to which the lower electrode and the upper electrode are exposed, wherein at least a side surface portion of the upper electrode is covered and protected with an insulating paste. 1 covering step, and electrically connecting the upper surface of the upper electrode and the first wiring part of the desired circuit board with the first conductive paste by covering the insulating paste, Of the lower electrode A second covering step of covering and electrically connecting a surface and the second wiring portion of the desired circuit board with a second conductive paste, wherein the main body portion of the structure is A new electronic device having a structure transferred to a desired circuit board is manufactured.

また、上記の目的を達成するため、第７の発明の電子デバイスの製造方法は、第５又は第６の発明の剥離工程が、チップ実装機の吸引コレットの先端に吸引された前記粘着材を、前記構造体の本体部分の最上面に粘着した後、前記粘着材に前記構造体の本体部分を粘着させた状態で前記吸引コレットにより前記粘着材を引き上げることで前記構造体の本体部分を前記基板から剥離する工程であり、前記転写工程が、前記吸引コレットに吸引されている前記粘着材に前記構造体の本体部分を粘着させた状態で、前記所望の回路基板の前記所定領域に予め形成されている接着層に接着させた後、前記吸引コレットにより前記粘着材を引き上げることで前記構造体の本体部分を前記所望の回路基板の所定領域に転写する工程であることを特徴とする。 In order to achieve the above object, the electronic device manufacturing method according to a seventh aspect of the present invention is the method of manufacturing the electronic device according to the fifth or sixth aspect, wherein the peeling step is performed by sucking the adhesive material sucked into the tip of the suction collet of the chip mounting machine. Then, after adhering to the uppermost surface of the main body portion of the structure, the main body portion of the structure is lifted by the suction collet while the main body portion of the structure is adhered to the adhesive material. A step of peeling from the substrate, wherein the transfer step is previously formed in the predetermined region of the desired circuit board in a state where the main body portion of the structure is adhered to the adhesive material sucked by the suction collet The step of transferring the main body portion of the structure to a predetermined region of the desired circuit board by pulling up the adhesive material with the suction collet after bonding to the adhesive layer that has been made.

また、上記の目的を達成するため、第８の発明の電子デバイスは、第５乃至第７の発明のいずれかの発明の転写工程により、前記構造体の本体部分が前記所望の回路基板に転写された構造であることを特徴とする。ここで、前記所望の回路基板はフレキシブル回路基板であってもよい。 In order to achieve the above object, an electronic device according to an eighth aspect of the invention is configured such that the main body portion of the structure is transferred to the desired circuit board by the transfer process according to any of the fifth to seventh aspects of the invention. It is characterized by having a structure. Here, the desired circuit board may be a flexible circuit board.

本発明によれば、構造体サイズの制約なく、材料の特殊な処理をすることなく、所定の機能を実現するための機能性素子と、機能性素子の入力信号又は出力信号用電極と、電極用の電極パッドとが積層された極薄の構造体本体部分を回路基板上に簡便に転写できる。 According to the present invention, a functional element for realizing a predetermined function without restriction of a structure size and without special processing of a material, an input signal or output signal electrode of the functional element, and an electrode An ultra-thin structure main body portion on which electrode pads are laminated can be easily transferred onto a circuit board.

本発明に係る電子デバイスの製造方法の一実施形態の要部の各工程の素子平面図である。It is an element top view of each process of the principal part of one Embodiment of the manufacturing method of the electronic device which concerns on this invention. 本発明に係る電子デバイスの製造方法の一実施形態の要部の各工程の素子断面図である。It is element sectional drawing of each process of the principal part of one Embodiment of the manufacturing method of the electronic device which concerns on this invention. 本発明に係る電子デバイスの第１の実施形態の説明用平面図である。1 is a plan view for explaining a first embodiment of an electronic device according to the present invention. 本発明に係る電子デバイスの製造方法の第２の実施形態の各工程説明図である。It is each process explanatory drawing of 2nd Embodiment of the manufacturing method of the electronic device which concerns on this invention. 本発明に係る電子デバイスの配線構造の一例を説明する素子断面図である。It is element sectional drawing explaining an example of the wiring structure of the electronic device which concerns on this invention. 本発明に係る電子デバイスの配線構造の一例を説明する素子平面の顕微鏡写真である。It is a microscope picture of the element plane explaining an example of the wiring structure of the electronic device concerning the present invention. 本発明に係る電子デバイスの効果確認のための実験装置の一例の概略構成図である。It is a schematic block diagram of an example of the experimental apparatus for the effect confirmation of the electronic device which concerns on this invention. 図７の各部の一例の特性図である。It is a characteristic view of an example of each part of FIG. 本発明に係る電子デバイスにおける支持構造の各例を示す平面図である。It is a top view which shows each example of the support structure in the electronic device which concerns on this invention.

次に、本発明の実施形態について図面を参照して説明する。
図１は、本発明に係る電子デバイスの製造方法の一実施形態の要部の各工程の素子平面図を示し、図２は、本発明に係る電子デバイスの製造方法の一実施形態の要部の各工程の素子断面図を示す。ここで、図２(Ａ)、(Ｂ)、(Ｃ)及び(Ｄ)は、それぞれ対応する図１(Ａ)、(Ｂ)、(Ｃ)及び(Ｄ)の素子平面図の水平線Ｘで切断した素子断面図を示す。 Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an element plan view of each step of an essential part of an embodiment of an electronic device manufacturing method according to the present invention, and FIG. 2 shows an essential part of an embodiment of an electronic device manufacturing method according to the present invention. The element sectional drawing of each process of these is shown. 2A, 2B, 2C, and 2D are respectively horizontal lines X in the corresponding element plan views of FIGS. 1A, 1B, 1C, and 1D. A cut element sectional view is shown.

まず、図２(Ａ)に示すように、シリコン(Ｓi)基板１２、二酸化シリコン(ＳiＯ₂)層１３及び表面シリコン(Ｓi)層１４がこの順で積層された、扁平な直方体形状のＳＯＩ基板１１の表面に下部電極層、圧電薄膜層及び上部電極層を積層した後、フォトリソグラフィーやエッチングなどの公知の技術を適用して、下部電極層を互いに離間する下部電極１５ａ及び１５ｂに形成し、更に圧電薄膜層及び上部電極層をそれぞれ所定の長さの直方体形状の圧電薄膜１６ａ及び１６ｂ、上部電極１７ａ及び１７ｂに形成する。このとき、図１(Ａ)及び図２(Ａ)に示すように、圧電薄膜１６ａ及び１６ｂと上部電極１７ａ及び１７ｂは、それらの長手方向上の各一方の端部が、下部電極１５ａ及び１５ｂの端部側表面の一部が露出するように短く形成される。 First, as shown in FIG. 2A, a flat rectangular parallelepiped SOI substrate in which a silicon (Si) substrate 12, a silicon dioxide (SiO ₂ ) layer 13, and a surface silicon (Si) layer 14 are laminated in this order. After laminating the lower electrode layer, the piezoelectric thin film layer and the upper electrode layer on the surface of 11, a known technique such as photolithography or etching is applied to form the lower electrode layer on the lower electrodes 15a and 15b spaced apart from each other, Further, the piezoelectric thin film layer and the upper electrode layer are respectively formed in rectangular parallelepiped piezoelectric thin films 16a and 16b and upper electrodes 17a and 17b having a predetermined length. At this time, as shown in FIGS. 1 (A) and 2 (A), the piezoelectric thin films 16a and 16b and the upper electrodes 17a and 17b are arranged such that one end in the longitudinal direction thereof is lower electrodes 15a and 15b. It is formed short so that a part of the end portion side surface is exposed.

ここで、表面シリコン層１４は、Ｓi基板１２及びＳiＯ₂層１３よりも薄い厚さ(例えば３μｍ)である。また、下部電極１５ａ及び１５ｂと上部電極１７ａ及び１７ｂは、それぞれ同一構成で、例えばチタン(Ｔi)膜と白金(Ｐt)膜とが積層された厚さ１００ｎｍの構造である。一方、圧電薄膜１６ａ及び１６ｂは、所定の機能を実現するための機能性素子の一例で、例えばチタン酸ジルコン酸鉛(ＰＺＴ：lead zirconate titanate)製の圧電特性を有する薄膜で、その厚さは例えば１.９μｍである。 Here, the surface silicon layer 14 is thinner than the Si substrate 12 and the SiO ₂ layer 13 (for example, 3 μm). Further, the lower electrodes 15a and 15b and the upper electrodes 17a and 17b have the same configuration, for example, a structure having a thickness of 100 nm in which a titanium (Ti) film and a platinum (Pt) film are stacked. On the other hand, the piezoelectric thin films 16a and 16b are examples of functional elements for realizing a predetermined function, and are thin films having piezoelectric characteristics made of, for example, lead zirconate titanate (PZT) and having a thickness of For example, it is 1.9 μm.

続いて、図１(Ｂ)及び図２(Ｂ)に示すように、蒸着、パターニング及びエッチングなどの公知の技術を適用して、露出した下部電極１５ａ、１５ｂの端部側表面の上に矩形状の電極パッド１８ａ、１８ｂを形成すると共に、電極パッド１８ａ、１８ｂの形成位置と対向する上部電極１７ａ、１７ｂの表面位置に矩形状の電極パッド１９ａ、１９ｂを形成する。電極パッド１８ａ、１８ｂ、１９ａ、１９ｂは例えば金(Ａu)により構成されている。 Subsequently, as shown in FIGS. 1B and 2B, a known technique such as vapor deposition, patterning, and etching is applied to form a rectangular pattern on the exposed end surface of the lower electrodes 15a and 15b. The electrode pads 18a and 18b having the shape are formed, and the rectangular electrode pads 19a and 19b are formed at the surface positions of the upper electrodes 17a and 17b opposite to the formation positions of the electrode pads 18a and 18b. The electrode pads 18a, 18b, 19a, 19b are made of, for example, gold (Au).

続いて、図１(Ｃ)及び図２(Ｃ)に示すように、フォトリソグラフィーやエッチングなどの公知の技術をＳＯＩ基板１１のＳiＯ₂層１３及び表面Ｓi層１４に適用して、下部電極１５ａ、１８ｂよりも長手方向の長さが長い所定の長さの直方体形状のＳiＯ₂膜１３ａ、１３ｂ及び表面Ｓi膜１４ａ、１４ｂをそれぞれ離間して形成する。これにより、Ｓi基板１２の表面の一部が露出する。また、この工程では、図１(Ｃ)の平面図に示すような後述するテーパ形状の支持部２０及び２１が複数個所に形成される。支持部２０はＳiＯ₂膜１３ａ及び表面Ｓi膜１４ａの積層部分であり、支持部２１はＳiＯ₂膜１３ｂ及び表面Ｓi膜１４ｂの積層部分である。 Subsequently, as shown in FIGS. 1C and 2C, a known technique such as photolithography or etching is applied to the SiO ₂ layer 13 and the surface Si layer 14 of the SOI substrate 11 to thereby form the lower electrode 15a. The rectangular parallelepiped shaped SiO ₂ films 13a and 13b and the surface Si films 14a and 14b are formed apart from each other by a predetermined length longer than the lengths 18b and 18b. Thereby, a part of the surface of the Si substrate 12 is exposed. In this step, tapered support portions 20 and 21 to be described later as shown in the plan view of FIG. 1C are formed at a plurality of locations. The support part 20 is a laminated part of the SiO ₂ film 13a and the surface Si film 14a, and the support part 21 is a laminated part of the SiO ₂ film 13b and the surface Si film 14b.

そして、図２(Ｄ)の断面図に示すように、Ｓi基板１２の裏面側から、例えばＤＲＩＥなどの深掘エッチングにより、Ｓi基板１２とＳiＯ₂膜１３ａ、１３ｂの各所定幅の周縁部分を残し、それ以外を除去する。これにより、ＳＯＩ基板１１は、Ｓi基板が１２’で、ＳiＯ₂膜１３ａが１３ａ’で、ＳiＯ₂膜１３ｂが１３ｂ’でそれぞれ示すように、周縁部分の一部のみが残された凹部２２ａ、２２ｂが形成されたものとなる。これにより、表面Ｓi膜１４ａ、下部電極１５ａ、圧電薄膜１６ａ、上部電極１７ａ、電極パッド１８ａ及び１９ａからなる第１の積層構造体を本体部分とする第１の電子デバイスと、表面Ｓi膜１４ｂ、下部電極１５ｂ、圧電薄膜１６ｂ、上部電極１７ｂ、電極パッド１８ｂ及び１９ｂからなる第２の積層構造体を本体部分とする第２の電子デバイスとが、図１(Ｄ)及び図２(Ｄ)に示すように、支持部２０、２１により少なくとも長手方向の両端部分でＳi基板１２’の凹部２２ａ、２２ｂ以外の部分(すなわち平面四角枠形状の枠部分)で支持される。 Then, as shown in the cross-sectional view of FIG. 2 (D), the peripheral portions of the Si substrate 12 and the SiO ₂ films 13a and 13b having respective predetermined widths are formed from the back side of the Si substrate 12 by deep etching such as DRIE. Leave and remove the rest. As a result, the SOI substrate 11 has a recess 22a in which only a part of the peripheral portion is left, as shown by 12 ′ for the Si substrate, 13a ′ for the SiO ₂ film 13a, and 13b ′ for the SiO ₂ film 13b. 22b is formed. As a result, the first electronic device having the first laminated structure including the surface Si film 14a, the lower electrode 15a, the piezoelectric thin film 16a, the upper electrode 17a, and the electrode pads 18a and 19a as the main body portion, the surface Si film 14b, A second electronic device having a second laminated structure composed of a lower electrode 15b, a piezoelectric thin film 16b, an upper electrode 17b, and electrode pads 18b and 19b as a main body portion is shown in FIGS. 1 (D) and 2 (D). As shown, at least both ends in the longitudinal direction are supported by the support portions 20 and 21 at portions other than the recesses 22a and 22b of the Si substrate 12 '(that is, a flat rectangular frame-shaped frame portion).

以上の実施形態の製造方法は、公知のＭＥＭＳ(Micro Electro Mechanical Systems)デバイスの作製方法と同様であり、本実施形態によれば、この公知の方法と同様の工程を経て電子デバイスを製造することができる。ただし、ＭＥＭＳデバイスと本実施形態の電子デバイスとの違いは、必要な構成素子がすべて構造体上に存在していることである。また、本実施形態の製造方法で製造する電子デバイスは、ＳＯＩ基板の上側の積層構造体の本体部分と、その本体部分をＳＯＩ基板のＳi基板上に支持する支持構造とからなるが、その支持構造が後述するように積層構造体の底面の長手方向に直交する幅よりも短い部分からなる平面形状の複数の支持部からなる点に特徴がある。上記の支持部は図１及び図２の実施形態では平面がテーパ形状の支持部である。 The manufacturing method of the above embodiment is the same as the manufacturing method of a well-known MEMS (Micro Electro Mechanical Systems) device, and according to this embodiment, an electronic device is manufactured through the same process as this well-known method. Can do. However, the difference between the MEMS device and the electronic device of the present embodiment is that all necessary constituent elements are present on the structure. In addition, the electronic device manufactured by the manufacturing method of the present embodiment includes a main body portion of the laminated structure on the upper side of the SOI substrate and a support structure that supports the main body portion on the Si substrate of the SOI substrate. As will be described later, the structure is characterized in that it is composed of a plurality of planar-shaped support portions composed of portions shorter than the width orthogonal to the longitudinal direction of the bottom surface of the laminated structure. In the embodiment shown in FIGS. 1 and 2, the support portion is a support portion having a tapered surface.

すなわち、表面Ｓi膜１４ａ、下部電極１５ａ、圧電薄膜１６ａ、上部電極１７ａ、電極パッド１８ａ及び１９ａからなる第１の積層構造体の端部は、支持部として積層構造体の底面の長手方向に直交する幅よりも短い部分からなる平面がテーパ形状のＳiＯ₂膜１３ａ’によりＳi基板１２’上に支持され、また、表面Ｓi膜１４ｂ、下部電極１５ｂ、圧電薄膜１６ｂ、上部電極１７ｂ、電極パッド１８ｂ及び１９ｂからなる第２の積層構造体の端部は、支持部として積層構造体の底面の長手方向に直交する幅よりも短い部分からなる平面がテーパ形状のＳiＯ₂膜１３ｂ’によりＳi基板１２’上に支持されている。これにより、後述するように、第１の積層構造体及び第２の積層構造体を目的の電子デバイスとして製造するために、平面形状が四角枠状のＳi基板１２'から剥離する際に極めて容易に剥離することができる。 That is, the end portion of the first laminated structure including the surface Si film 14a, the lower electrode 15a, the piezoelectric thin film 16a, the upper electrode 17a, and the electrode pads 18a and 19a is orthogonal to the longitudinal direction of the bottom surface of the laminated structure as a support portion. A plane composed of a portion shorter than the width to be formed is supported on the Si substrate 12 ′ by a tapered SiO ₂ film 13a ′, and the surface Si film 14b, the lower electrode 15b, the piezoelectric thin film 16b, the upper electrode 17b, and the electrode pad 18b. The end portion of the second laminated structure composed of 19b and 19b serves as a Si substrate 12 by an SiO ₂ film 13b ′ having a tapered surface that is shorter than the width perpendicular to the longitudinal direction of the bottom surface of the laminated structure as a support portion. 'Supported on. Thereby, as will be described later, in order to manufacture the first laminated structure and the second laminated structure as a target electronic device, it is extremely easy to peel off from the Si substrate 12 ′ having a square frame shape. Can be peeled off.

次に、本発明に係る電子デバイスの第１の実施形態について説明する。
図３は、本発明に係る電子デバイスの第１の実施形態の説明用平面図を示す。同図中、図１及び図２と同一構成部分には同一符号を付してある。ただし、図１及び図２に示した符号の添字ａ、ｂは省略してある。図３(Ａ)は、本発明に係る電子デバイスの第１の実施形態の平面図を示す。図３(Ａ)の平面図に示す本実施形態の電子デバイス３０は、図１及び図２と共に説明した第１、第２の積層構造体及びその支持部と同様の構造であり、平面が概略四角枠状のＳi基板１２’の上に、ＳiＯ₂膜、表面Ｓi膜、下部電極１５、機能性素子である圧電薄膜１６、及び上部電極１７が積層され、かつ、下部電極１５の所定位置と上部電極１７の所定位置に矩形状の電極パッド１８、１９が形成された積層構造体の本体部分と、後述する平面形状の複数の支持部とからなる構造である。 Next, a first embodiment of an electronic device according to the present invention will be described.
FIG. 3 is a plan view for explaining the first embodiment of the electronic device according to the present invention. In the figure, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals. However, the suffixes a and b of the reference numerals shown in FIGS. 1 and 2 are omitted. FIG. 3A shows a plan view of the first embodiment of the electronic device according to the present invention. The electronic device 30 of the present embodiment shown in the plan view of FIG. 3A has the same structure as the first and second laminated structures and the support portions described together with FIGS. An SiO ₂ film, a surface Si film, a lower electrode 15, a piezoelectric thin film 16 that is a functional element, and an upper electrode 17 are laminated on a square frame-shaped Si substrate 12 ′. This is a structure composed of a main body portion of a laminated structure in which rectangular electrode pads 18 and 19 are formed at predetermined positions of the upper electrode 17 and a plurality of planar support portions described later.

この電子デバイス３０を構成する、ＳＯＩ基板１１よりも薄い偏平な直方体形状の積層構造体の本体部分には、表面に下部電極１５、圧電薄膜１６、上部電極１７、電極パッド１８、１９がすべて搭載されている。下部電極１５及び上部電極１７は、機能性素子の入力信号又は出力信号用電極であるが、ここでは機能性素子が圧電薄膜１６であることから、それぞれには圧電薄膜１６に所定の機能動作(収縮又は伸張動作)を行わせるための駆動信号が印加されるか、圧電薄膜１６の収縮又は伸張動作により発生した信号を出力する。 The lower electrode 15, the piezoelectric thin film 16, the upper electrode 17, and the electrode pads 18 and 19 are all mounted on the surface of the main body portion of the flat rectangular parallelepiped structure that is thinner than the SOI substrate 11 that constitutes the electronic device 30. Has been. The lower electrode 15 and the upper electrode 17 are electrodes for input signals or output signals of functional elements. Here, since the functional element is the piezoelectric thin film 16, each has a predetermined functional operation on the piezoelectric thin film 16 ( A drive signal for performing a contraction or expansion operation) is applied, or a signal generated by the contraction or expansion operation of the piezoelectric thin film 16 is output.

ここで、本実施形態の電子デバイス３０は、ＳＯＩ基板の平面四角枠状のＳi基板１２’の枠部分のみに、積層構造体の本体部分が支持部(図３(Ａ)の２０(２１)で示す部分)で支持されるように架け渡される構造であるが、その支持構造が積層構造体の底面の長手方向に直交する幅よりも短い部分で構成された複数の支持部からなる点に特徴がある。複数の支持部は或る間隔を空けて形成されており、それぞれの平面形状は一例としてテーパ形状である。このことについて更に説明する、図３(Ａ)の積層構造体の平面図において、表面Ｓi膜の上側の積層構造部分を除いた構成は図３(Ｂ)に示す如くになる。なお、図３(Ａ)の電極パッド１８及び支持部２０(２１)付近の模式図を図３(Ｅ)に示す。 Here, in the electronic device 30 of this embodiment, the main body portion of the laminated structure is supported only on the frame portion of the Si substrate 12 ′ having a planar square frame shape of the SOI substrate (20 (21) in FIG. 3A). It is a structure that is spanned so as to be supported by a portion), but the support structure is composed of a plurality of support portions configured by a portion shorter than the width orthogonal to the longitudinal direction of the bottom surface of the laminated structure. There are features. The plurality of support portions are formed at a certain interval, and each planar shape is a tapered shape as an example. In the plan view of the laminated structure of FIG. 3 (A), which will be further described, the configuration excluding the laminated structure portion above the surface Si film is as shown in FIG. 3 (B). FIG. 3E shows a schematic diagram in the vicinity of the electrode pad 18 and the support portion 20 (21) in FIG.

図３(Ｃ)は、図３(Ｂ)の破線の四角部分２５で囲んだ支持部２０(２１)を拡大した図である。図３(Ｂ)及び(Ｃ)から分かるように、階層構造体の支持部２０(２１)は、平面形状が２つの直線状の稜線が鋭角で交わる端点付近のテーパ形状の先端部分(換言すると、先細りの形状の先端部分)において、Ｓi基板１２’の上に積層構造体を支持する。支持部２０(２１)を構成するテーパ形状の先端部分は、Ｓi基板１２’の枠部分の上においてはそれぞれ階層構造体の長手方向に直交する長さである幅(図３(Ｂ)にＷで示す)よりも短い長さの３辺からなる三角形状である。 FIG. 3C is an enlarged view of the support portion 20 (21) surrounded by the broken-line square portion 25 in FIG. 3B. As can be seen from FIGS. 3B and 3C, the support portion 20 (21) of the hierarchical structure has a tapered tip end portion (in other words, near the end point where two linear ridge lines intersect at an acute angle). In the tapered tip portion), the laminated structure is supported on the Si substrate 12 ′. The tapered tip portion constituting the support portion 20 (21) has a width (W in FIG. 3B) that is a length perpendicular to the longitudinal direction of the hierarchical structure on the frame portion of the Si substrate 12 ′. It is a triangular shape consisting of three sides with a shorter length than

更に、図３(Ｃ)中の破線の四角部分２６を拡大した図３(Ｄ)の斜視図及び図３(Ｆ)の模式図に示すように、上記のテーパ形状の先端部分は、四角枠状に形成されたＳi基板１２’に対して、ＳＯＩ基板のＳiＯ₂膜１３’及び表面シリコン膜１４’が積層された部分からなる。かかる構造の電子デバイス３０によれば、犠牲層エッチングのためのサイズの制約や、特殊な材料の導入をすることなく、機能性素子である圧電薄膜１６と、その入力信号又は出力信号用の下部電極１５及び上部電極１７と、電極パッド１８及び１９とが積層された極薄の構造体の本体部分をＳi基板１２’から極めて容易に剥離して、任意の位置に転写することができる。 Furthermore, as shown in the perspective view of FIG. 3D and the schematic view of FIG. 3F in which the broken-line square portion 26 in FIG. 3C is enlarged, the tapered tip portion is a square frame. The SiO ₂ film 13 ′ and the surface silicon film 14 ′ of the SOI substrate are laminated on the Si substrate 12 ′ formed in a shape. According to the electronic device 30 having such a structure, the piezoelectric thin film 16 which is a functional element and the lower portion for the input signal or output signal can be obtained without restricting the size for sacrificial layer etching or introducing a special material. The main body portion of the ultra-thin structure in which the electrode 15 and the upper electrode 17 and the electrode pads 18 and 19 are laminated can be peeled off from the Si substrate 12 ′ very easily and transferred to an arbitrary position.

次に、本発明に係る電子デバイスの製造方法の第２の実施形態について説明する。
図４は、本発明に係る電子デバイスの製造方法の第２の実施形態の各工程説明図を示す。同図中、図１及び図２と同一構成部分には同一符号を付し、その説明を省略する。図４(Ａ)において、チップ実装機の吸引コレット４１の先端に弾力性のある粘着材４２が真空吸引されている。粘着材４２としては、例えばポリジメチルシロキサン(ＰＤＭＳ)などがある。粘着材４２の平面の大きさはＳi基板１２’に支持されている第１の積層構造体３５ａや第２の積層構造体３５ｂの平面の大きさと同程度とされている。 Next, a second embodiment of the electronic device manufacturing method according to the present invention will be described.
FIG. 4 shows each process explanatory drawing of 2nd Embodiment of the manufacturing method of the electronic device which concerns on this invention. In the figure, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 4A, the elastic adhesive material 42 is vacuum-sucked at the tip of the suction collet 41 of the chip mounting machine. Examples of the adhesive material 42 include polydimethylsiloxane (PDMS). The size of the plane of the adhesive material 42 is approximately the same as the size of the plane of the first laminated structure 35a and the second laminated structure 35b supported by the Si substrate 12 ′.

実施形態では、図１と共に説明した製造方法で第１及び第２の積層構造体３５ａ及び３５ｂを作成した後、続いて、図４(Ａ)の断面図に示すように、吸引コレット４１の先端に粘着材４２を真空吸引した状態で、矢印４３で示すように粘着材４２を例えば第２の積層構造体３５ｂの最上面の上部電極１７ｂに押し付けて粘着する。 In the embodiment, after the first and second laminated structures 35a and 35b are produced by the manufacturing method described with reference to FIG. 1, then, as shown in the sectional view of FIG. In a state where the adhesive material 42 is vacuum-sucked, the adhesive material 42 is pressed and adhered to the upper electrode 17b on the uppermost surface of the second laminated structure 35b, for example, as indicated by an arrow 43.

次に、吸引コレット４１に吸引されている粘着材４２と上部電極１７ｂとの粘着状態を保ったまま、図４(Ｂ)の断面図に矢印４４で示すように上方向に粘着材４２を引き上げると、第２の積層構造体３５ｂは、厚さが薄く、かつ、面積が小さなテーパ形状の支持部(図１(Ｄ)及び図２(Ｄ)、図３(Ａ)の２０、２１等)により本体部分がＳi基板１２’に支持されているだけであるので、応力がそのテーパ形状の支持部に集中して、小なる力によりテーパ形状の支持部で破断されて図４(Ｂ)に示すように粘着材４２と共に引き上げられ、Ｓi基板１２’から剥離(分離)される。 Next, while maintaining the adhesive state of the adhesive material 42 sucked by the suction collet 41 and the upper electrode 17b, the adhesive material 42 is pulled upward as shown by the arrow 44 in the sectional view of FIG. The second laminated structure 35b has a tapered support portion with a small thickness and a small area (20, 21 in FIGS. 1D, 2D, and 3A). 4B, since the main body portion is only supported by the Si substrate 12 ′, the stress concentrates on the tapered support portion, and is broken by the tapered support portion with a small force. As shown, it is pulled up together with the adhesive 42 and peeled (separated) from the Si substrate 12 '.

このとき、図４(Ｂ)の断面図及び図４(Ｃ)の平面図に示すように、支持部２１を構成するＳiＯ₂膜１３’と共に、その上の表面Ｓi膜の一部１４ｂ’も破断する。図４(Ｃ)の２１’はＳi基板１２’の表面に残ったＳiＯ₂膜１３ｂ’及び表面Ｓi膜の一部１４ｂ’の積層部分(支持部２１の一部)を示す。なお、ここでは第２の積層構造体３５ｂの本体部分をＳi基板１２’から剥離するように説明しているが、同様にして第１の積層構造体３５ａの本体部分をＳi基板１２’から剥離することもできることは勿論である。なお、粘着材４２を用いることなく吸引コレット４１で直接に積層構造体３５ａ又は３５ｂの本体部分を吸引してＳi基板１２’から剥離することも可能である。ただし、この場合は吸引した際の衝撃により、積層構造体３５ａ又は３５ｂの本体部分の一部が破損する可能性がある。 At this time, as shown in the sectional view of FIG. 4B and the plan view of FIG. 4C, the SiO ₂ film 13 ′ constituting the support portion 21 and a part 14b ′ of the surface Si film thereon are also formed. Break. Reference numeral 21 ′ in FIG. 4C denotes a laminated portion (a part of the support portion 21) of the SiO ₂ film 13b ′ remaining on the surface of the Si substrate 12 ′ and a part 14b ′ of the surface Si film. Here, it is described that the main body portion of the second laminated structure 35b is peeled off from the Si substrate 12 ′. Similarly, the main body portion of the first laminated structure 35a is peeled off from the Si substrate 12 ′. Of course, it can also be done. Note that the main body portion of the laminated structure 35a or 35b can be directly sucked by the suction collet 41 without using the adhesive material 42 and peeled from the Si substrate 12 ′. However, in this case, a part of the main body portion of the laminated structure 35a or 35b may be damaged by an impact when sucked.

続いて、Ｓi基板１２’から剥離され、かつ、吸引コレット４１に吸引されている粘着材４２に粘着されている第２の積層構造体３５ｂの本体部分を、図４(Ｄ)に示すようにフレキシブル回路基板５１の上方の所定位置に移動した後、図４(Ｄ)に矢印４５で示すように下方向に移動してフレキシブル回路基板５１の表面の所定領域に形成されている接着層５３に接着する。ここで、フレキシブル回路基板５１の表面の上記所定領域は、銅製の配線５４、５５の形成領域の間の第２の積層構造体３５ｂの本体部分が転写されるべき領域であり、そこには予め印刷やディスペンス技術により第２の積層構造体３５ｂ(及び第１の積層構造体３５ａ)の本体部分と同程度の大きさで接着層５３が形成されている。 Subsequently, as shown in FIG. 4D, the main body portion of the second laminated structure 35b peeled from the Si substrate 12 ′ and adhered to the adhesive material 42 sucked by the suction collet 41 is obtained. After moving to a predetermined position above the flexible circuit board 51, it moves downward as shown by an arrow 45 in FIG. 4D to form an adhesive layer 53 formed in a predetermined area on the surface of the flexible circuit board 51. Glue. Here, the predetermined region on the surface of the flexible circuit board 51 is a region to which the main body portion of the second laminated structure 35b between the formation regions of the copper wirings 54 and 55 is to be transferred. The adhesive layer 53 is formed in the same size as the main body portion of the second laminated structure 35b (and the first laminated structure 35a) by printing or dispensing technology.

なお、チップ実装機は顕微鏡などを用いたアライメント機能により、吸引コレット４１を移動してフレキシブル回路基板５１の任意の場所に、剥離させた積層構造体３５ｂ(及び３５ａ)の本体部分を±数μｍの精度でマウントできる。接着層５３は例えばエポキシ樹脂をスクリーン印刷したものであり、その接着力は粘着材４２の粘着力より大であるので、その後、粘着材４２を吸引している吸引コレット４１を上方向に引き上げると粘着材４２を第２の積層構造体３５ｂの本体部分から分離することができる。このようにして、フレキシブル回路基板５１の所定領域に第２の積層構造体３５ｂの本体部分が転写された極薄の電子デバイスを製造することができる。なお、一例として、フレキシブル回路基板５１は５０μｍの厚さであり、接着層５３は３０μｍの厚さであり、配線５４、５５は１８μｍの厚さである。したがって、電子デバイスは極薄の積層構造体の本体部分とフレキシブル回路基板５１とからなる極薄の構造である。 Note that the chip mounter moves the suction collet 41 by an alignment function using a microscope or the like, and places the main body portion of the laminated structure 35b (and 35a) peeled off at an arbitrary location on the flexible circuit board 51 by ± several μm. It can be mounted with the accuracy of. The adhesive layer 53 is, for example, screen-printed with an epoxy resin, and the adhesive strength thereof is greater than the adhesive strength of the adhesive material 42. Therefore, when the suction collet 41 that is sucking the adhesive material 42 is pulled upward thereafter. The adhesive 42 can be separated from the main body portion of the second laminated structure 35b. In this way, it is possible to manufacture an ultrathin electronic device in which the main body portion of the second laminated structure 35b is transferred to a predetermined region of the flexible circuit board 51. As an example, the flexible circuit board 51 has a thickness of 50 μm, the adhesive layer 53 has a thickness of 30 μm, and the wirings 54 and 55 have a thickness of 18 μm. Therefore, the electronic device has an extremely thin structure including the main body portion of the extremely thin laminated structure and the flexible circuit board 51.

次に、本発明に係る電子デバイスの配線構造について説明する。電子デバイスを駆動するためには配線処理が必要になる。微小サイズの電子デバイスでは、通常、直径数十μｍの金ワイヤなどによるワイヤボンディングや、はんだバンプを利用したリフローなどにより構造体の電極と基板上の配線とを接続する方法がとられる。しかし、本発明に係る電子デバイスのような極薄構造体では、ワイヤを電極に圧着させる際の衝撃で損傷することが確認されている。また、低融点であるポリマー材料などのフレキシブル回路基板に構造体を転写するため、高温となるリフローを用いることも困難である。 Next, the wiring structure of the electronic device according to the present invention will be described. Wiring processing is required to drive the electronic device. In a micro-sized electronic device, a method of connecting an electrode of a structural body and a wiring on a substrate by wire bonding using a gold wire having a diameter of several tens of μm, reflow using a solder bump, or the like is usually employed. However, it has been confirmed that an ultrathin structure such as an electronic device according to the present invention is damaged by an impact when a wire is crimped to an electrode. In addition, since the structure is transferred to a flexible circuit board such as a polymer material having a low melting point, it is difficult to use reflow at a high temperature.

そこで、本発明に係る電子デバイスにおいては、スクリーン印刷やインクジェット印刷、ディスペンサを用いた導電性ペーストの塗布による配線接続を行う。これらの印刷・塗布技術は段差のある箇所で断線することなくペースト材料を印刷・塗布することが苦手であるが、本発明に係る電子デバイスのような極薄の積層構造体は厚さが５μｍ程度であるため、その端部においても断線することなくペースト材料を印刷・塗布することが可能である。しかし、本発明に係る電子デバイスは、積層構造体の側面に上部電極(１７；１７ａ，１７ｂ)及び下部電極(１５；１５ａ，１５ｂ)が暴露された構造であるため、導電性ペーストを直接印刷・塗布するとショートが発生する。そこで、このショートが発生しないように配線する必要がある。 Therefore, in the electronic device according to the present invention, wiring connection is performed by screen printing, ink jet printing, or application of a conductive paste using a dispenser. These printing / coating techniques are not good at printing / coating the paste material without disconnection at the stepped portion, but the ultra-thin laminated structure like the electronic device according to the present invention has a thickness of 5 μm. Therefore, it is possible to print and apply the paste material without disconnection at the end portion. However, since the electronic device according to the present invention has a structure in which the upper electrode (17; 17a, 17b) and the lower electrode (15; 15a, 15b) are exposed on the side surface of the laminated structure, the conductive paste is directly printed.・ Short occurs when applied. Therefore, it is necessary to perform wiring so that this short circuit does not occur.

図５は、上記のショートの発生を防止した本発明に係る電子デバイスの配線構造の一例を説明する素子断面図を示す。図５中、図４と同一構成部分には同一符号を付し、その説明を省略する。ただし、図５では図４に示した符号の添字ｂは省略してある。添字ａを付して示す符号の第１の積層構造体についても同様に適用できるためであり、どちらでもよく区別が不要であるからである。 FIG. 5 is an element cross-sectional view illustrating an example of the wiring structure of the electronic device according to the present invention in which the occurrence of the short circuit is prevented. 5, the same components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted. However, in FIG. 5, the subscript b of the reference numeral shown in FIG. 4 is omitted. This is because the present invention can be similarly applied to the first laminated structure denoted by the suffix “a”, and it is not necessary to distinguish between them.

本発明の配線構造では、まず、図５(Ａ)の断面図に示すように、フレキシブル回路基板５１の表面の接着層５３に接着された積層構造体３５の本体部分の上部電極１７に接続された電極パッド１９側の端部に対して、絶縁性ペースト６１を印刷・塗布することで、積層構造体３５の電極パッド１９側の側面を保護する。絶縁性ペースト６１は、電極パッド１９の上面の一部、上部電極１７の端部、圧電薄膜１６の端部、下部電極１５の端部、表面Ｓi膜１４の端部、接着層５３の端部及びフレキシブル回路基板５１の表面の一部をそれぞれ被覆するように印刷・塗布されるが、配線５５には印刷・塗布されない。 In the wiring structure of the present invention, first, as shown in the cross-sectional view of FIG. 5A, it is connected to the upper electrode 17 of the main body portion of the laminated structure 35 adhered to the adhesive layer 53 on the surface of the flexible circuit board 51. The side surface on the electrode pad 19 side of the laminated structure 35 is protected by printing and applying the insulating paste 61 to the end portion on the electrode pad 19 side. The insulating paste 61 is a part of the upper surface of the electrode pad 19, the end of the upper electrode 17, the end of the piezoelectric thin film 16, the end of the lower electrode 15, the end of the surface Si film 14, and the end of the adhesive layer 53. The printed circuit board 51 is printed and applied so as to cover a part of the surface of the flexible circuit board 51, but is not printed or applied to the wiring 55 .

その後、図５(Ｂ)の断面図に示すように、電極パッド１９の上面から絶縁性ペースト６１の表面を経由して配線５５の表面の一部に至るまでの範囲を被覆するように導電性ペースト６２を印刷・塗布すると共に、積層構造体３５の下部電極１５に接続された電極パッド１８側の端部から配線５４までの範囲を被覆するように導電性ペースト６３を印刷・塗布する。これにより、上部電極１７と下部電極１５とのショートを発生させることなく、上部電極１７と配線５５とを電気的に接続できると共に、下部電極１５と配線５４とを電気的に接続できる。 Thereafter, as shown in the cross-sectional view of FIG. 5B, the conductive layer is covered so as to cover a range from the upper surface of the electrode pad 19 to a part of the surface of the wiring 55 via the surface of the insulating paste 61. The paste 62 is printed and applied, and the conductive paste 63 is printed and applied so as to cover the range from the end on the electrode pad 18 side connected to the lower electrode 15 of the laminated structure 35 to the wiring 54. Thus, the upper electrode 17 and the wiring 55 can be electrically connected without causing a short circuit between the upper electrode 17 and the lower electrode 15, and the lower electrode 15 and the wiring 54 can be electrically connected.

図６は、本発明に係る電子デバイスの配線構造の一例を説明する素子平面の顕微鏡写真の図を示す。同図中、図５と同一構成部分には同一符号を付し、その説明を省略する。図６(Ａ)は、フレキシブル回路基板５１の表面に積層構造体３５が転写された電子デバイスの平面の顕微鏡写真を示す。図６(Ｂ)は、図５(Ａ)と共に説明した積層構造体３５の本体部分の上部電極１７に接続された電極パッド１９側の端部に対して、絶縁性ペースト６１が印刷・塗布された状態の電子デバイスの平面の顕微鏡写真を示す。図６(Ｃ)は、図５(Ｂ)と共に説明した積層構造体３５の本体部分の下部電極パッド１９の上面から絶縁性ペースト６１の表面を経由して配線５５の表面の一部に至るまでの範囲に導電性ペースト６２が印刷・塗布され、かつ、積層構造体３５の本体部分の下部電極１５に接続された電極パッド１８側の端部及び配線５４とそれらの間に導電性ペースト６３が印刷・塗布された状態の電子デバイスの平面の顕微鏡写真を示す。 FIG. 6 shows a micrograph of the element plane for explaining an example of the wiring structure of the electronic device according to the present invention. In the figure, the same components as those in FIG. FIG. 6A shows a planar micrograph of an electronic device in which the laminated structure 35 is transferred to the surface of the flexible circuit board 51. In FIG. 6B, an insulating paste 61 is printed and applied to the end on the electrode pad 19 side connected to the upper electrode 17 of the main body portion of the laminated structure 35 described with reference to FIG. The plane micrograph of the electronic device in the state where it was in a state is shown. FIG. 6C shows from the upper surface of the lower electrode pad 19 of the main body portion of the laminated structure 35 described with reference to FIG. 5B to a part of the surface of the wiring 55 via the surface of the insulating paste 61. The conductive paste 62 is printed and applied in the range of the electrode pad 18 side and the wiring 54 connected to the lower electrode 15 of the main body portion of the laminated structure 35, and the conductive paste 63 is between them. The plane photomicrograph of the electronic device of the state printed and apply | coated is shown.

次に、本発明に係る電子デバイスの利用例について説明する。
図７は、本発明に係る電子デバイスの効果確認のための実験装置の一例の概略構成図を示す。同図において、一端が固定され、他端が上下に振動可能の非固定端とされた、扁平な直方体形状のステンレス板７１の固定端側付近に、本発明に係る電子デバイス７２と市販の歪みゲージ７３とが近接並行して接着されている。本発明に係る電子デバイス７２は例えば図５(Ｂ)の断面図に示した、機能性素子として圧電薄膜１６を備える電子デバイスで、その配線５４及び５５が増幅器７４を介してオシロスコープ７５の入力端子に接続されている。一方、市販の歪みゲージ７３は、出力端子が増幅器７６を介してパーソナルコンピュータ(パソコン)７７に接続されている。 Next, an application example of the electronic device according to the present invention will be described.
FIG. 7 shows a schematic configuration diagram of an example of an experimental apparatus for confirming the effect of the electronic device according to the present invention. In the figure, an electronic device 72 according to the present invention and a commercially available strain are placed near the fixed end side of a flat rectangular parallelepiped stainless steel plate 71, one end of which is fixed and the other end is a non-fixed end capable of vibrating up and down. The gauge 73 is bonded in close proximity and in parallel. The electronic device 72 according to the present invention is an electronic device including the piezoelectric thin film 16 as a functional element shown in the cross-sectional view of FIG. 5B, for example, and wirings 54 and 55 thereof are input terminals of an oscilloscope 75 via an amplifier 74. It is connected to the. On the other hand, the commercially available strain gauge 73 has an output terminal connected to a personal computer (personal computer) 77 via an amplifier 76.

かかる構成の装置におけるステンレス板７１の他端を図７に示すように、ステンレス板７１の反発力に抗して指先７８で下方向に押下した後、指先７８をステンレス板７１から離すと、ステンレス板７１の先端が固定端を支点として上下に振動する。このとき、オシロスコープ７５では図８に実線Iで示すように時間の経過とともに振動する波形の電圧(縦軸の左側の目盛り)が観測された。一方、このときパソコン７７では図８に一点鎖線IIで示すように時間の経過とともに振動するマイクロストレイン(縦軸の右側の目盛り)が観測された。上記の電圧波形の振幅値及びマイクロストレインの値は、指先７８の押圧力に対応した振動の大きさに応じて変化した。これにより、本発明に係る電子デバイス７２は、市販の歪みゲージ７３と同様に歪みセンサとしての応用例が可能であることが示された。 As shown in FIG. 7, the other end of the stainless steel plate 71 in the apparatus having such a configuration is pressed downward by the fingertip 78 against the repulsive force of the stainless steel plate 71, and then the fingertip 78 is separated from the stainless steel plate 71. The tip of the plate 71 vibrates up and down with the fixed end as a fulcrum. At this time, as shown by a solid line I in FIG. 8, the oscilloscope 75 observed a waveform voltage (scale on the left side of the vertical axis) that oscillates with time. On the other hand, at this time, as shown by a one-dot chain line II in FIG. The amplitude value of the voltage waveform and the value of the microstrain changed according to the magnitude of vibration corresponding to the pressing force of the fingertip 78. Thereby, it was shown that the electronic device 72 according to the present invention can be applied as a strain sensor in the same manner as the commercially available strain gauge 73.

なお、本発明は以上の実施形態に限定されるものではなく、その他種々の変形例を包含するものである。例えば、本発明に係る電子デバイスは、ＳＯＩ基板の平面四角枠状のＳi基板の枠部分のみに、積層構造体の本体部分が支持部で支持されるように架け渡される構造であるが、その支持構造は積層構造体の底面の長手方向に直交する幅よりも短い長さ部分からなる平面形状の複数の支持部からなる構成であれば形状を問わない。例えば、実施形態ではＳi基板１２’の枠部分に積層構造体の本体部分を支持する支持部２０、２１の平面形状は、図１(Ｄ)及び図９(Ａ)に示したようなテーパ形状であったが、本発明は図９(Ｂ)〜(Ｆ)に示した各形状のいずれであってもよい。なお、積層構造体の底面の幅である積層構造体の底面の長手方向に直交する方向の長さは、例えば下部電極の幅に略等しい。 In addition, this invention is not limited to the above embodiment, It includes other various modifications. For example, the electronic device according to the present invention has a structure in which the main body portion of the laminated structure is spanned only on the frame portion of the planar square frame Si substrate of the SOI substrate so that the main body portion is supported by the support portion. The shape of the support structure is not limited as long as the support structure includes a plurality of planar support portions each having a length shorter than the width orthogonal to the longitudinal direction of the bottom surface of the laminated structure. For example, in the embodiment, the planar shape of the support portions 20 and 21 that support the main body portion of the laminated structure on the frame portion of the Si substrate 12 ′ is a tapered shape as shown in FIG. 1 (D) and FIG. 9 (A). However, the present invention may have any of the shapes shown in FIGS. Note that the length in the direction perpendicular to the longitudinal direction of the bottom surface of the multilayer structure, which is the width of the bottom surface of the multilayer structure, is approximately equal to the width of the lower electrode, for example.

ここで、図９(Ｂ)は、Ｓi基板１２’の枠部分に積層構造体を支持する支持部８１、８２の平面形状がテーパ形状を示しているが、図１(Ｄ)及び図９(Ａ)に示す実施形態のテーパ形状がＳi基板１２’の枠部分方向に従って幅が狭くなる形状であるのに対し、Ｓi基板１２’の枠部分において最も幅が広く積層構造体本体方向に従って幅が狭くなる形状である点で異なる。すなわち、図１(Ｄ)及び図９(Ａ)に示す実施形態の支持部８１、８２はテーパ形状の先細りの先端部分付近がＳi基板１２’の枠部分に位置し、図９(Ｂ)に示す支持部８３、８４は積層構造体の本体部分に位置する。 Here, FIG. 9B shows that the planar shape of the support portions 81 and 82 for supporting the laminated structure on the frame portion of the Si substrate 12 ′ is a taper shape, but FIG. 1D and FIG. The taper shape of the embodiment shown in A) is a shape in which the width becomes narrower in the frame portion direction of the Si substrate 12 ′, whereas the width is widest in the frame portion of the Si substrate 12 ′, and the width in the direction of the stacked structure body. The difference is that the shape is narrower. That is, in the support portions 81 and 82 of the embodiment shown in FIGS. 1D and 9A, the vicinity of the tapered tip end portion is located at the frame portion of the Si substrate 12 ′, and FIG. The support parts 83 and 84 shown are located in the main-body part of a laminated structure.

また、図９(Ｃ)に示す支持部８３、８４の平面形状、及び図９(Ｄ)に示す支持部８５、８６の平面形状がいずれも直線と曲線とで囲まれた半円形状であるが、曲線部分の位置が異なる。また、図９(Ｅ)に示す支持部８７、８８は、その平面形状が鼓のように三角形の頂点同士が結合された対向する２つの三角形からなる形状である。更に、図９(Ｆ)に示す支持部８９、９０は、その平面形状が幅の狭い長方形状である。 Also, the planar shape of the support portions 83 and 84 shown in FIG. 9C and the planar shape of the support portions 85 and 86 shown in FIG. 9D are both semicircular shapes surrounded by straight lines and curves. However, the position of the curved part is different. Further, the support portions 87 and 88 shown in FIG. 9 (E) have a shape formed by two opposing triangles in which the vertexes of the triangles are joined like a drum. Further, the support portions 89 and 90 shown in FIG. 9F have a rectangular shape with a narrow planar shape.

また、図１及び図３ではＳＯＩ基板のＳi基板に対してＳiＯ₂膜及び表面Ｓi膜の積層部分をテーパ形状に形成しているが、ＳＯＩ基板のＳi基板及びＳiＯ₂膜の積層部分に対して表面Ｓi膜のみをテーパ形状に形成するようにしてもよい。また、図５では積層構造体３５の電極パッド１９側の側面のみを絶縁性ペースト６１により保護するように説明したが、積層構造体３５の電極パッド１８側の側面も絶縁性ペーストにより保護するようにしてもよい。 1 and 3, the laminated portion of the SiO ₂ film and the surface Si film is formed in a tapered shape with respect to the Si substrate of the SOI substrate, but the laminated portion of the Si substrate and the SiO ₂ film of the SOI substrate. Only the surface Si film may be formed in a tapered shape. In FIG. 5, the side surface on the electrode pad 19 side of the laminated structure 35 is described as being protected by the insulating paste 61, but the side surface on the electrode pad 18 side of the laminated structure 35 is also protected by the insulating paste. It may be.

また、本発明における所定の機能を実現するための機能性素子には、上記の実施形態の圧電薄膜以外に、半導体歪みゲージ、磁性薄膜、ホール素子、熱電変換材料、赤外線検出素子、半導体信号処理回路などを含む。また、転写される回路基板はフレキシブル回路基板５１として説明したが、フレキシブルでなくても構わない。更に、基板はＳＯＩ基板でなくてもよく、例えばＳi基板上のＳiＯ₂層の表面にアルミナの薄膜が形成されたアルミナオンインシュレータのような基板でもよい。 In addition to the piezoelectric thin film of the above embodiment, the functional element for realizing a predetermined function in the present invention includes a semiconductor strain gauge, a magnetic thin film, a Hall element, a thermoelectric conversion material, an infrared detection element, and a semiconductor signal processing. Including circuits. Moreover, although the circuit board to be transferred has been described as the flexible circuit board 51, it may not be flexible. Further, the substrate may not be an SOI substrate, and may be a substrate such as an alumina-on-insulator in which an alumina thin film is formed on the surface of the SiO ₂ layer on the Si substrate.

更に、本発明は、例えば互いに同一又は少なくとも一部が異なる種類の機能性素子をそれぞれ有する複数の積層構造体の本体部分を、粘着材で複数の電子デバイスの各積層基板から同時にあるいは個別に剥離し、剥離したそれら複数の積層構造体の本体部分を大面積の一の回路基板上に接着して転写するような構成も包含するものである。この場合、大面積の一の回路基板に異なる複数の積層構造体の本体部分を同時に接着して転写するか、あるいは素子ごとに別個に接着して転写する。例えば、温度センサ、加速度センサ、信号処理回路では、別々のウェハで異なる種類の構造体を作製し、それら異なる種類の複数の構造体を剥離して一の回路基板に接着して転写する。 Furthermore, the present invention provides a method in which the main body portions of a plurality of laminated structures each having, for example, the same or different types of functional elements are separated from each laminated substrate of a plurality of electronic devices simultaneously or individually with an adhesive. In addition, a configuration is also included in which the peeled main body portions of the laminated structures are bonded and transferred onto a circuit board having a large area. In this case, the main body portions of a plurality of different laminated structures are simultaneously bonded and transferred to a circuit board having a large area, or are bonded and transferred separately for each element. For example, in a temperature sensor, an acceleration sensor, and a signal processing circuit, different types of structures are manufactured using different wafers, and a plurality of different types of structures are peeled off and bonded to a single circuit board for transfer.

本発明は、橋梁やトンネルなどのコンクリート構造体の歪みモニタリング、産業機械の振動モニタリング、人や動物などの健康モニタリングその他各種の用途に使用可能である。 INDUSTRIAL APPLICABILITY The present invention can be used for strain monitoring of concrete structures such as bridges and tunnels, vibration monitoring of industrial machines, health monitoring of humans and animals, and other various uses.

１１ＳＯＩ基板
１２シリコン(Ｓi)基板
１２’ 平面四角枠状のシリコン(Ｓi)基板
１３二酸化シリコン(ＳiＯ₂)層
１３ａ、１３ａ’、１３ｂ、１３ｂ’ 二酸化シリコン(ＳiＯ₂)膜
１４表面シリコン(Ｓi)層
１４ａ、１４ｂ表面シリコン(Ｓi)膜
１５ａ、１５ｂ、１５下部電極
１６ａ、１６ｂ、１６圧電薄膜
１７ａ、１７ｂ、１７上部電極
１８ａ、１８ｂ、１８、１９ａ、１９ｂ、１９電極パッド
２０、２１、８１〜９０支持部
２１’ 残存した支持部
２２ａ、２２ｂ凹部
３０、７２電子デバイス
３５積層構造体
３５ａ第１の積層構造体
３５ｂ第２の積層構造体
４１吸引コレット
４２粘着材
４３〜４５矢印
５１フレキシブル回路基板
５３接着層
５４、５５配線
６１絶縁性ペースト
６２、６３導電性ペースト
７１ステンレス板
７３市販の歪みゲージ
７４、７６増幅器
７５オシロスコープ
７７パーソナルコンピュータ(パソコン) 11 SOI substrate 12 a silicon (Si) substrate 12 'flat rectangular frame-shaped silicon (Si) substrate 13 of silicon dioxide (SiO ₂₎ layer 13a, 13a', 13b, 13b ' of silicon dioxide (SiO ₂₎ film 14 surface silicon (Si ) Layers 14a, 14b Surface silicon (Si) films 15a, 15b, 15 Lower electrodes 16a, 16b, 16 Piezoelectric thin films 17a, 17b, 17 Upper electrodes 18a, 18b, 18, 19a, 19b, 19 Electrode pads 20, 21, 81 -90 Support part 21 'Remaining support part 22a, 22b Recessed part 30, 72 Electronic device 35 Laminated structure 35a First laminated structure 35b Second laminated structure 41 Suction collet 42 Adhesive material 43-45 Arrow 51 Flexible circuit Substrate 53 Adhesive layer 54, 55 Wiring 61 Insulating paste 62, 63 Conductive paste 71 Stainless steel 73 commercially available strain gauges 74, 76, amplifier 75 oscilloscope 77 personal computer (PC)

Claims

A silicon substrate having a square frame shape in plan view,
A silicon layer and the functional element and the functional input signal or the electrode and the and an electrode pad of the electrode which is stacked structure for the output signal of the device for realizing a predetermined function on the ,
A plurality of support portions in which the silicon layer extends to the periphery of the structure, and the silicon layers are in contact with the silicon substrate via the silicon dioxide layer ;
With
The support portion has a planar shape including a portion shorter than the length of the width orthogonal to the longitudinal direction of the structure, and the structure is supported by the support portion only on the frame portion of the silicon substrate. It has a body and hung on the silicon substrate structure, so formed as to be capable of transferring the structure to a desired circuit board was peeled from the silicon substrate, an electronic device.

The electronic device according to claim 1 , wherein the planar shape of the support portion is a shape formed of two opposing triangles in which vertices are coupled to each other .

The electronic device according to claim 1 , wherein the planar shape of the support portion is a rectangular shape having a width shorter than the width of the structure .

A functional element for realizing a predetermined function on the surface of the SOI substrate in which a silicon substrate, a silicon dioxide layer, and a silicon layer are formed in this order, an electrode for an input signal or an output signal of the functional element, and the electrode A step of forming a structure having a plurality of electrode pads and a plurality of support portions in a peripheral portion of the structure, wherein the support portions are shorter than a width perpendicular to the longitudinal direction of the structure A process having a planar shape comprising:
Removing the silicon substrate and the silicon dioxide layer from the back surface of the SOI substrate to form the frame-shaped silicon substrate and the plurality of support portions made of the silicon layer, whereby the structure A structure is formed in which the frame-like silicon substrate is bridged by the plurality of support portions via the silicon dioxide layer, and
A peeling step of breaking the structure by breaking the support part ;
The structure and the release, a transfer step of transferring to a predetermined area of the desired flexible circuit board,
A first covering step of applying an insulating paste that covers a part of the surface of the electrode pad, an end of the functional element, and an end of the electrode, and extends to the surface of the flexible circuit board; ,
Covering a surface other than the part of the surface of the electrode pad and a part of the surface of the insulating paste and extending to the surface of the wiring part on the flexible circuit board, the electrode pad and the wiring part, A second coating step of applying a conductive paste that electrically connects
A method of manufacturing an electronic device comprising :

The method of manufacturing an electronic device according to claim 4, wherein the planar shape of the support portion is a shape formed of two opposing triangles whose vertices are coupled to each other.

5. The method of manufacturing an electronic device according to claim 4, wherein the support portion has a rectangular shape having a shorter planar shape than a width perpendicular to the longitudinal direction of the structure.

In the peeling step, the adhesive material sucked at the tip of the suction collet of the chip mounting machine is adhered to the uppermost surface of the structure, and then the structure is adhered to the adhesive material by the suction collet. It is a step of peeling the structure from the substrate by pulling up the adhesive material,
The transfer step is performed after adhering to an adhesive layer formed in advance in the predetermined area of the desired circuit board in a state where the structure is adhered to the adhesive material sucked by the suction collet. The method for manufacturing an electronic device according to claim 4, wherein the structure is a step of transferring the structure to a predetermined region of the desired circuit board by pulling up the adhesive material with the suction collet.

A flexible substrate;
A structure on the flexible substrate, a silicon layer, a functional element for realizing a predetermined function thereon, an electrode for an input signal or an output signal of the functional element, and an electrode pad for the electrode And the structure in which they are laminated,
A wiring portion on the flexible substrate;
An insulating paste that covers a part of the surface of the electrode pad, an end of the functional element, and an end of the electrode, and extends to the surface of the flexible substrate;
A conductive paste covering a surface other than the part of the surface of the electrode pad and a part of the surface of the insulating paste and extending to the surface of the wiring part, the electrode pad and the wiring part being The conductive paste for electrical connection;
An electronic device comprising:

The electronic device according to claim 8, further comprising an adhesive layer between the silicon layer and the flexible substrate of the structure.

10. The functional element according to claim 1, wherein the functional element is at least one of a piezoelectric thin film, a semiconductor strain gauge, a magnetic thin film, a Hall element, a thermoelectric conversion material, an infrared detection element, and a semiconductor signal processing circuit. The electronic device as described in any one of them, or the manufacturing method of the electronic device as described in any one of Claims 4-7.