JP6558317B2 - Electronic equipment - Google Patents

Description

  The present invention relates to an electronic device that performs an operation.

  Conventionally, there is an in-vehicle control device disclosed in Patent Document 1 as an example of an electronic device that executes a calculation. This in-vehicle control device initializes a variable in which a non-number has occurred, and initializes variables affected by the variable in which a non-number has occurred, such as a variable calculated by referring to the variable.

JP 2011-164814 A

  Incidentally, some electronic devices include a plurality of processing units that execute operations in parallel. In such an electronic apparatus, a variable in which an operation error has occurred, for example, the operation result becomes non-numeric, and a variable affected by this variable may be arranged in different processing units. In addition, when a variable is calculated in another processing unit of the plurality of processing units, the processing unit holds the value of the variable, and then performs calculation of another variable using the stored value.

  Therefore, when an error occurs in a calculation in another processing unit, the processing unit may hold a variable value before the error occurs. For this reason, even if the variable obtained by the operation in which the error has occurred is initialized by another processing unit, and the variable affected by this variable is initialized, the stored error is The calculation of other variables is performed using the variable value obtained by the calculation before the occurrence. Therefore, the electronic device has a problem that the variable calculated using the variable value obtained by the calculation before the error is not initialized.

  The present disclosure has been made in view of the above-described problem, and a plurality of processing units that execute variable operations in parallel are calculated using this variable in addition to the variable obtained by the operation in which the error occurred. An object is to provide an electronic device capable of initializing variables.

In order to achieve the above object, the present disclosure
An electronic device including a plurality of processing units,
Each processing unit
A calculation unit (S10, S22) for calculating a variable;
A determination unit (S11, S23) for determining whether or not an error has occurred in the calculation in the calculation unit in the processing unit;
A first initialization unit (S14, S26) that initializes a variable of the processing unit obtained by an operation in which it is determined that an error has occurred when the determination unit determines that an error has occurred; ,
While holding the variable value obtained by the calculation of the calculation unit in the other processing unit, the calculation unit calculates the variable related to the variable calculated by the other processing unit using the held variable value,
further,
When the calculation of the calculation unit is executed in parallel between multiple processing units and the determination unit determines that an error has occurred, an error has occurred in order to share that the error has occurred among the multiple processing units An error storage unit (S13, S25) for storing
A monitoring unit (S15, S27) for monitoring whether or not an error has occurred in the calculation in the calculation unit of the other processing unit by checking the error storage unit;
A second initialization unit (S16, S28) that initializes a variable of the self-processing unit related to a variable obtained by an operation in which the error has occurred when an error has occurred in monitoring by the monitoring unit; It is characterized by having.

  As described above, the present disclosure is obtained by the operation in which it is determined that an error has occurred when it is determined whether or not an error has occurred in the operation in the operation unit in the processing unit. Initialize the variables of the self-processing section. In addition, when it is determined that an error has occurred, the present disclosure stores the fact that an error has occurred in a storage unit in order to share the occurrence of the error among a plurality of processing units, and confirms this storage unit. Then, it is monitored whether or not an error has occurred in the calculation in the calculation unit of the other processing unit.

  For this reason, each processing unit of the present disclosure can grasp whether or not the variable used in the calculation in the calculation unit in the self-processing unit is a variable obtained by the calculation in which an error has occurred. And this indication initializes the variable of the self-processing part relevant to the variable obtained by the calculation in which the error has generate | occur | produced, when the monitoring part monitors and the error has generate | occur | produced. Therefore, according to the present disclosure, a plurality of processing units that execute a variable calculation can initialize a variable calculated using this variable in addition to the variable obtained by the calculation in which the error has occurred.

  It should be noted that the reference numerals in parentheses described in the claims and in this section indicate the correspondence with the specific means described in the embodiments described later as one aspect, and the technical scope of the invention It is not limited.

It is a block diagram which shows schematic structure of the microcomputer in embodiment. It is a sequence diagram which shows the processing operation of the microcomputer in embodiment. It is a flowchart which shows the processing operation of the 1st core in embodiment. It is a flowchart which shows the processing operation of the 2nd core in embodiment.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. As shown in FIG. 1, the ECU 200 is provided with a microcomputer 100. The ECU 200 may be provided with various electronic elements in addition to the microcomputer 100.

  The microcomputer 100 corresponds to an electronic device. In the following, the microcomputer 100 is abbreviated as the microcomputer 100. The microcomputer 100 includes a first core 10, a first core RAM 12, a second core 20, a second core RAM 22, a shared RAM 30, and the like. Thus, the microcomputer 100 is a so-called dual core microcomputer. However, the present invention can also be adopted in a multi-core microcomputer including three or more cores.

  Each of the first core 10 and the second core 20 corresponds to a processing unit. Each of the cores 10 and 20 executes a predetermined program in accordance with a predetermined calculation order. Each of the cores 10 and 20 is configured to be able to execute a floating point operation. The core can also be called an arithmetic processor or a CPU core. The processing operations of the cores 10 and 20 will be described in detail later.

  The first core 10 includes a first flag area 11 that is a storage area in which a first core flag is stored. The first core flag is a flag whose value is set by the first core 10. The first core flag is a flag indicating whether or not an error has occurred in the calculation by the first core 10, that is, the calculation state of the first core 10. Therefore, the value of the first core flag is rewritten depending on whether or not an error has occurred in the calculation performed by the first core 10. Only the first core 10 can set the value of the first core flag. For this reason, the second core 20 cannot set the value of the first core flag.

It can be said that the first core 10 turns on the first core flag when it is determined that an error has occurred in the calculation of its own core 10 and turns off the first core flag when it is not determined that an error has occurred. The first core 10 can be said to write an error state by turning on the first core flag and write a non-error state by turning off the first core flag.
On the other hand, the second core 20 includes a second flag area 21 which is a storage area in which a second core flag is stored. The second core flag is a flag whose value is set by the second core 20. The second core flag is a flag indicating whether or not an error has occurred in the calculation by the second core 20, that is, the calculation state of the second core 20. Therefore, the value of the second core flag is rewritten depending on whether or not an error has occurred in the calculation by the second core 20. Only the second core 20 can set the value of the second core flag. For this reason, the first core 10 cannot set the value of the second core flag.

  It can be said that the second core 20 turns on the second core flag when it is determined that an error has occurred in the calculation of its own core 20 and turns off the second core flag when it is not determined that an error has occurred. Further, it can be said that the second core 20 writes an error state by turning on the second core flag and writes a non-error state by turning off the second core flag.

  As described above, each of the cores 10 and 20 is configured to be able to store the fact that an error has occurred in the calculation of the own core. The setting of each core flag will be described later together with the processing operations of the cores 10 and 20.

  The first core RAM 12 (hereinafter referred to as the first RAM 12) is a storage device dedicated to the first core 10. The first RAM 12 stores variables used only by the first core 10. On the other hand, the second core RAM 22 (hereinafter, the second RAM 22) is a storage device dedicated to the second core 20.

  The second RAM 22 includes a variable area 22a as a storage area, and stores variables used only by the second core 20. For example, the variable area 22a stores a variable d used only by the second core 20. The variable d is calculated by the second core 20 and the value is rewritten. The variable area 22a corresponds to a variable storage unit.

  The shared RAM 30 is a storage device provided in common for the first core 10 and the second core 20. The shared RAM 30 includes a first shared area 31, a second shared area 32, and a third shared area 33 as storage areas. The first shared area 31 stores a first flag whose value is set by the first core 10. The second shared area 32 stores a second flag whose value is set by the second core 20. Therefore, the first core 10 can refer to the value of the second flag. Similarly, the second core 20 can refer to the value of the first flag.

  The first flag is a flag indicating whether or not an error has occurred in the calculation performed by the first core 10, similarly to the first core flag. Therefore, the value of the first flag indicates the same calculation state of the first core 10 as the first core flag. For this reason, the second core 20 can recognize the calculation state of the first core 10 by referring to the value of the first flag.

  On the other hand, the second flag is a flag indicating whether or not an error has occurred in the calculation by the second core 20, similarly to the second core flag. Therefore, the value of the second flag indicates the same calculation state of the second core 20 as the second core flag. Therefore, the first core 10 can recognize the calculation state of the second core 20 by referring to the value of the second flag.

  It can be said that the first core 10 turns on the first flag when it is determined that an error has occurred in the calculation of its own core 10 and turns off the first flag when it is not determined that an error has occurred. Similarly, it can be said that the second core 20 turns on the second flag when it is determined that an error has occurred in the calculation of its own core 20 and turns off the second flag when it is not determined that an error has occurred.

  The third shared area 33 stores variables used by both the first core 10 and the second core 20. For example, the third shared area 33 stores a variable c used by the first core 10 and the second core 20. The variable c is calculated by the first core 10 and the value is rewritten.

  By the way, the floating point calculation executed by each of the cores 10 and 20 is an operation using floating point type data. The floating-point type data as a result of the operation is stored in the first RAM 12, the second RAM 22, or the shared RAM 30. The floating point type data of the calculation result corresponds to a variable. Therefore, the variable c and variable d are floating point type data.

  The variable c is obtained when the first core 10 performs a floating point operation. That is, the first core 10 calculates the variable c stored in the third shared area 33 and updates the variable c to a value obtained by the calculation. Therefore, it can be said that the first core 10 rewrites the variable c of the third shared region 33 with the value of the calculation result.

  On the other hand, the variable d is obtained when the second core 20 performs a floating point operation. That is, the second core 20 calculates the variable d stored in the variable area 22a and updates the variable d to a value obtained by the calculation. Therefore, it can be said that the second core 20 rewrites the variable d in the variable area 22a with the value of the calculation result. Further, the second core 20 calculates the variable d using the held value while holding the value of the variable c. For this reason, the variable c corresponds to a variable obtained by calculation of the calculation unit in the other processing unit. The variable d corresponds to a variable related to the held variable. Moreover, it can be said that the variable c and the variable d are related variables.

  Thus, the variable c is stored in the third shared area 33 of the shared RAM 30 because it is used by both the first core 10 and the second core 20. On the other hand, the variable d is stored in the second RAM 22 because it is not used by the first core 10 and does not need to be stored in the shared RAM 30.

  Each of the cores 10 and 20 represents floating point type data in a data format in accordance with, for example, the IEEE754 standard. Single-precision floating-point data conforming to the IEEE 754 standard is composed of a 1-bit sign part, an 8-bit exponent part, and a 23-bit mantissa part.

  In the floating point data of this standard, for example, an operation result that cannot be expressed as a numerical value can be expressed as a non-number. An operation result such as an operation that divides by 0 or an operation that uses ∞ (infinity) is an example of an operation result that cannot be expressed as a numerical value.

  For example, in this standard, when all the 8 bits of the exponent part are 1, that is, when the exponent part is 255 in decimal notation and the mantissa part is other than 0, this floating point type data is represented as a non-number. Also, in this standard, when all 8 bits of the exponent part are 1 and the mantissa part is 0, this floating point type data is represented as infinity. Note that an operation that results in an operation that cannot be expressed as a numerical value, such as an operation that divides by 0 or an operation that uses infinity, is an invalid operation.

  Further, when the data calculated by the cores 10 and 20 is non-numeric or infinite, it can be said that an error has occurred in the calculation by the cores 10 and 20. Furthermore, when the calculation in each of the cores 10 and 20 is an invalid calculation, it can be said that an error has occurred in the calculation in each of the cores 10 and 20.

  In the following, a case where the floating point type data calculated by each of the cores 10 and 20 is a non-numeric is adopted as an example in which an error has occurred in the calculation. Therefore, it is assumed that the first core flag and the first flag indicate whether or not the variable obtained by the calculation of the first core 10 is non-numeric. On the other hand, the second core flag and the second flag indicate whether or not the variable obtained by the calculation of the second core 20 is non-numeric.

  Here, processing operations of the first core 10 and the second core 20 will be described with reference to FIGS. 2, 3, and 4. The first core 10 and the second core 20 execute operations in parallel as shown in FIG. In the present embodiment, as an example, a case where a non-number occurs in the first core 10 and a non-number does not occur in the second core 20 is employed.

  First, the processing operation of the first core 10 will be described with reference to FIG. The first core 10 starts the flowchart of FIG. 3 at a predetermined execution timing.

  In step S10, the variable c is calculated (calculation unit). When the first core 10 starts processing, the first core 10 calculates a variable c.

  In step S11, it is determined whether or not a non-number has occurred (determination unit). The first core 10 determines whether or not a non-number has occurred in the calculation in step S10. In other words, the first core 10 determines whether an error has occurred in the calculation in the own core 10. In the first core 10, for example, when c = 9/0, a non-number occurs.

  If the first core 10 determines that a non-number has occurred in step S11, the process proceeds to step S12. In step S12, the second core 20 is notified of the non-number state. If the first core 10 determines that a non-number has occurred in step S <b> 11, the first core 10 notifies the second core 20 that a non-number has occurred in its own core 10. Note that the present invention can achieve the object even if step S12 is omitted.

  In step S13, the first flag is turned on (error storage unit). The first core 10 turns on the first flag of the first shared area 31 when it is determined in step S11 that the non-number has occurred. In other words, the first core 10 writes a non-numbered state in the first shared area 31.

  As described above, the first core 10 performs the operation in parallel with the second core 20, and when it is determined that a non-number has occurred, the first core 10 shares that the non-number has occurred with the second core 20. Therefore, it can be said that the occurrence of the non-number is stored in the shared RAM 30. In addition, the first core 10 turns on the first flag of the first shared area 31 to indicate that a non-number has occurred in the own core 10 with the second core 20 that is executing operations in parallel. Share it. In addition, the 1st core 10 turns on the 1st flag of the 1st shared area 31 while turning ON a 1st core flag, when it determines with the non-number having generate | occur | produced at step S11.

  In step S14, the variable c is initialized (first initialization unit). The first core 10 initializes the variable c in which the non-number has occurred. That is, when the first core 10 determines that a non-number has occurred, the first core 10 initializes the variable c of the own core 10 obtained by the operation determined that the non-number has occurred.

  If the first core 10 does not determine that a non-number has occurred in step S11, the first core 10 proceeds to step S15. In step S15, it is determined whether or not the second flag is on (monitoring unit). Whether the first core 10 confirms the second shared area 32, that is, confirms the second flag, whether or not a non-number has occurred in the calculation in the second core 20 that is another processing unit. To monitor.

  If the first core 10 determines that the second flag is on, the process proceeds to step S16. If the first core 10 does not determine that the second flag is on, the process proceeds to step S17. As will be described later, the second core 20 turns on the second flag when a non-number occurs in the calculation in the own core 20 as in the first core 10.

  In step S16, the variable c is initialized (second initialization unit). If the first core 10 determines in step S15 that the second flag is on and an arithmetic operation in the second core 20 has caused a non-number, the variable c related to the variable d in which the non-number has occurred. Is initialized. The first core 10 is set to c = 0, for example. The first core 10 can confirm whether or not the variable c is related to the variable d, for example, according to the contents of the program. In addition, the 1st core 10 does not need to perform step S16, when it determines with the variable c not relating to the variable d.

  In step S17, the calculation result is written in the variable c. The first core 10 writes the calculation result in step S <b> 10 in the third shared area 33.

  Next, the processing operation of the second core 20 will be described with reference to FIG. The second core 20 starts the flowchart of FIG. 4 at a predetermined execution timing.

  In step S20, the variable c is latched. The second core 20 reads the variable c stored in the third shared area 33 and stores (holds) the variable c in the second RAM 22.

  In step S21, the variable d is initialized by notification. When the second core 20 is notified of the non-number state from the first core 10, the second core 20 initializes the variable d. The second core 20 has d = 0, for example. Naturally, the second core 20 does not initialize the variable d when there is no notification of the non-number state from the first core 10.

  In step S22, the variable d is calculated (calculation unit). The second core 20 calculates the variable d using the variable c latched in step S20. As described above, the second core 20 calculates the variable d related to the held variable c using the held variable c while holding the variable c obtained by the calculation in the first core 10.

  In step S23, it is determined whether or not a non-number has occurred (determination unit). The second core 20 determines whether or not an error has occurred in the calculation in the own core 20. If the second core 20 determines that a non-number has occurred in step S23, the process proceeds to step S24.

  In step S24, the first core 10 is notified of non-numeric information. The second core 20 can achieve its purpose even if step S24 is omitted.

  In step S25, the second flag is turned on (error storage unit). The second core 20 turns on the second flag of the second shared area 32 when it is determined in step S23 that the non-number has occurred. In other words, the second core 20 writes the non-number state in the second shared area 32.

  As described above, the second core 20 performs the operation in parallel with the first core 10, and when it is determined that a non-number has occurred, the second core 20 shares that the non-number has occurred with the first core 10. Therefore, it can be said that the occurrence of the non-number is stored in the shared RAM 30. In addition, the second core 20 turns on the second flag of the second shared area 32, so that a non-number has occurred in the own core 20 with the first core 10 that is executing operations in parallel. Share it. If the second core 20 determines that a non-number has occurred in step S23, the second core 20 turns on the second core flag and turns on the second flag of the second shared region 32.

  In step S26, the variable d is initialized (first initialization unit). The second core 20 initializes the variable d in which the non-number has occurred. That is, when the second core 20 determines that a non-number has occurred, the second core 20 initializes the variable d of the own core 20 obtained by the operation determined that the non-number has occurred.

  If the second core 20 does not determine that a non-number has occurred in step S23, the process proceeds to step S27. In step S27, it is determined whether or not the first flag is on (monitoring unit). Whether the second core 20 confirms the first shared area 31, that is, confirms the first flag, whether or not a non-number has occurred in the calculation in the first core 10 that is another processing unit. To monitor. If the second core 20 determines that the first flag is on, the process proceeds to step S28. If the second core 20 does not determine that the first flag is on, the process proceeds to step S29.

  In step S28, the variable d is initialized (second initialization unit). If the second core 20 determines that the first flag is on in step S27 and that a non-number has occurred in the calculation in the first core 10, the variable d related to the variable c in which the non-number has occurred. Is initialized. That is, the second core 20 initializes the variable d calculated by the own core 20 using the variable c when a non-number has occurred in the variable c calculated by the other core 10. The second core 20 has d = 0, for example. The second core 20 can confirm whether or not the variable d is related to the variable c, for example, based on the contents of the program.

  Note that the second core 20 may perform a calculation using the variable c even for a variable different from the variable d. Variables that are calculated by the second core 20 using the variable c are stored in the second RAM 22 and the shared RAM 30. In this case, in step S <b> 28, the second core 20 may initialize not only the variable d but also all variables that perform the calculation using the variable c.

  In addition, when the variable d is calculated in step S22, the second core 20 may update the variable d in the variable region 22a to a value obtained by the calculation before step S27. However, in this embodiment, when it is determined in step S27 that the first flag is on, the variable d in the variable area 22a is initialized before the variable d in the variable area 22a is updated to a value obtained by the calculation. To do. Thereby, the microcomputer 100 can suppress the variable d of the variable area 22a being updated twice. Further, the microcomputer 100 can suppress the variable d in the variable area 22a from being updated to a value calculated using the variable c in which a non-number has occurred.

  The variables c and d calculated by the cores 10 and 20 may be used for various controls. In this case, the microcomputer 100 can prevent the variable d in the variable area 22a from being updated to a value calculated using the variable c in which a non-number has occurred, and thus can improve the reliability of control using the variable d. .

  In step S29, the calculation result is written in the variable d. The second core 20 writes the calculation result in step S22 in the variable area 22a.

  Next, processing operations of the first core 10 and the second core 20 will be described with reference to the sequence diagram of FIG. At timing t1, the first core 10 and the second core 20 start processing. Therefore, the first core executes the process of step S10, and the second core 20 executes step S20.

  At timing t2, the first core 10 executes steps S11 and S12, and the second core 20 receives the notification of the non-number state and executes step S21. At timing t3, the first core 10 executes step S13, and the second core 20 executes step S22. At this time, the second core 20 calculates the variable d using the variable c latched in step S20.

  At timing t4, the first core 10 executes step S14, and the second core 20 executes step S23. At timing t5, the second core 20 executes step S27. At timing t6, step S28 is executed. Note that at the timing t6, the first core 10 is in an idle state.

  As described above, the microcomputer 100 determines whether or not a non-number has occurred in the calculation in the first core 10, and when it is determined that a non-number has occurred, the microcomputer 100 can obtain the calculation that has determined that the non-number has occurred. The variable c of the own core 10 is initialized. Similarly, the microcomputer 100 determines whether or not a non-number has occurred in the calculation in the second core 20, and when it is determined that a non-number has occurred, the microcomputer 100 is obtained by the operation determined to have generated the non-number. The variable d of the own core 20 is initialized.

  In addition, when it is determined that the non-number has occurred, the microcomputer 100 shares that the non-number has occurred in order to share the occurrence of the non-number between the first core 10 and the second core 20. Store in the RAM 30. Then, the microcomputer 100 checks whether the cores 10 and 20 check the shared RAM 30 and whether or not an innumerable number is generated in the calculation in the other cores.

  For this reason, each core 10 and 20 can grasp | ascertain whether the variable used by the calculation in a self-core is the variable obtained by the calculation in which the non-number generate | occur | produced. Then, the microcomputer 100 initializes the variable d of the own core 20 related to the variable c obtained by the operation in which the non-number occurs when the non-number is generated by monitoring as described above. Therefore, the microcomputer 100 initializes the variable d calculated by using the variable c in addition to the variable c obtained by the arithmetic operation in which the plurality of cores 10 and 20 executing the calculation of the variable are innumerable. can do. That is, it can be said that the microcomputer 100 can collectively initialize the related variables of its own core according to the occurrence of a non-number of other cores.

  The variables c and d calculated by the cores 10 and 20 may be used for various controls. As described above, the microcomputer 100 can not only initialize the variable c in which the innumerable number is generated, but also can initialize the variable d calculated by the other core 20 using the variable c. For this reason, the microcomputer 100 can improve the reliability of control using the variable d, compared with the case where the variable d calculated using the variable c in which the non-number is generated is used without being initialized.

  In this embodiment, an example applied to a dual core microcomputer provided with cores 10 and 20 as processing units is adopted. However, the present invention is not limited to this. The present invention can also be applied to an electronic apparatus including a plurality of microcomputers as processing units.

  In addition to the variable d, the second RAM 22 stores a plurality of variables that are not calculated using the variable c. When the variable d is initialized in step S28, the second core 20 may initialize not only the variable d but also all variables including other variables that are not calculated using the variable c. That is, the second core 20 may initialize all variables stored in the second RAM 22 in step S28. In this case, the second core 20 does not need to select the variable d to be calculated using the variable c from the second RAM 22. Therefore, the microcomputer 100 can initialize the variable d more easily than selecting a variable to be calculated using the variable c from the second RAM 22.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10 ... 1st core, 11 ... 1st flag area | region, 12 ... RAM for 1st cores, 20 ... 2nd core, 21 ... 2nd flag area | region, 22 ... RAM for 2nd cores, 22a ... Variable area | region, 30 ... Sharing RAM,
31 ... 1st shared area, 32 ... 2nd shared area, 33 ... 3rd shared area, 100 ... Microcomputer, 200 ... ECU

Claims (4)

An electronic device including a plurality of processing units,
Each processing unit
A calculation unit (S10, S22) for calculating a variable;
A determination unit (S11, S23) for determining whether or not an error has occurred in the calculation in the calculation unit in the processing unit;
A first initialization unit (S14, S26) that initializes a variable of the processing unit obtained by an operation in which it is determined that an error has occurred when the determination unit determines that an error has occurred; With
While holding the variable value obtained by the calculation of the calculation unit in the other processing unit, the calculation unit calculates the variable related to the variable calculated by the other processing unit using the held variable value,
further,
In order to execute the calculation of the calculation unit in parallel between the plurality of processing units, and when the determination unit determines that an error has occurred, in order to share that the error has occurred among the plurality of processing units, An error storage unit (S13, S25) for storing that an error has occurred;
A monitoring unit (S15, S27) for monitoring whether or not an error has occurred in the calculation in the calculation unit of another processing unit by checking the error storage unit;
If an error has occurred during monitoring by the monitoring unit, a second initialization unit (S16, S28) that initializes a variable of the self-processing unit related to a variable obtained by a calculation in which the error has occurred. ) And the electronic device provided.   The electronic device according to claim 1, wherein the plurality of processing units are cores provided in one microcomputer. A variable storage unit in which variable values are stored;
The calculation unit calculates a variable stored in the variable storage unit, updates the variable to a value obtained by the calculation,
The monitoring unit checks the error storage unit before updating the variable to the value obtained by the calculation of the calculation unit in the self-processing unit,
When an error has occurred during monitoring by the monitoring unit, the second initialization unit may update the variable storage unit before updating the variable to a value obtained by the calculation of the calculation unit in the processing unit. The electronic device according to claim 1, wherein the variable of the self-processing unit stored in is initialized.   The second initialization unit, when an error occurs in the calculation in the calculation unit of another processing unit, the variable of the self-processing unit related to the variable obtained in the calculation in which the error occurs The electronic device according to claim 1, wherein all of the variables in the processing unit are initialized.

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