JP6561798B2 - Current source model generation apparatus, current source model generation program and method thereof - Google Patents

Description

  The present invention relates to a current source model generation device, a current source model generation program, and a method thereof.

  Various proposals have been made in order to improve the accuracy of delay estimation in delay simulation used for designing a semiconductor integrated circuit (see, for example, Patent Documents 1 and 2 and Non-Patent Documents 1 and 2).

  For example, a technique for estimating a delay value of a cell using a current source model including a DC power source that outputs a non-linear current and a capacitance component in which a relationship between input and output voltages is indicated by a lookup table is known. .

JP-T-2004-501438 JP 2009-253218 A

I. Keller et al., "A robust cell-level crosstalk delay change analysis", ICCAD 2004 A.Goel, S. Vrudhula, "Current source based standard cell model for accurate signal integrity and timing analysis", EDAA 2008

  The delay between cells mounted on a semiconductor integrated circuit is due to the wiring delay caused by the parasitic capacitance and parasitic resistance of the wiring connecting the cells, the wiring connecting the internal elements of the cell and the parasitic capacitance of the internal elements, etc. Resulting cell delay. In conventional semiconductor integrated circuits, wiring delay accounts for a large percentage of inter-cell delay, and wiring delay is the main factor affecting the calculation accuracy of inter-cell delay. Cell delay was ignored when estimating.

  However, in recent semiconductor integrated circuits, with the progress of miniaturization technology and the improvement of placement and routing technology, it is desired to improve the accuracy of estimation of cell delay.

  An object of one embodiment is to accurately estimate a cell delay of a cell arranged in a semiconductor integrated circuit.

  In one aspect, a current source model generation method includes an input terminal pair having a first input terminal and a second input terminal, an output terminal pair having a first output terminal and a second output terminal, a mirror capacitor, and an output capacitor. And a direct current source. The mirror capacitor has one terminal connected to the first input terminal, the other terminal connected to the first output terminal, the output capacitor connected to the first output terminal, and the other terminal connected to the second output terminal. Connected to. The DC current source has one terminal connected to the second input terminal and the second output terminal, and the other terminal connected to the first output terminal, and supplies a DC current to the mirror capacitor and the output capacitor. In one aspect, the first input current, the first input voltage, and the first output voltage when an input ramp voltage is applied to the input terminal and a DC voltage is applied to the output terminal are acquired. In one aspect, the second input current, the second input voltage, and the second output voltage when the input ramp voltage is applied to the input terminal and the output ramp voltage is applied to the output terminal are acquired. In one aspect, the capacitance value of the mirror capacitance is calculated based on the difference between the first input current and the second input current and the slope of the second output voltage.

  In one embodiment, the cell delay of cells arranged in a semiconductor integrated circuit can be accurately estimated.

(A) is a figure which shows an example of the delay between cells mounted in a semiconductor integrated circuit, (b) is a figure which shows the other example of the delay between cells mounted in a semiconductor integrated circuit, (c) is It is a figure which shows an example of the cell mounted in a semiconductor integrated circuit, (d) is an internal circuit figure of the cell shown to (c), (e) is for demonstrating the cell delay of the cell shown to (c). FIG. FIG. 2 is a circuit diagram of a current source model of the inverter shown in FIG. It is a block diagram of the current source model generation device concerning an embodiment. It is a flowchart of the current source model generation process by the current source model generation device shown in FIG. 5 is a more detailed flowchart of the process of S103 shown in FIG. (A) is a circuit diagram of the 1st extraction circuit used by the process of S103 shown in FIG. 4, (b) is a circuit diagram of the 2nd extraction circuit used by the process of S103 shown in FIG. (A) is a circuit diagram which shows the 1st state of the 1st extraction circuit shown to Fig.6 (a), (b) is the voltage applied to the input-output terminal of the 1st DC cell shown to Fig.6 (a). FIG. It is a figure which shows the output DC memory table which a 1st simulation part memorize | stores in a memory | storage part. (A) is a circuit diagram which shows the 2nd state of the 1st extraction circuit shown to Fig.6 (a), (b) shows the voltage applied to the input-output terminal of the 1st lamp cell shown to Fig.6 (a). FIG. It is a figure which shows the output lamp memory | storage table which a 2nd simulation part memorize | stores in a memory | storage part. (A) is a circuit diagram which shows the simulation state of the 2nd extraction circuit shown in FIG.6 (b), (b) shows the voltage applied to the input-output terminal of the 2nd lamp cell shown in FIG.6 (b). FIG. It is a figure which shows the input DC memory table which a 3rd simulation part memorize | stores in a memory | storage part. It is a figure which shows the capacitance value of the mirror capacity | capacitance which a mirror capacity | capacitance calculating part calculates. It is a figure which shows the related current source model production | generation method, (a) is a circuit diagram of a 1st extraction circuit, (b) shows the 1st output current extracted from the 1st extraction circuit shown to (a). (C) is a circuit diagram of the second extraction circuit, (d) is a diagram showing a voltage applied to the second extraction circuit shown in (c), and (e) is shown in (c). It is a figure which shows the 2nd output current extracted from the 2nd extraction circuit shown, (f) is a circuit diagram of a 3rd extraction circuit, (g) is applied to the 3rd extraction circuit shown to (f). It is a figure which shows a voltage, (h) is a figure which shows the 3rd output current extracted from the 3rd extraction circuit shown to (f). (A) is an internal circuit diagram of a cell when there is no IR drop in the related current source model generation method, and (b) is an internal circuit diagram of a cell when there is an IR drop in the related current source model generation method. is there. It is a figure which shows the comparison with the capacitance value of the mirror capacity | capacitance extracted with the related current source model production | generation method, and the capacitance value of an actual mirror capacity | capacitance. (A) is an equivalent circuit diagram of an extraction circuit for extracting the capacitance value of the mirror capacitance in the related current source model generation method, and (b) is an extraction of the capacitance value of the mirror capacitance in the current source model generation method according to the embodiment. It is an equivalent circuit diagram of the extraction circuit to perform. The comparison of the capacitance value of the mirror capacitance extracted by the current source model generation method according to the embodiment, the capacitance value of the mirror capacitance extracted by the related current source model generation method, and the capacitance value of the actual mirror capacitance is shown. FIG. Further comparison between the capacitance value of the mirror capacitance extracted by the current source model generation method according to the embodiment, the capacitance value of the mirror capacitance extracted by the related current source model generation method, and the capacitance value of the actual mirror capacitance FIG.

  Hereinafter, a current source model generation device, a current source model generation program, and a method thereof according to the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments.

(Outline of current source model generation method according to the embodiment)
The current source model generation method according to the embodiment uses the input current value when the lamp voltage is applied to the cell output terminal without using the output current value when the lamp voltage is applied to the cell input terminal. Then, the mirror capacitance of the current source model is calculated. By using the input current value when the lamp voltage is applied to the cell output terminal instead of the output current value when the lamp voltage is applied to the cell input terminal, the mirror capacitance extraction error caused by the IR drop is reduced. Can be reduced.

(Technology related to the current source model generation method according to the embodiment)
1A is a diagram illustrating an example of an inter-cell delay mounted on a semiconductor integrated circuit, and FIG. 1B is a diagram illustrating another example of an inter-cell delay mounted on a semiconductor integrated circuit. FIG. 1C is a diagram showing an example of a cell mounted on a semiconductor integrated circuit. FIG. 1D is an internal circuit diagram of the cell shown in FIG. 1C, and FIG. 1E is a diagram for explaining the cell delay of the cell shown in FIG. 1C.

  In the example illustrated in FIG. 1A, the first cell 801 and the second cell 802 are connected by a wiring 803. The inter-cell delay Td from the input terminal of the first cell 801 to the input terminal of the second cell 802 is the sum of the cell delay Tc of the first cell 801 and the wiring delay Tw of the wiring 803. When the length of the wiring 803 is relatively short, the ratio of the cell delay Tc to the inter-cell delay Td is relatively large.

  In the example shown in FIG. 1B, the first cell 801 and the second cell 802 are connected by wirings 803a and 803b and a repeater 804. The repeater 804 is a buffer inserted when the wiring length of the wiring between cells is long in order to reduce the delay of the critical path. The inter-cell delay Td from the input terminal of the first cell 801 to the input terminal of the second cell 802 is the cell delay Tc of the first cell 801, the wiring delay Tw1 of the wiring 803a, the cell delay Tr of the repeater 804, and the wiring 803b. This is the sum of the wiring delay Tw2. When the wiring length between cells is relatively long, one or a plurality of repeaters 804 are inserted between the first cell 801 and the second cell 802, so that the cell delays Tc and Tr occupying the inter-cell delay Td The proportion increases.

  The inverter 810 is an example of the first cell 801 and the second cell 802. The first cell 801 and the second cell 802 are constituent elements of a combinational logic circuit, and may be constituent elements of a combinational logic circuit other than the inverter 810, such as a NAND element, a NOR element, an AND element, an OR element, and an XOR element. Good. The inverter 810 includes an nMOS transistor 811 and a pMOS transistor 812. The gates of the nMOS transistor 811 and the pMOS transistor 812 are connected to the input terminal 813, and the drains of the nMOS transistor 811 and the pMOS transistor 812 are connected to the output terminal 814.

  When the input voltage 821 indicated by a broken line in FIG. 1E is applied to the input terminal 813 of the inverter 810, the ideal output voltage 822 indicated by the alternate long and short dash line of the inverter 810 is obtained when the inverter 810 does not have a cell delay. An output terminal 814 is output. However, the output voltage 823 indicated by the solid line is output from the output terminal 814 of the inverter 810 due to the influence of the threshold voltage of the MOS transistor 811 and the pMOS transistor 812 and the parasitic capacitance. The cell delay Tc of the inverter 810 is a time difference between the time when the input voltage 821 rises to ½ VDD and the time when the output voltage falls to ½ VDD. FIG. 1E shows the cell delay of the inverter 810, but the cell delay of an element having two or more input terminals such as a two-input NAND element and a two-input NOR element is an input voltage applied to one input terminal. Is shown in the same manner as the cell delay of the inverter 810.

  Cell delay estimation techniques for estimating cell delay of the inverter 810 and the like include a linear delay model, a SPICE simulation model, and a current source model. In the linear delay model, the processing speed per gate is in microseconds (μs) (μs / gate), and the cell delay is estimated relatively fast. However, the linear delay model does not reflect the precise operation or the like of the MOS transistor forming the cell, and thus there is a possibility that the estimation error becomes large. In the SPICE simulation model, since the operation of the transistor and the influence of the parasitic capacitance are analyzed in detail, the cell delay can be estimated with high accuracy. However, since the SPICE simulation model uses many parameters, the estimation time for estimating the cell delay may be long. In one example, the estimated speed per gate in the SPICE simulation model is in seconds (s / gate), and the estimated time of the SPICE simulation model may be about 1 million times the estimated time of the linear delay model. When a semiconductor integrated circuit is mounted with several hundred thousand gates, it is not easy to execute an overall delay estimation of the semiconductor integrated circuit using a SPICE simulation model. In the current source model, the estimated time per gate is in microseconds (μs) (ms / gate). The estimated time of the cell delay of the SPICE simulation model is longer than the estimated time of the linear delay model, but is about 1/1000 of the estimated delay of the SPICE simulation model.

(Configuration of current source model)
FIG. 2 is a circuit diagram of a current source model of the inverter 810.

  The current source model 100 includes a mirror capacitor Cm, an output capacitor Co, a DC current source 101, an input terminal pair 110 including a first input terminal 111 and a second input terminal 112, a first output terminal 121, and a second output. An output terminal pair 120 including a terminal 122. The mirror capacitor Cm has one terminal connected to the first input terminal 111 and the other terminal connected to the first output terminal 121. The output capacitor Co has one terminal connected to the first output terminal 121 and the other terminal connected to the second output terminal 122. The DC current source 101 has one terminal connected to the second input terminal 112 and the second output terminal 122, the other terminal connected to the first output terminal 121, and a DC current Idc to the mirror capacitor Cm and the output capacitor Co. Supply. An input voltage Vin is applied between the first input terminal 111 and the second input terminal 112, and an output voltage Vout is output from the first output terminal 121 and the second output terminal 122.

(Configuration and Function of Current Source Model Generation Device According to Embodiment)
FIG. 3 is a block diagram of the current source model generation device according to the embodiment.

  The current source model generation device 1 includes an input unit 11, an output unit 12, a storage unit 13, and a processing unit 14.

  The input unit 11 may be any device that can input data, such as a keyboard, a mouse, a touch panel, and a key button. The operator can input characters, numbers, symbols, and the like using the input unit 11. When operated by the operator, the input unit 11 generates a signal corresponding to the operation. Then, the generated signal is supplied to the processing unit 14 as an instruction from the operator.

  The output unit 12 may be any device as long as it can display video, images, and the like, and is, for example, a liquid crystal display or an organic EL (Electro-Luminescence) display. The output unit 12 displays a video corresponding to the video data supplied from the processing unit 14, an image corresponding to the image data, and the like. The output unit 12 may be an output device that prints video, images, characters, or the like on a display medium such as paper.

  The storage unit 13 includes, for example, at least one of a magnetic tape device, a magnetic disk device, and an optical disk device. The storage unit 13 stores an operating system program, a driver program, an application program, data, and the like used for processing in the processing unit 14. For example, the storage unit 13 stores a current source model generation program for causing the processing unit 14 to execute a process of generating a current source model as an application program. In addition, the storage unit 13 stores a cell delay estimation program for causing the processing unit 14 to execute a process of estimating a cell delay using a current source model as an application program. The current source model generation program and the cell delay estimation program may be installed in the storage unit 13 using a known setup program or the like from a computer-readable portable recording medium such as a CD-ROM or DVD-ROM.

  The storage unit 13 stores a process design kit (PDK) 131, a cell library 132, and a SPICE netlist 133 used in the current source model generation process. The PDK 131 is a standard design data set for circuit design including semiconductor process design rules, SPICE models, SPICE parameters, and the like. The cell library 132 is a list of cells including constituent elements of a combinational logic circuit such as an inverter element, a 2-input NAND element, and a 2-input NOR element. The SPICE net list 133 is a SPICE net list extracted from layout information of a desired semiconductor integrated circuit. Furthermore, the storage unit 13 may temporarily store temporary data related to a predetermined process.

  The processing unit 14 includes one or a plurality of processors and their peripheral circuits. The processing unit 14 controls the overall operation of the current source model generation device 1 and is, for example, a CPU. The processing unit 14 executes processing based on programs (driver program, operating system program, application program, etc.) stored in the storage unit 13. The processing unit 14 can execute a plurality of programs (such as application programs) in parallel.

  The processing unit 14 includes a simulation execution unit 141, a direct current extraction unit 142, a mirror capacity calculation unit 143, an output capacity calculation unit 144, and a state space generation unit 145. The simulation execution unit 141 includes a net list acquisition unit 150, a first simulation unit 151, a second simulation unit 152, and a third simulation unit 153. Each of these units is a functional module realized by a program executed by a processor included in the processing unit 14. Alternatively, these units may be implemented in the current source model generation device 1 as firmware.

(Operation of Current Source Model Generation Device According to Embodiment)
FIG. 4 is a flowchart of current source model generation processing by the current source model generation device 1. The current source model generation process is executed mainly by the processing unit 14 in cooperation with each element of the current source model generation device 1 based on a program stored in the storage unit 13 in advance.

  First, the net list acquisition unit 150 of the simulation execution unit 141 selects a cell for generating a current source model from the cell library 132 (S101), and acquires a net list corresponding to the selected cell from the SPICE net list 133 (S102). ). Next, the simulation execution unit 141 executes SPICE simulation using the PDK 131 for the acquired netlist (S103).

  FIG. 5 is a more detailed flowchart of the process of S103, FIG. 6A is a circuit diagram of the first extraction circuit used in the process of S103, and FIG. 6B is used in the process of S103. It is a circuit diagram of a 2nd extraction circuit.

  The first simulation unit 151 executes a SPICE simulation in the first state of the first extraction circuit 201 (S201). The first extraction circuit 201 includes a first DC cell 211, a first lamp cell 212, a first input lamp voltage source 213, a first output DC voltage source 214, and a first output lamp voltage source 215. Inside each of the first DC cell 211 and the first lamp cell 212, the net list of the cells acquired in S102 is arranged.

  The first input lamp voltage source 213 is connected to the input terminals of the first DC cell 211 and the first lamp cell 212. When the net list of the cells arranged inside each of the first DC cell 211 and the first lamp cell 212 has two or more input terminals, it is connected to any one input terminal. The first input ramp voltage source 213 applies a first input ramp voltage having a slope Kin to the input terminals of the first DC cell 211 and the first ramp cell 212.

  The first output DC voltage source 214 is connected to the output terminal of the first DC cell 211. The first output DC voltage source 214 applies a DC voltage having a plurality of voltages between VSS and VDD to the output terminal of the first DC cell 211 in the first state.

  The first output lamp voltage source 215 is connected to the output terminal of the first lamp cell 212. The first output ramp voltage source 215 applies a ramp voltage having a slope Kout to the output terminal of the first ramp cell 212 in the second state. The slope Kout of the lamp voltage applied by the first output lamp voltage source 215 can be set to a plurality of values.

  FIG. 7A is a circuit diagram illustrating a first state of the first extraction circuit 201, and FIG. 7B is a diagram illustrating a voltage applied to an input / output terminal of the first DC cell 211. In FIG. 7B, the horizontal axis indicates time, the vertical axis indicates voltage, the thick solid line indicates voltage applied from the first input lamp voltage source 213 to the input terminal of the first DC cell 211, and a thick broken line. Indicates a voltage applied from the first output DC voltage source 214 to the output terminal of the first DC cell 211.

  The first simulation unit 151 applies a first input ramp voltage having a predetermined slope Kin from the first input ramp voltage source 213 to the input terminal of the first DC cell 211. The first simulation unit 151 applies a first output DC voltage having a plurality of voltage values from the first output DC voltage source 214 to the output terminal of the first DC cell 211. The first simulation unit 151 applies the first input ramp voltage having a slope Kin to the input terminal of the first DC cell 211 and the voltage value of the first output DC voltage applied to the output terminal of the first DC cell 211. , And sequentially change from VSS to VDD. When VSS is 0V and VDD is 5V, the first simulation unit 151 applies six first output DC voltages of 0V, 1V, 2V, 3V, 4V, and 5V to the output terminal of the first DC cell 211. May be.

  The first simulation unit 151 detects changes with time of the first input voltage Vin, the first output voltage Vout, and the first input current Iin1 for each first output DC voltage applied to the output terminal of the first DC cell 211. And stored in the storage unit 13 in a table format.

  FIG. 8 is a diagram illustrating an output DC storage table stored in the storage unit 13 by the first simulation unit 151.

  The output DC storage table 310 includes m tables of the first output DC storage table 311 to the m-th output DC storage table 31m for every m first output DC current values to be applied. Each of the first output DC storage table 311 to the m-th output DC storage table 31m has a first input voltage Vin, for each elapsed time t after the voltage is applied to the input terminal and the output terminal of the first DC cell 211. The first output voltage Vout and the first input current Iin1 are stored.

  Next, the second simulation unit 152 executes a SPICE simulation in the second state of the first extraction circuit 201 (S202).

  FIG. 9A is a circuit diagram showing a second state of the first extraction circuit 201, and FIG. 9B is a diagram showing a voltage applied to the input / output terminal of the first lamp cell 212. FIG. In FIG. 9B, the horizontal axis indicates time, and the vertical axis indicates voltage. The thick solid line indicates the voltage applied from the first input ramp voltage source 213 to the input terminal of the first lamp cell 212, and the thick dashed line is applied from the first output ramp voltage source 215 to the output terminal of the first lamp cell 212. Voltage. A thick broken line indicates a relative inclination of the voltage applied to the output terminal of the first ramp cell 212 with respect to the voltage applied to the input terminal of the first ramp cell 212.

  The second simulation unit 152 applies the first input ramp voltage having the same slope Kin as the first state from the first input ramp voltage source 213 to the input terminal of the first ramp cell 212. The second simulation unit 152 applies a first output ramp voltage having a plurality of gradients Kout from the first output ramp voltage source 215 to the output terminal of the first ramp cell 212. The second simulation unit 152 applies a first output ramp voltage having a slope Kin to the input terminal of the first ramp cell 212, and sequentially changes the slope Kout of the first output ramp voltage applied to the output terminal of the first ramp cell 212. Let

  The second simulation unit 152 detects temporal changes in the second input voltage Vin, the second output voltage Vout, and the second input current Iin2 for each slope Kout of the first output ramp voltage applied to the output terminal of the first lamp cell 212. And it memorize | stores in the memory | storage part 13 with a table format.

  FIG. 10 is a diagram illustrating an output lamp storage table stored in the storage unit 13 by the second simulation unit 152.

  The output lamp storage table 320 includes p tables of the first output lamp storage table 321 to the p-th output lamp storage table 32p for each inclination Kout of the p first output lamp voltages to be applied. Each of the first output lamp storage table 321 to the p-th output lamp storage table 32p has a second input voltage Vin, for each elapsed time t after the voltage is applied to the input terminal and the output terminal of the first DC cell 211. The second output voltage Vout and the second input current Iin2 are stored.

  Next, the third simulation unit 153 performs a SPICE simulation in the second extraction circuit 102 (S203). The second extraction circuit 202 includes a second lamp cell 221, a second input DC voltage source 222, and a second output lamp voltage source 223. Inside the second ramp cell 221, the net list of the cell acquired in S102 is arranged.

  The second input DC voltage source 222 is connected to the input terminal of the second lamp cell 221. When the netlist of the cell arranged inside the second lamp cell 221 has two or more input terminals, it is connected to any one input terminal. The second input DC voltage source 222 applies a DC voltage having a plurality of voltages between VSS and VDD to the output terminal of the second lamp cell 221.

  The second output lamp voltage source 223 is connected to the output terminal of the second lamp cell 221. The second output ramp voltage source 223 applies a ramp voltage having a slope Kout2 to the output terminal of the second ramp cell 212 in the second state.

  FIG. 11A is a circuit diagram showing a simulation state of the second extraction circuit 202, and FIG. 11B is a diagram showing a voltage applied to the input / output terminal of the second lamp cell 221. In FIG.11 (b), a horizontal axis shows time and a vertical axis | shaft shows a voltage. A thick solid line indicates a voltage applied from the second input DC voltage source 222 to the input terminal of the second lamp cell 221, and a thick broken line indicates a voltage applied from the second output lamp voltage source 223 to the output terminal of the second lamp cell 221. Indicates voltage.

  The third simulation unit 153 applies a second input DC voltage having a plurality of voltage values from the second input DC voltage source 222 to the input terminal of the second lamp cell 221. The third simulation unit 153 applies a second output ramp voltage having a predetermined slope Kout2 from the second output ramp voltage source 223 to the output terminal of the second ramp cell 221. The third simulation unit 153 sequentially changes the voltage value of the second input ramp voltage applied to the input terminal of the second ramp cell 221 from VSS to VDD, and has a predetermined slope Kout2 at the output terminal of the second ramp cell 221. A second output ramp voltage is applied.

  The third simulation unit 153 detects temporal changes in the third input voltage Vin, the third output voltage Vout, and the second input current Iin2 for each second input DC voltage applied to the input terminal of the second lamp cell 221. The data is stored in the storage unit 13 in a table format.

  FIG. 12 is a diagram illustrating an input DC storage table stored in the storage unit 13 by the third simulation unit 153.

  The input DC storage table 330 includes q tables of the first input DC storage table 331 to the qth input DC storage table 33q for every q second input DC voltages to be applied. Each of the first input DC storage table 331 to the qth input DC storage table 33q has a third input voltage Vin, a first input voltage, and a third input voltage Vin for each elapsed time t after the voltage is applied to the input terminal and output terminal of the second lamp cell 221. The third output voltage Vout and the third output current Iin3 are stored.

  Next, the direct current extraction unit 142 extracts the direct current Idc of the direct current source 101 (S104). The DC current extraction unit 142 extracts a current flowing through the output terminal as a DC current Idc when a simulation is performed by applying a DC voltage to the input terminal and the output terminal of the netlist of the cell acquired in S102. The direct current extraction unit 142 sequentially changes the input voltage Vin applied to the input terminal and the output voltage Vout applied to the output terminal, and the direct current Idc (Vin, Vout) is obtained for each of the plurality of input voltages Vin and output voltages Vout. ). The direct current extraction unit 142 stores the extracted direct current Idc (Vin, Vout) in the storage unit 13.

  Next, the mirror capacitance calculation unit 143 calculates the capacitance value of the mirror capacitance Cm of the current source model 100 based on the difference between the first input current Iin1 and the second input current Iin2 and the gradient Kout2 of the second output voltage. (S105). More specifically, from the difference between the first input current Iin1 and the second input current Iin2 in the plurality of input voltages Vin and the plurality of output voltages Vout and the slope Kout2 of the second output voltage, the input voltage Vin and the output voltage are calculated. The capacitance value of the mirror capacitance Cm according to Vout is calculated.

  FIG. 13 is a diagram illustrating a capacitance value of the mirror capacitance Cm calculated by the mirror capacitance calculation unit 143.

The mirror capacitance calculation unit 143 acquires the first input current Iin1 at the plurality of first input voltages Vin and the first output voltage Vout from the output DC storage table 310. Next, the Miller capacitance calculator 143 obtains the second input current Iin2 in the second input voltage Vin and the second output voltage Vout corresponding to the first input voltage Vin and the first output voltage Vout obtained from the first input current Iin1, Obtained from the output lamp storage table 320. Then, the mirror capacitance calculation unit 143 calculates the mirror capacitance Cm (Vin, Vout) for each of the plurality of predetermined input voltages Vin and output voltages Vout.
Cm (Vin, Vout) = (Iin2 (Vin, Vout)-Iin1 (Vin, Vout)) / Kout
Calculate from. Here, the gradient Kout of the output voltage is obtained from the gradient Kin of the second input voltage Vin, the second output voltage Vout, and the input ramp voltage.
Kout = Kin * Vout / Vin
Indicated by The output voltage slope Kout is calculated based on the simulation result by calculating the slope Kout of the output voltage from the slope Kin of the second input ramp voltage and the second input voltage Vin and the second output voltage Vout detected by the SPICE simulation. It can be calculated.

Next, the output capacitance calculation unit 144 calculates the capacitance value of the mirror capacitance Co of the current source model 100 based on the third output current Iin3, the slope Kout2 of the second output ramp voltage, and the mirror capacitance Cm (Vin, Vout). (S105). The output capacity calculation unit 144 acquires the third output current Iin3 in each of the third input voltage Vin and the third output voltage Vout acquired by the mirror capacity calculation unit 143 from the input DC storage table 330. Then, the mirror capacitance calculating unit 143 calculates the output capacitance Co (Vin, Vout) for each of the plurality of predetermined input voltages Vin and output voltages Vout.
Co (Vin, Vout) = (Iin3 (Vin, Vout) -Idc (Vin, Vout)) / Kout2-Cm (Vin, Vout)
Calculate from.

  Next, the state space generation unit 145 generates a state space indicating the state transition of the input voltage Vin and the output voltage Vout of the current source model 100 of the cell (S107). The state space of the cell current source model 100 includes a mirror capacitance Cm (Vin, Vout), an output capacitance Co (Vin, Vout), and a DC current value Idc (Vin, Vout), respectively, corresponding input voltage Vin and output voltage. It is generated in association with Vout.

  Then, the netlist acquisition unit 150 determines whether or not the state space of all the cells included in the cell library 132 has been generated (S108), and has generated the state space of all the cells included in the cell library 132. If it is determined that there is no, the process returns to S101. When it is determined that the state spaces of all the cells included in the cell library 132 have been generated, the process ends.

(Operational effect of the current source model generation device according to the embodiment)
The current source model generation device 1 applies a DC voltage to the output terminal of one cell of a pair of cells to which the same lamp voltage is applied to the input terminal, and applies a lamp voltage to the output terminal of the other cell. The 1 extraction circuit 201 is used to extract the mirror capacitance Cm. The current source model generation device 1 extracts the mirror capacitance Cm from the difference between the input currents of a pair of cells having different output voltages applied to the cell output terminals. On the other hand, in the related current source model generation method disclosed in Non-Patent Document 1 and the like, the mirror capacitance is extracted from the difference between the input currents of a pair of cells having different input voltages applied to the cell input terminals.

  FIG. 14 is a diagram showing a related current source model generation method, FIG. 14 (a) is a circuit diagram of the first extraction circuit, and FIG. 14 (b) is a diagram from the first extraction circuit shown in FIG. 14 (a). It is a figure which shows the 1st output current extracted. 14C is a circuit diagram of the second extraction circuit, FIG. 14D is a diagram showing a voltage applied to the second extraction circuit shown in FIG. 14C, and FIG. It is a figure which shows the 2nd output current extracted from the 2nd extraction circuit shown in FIG.14 (c). FIG. 14F is a circuit diagram of the third extraction circuit, FIG. 14G is a diagram showing a voltage applied to the third extraction circuit shown in FIG. 14F, and FIG. It is a figure which shows the 3rd output current extracted from the 3rd extraction circuit shown in FIG.14 (f).

  In the related current source model generation method, the first extraction circuit 901 applies a DC voltage from the first input DC voltage source 912 to the input terminal of the cell 911 and also uses the first output DC voltage source 913 to the output terminal of the cell 911. DC voltage is applied. The first input DC voltage source 912 applies a first input DC voltage having a plurality of voltage values to the input terminal of the cell 911, and the first output DC voltage source 913 has a plurality of voltage values at the output terminal of the cell 911. Apply 1 output DC voltage. In the first extraction circuit 901, the first output current Iout1 of the cell 911 at a plurality of input DC voltage values and output DC voltage values is detected, and the DC current Idc (Vin, Vout) is related to the input voltage Vin and the output voltage Vout to be applied. ).

  Next, in the second extraction circuit 902, a ramp voltage is applied from the second input ramp voltage source 922 to the input terminal of the cell 921, and a DC voltage is applied from the second output DC voltage source 923 to the output terminal of the cell 921. The second input ramp voltage source 922 applies a second input ramp voltage having a predetermined slope to the input terminal of the cell 921, and the second output DC voltage source 923 has a second voltage having a plurality of voltage values at the output terminal of the cell 921. Apply output DC voltage. In the second extraction circuit 902, the second output current Iout2 of the cell 921 at the input ramp voltage value having a predetermined slope and the plurality of output DC voltage values is detected and stored.

  Next, in the third extraction circuit 903, a DC voltage is applied from the third input DC voltage source 932 to the input terminal of the cell 931, and a lamp voltage is applied from the third output ramp voltage source 933 to the output terminal of the cell 931. The third input DC voltage source 932 applies a third input DC voltage having a plurality of voltage values to the input terminal of the cell 931, and the third output ramp voltage source 933 has a third slope having a predetermined slope at the output terminal of the cell 931. Apply input ramp voltage. The third extraction circuit 903 detects and stores the third output current Iout3 of the cell 921 at a plurality of input DC voltage values and an output ramp voltage value having a predetermined slope.

Then, the mirror capacitance Ccm of the current source model of the cell is
Ccm (Vin, Vout) = (Iout2 (Vin, Vout)-Iout1 (Vin, Vout)) / Kin
The output capacity Cco of the current source model of the cell is
Cco (Vin, Vout) = Iout3 (Vin, Vout) / Kout-Ccm (Vin, Vout)
Is calculated from

  In the related current source model generation method, the mirror capacitance is extracted from the difference between the output currents of a pair of cells having different input voltages applied to the input terminals of the cells, so that an extraction error of the mirror capacitance due to the IR drop is likely to occur. .

  FIG. 15A is an internal circuit diagram of a cell when there is no IR drop in the related current source model generation method, and FIG. 15B is a diagram of the cell when there is an IR drop in the related current source model generation method. It is an internal circuit diagram.

  The cell 950 includes a first transistor 951, a second transistor 952, and a first parasitic capacitance 953 to a fourth parasitic capacitance 956. The first transistor 951 is a pMOS transistor, and the second transistor 952 is an nMOS transistor. The first parasitic capacitance 953 is a gate-source capacitance of the first transistor 951, and the second parasitic capacitance 954 is a gate-drain capacitance of the first transistor 951. The third parasitic capacitance 955 is a gate-source capacitance of the second transistor 952, and the fourth parasitic capacitance 956 is a gate-drain capacitance of the second transistor 952.

  The cell 960 further includes a second parasitic resistor 968 in addition to the first transistor 961, the second transistor 962, the first parasitic capacitor 963 to the fourth parasitic capacitor 966, and the first parasitic resistor 967. The first transistor 961, the second transistor 962, and the first parasitic capacitor 963 to the fourth parasitic capacitor 966 have a configuration corresponding to the first transistor 951, the second transistor 952, and the first parasitic capacitor 953 to the fourth parasitic capacitor 956. Therefore, detailed description is omitted here. The first parasitic resistance 967 is a parasitic resistance between the source of the first transistor 961 and the power supply voltage source, and the second parasitic resistance 968 is a parasitic resistance between the source of the second transistor 962 and the ground. The resistance values of the first parasitic resistor 967 and the second parasitic resistor 968 increase as the wiring width of the wiring such as the power supply line becomes narrow as the semiconductor process becomes finer.

  FIG. 16 is a diagram showing a comparison between the mirror capacitance value extracted by the related current source model generation method and the actual mirror capacitance value. In the example shown in FIG. 16, the output voltage Vout is fixed at 0V. In FIG. 16, the horizontal axis represents the input voltage, the vertical axis represents the capacitance value, the waveform 401 represents the actual mirror capacitance value, and the waveform 402 represents the mirror capacitance extracted by the related current source model generation method. Indicates the capacity value.

  In the related current source model generation method, the ramp voltage is applied to the input terminals connected to the gates of the first transistor 961 and the second transistor 962. When a ramp voltage is applied to the input terminals connected to the gates of the first transistor 961 and the second transistor 962, the current flowing in the first parasitic capacitor 963 and the third parasitic capacitor 965 is changed to the first parasitic resistor 967 and the second parasitic resistor 967. It flows through the parasitic resistance 968. By flowing through the first parasitic resistor 967 and the second parasitic resistor 968, the source voltages of the first transistor 961 and the second transistor 962 fluctuate, the drain current of the first transistor 961 increases, and the second transistor 962 The drain current decreases. As the drain current of the first transistor 961 increases and the drain current of the second transistor 962 decreases, the capacitance value of the mirror capacitance is extracted larger than the actual value. In the example shown in FIG. 16, the average extraction error of the capacitance value of the mirror capacitance in the related current source model generation method is 155%.

  FIG. 17A is an equivalent circuit diagram of an extraction circuit for extracting the capacitance value of the mirror capacitance in the related current source model generation method, and FIG. 17B is a diagram of the mirror capacitance in the current source model generation method according to the embodiment. It is an equivalent circuit diagram of the extraction circuit which extracts a capacitance value.

  In the related current source model generation method, the input terminal is greatly influenced by the first parasitic capacitance 963 that is the gate-source capacitance of the first transistor 961 and the third parasitic capacitance 965 that is the gate-source capacitance of the second transistor 962. The voltage applied to is switched. On the other hand, in the current source model generation method according to the embodiment, the voltage applied to the output terminal that is less affected by the first parasitic capacitance 963 and the third parasitic capacitance 965 is switched. At the output terminal, the source-drain capacitance of the first transistor 961 and the second transistor 962 is parasitic as parasitic capacitance. In the MOS transistor, the capacitance value of the source-drain capacitance is the capacitance of the gate-source capacitance. Less than the value. In the current source model generation method according to the embodiment, the mirror capacitor extraction accuracy of the current source model is improved by switching the voltage applied to the output terminal that is less affected by the capacitance value of the gate-source capacitance of the transistor.

  FIG. 18 shows the capacitance value of the mirror capacitance extracted by the current source model generation method according to the embodiment, the mirror capacitance value extracted by the related current source model generation method, and the actual mirror capacitance value. It is a figure which shows comparison of these. In the example shown in FIG. 18, the output voltage Vout is fixed at 0V. In FIG. 18, the horizontal axis indicates the input voltage, and the vertical axis indicates the capacitance value. A waveform 401 shows the actual capacitance value of the mirror capacitance, a waveform 402 shows the capacitance value of the mirror capacitance extracted by the related current source model generation method, and a waveform 403 is extracted by the current source model generation method according to the embodiment. The capacity value of the mirror capacity.

  In the current source model generation method according to the embodiment, the mirror voltage extraction accuracy of the current source model is improved by applying the ramp voltage to the output terminal that is less affected by the capacitance value of the gate-source capacitance of the transistor. The average error of the capacitance value of the mirror capacitance in the related current source model generation method is 155%, whereas the average extraction error of the capacitance value of the mirror capacitance in the current source model generation method according to the embodiment is −1.2%. It is.

  FIG. 19 shows the capacitance value of the mirror capacitance extracted by the current source model generation method according to the embodiment, the mirror capacitance value extracted by the related current source model generation method, and the actual mirror capacitance value. It is a figure which shows the further comparison of. In the example shown in FIG. 18, the output voltage Vout is fixed at 0V. In FIG. 18, the vertical axis indicates the capacitance value when the input voltage and the output voltage are changed. The star symbol indicates the actual capacitance value of the mirror capacitance, the cross symbol indicates the capacitance value of the mirror capacitance extracted by the related current source model generation method, and the cross symbol is extracted by the current source model generation method according to the embodiment. The capacity value of the mirror capacity.

  In the example shown in FIG. 19, the average extraction error of the capacitance value of the mirror capacitance in the related current source model generation method is 165%, whereas the average of the capacitance value of the mirror capacitance in the current source model generation method according to the embodiment. The extraction error is -2.1%.

DESCRIPTION OF SYMBOLS 1 Current source model production | generation apparatus 141 Simulation execution part 142 Mirror capacity calculation part 143 Output capacity calculation part 144 DC current calculation part 145 State space generation part 150 Netlist acquisition part 151 1st simulation part 152 2nd simulation part 153 3rd simulation part

Claims (5)

An input terminal pair having a first input terminal and a second input terminal;
An output terminal pair having a first output terminal and a second output terminal;
A mirror capacitor having one terminal connected to the first input terminal and the other terminal connected to the first output terminal;
An output capacitor having one terminal connected to the first output terminal and the other terminal connected to the second output terminal;
A DC current source having one terminal connected to the second input terminal and the second output terminal, the other terminal connected to the first output terminal, and supplying a DC current to the mirror capacitor and the output capacitor; A method of generating a current source model having
Obtaining a first input current, a first input voltage and a first output voltage when an input lamp voltage is applied to the input terminal and a DC voltage is applied to the output terminal;
Obtaining a second input current, a second input voltage and a second output voltage when the input ramp voltage is applied to the input terminal and the output ramp voltage is applied to the output terminal;
Calculating a capacitance value of the mirror capacitance based on a difference between the first input current and the second input current and a slope of the second output voltage;
A method of generating a current source model.   The computing of the capacitance value of the mirror capacitance includes computing the slope of the second output voltage from the slope of the input lamp voltage, the second input voltage, and the second output voltage. A method for generating the described current source model.   The calculation of the capacitance value of the mirror capacitance includes calculating the capacitance value of the mirror capacitance by dividing the difference between the first input current and the second input current by the slope of the second output voltage. The method of generating a current source model according to claim 2, further comprising: An input terminal pair having a first input terminal and a second input terminal;
An output terminal pair having a first output terminal and a second output terminal;
A mirror capacitor having one terminal connected to the first input terminal and the other terminal connected to the first output terminal;
An output capacitor having one terminal connected to the first output terminal and the other terminal connected to the second output terminal;
A DC current source having one terminal connected to the second input terminal and the second output terminal, the other terminal connected to the first output terminal, and supplying a DC current to the mirror capacitor and the output capacitor; A current source model generating device for generating a current source model having:
A first simulation unit for obtaining a first input current, a first input voltage, and a first output voltage when an input lamp voltage is applied to the input terminal and a DC voltage is applied to the output terminal;
A second simulation unit that obtains a second input current, a second input voltage, and a second output voltage when the input ramp voltage is applied to the input terminal and the output ramp voltage is applied to the output terminal;
A mirror capacitance calculation unit that calculates a capacitance value of the mirror capacitance based on a difference between the first input current and the second input current and a slope of the second output voltage;
A current source model generation device. An input terminal pair having a first input terminal and a second input terminal;
An output terminal pair having a first output terminal and a second output terminal;
A mirror capacitor having one terminal connected to the first input terminal and the other terminal connected to the first output terminal;
An output capacitor having one terminal connected to the first output terminal and the other terminal connected to the second output terminal;
A DC current source having one terminal connected to the second input terminal and the second output terminal, the other terminal connected to the first output terminal, and supplying a DC current to the mirror capacitor and the output capacitor; A current source model generation program comprising:
Obtaining a first input current, a first input voltage and a first output voltage when an input lamp voltage is applied to the input terminal and a DC voltage is applied to the output terminal;
Obtaining a second input current, a second input voltage and a second output voltage when the input ramp voltage is applied to the input terminal and the output ramp voltage is applied to the output terminal;
Calculating a capacitance value of the mirror capacitance based on a difference between the first input current and the second input current and a slope of the second output voltage;
A program for generating a current source model that causes a computer to execute processing.

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