JP6563716B2 - Electric vehicle control device - Google Patents

Description

  Embodiments according to the present invention relate to an electric vehicle control apparatus.

  Various safety devices and driving support devices have been developed in order for electric vehicles used in railways to travel safely and stop. For example, an automatic train stop device (ATS (Automatic Train Stop)) and an automatic train control device (ATC (Automatic Train Control)) are known as security devices. As driving assistance devices, automatic driving devices (ATO (Automatic Train Operation)) and fixed position stopping devices (TASC (Train Automatic Stop-position Controller)) are known.

  The electric vehicle control devices in these safety devices and driving support devices collectively convert analog signals received from the ground into digital signals, and control the electric vehicles based on the digital signals. The receiving unit of such an electric vehicle control device may be configured in a parallel dual system so as to ensure its own soundness and to detect a failure when a failure occurs.

  However, since the analog signal processing unit is composed of analog elements in the receiving unit, there are variations in characteristics. Therefore, if the analog signal processing unit is a parallel dual system, variations occur between the signals processed by the two analog signal processing units. Since the characteristic variation of the analog element is not a failure, it is necessary to set the determination standard for determining the soundness of the signal processing system so as to allow the characteristic variation of the analog signal processing unit. This makes it difficult to accurately determine the soundness of the signal processing system, and it becomes difficult to accurately detect a failure of the on-vehicle receiving unit.

  Further, even if the signal processing system fails, a standby dual system may be employed so that the electric vehicle does not become unmovable. However, if both the standby duplex system and the parallel duplex system are applied to the on-vehicle receiver, a total of four signal processing systems are required. In this case, the size of the on-vehicle receiving unit is increased, and the installation area is increased.

Japanese Patent No. 5204205

  An electric vehicle control device capable of accurately detecting an abnormality in a signal processing system and having a small size is provided.

  The electric vehicle control apparatus according to the present embodiment includes an analog signal processing unit that processes an analog reception signal received via an antenna. The analog / digital conversion unit converts the analog signal from the analog signal processing unit into a digital signal. The digital signal processing unit processes a digital signal. The control unit controls the electric vehicle based on the digital signal from the digital signal processing unit. The test signal generation unit provides the analog signal processing unit with an analog test signal different from the analog reception signal in frequency or signal content.

The block diagram which shows an example of a structure of the electric vehicle control apparatus 1 (henceforth the control apparatus 1) by this embodiment. The conceptual diagram which shows an example of the comparison collation operation | movement in control part 40a, 40b. The graph which shows an example of the relationship between the frequency band Scnt of an analog received signal, and the frequency band Test of an analog test signal. The graph which shows the pattern of an analog test signal. The graph which shows the other example of the pattern of an analog test signal. The graph which shows the relationship between the frequency band Scnt of the analog reception signal by the modification, and the frequency band Test of an analog test signal. The graph which shows the pattern of the analog test signal by a modification. The block diagram which shows an example of a structure of the electric vehicle control apparatus 2 by 2nd Embodiment. The conceptual diagram which shows an example of operation | movement of the electric vehicle control apparatus by 3rd Embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

  FIG. 1 is a block diagram illustrating an example of a configuration of an electric vehicle control device 1 (hereinafter also referred to as a control device 1) according to the present embodiment. The control device 1 is mounted on an electric vehicle such as a railroad, and receives a signal from a ground element with an antenna (for example, a vehicle upper element, a power receiver) 95 and sends the signal to the control device 1 via a transformer 90. input. The control device 1 processes a signal from the ground unit and outputs a control signal CNT. The control signal CNT is used for controlling the electric vehicle.

  The control device 1 includes an analog signal processing unit 10, an ADC (Analog to Digital Converter) 20, digital signal processing units 30a and 30b, control units 40a and 40b, a test signal generation unit 50, and an addition unit 80. I have. Although not shown, the control device 1 may be configured as a standby dual system. The standby duplex system has a configuration in which a plurality of signal processing systems are provided, and when one signal processing system fails, the signal processing is switched to the other signal processing system. Therefore, when the control device 1 is configured as a standby dual system, two signal processing systems from the analog signal processing unit 10 to the control units 40a and 40b are connected in parallel.

  The analog signal processing unit 10 performs analog processing (for example, amplification processing, filtering processing) so that the analog reception signal received by the antenna 95 and the analog test signal from the test signal generation unit 50 can be digitally converted by the ADC 20.

  The ADC 20 as an analog / digital conversion unit converts the analog reception signal and the analog test signal processed by the analog signal processing unit 10 into a digital signal.

  The digital signal processing units 30a and 30b both receive a digital signal from the ADC 20 and digitally process the digital signal. For example, the digital signal processing units 30a and 30b convert the digital signal into the frequency domain by performing a Fourier transform. Further, the digital signal processing units 30a and 30b take out a signal level (signal strength) at a certain frequency from the digital signal and output the frequency and signal level to the control units 40a and 40b. For example, the digital signal processing units 30a and 30b transmit the resonance frequency and the signal level at the resonance frequency when the ground unit and the antenna 95 are electromagnetically coupled to the control units 40a and 40b as digital control signals. Alternatively, the digital signal processing units 30a and 30b transmit a predetermined frequency and a signal level at the frequency to the control units 40a and 40b as digital test signals. The digital control signal is used to generate a control signal CNT for controlling the electric vehicle. The digital test signal is used to confirm the soundness of the analog signal processing unit 10 and the ADC 20. Soundness means that the device is not malfunctioning and is operating normally. The digital control signal and the digital test signal are collectively referred to as a digital signal.

  The control units 40a and 40b generate the control signal CNT based on the frequency and signal level received from the digital signal processing units 30a and 30b, or check the soundness of the control device 1. The storage units 41a and 41b store in advance a reference pattern of normal digital test signals. The reference pattern of the normal digital test signal is used when confirming the soundness of the analog signal processing unit 10 and the ADC 20 and has a predetermined frequency and a predetermined signal level.

  Here, in this embodiment, a plurality of digital signal processing units 30a and 30b and control units 40a and 40b that execute digital signal processing are provided, and constitute a parallel duplex system. The parallel duplex system connects two identical signal processing systems in parallel and compares (matches) signals processed by both signal processing systems. If both signals are equal as a result of the comparison, the two signal processing systems can be confirmed to be healthy.

  If the digital signal processing unit 30a and the control unit 40a are a first system and the digital signal processing unit 30b and the control unit 40b are a second system, the first system and the second system have the same configuration. That is, the digital signal processing units 30a and 30b have the same configuration, and the control units 40a and 40b also have the same configuration. The first system and the second system receive the same digital signal. Therefore, when both the first system and the second system are normal, the first system and the second system should process the digital signal in the same manner and output the same control signal CNT. Therefore, the control unit 40a or 40b compares (matches) the frequency and signal level of the digital signal in the control unit 40a with the frequency and signal level of the digital signal in the control unit 40b. As a result, it can be seen that both the first system and the second system are normal when the frequencies and signal levels of the digital signals in the control units 40a and 40b are substantially the same. When the frequencies and signal levels of the digital signals in the control units 40a and 40b are greatly different, it can be seen that the first system or the second system has an abnormality. Thereby, control part 40a, 40b can confirm the soundness of the structure after digital signal processing part 30a, 30b. Hereinafter, the digital signal processing units 30a and 30b and the control units 40a and 40b that execute digital signal processing are collectively referred to as a digital signal processing system.

  On the other hand, the analog signal processing unit 10 and the ADC 20 that execute analog signal processing are not a parallel dual system, but are configured by one system. This is because the digital signals input to the digital signal processing units 30a and 30b are the same.

  If the analog signal processing unit 10 and the ADC 20 are also configured in a parallel duplex system, as described above, variation occurs between two analog reception signals due to variation in characteristics of analog elements. When the analog reception signal varies, the timing of changing the digital control signal output from the ADC 20 varies. In this case, the digital signals input to the digital signal processing units 30a and 30b cannot be made the same, and it is difficult to accurately check the soundness of the digital signal processing system.

  On the other hand, in this embodiment, the analog signal processing unit 10 and the ADC 20 are configured in one system, so that the digital signals input to the digital signal processing units 30a and 30b are the same signal (common signal). be able to. Thereby, control part 40a, 40b can confirm the soundness of the said digital signal processing system correctly. Hereinafter, the analog signal processing unit 10 and the ADC 20 that execute analog signal processing are collectively referred to as an analog signal processing system.

  The test signal generator 50 receives an instruction from the controller 40 a or 40 b and outputs an analog test signal to the adder 80. The analog test signal is a signal used for detecting a failure of the analog signal processing system, and is processed by the analog signal processing system and the digital signal processing system together with the analog reception signal.

  The test signal generator 50 includes a digital test signal generator 51, a DAC (Digital to Analog Converter) 52, and an analog test signal output unit 53. The digital test signal generator 51 receives a command from the controller 40a or 40b and generates a digital test signal. The digital test signal is a signal indicating a predetermined level (signal strength) as a digital value at a predetermined frequency. The DAC 52 converts the digital test signal into analog and outputs the analog test signal. The analog test signal output unit 53 receives the analog test signal from the DAC 52, amplifies the analog test signal, and outputs it to the adder 80. The analog test signal becomes a signal having a predetermined level (signal strength) at a predetermined frequency based on the digital test signal. The frequencies and signal levels of the digital test signal and the analog test signal are preset and stored in the control units 40a and 40b.

  The adder 80 is provided between the transformer 90 and the input unit of the analog signal processing unit 10, and between the output of the test signal generation unit 50 and the input unit of the analog signal processing unit 10. The adder 80 adds the analog test signal from the test signal generation unit 50 to the analog reception signal from the antenna 95 and outputs it to the analog signal processing unit 10. Hereinafter, the analog reception signal and the analog test signal are collectively referred to as an analog signal. The analog signal is processed by an analog signal processing system and converted into a digital signal. At this time, the analog test signal is simultaneously processed without being distinguished from the analog reception signal, and is converted into a digital signal by the ADC 20. The digital signal is output to the digital signal processing units 30a and 30b. The digital signal processing units 30a and 30b convert the digital signal into a frequency domain by Fourier transform, and extract a digital control signal and a digital test signal from the digital signal.

  The control units 40a and 40b output a control signal CNT based on the digital control signal, and confirm the soundness of the analog signal processing system based on the digital test signal.

  Here, confirmation of the soundness of the analog signal processing system will be described.

  Characteristics such as the gain of the analog signal processing unit 10 and the ADC 20 are known in advance. Therefore, when the analog signal processing system and the digital processing system are operating normally, the digital test signal processed by the analog signal processing system and the digital processing system should have a predetermined level (signal strength) at a predetermined frequency. It is. Hereinafter, a digital test signal during normal operation is referred to as a normal digital test signal. The storage units 41a and 41b store a reference pattern of normal digital test signals in advance, and compare them with the digital test signals from the digital signal processing units 30a and 30b, respectively. Note that the reference pattern of the normal digital test signal may be set using a digital test signal obtained by actually inputting the analog test signal to the analog signal processing unit 10, ADC 20, or the like during normal operation. Alternatively, the reference pattern of the normal digital test signal may be set in common to the plurality of control devices 1 using a statistically obtained average normal digital test signal.

  When the level difference (signal intensity difference or gain difference) between the digital test signal from the digital signal processing units 30a and 30b and the reference pattern of the normal digital test signal is less than a predetermined value, the control units 40a and 40b It is determined that the signal processing unit 10 and the ADC 20 are operating normally.

  On the other hand, when the difference (signal strength difference or gain difference) between the digital test signal from the digital signal processing units 30a and 30b and the reference pattern of the normal digital test signal is a predetermined value or more, the control units 40a and 40b It is determined that the analog signal processing unit 10 or the ADC 20 is not operating normally and an abnormality has occurred in any of the configurations. As described above, the control device 1 according to the present embodiment can check the soundness of the analog signal processing system using the test signal without making the analog signal processing system a parallel dual system.

  In addition, since the soundness of the digital signal processing system can be confirmed by the parallel dual system, the digital test signal is used for confirming the soundness of the analog signal processing system. That is, as long as the soundness of the digital signal processing system is ensured by the parallel duplex system, the digital test signal may be used to check the soundness of the analog signal processing system.

  Next, a comparison / collation operation for detecting an abnormality or failure will be described.

  FIG. 2A to FIG. 2D are conceptual diagrams illustrating an example of the comparison and collation operation in the control units 40a and 40b.

  FIG. 2A shows a reference pattern of normal digital test signals stored in the register. The reference pattern of the normal digital test signal is stored in advance in the storage units 41a and 41b. The control units 40a and 40b generate a predetermined analog test signal from the test signal generation unit 50 based on the reference pattern of the normal digital test signal.

  ADDRESS indicates the address of the write register, and DATA indicates the level of the analog test signal. DATA indicates the level of the analog test signal. For example, when DATA is 1, the level of the analog test signal is −40 dBv. When DATA is 2, the level of the analog test signal is −35 dBv. When DATA is 3, the level of the analog test signal is −30 dBv. Thus, every time the DATA value increases by 1, the level of the analog test signal increases by 5 dBv. That is, each time the DATA value changes, the level of the analog test signal changes.

  The DATA of each ADDRESS is read in the order of ADDESS. The read time interval is set to a predetermined time interval (for example, 50 ms). Therefore, for example, when DATA shown in each ADDRESS is read and executed at an interval of 50 ms, the level of the analog test signal is 3 (for example, −30 dBv), 0 (for example, −45 dBv), 0 for every 50 ms. (For example, −45 dBv), 3 (for example, −30 dBv), and 0 (for example, −45 dBv). As described above, the control units 40a and 40b can generate the analog test signal from the test signal generation unit 50 based on the reference pattern of the normal digital test signal.

  Of course, the correspondence between ADDRESS and DATA, ADDRESS value setting, DATA value setting, and analog test signal level setting are not limited and arbitrary.

  2B to 2D show the result patterns of the digital test signal obtained by inputting the analog test signal generated according to the reference pattern shown in FIG. It takes a certain amount of time (hereinafter also referred to as delay time) from the generation of the analog test signal to the storage of the digital test signal. In consideration of such a delay time, the control units 40a and 40b respectively compare the ADDRESS 1 to 5 DATA of the reference pattern of FIG. 2A and the ADDRESS 2 to 6 of the result pattern of FIG. 2B. To do.

  For example, assuming that ± 1 of DATA is within the allowable range within ADDRESS + 1 of the reference pattern, the result pattern in FIG. 2B is within the allowable range with respect to the reference pattern in FIG. , 40b determine that the analog signal processing system is normal.

  On the other hand, since the result pattern in FIG. 2C is outside the allowable range with respect to the reference pattern in FIG. 2A, the control units 40a and 40b determine that the analog signal processing system is abnormal.

  The result pattern of FIG. 2D is out of the allowable range with respect to the reference pattern of FIG. Also in this case, the control units 40a and 40b determine that the analog signal processing system is abnormal.

  When it is determined that the analog signal processing system is abnormal, the control units 40a and 40b display a warning or issue a warning on the monitor for the crew of the electric vehicle. Or control part 40a, 40b may control the brake of an electric vehicle, or may transmit that to the exterior (ground child etc.) of an electric vehicle.

  Next, frequency bands of the analog reception signal and the analog test signal will be described.

  FIG. 3 is a graph showing an example of the relationship between the frequency band Scnt of the analog reception signal and the frequency band Test of the analog test signal. In this graph, the vertical axis indicates the signal level (signal strength or gain). The horizontal axis indicates the frequency. Although the digital control signal and the digital test signal are different in form from the analog reception signal and the analog test signal, they have the same characteristics (frequency and signal level) as the analog reception signal and the analog test signal, respectively. Therefore, illustration of the frequency bands of the digital reception signal and the digital test signal is omitted.

  The frequency band Scnt that the analog reception signal can take is defined by a standard or the like. On the other hand, the frequency band Stest of the analog test signal is set to the high band side or the low band side of the frequency band Scnt of the analog reception signal, and the peak frequency Fp of the analog test signal is the frequency band Scnt of the analog reception signal. Near and outside. For example, in FIG. 3, the peak frequency Fp of the analog test signal is in the vicinity of the maximum value Fmax of the frequency band Scnt of the analog reception signal and is larger than the maximum value Fmax (Fp> Fmax). Since the peak frequency Fp is larger than the maximum value Fmax, the control units 40a and 40b can distinguish between the digital control signal and the digital test signal by the difference in frequency after the digital signal processing. The peak frequency Fp exceeds the maximum value Fmax, but is in the vicinity of the maximum value Fmax. Thereby, control part 40a, 40b can test an analog signal processing system using the analog test signal which has a frequency close | similar to an analog received signal, and can confirm the soundness correctly. Although not shown, when the peak frequency Fp of the analog test signal is set to the lower side of the frequency band Scnt of the analog reception signal, the peak frequency Fp of the analog test signal is equal to the frequency band Scnt of the analog reception signal. And is smaller than the minimum value Fmin (Fp <Fmin). When the peak frequency Fp is smaller than the minimum value Fmin, the control units 40a and 40b can distinguish between the digital control signal and the digital test signal according to the frequency difference after the digital signal processing. Moreover, although the peak frequency Fp is below the minimum value Fmin, it is in the vicinity of the minimum value Fmin. Thereby, control part 40a, 40b can test an analog signal processing system using the analog test signal which has a frequency close | similar to an analog received signal, and can confirm the soundness correctly.

  Further, the strength of the analog test signal in the frequency band Scnt of the analog reception signal is set to be equal to or less than the noise level (thermal noise level) NL of the analog reception signal. For example, in FIG. 3, the intensity of the analog test signal is equal to or lower than the noise level NL of the analog reception signal at a frequency equal to or lower than the maximum value Fmax. As a result, the influence of the analog test signal on the analog reception signal can be minimized.

  Thus, in this embodiment, the peak frequency Fp of the analog test signal is in the vicinity and outside of the frequency band Scnt of the analog reception signal. Further, the strength of the analog test signal in the frequency band Scnt of the analog reception signal is equal to or lower than the noise level NL of the analog reception signal. Thereby, control part 40a, 40b can confirm the soundness of an analog signal processing system correctly using the frequency close | similar to an analog received signal, without affecting an analog received signal.

  Next, an analog test signal pattern will be described.

  FIG. 4 is a graph showing a pattern of the analog test signal. The vertical axis of this graph indicates the signal level (signal strength or gain) of the analog test signal. The horizontal axis indicates time. The analog test signal in this graph is obtained by extracting the analog test signal from the signal input to the ADC 20 through the analog signal processing unit 10. Therefore, the analog test signal added in the adder 80 may contain noise N. The analog test signal pattern is generated by the test signal generator 50 in response to an instruction from the controller 40b or 40a.

  As shown in FIG. 4, the analog test signal is periodically output in a pattern of a predetermined signal level. Before t1, t2 to t3 and t4 to t5 are periods in which the signal level of the analog test signal is zero (that is, the analog test signal is not output). Therefore, when the analog signal processing unit 10 is normal and there is no noise N, the signal levels before t1, t2 to t3, and t4 to t5 are below the threshold value Sth. The threshold value Sth indicates the lowest signal level detected by the control units 40a and 40b as a signal. Further, the signal level that the analog reception signal can take is defined by a standard or the like. Therefore, the threshold value Sth may be said to be the lower limit of the standard of the signal level that the analog reception signal can take.

  First, at time t1 to t2, the analog test signal has a signal level (first signal strength) close to the lower limit, although it is larger than the lower limit (threshold value Sth) of the signal level standard. Next, at t2 to t3, the signal level of the analog test signal becomes zero. Next, at t3 to t4, the analog test signal has a signal level (second signal strength) close to the upper limit although it is smaller than the upper limit of the standard of the signal level. Next, from t4 to t5, the signal level of the analog test signal becomes zero. As described above, the analog test signal periodically repeats the signal having the first signal strength near the lower limit and the signal having the second signal strength near the upper limit within the range of the signal level standard. Thereby, the control part 40a or 40b can confirm the soundness of an analog signal processing system in the whole range of the standard of a received signal level. That is, the soundness of the dynamic range over a wide range of the analog signal processing system can be confirmed.

  Note that noise N is generated from t2 to t3. Since the noise N is different from the failure of the analog signal processing system, the control units 40a and 40b need to make a determination by removing the noise N. For example, noise usually occurs only for a short time in a transient manner, and failure of an analog signal processing system continuously generates an abnormal signal. Therefore, the control units 40a and 40b may determine the noise based on the noise generation period (period in which the noise level exceeds the threshold value Sth). For example, a noise allowable period (for example, about 10 ms) is set in advance, and the control units 40a and 40b determine that the abnormal signal is noise when the abnormal signal generation period is equal to or shorter than the noise allowable period. The control units 40a and 40b do not use the abnormal signal determined to be noise to determine the soundness of the analog signal processing system. Thereby, even if noise is included in the analog test signal, the control units 40a and 40b can accurately determine the soundness of the analog signal processing system.

  FIG. 5 is a graph showing another example of an analog test signal pattern. The analog test signal shown in FIG. 5 has any (intermediate) signal strength (hereinafter also referred to as standard signal strength) between the lower limit and the upper limit of the standard of the analog reception signal. The analog test signal periodically repeats the standard signal strength. For example, at times t11-t12, the analog test signal has a standard signal strength. Next, from t12 to t13, the signal level of the analog test signal becomes zero. Thereafter, the analog test signal repeats the signal pattern from t11 to t13. In this way, the analog test signal may periodically repeat the standard signal strength that is between the upper limit and the lower limit of the standard range of the received signal level. Even with such an analog test signal pattern, the soundness of the analog signal processing system can be confirmed.

  Note that noise N1 occurs before t11, and noise N2 occurs between t11 and t12. The determination of the noises N1 and N2 may be the same as the determination of the noise N described with reference to FIG. Therefore, when the noise N1 and N2 generation period (period in which the noise signal intensity exceeds the threshold Sth) is equal to or less than the noise allowable period, the control units 40a and 40b treat the noise N1 and N2 as soundness of the analog signal processing system. Not used for judgment. Thereby, even if the noises N1 and N2 are included in the analog test signal, the control units 40a and 40b can accurately determine the soundness of the analog signal processing system.

(Modification)
FIG. 6 is a graph showing the relationship between the frequency band Scnt of the analog reception signal and the frequency band Test of the analog test signal according to the modification. In this graph, the vertical axis indicates the signal level (signal strength or gain). The horizontal axis indicates the frequency. Although the digital control signal and the digital test signal are different in form from the analog reception signal and the analog test signal, they exhibit the same characteristics (frequency and signal level) as the analog reception signal and the analog test signal, respectively.

  In FIG. 6, the analog test signal is transmitted using two frequency bands. Similarly to the analog test signal shown in FIG. 3, the frequency band Test_H of the analog test signal is set on the high frequency side of the frequency band Scnt of the analog reception signal, and the peak frequency (first frequency) Fp_H of the analog test signal is , Near and outside the frequency band Scnt of the analog received signal. For example, the peak frequency Fp_H of the analog test signal is in the vicinity of the maximum value Fmax of the frequency band Scnt of the analog reception signal and is larger than the maximum value Fmax (Fp_H> Fmax). Since the peak frequency Fp is larger than the maximum value Fmax, the control units 40a and 40b can distinguish between the digital control signal and the digital test signal by the difference in frequency after the digital signal processing. The peak frequency Fp_H exceeds the maximum value Fmax, but is in the vicinity of the maximum value Fmax. Thereby, control part 40a, 40b can test an analog signal processing system using the frequency close | similar to an analog received signal, and can confirm the soundness correctly.

  On the other hand, the frequency band Stest_L of the analog test signal is set on the lower side of the frequency band Scnt of the analog reception signal, and the peak frequency Fp_L of the analog test signal is near and outside the frequency band Scnt of the analog reception signal. . For example, the peak frequency (second frequency) Fp_L of the analog test signal is in the vicinity of the minimum value Fmin of the frequency band Scnt of the analog reception signal and is smaller than the minimum value Fmin (Fp_L <Fmin). When the peak frequency Fp_L is smaller than the minimum value Fmin, the control units 40a and 40b can distinguish between the digital control signal and the digital test signal by the difference in frequency after the digital signal processing. The peak frequency Fp_L is below the minimum value Fmin, but is in the vicinity of the minimum value Fmin. Thereby, control part 40a, 40b can test an analog signal processing system using the frequency close | similar to an analog received signal, and can confirm the soundness correctly.

  Further, the strength of the analog test signal in the frequency band Scnt of the analog reception signal is set to be equal to or less than the noise level (thermal noise level) NL of the analog reception signal. For example, in FIG. 6, the strength of the analog test signal in the frequency band from the minimum value Fmin to the maximum value Fmax is equal to or lower than the noise level NL of the analog reception signal. As a result, the influence of the analog test signal on the analog reception signal can be minimized.

  Thus, the frequency of the analog test signal is set to two frequency bands Test_L and Test_H on both sides of the frequency band Scnt of the analog reception signal. Thereby, not only the soundness of the analog signal processing system on the high band side of the analog reception signal but also the soundness of the analog signal processing system on the low band side of the analog reception signal can be confirmed. When the soundness of the analog signal processing system is confirmed in the frequency band Test_L and the frequency band Test_H, the control units 40a and 40b can perform the analog operation in the entire frequency band Scnt between the frequency band Test_L and the frequency band Stest_H. It can be assumed that the signal processing system is healthy.

  FIG. 7 is a graph showing a pattern of an analog test signal according to a modification. In this modification, the analog test signal periodically repeats a certain signal strength (for example, standard signal strength) in each of the frequency band (first frequency) Test_H and the frequency band (second frequency) Test_L. However, the analog test signal rises alternately at different timings in the frequency band Test_L and the frequency band Test_H. For example, the analog test signal in the frequency band Test_L has the standard signal strength at times t23 to t24 and t27 to t28, and the period of the standard signal strength is t23 to t27. On the other hand, the analog test signal in the frequency band Test_H has the standard signal strength at times t21 to t22 and t25 to t26, and the period of the standard signal strength is t21 to t25. That is, the generation period of the analog test signal in the frequency band Test_L and the generation period of the analog test signal in the frequency band Test_H are shifted from each other by a half period. Thereby, it can suppress that the amplifier of ADC20 is saturated.

  In addition, the control units 40a and 40b can confirm the soundness of the analog signal processing system in both the frequency band Test_H and the frequency band Test_L. Since the analog test signal in the frequency band Test_L and the analog test signal in the frequency band Test_H are shifted from each other by a half cycle, the control units 40a and 40b may frequently detect failures in the analog signal processing system in a relatively short cycle. it can. That is, the duty ratio for failure detection can be increased. Furthermore, in this modification, the failure detection cycle of the analog signal processing system by the control units 40a and 40b can be made shorter than the failure detection cycle defined in the specifications of the safety device or the driving support device. As a result, the control units 40a and 40b detect a failure of the analog signal processing system within the failure detection cycle defined in the specification, and display a warning on the monitor (not shown) of the electric vehicle accordingly. Alternatively, the brake can be controlled.

(Second Embodiment)
FIG. 8 is a block diagram showing an example of the configuration of the electric vehicle control device 2 according to the second embodiment. The second embodiment is different from the first embodiment in that the digital signal processing unit 30 a includes a bit monitor 32. Other configurations of the second embodiment may be the same as the corresponding configurations of the first embodiment. The digital signal processing unit 30a is configured by, for example, a one-chip FPGA (Field Programmable Gate Array), and includes an input unit 31, a filter processing unit 33, and an output unit 34. The control unit 40a is communicably connected to the output unit 34 via the VME bus. The control unit 40a may be configured with a one-chip CPU, for example. In FIG. 8, for convenience, the digital signal processing unit 30a and the control unit 40a are illustrated, and the digital signal processing unit 30b and the control unit 40b are not illustrated. Note that the digital signal processing unit 30b may be configured by a one-chip FPGA, similarly to the digital signal processing unit 30a. The control unit 40b may be composed of a one-chip CPU, like the control unit 40a.

  The bit monitor 32 is provided in the input unit 31 and monitors the bits of the digital test signal from the ADC 20. The test signal generator 50 periodically and repeatedly outputs an analog test signal while the electric vehicle is running and stopped. Accordingly, the bit monitor 32 monitors the bit change of the digital control signal at a period longer than or equal to the input period of the analog test signal.

  If the analog signal processing system is operating normally, the bits of the digital control signal should change with periodic changes in the analog test signal. However, if the bits of the digital control signal do not change over a predetermined period (the period of the analog test signal) and are fixed, there is a high possibility that the analog signal processing system has failed. In this case, the digital signal processing units 30a and 30b output error signals to the control units 40a and 40b. The control units 40a and 40b may determine that the analog signal processing system is abnormal when receiving an error signal.

  Further, the bit monitor 32 may monitor the bit of the digital control signal instead of the digital test signal or together with the digital test signal while the electric vehicle is running. This is because the bit of the digital control signal can be fixed while the electric vehicle is stopped, but fluctuates frequently while the electric vehicle is running. Therefore, the bit monitor 32 may determine the abnormality of the analog signal processing system by monitoring the bit of the digital control signal while the electric vehicle is traveling.

  As described above, the bit monitor 32 monitors the bit of the digital test signal or the digital control signal, and the control units 40a and 40b detect the abnormality of the analog signal processing system based on the fixed time of the bit of the digital test signal or the digital control signal. May be judged. Thereby, 2nd Embodiment can confirm the soundness of ADC20 easily.

  If the comparison and collation operation in the control units 40a and 40b is executed together with the bit monitoring by the bit monitor 32, the second embodiment can also obtain the effects of the first embodiment.

(Third embodiment)
FIG. 9 is a conceptual diagram showing an example of the operation of the electric vehicle control device according to the third embodiment.

  For example, since the transponder type ATS uses an FSK (Frequency Shift Keying) method, the frequency bandwidth of the control signal may be limited by a band pass filter. In this case, it is difficult to set the frequency of the analog test signal outside the frequency band of the analog reception signal.

  Therefore, in the third embodiment, the frequency of the analog test signal is set within the frequency band of the analog reception signal, and the signal content (telegram) is distinguished. For example, the telegram of the analog test signal is a telegram that cannot be used (not meaningful) in the analog reception signal, and is always different from the telegram of the analog reception signal. More specifically, an enumeration of the same characters can be considered as a telegram of an analog test signal. The configuration of the control device of the third embodiment may be the same as the configuration of any of the control devices of the first or second embodiment.

  For example, during a period when the analog reception signal is not received, the test signal generation unit 50 intermittently outputs the analog test signal at a constant period. As in the first or second embodiment, the control units 40a and 40b can confirm the soundness of the analog signal processing system based on the digital test signal corresponding to the analog test signal.

On the other hand, if the analog test signal is added to the analog reception signal during the period in which the analog reception signal is being received, the telegram of the analog reception signal may not be demodulated. However, normally, when an analog reception signal is transmitted, four telegrams having the same contents are transmitted continuously. The control units 40a and 40b adopt a message when two of the four consecutive messages can be accurately demodulated. This _is referred to as the 4 _{C 2} test.

Therefore, by using the ₄ C ₂ test, if one telegram analog test signals different from the analog reception signal is received, the test signal generating unit 50 immediately stops the generation of the analog test signal. As a result, the control units 40a and 40b can accurately demodulate at least two of the four consecutive messages. If the analog test signal overlaps with the first telegram of the analog reception signal, the first telegram may not be demodulated, but the subsequent second to fourth telegrams can be demodulated. If the analog test signal does not overlap the first telegram of the analog reception signal, the test signal generator 50 immediately stops generating the analog test signal after receiving the first telegram. In this case, all the first to fourth telegrams can be demodulated.

  As described above, in the third embodiment, although the frequency of the analog test signal overlaps the frequency band of the analog reception signal, the analog test signal and the analog reception signal are distinguished in the data content (telegram). Further, when an analog reception signal is received, the generation of the analog test signal is immediately stopped to allow demodulation of the analog reception signal. Thus, according to the third embodiment, the control units 40a and 40b can demodulate and identify both the analog reception signal and the analog test signal. Thereby, the soundness of an analog signal processing system can be confirmed.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Control apparatus, 10 ... Analog signal processing part, 20 ... ADC, 30a, 30b ... Digital signal processing part, 40a, 40b ... Control part, 50 ... Test signal generation part 51 ... Digital test signal generator 52 ... DAC 53 ... Analog test signal output unit 80 ... Adder

Claims (10)

An analog signal processing unit for processing an analog received signal received via an antenna;
An analog-digital converter that converts an analog signal from the analog signal processor into a digital signal;
A digital signal processing unit for processing the digital signal;
A control unit for controlling the electric vehicle based on the digital signal from the digital signal processing unit;
A test signal generator that provides the analog signal processing unit with an analog test signal that differs in frequency or signal content from the analog received signal ,
The electric vehicle control device , wherein a peak frequency of the analog test signal is outside a frequency band of the analog reception signal .   An analog signal processing unit for processing an analog received signal received via an antenna;
  An analog-digital converter that converts an analog signal from the analog signal processor into a digital signal;
  A digital signal processing unit for processing the digital signal;
  A control unit for controlling the electric vehicle based on the digital signal from the digital signal processing unit;
  A test signal generator that provides the analog signal processing unit with an analog test signal that differs in frequency or signal content from the analog received signal,
  The peak frequency of the analog test signal is one or both of a first frequency exceeding the maximum value of the frequency band of the analog reception signal and a second frequency falling below the minimum value of the frequency band of the analog reception signal. Electric car control device.   An analog signal processing unit for processing an analog received signal received via an antenna;
  An analog-digital converter that converts an analog signal from the analog signal processor into a digital signal;
  A digital signal processing unit for processing the digital signal;
  A control unit for controlling the electric vehicle based on the digital signal from the digital signal processing unit;
  A test signal generator that provides the analog signal processing unit with an analog test signal that differs in frequency or signal content from the analog received signal,
  The electric vehicle control device, wherein the signal strength of the analog test signal includes a first signal strength near the lower limit of the standard of the analog reception signal and a second signal strength near the upper limit of the standard of the analog reception signal.   An analog signal processing unit for processing an analog received signal received via an antenna;
  An analog-digital converter that converts an analog signal from the analog signal processor into a digital signal;
  A digital signal processing unit for processing the digital signal;
  A control unit for controlling the electric vehicle based on the digital signal from the digital signal processing unit;
  A test signal generator that provides the analog signal processing unit with an analog test signal that differs in frequency or signal content from the analog received signal,
  The test signal generator sets the frequency of the analog test signal different from the analog reception signal in the signal content within the frequency band of the analog reception signal,
  The electric vehicle control device, wherein when the analog reception signal is detected to be input according to the signal content, the test signal generation unit stops generating the analog test signal. The storage device further stores a normal digital test signal obtained from the digital signal processing unit by inputting an analog test signal when the analog signal processing unit and the analog / digital conversion unit are normal. The electric vehicle control device according to any one of claims 1 to 4 . The control unit compares the digital test signal output from the digital signal processing unit with the input of the analog test signal and the normal digital test signal, and according to the comparison result, the analog signal processing unit and the analog The electric vehicle control device according to claim 5 , wherein an abnormality of the digital conversion unit is detected. An adder provided between the test signal generator and the input of the analog signal processor;
The electric vehicle control device according to claim 1, wherein the adding unit adds the analog test signal to the analog reception signal. The peak frequency of the analog test signal is in the vicinity of the frequency band of the analog reception signal,
The electric vehicle control device according to claim 1 , wherein an intensity of the analog test signal within a frequency band of the analog reception signal is equal to or less than a noise level of the analog reception signal. The test signal generator provides the analog test signal the analog test signal the peak frequency is the first frequency and the peak frequency is the second frequency alternately to the analog signal processing unit, according to claim 2. The electric vehicle control device according to 2. The digital signal processing unit outputs an error signal to the control unit when the digital signal does not change over a predetermined period,
The electric vehicle according to any one of claims 1 to 9, wherein the control unit determines that the analog signal processing unit and the analog-digital conversion unit are abnormal when receiving the error signal. Control device.

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