JP6563835B2 - Light receiving element - Google Patents

Description

  The present invention relates to a light receiving element using an avalanche photodiode utilizing an avalanche phenomenon.

  Avalanche photodiodes (APDs), one of the photodiodes, generate secondary electrons and holes by colliding with lattice position atoms by accelerating the carriers generated in the semiconductor absorption layer with a high electric field. This is a photodiode using avalanche multiplication in which electrons and holes are accelerated by an electric field and repeatedly collide. In general photodiodes, the efficiency of converting light into electricity is limited to 100%, whereas in APDs, the element itself has a multiplication function, so that it is possible to increase the efficiency greatly exceeding 100%. .

  In high-speed and high-sensitivity APDs applied to optical communications, InGaAs is used as an absorption layer in order to efficiently convert optical signals in the communication wavelength band of 1.55 μm band and 1.3 μm band into electrical signals. However, in a high electric field state that causes avalanche multiplication, the leakage current in the absorption layer composed of InGaAs increases, so in the operation state while using InP or InAlAs having a larger band gap as a multiplication layer, A “Low-high” electric field structure is generally used in which the electric field strength of InGaAs constituting the absorption layer is low and the electric field strength of the multiplication layer is high. For this reason, in a high-speed, high-sensitivity APD for optical communication, a SAM (Separated Absorption) that separates the absorption layer and the multiplication layer by providing a layer for controlling the electric field strength (electric field control layer) around the multiplication layer. and Multiplication) structure is used (see Non-Patent Document 1).

N. Susa et al., "Characteristics in InGaAsAnP Avalanche Photodiodes with Separated Absorption and Multiplication Regions", IEEE Journal of Quantum Electronics, vol.QE-17, no.2, pp.243-250, 1981. T. Shimatsu and M. Uomoto, "Atomic diffusion bonding of wafers with thin nanocrystalline metal films", Journal of Vacuum Science & Technology B, vol.28, no.4, pp.706-714, 2010. C. R. Crowell and S. M. Sze, "BALLISTIC MEAN FREE PATH MEASUREMENTS OF HOT ELECTRONS IN Au FILMS", Physical Review Letters, vol.15, no.16, pp.659-661, 1965.

  Incidentally, when high reproducibility is required for the operating voltage (current-voltage characteristic) of the APD, high controllability is required for the impurity concentration of the electric field control layer. This is because the APD is designed so that the electric field control layer is first depleted and then the electric field strength of the absorption layer increases with the application of voltage. The deviation from the design value of the impurity concentration of the electric field control layer directly affects the on-voltage at which photocurrent starts to occur and the breakdown voltage. For example, within a range generally used as the film thickness and concentration of the electric field control layer, a 20% impurity concentration shift corresponds to a change in on-voltage and breakdown voltage of 2 V or more.

  As described above, in the SAM structure in which higher-speed and high-sensitivity operation can be obtained with the APD, in order to ensure the reproducibility of the operating voltage with an accuracy within 2 V, the impurity concentration of the electric field control layer is as high as ± 10% or less. Controllability is required. For this reason, the SAM structure realizing high-speed and high-sensitivity operation has a problem that it is not easy to manufacture.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to make it easier to manufacture an avalanche photodiode capable of realizing high-speed and high-sensitivity operation.

  A light receiving element according to the present invention is formed between an absorption layer made of a semiconductor formed on a substrate, a multiplication layer made of a semiconductor formed on the substrate, and the absorption layer and the multiplication layer. A voltage control layer made of a semiconductor or metal, a first contact layer made of a first conductivity type semiconductor formed on a side of the absorption layer opposite to the formation side of the multiplication layer, and a formation side of the absorption layer of the multiplication layer A second contact layer made of a second conductivity type semiconductor formed on the opposite side of the first contact layer, a first electrode electrically connected to the first contact layer, and a second electrode electrically connected to the second contact layer And a third electrode electrically connected to the voltage control layer.

  In the light receiving element, the voltage control layer may be made of a semiconductor having a conductivity type.

In the light receiving element, the voltage control layer, that is formed in a smaller area than the multiplication layer disposed absorption layer is disposed on the side of the substrate, or on the side of the substrate.

  As described above, according to the present invention, since the voltage control layer is provided between the absorption layer and the multiplication layer, an avalanche photodiode capable of realizing high-speed and high-sensitivity operation can be more easily manufactured. An excellent effect is obtained.

FIG. 1 is a cross-sectional view showing the configuration of the light receiving element according to Embodiment 1 of the present invention. FIG. 2 is a band diagram showing a change in band gap energy in the stacking direction of each layer of the light receiving element according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing the configuration of the light receiving element according to the second embodiment of the present invention. FIG. 4 is a cross-sectional view showing the configuration of the light receiving element according to Embodiment 3 of the present invention. FIG. 5 is a cross-sectional view showing the configuration of the light receiving element according to Embodiment 4 of the present invention. FIG. 6 is a cross-sectional view showing the configuration of the light receiving element in the fifth embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing the configuration of the light receiving element according to Embodiment 1 of the present invention. This light receiving element includes an absorption layer 104 made of a semiconductor formed on the substrate 101, a multiplication layer 106 made of a semiconductor formed on the substrate 101, and between the absorption layer 104 and the multiplication layer 106. And a voltage control layer 105 made of a semiconductor or metal.

  In addition, the light receiving element includes a first contact layer 102 made of a first conductivity type semiconductor formed on a side of the absorption layer 104 opposite to the side where the multiplication layer 106 is formed, and an absorption layer 104 of the multiplication layer 106. And a second contact layer 107 made of a second conductivity type semiconductor formed on the opposite side to the formation side. In addition, a first electrode 121 electrically connected to the first contact layer 102 and a second electrode 122 electrically connected to the second contact layer 107 are provided. In addition, a third electrode 123 that is electrically connected to the voltage control layer 105 is provided.

  In the first embodiment, the first contact layer 102, the etch stop layer 103, the absorption layer 104, the voltage control layer 105, the multiplication layer 106, and the second contact layer 107 are laminated on the substrate 101 in this order. Yes. Here, a first mesa is formed by the etch stop layer 103, the absorption layer 104, and the voltage control layer 105, and a second mesa is formed by the multiplication layer 106 and the second contact layer 107.

  The second mesa has a smaller area in plan view than the first mesa and is disposed inside the first mesa. Therefore, the shape of the side surface is a staircase shape. In this shape, the first electrode 121 is formed in contact with the upper surface of the first contact layer 102 around the first mesa. A third electrode 123 is formed on the upper surface of the first mesa (voltage control layer 105) around the second mesa. The second electrode 122 is formed in contact with the upper surface of the second contact layer 107. In Embodiment 1, the voltage control layer 105 is formed in the same area as the absorption layer 104 disposed on the substrate 101 side.

  In the first embodiment, the first contact layer 102 is composed of a p-type semiconductor, and the second contact layer 107 is composed of an n-type semiconductor. Therefore, in the first embodiment, the first conductivity type is p-type and the second conductivity type is n-type.

For example, on a substrate 101 made of InP, a p ⁺ -InGaAsP layer, an InP layer, an i-InGaAs layer into which p-type impurities are introduced at a higher concentration, and a p at which p-type impurities are introduced at a relatively low concentration. ^- a layer of -InP, a layer of i-InAlAs, more layers of high-concentration n ⁺ -InGaAsP doped with n type impurities, the well-known MOCVD epitaxial growth. The p ⁺ -InGaAsP layer becomes the first contact layer 102. Next, the second electrode 122 made of a metal such as Ti / Au is formed on the n ⁺ -InGaAsP layer by vapor deposition and lift-off.

Next, the i-InAlAs and n ⁺ -InGaAsP layers are patterned by a known lithography technique and wet etching technique to form a second mesa composed of the multiplication layer 106 and the second contact layer 107. Below the i-InAlAs layer serving as the multiplication layer 106 is a p ⁻ -InP layer, and there is selectivity regarding a sulfuric acid-based etchant between them. Therefore, in the wet etching for forming the multiplication layer 106 in the second mesa formation, the wet etching is stopped at the p ⁻ -InP layer by using the sulfuric acid-based etchant.

Next, the first mesa composed of the etch stop layer 103, the absorption layer 104, and the voltage control layer 105 is formed by patterning a layer of InP, i-InGaAs, and p ⁻ -InP by a known lithography technique and wet etching technique. Form. In the first mesa formation, the pattern shape of the etching mask formed by the lithography technique may be larger than the pattern shape of the etching mask in the second mesa formation. Here, between InP and InGaAs, there is selectivity with respect to a hydrochloric acid-based etchant. Therefore, first, ^p with hydrochloric acid based etchant - by etching a layer of -InP forming a voltage control layer 105, then form the absorbent layer 104 by etching a layer of i-InGaAs with sulfuric acid etchant, the following In addition, the etch stop layer 103 may be formed by etching the InP layer with a hydrochloric acid-based etchant. In each etching, the lower layer becomes an etching stop layer.

  After forming each layer as described above, the first electrode 121 and the third electrode 123 made of metal such as Pt / Ti / Au are formed by vapor deposition and lift-off. Each mesa may be formed by dry etching instead of wet etching. In this case, an etch stop layer is not necessary.

  Next, the operation principle of the light receiving element in the first embodiment of the present invention will be described.

  The SAM-structured APD that separates the absorption layer and the multiplication layer described above can apply different electric fields to the absorption layer and the multiplication layer. However, the electric field of the absorption layer needs to be less than the avalanche breakdown field strength of the semiconductor constituting the absorption layer or less than the zener breakdown field strength, and at the same time, the electric field of the multiplication layer constitutes the multiplication layer. The avalanche breakdown field strength of the semiconductor must be equal to or higher.

In the APD in the embodiment, as shown in FIG. 1, the voltage control layer 105 is grounded, the voltage V ₁ is applied between the first contact layer 102 and the voltage control layer 105, and the voltage control layer 105 and the second contact are applied. By applying the voltage V ₂ between the layers 107, it is possible to apply different voltages of V ₁ to the absorption layer 104 and V ₂ + V _BI to the multiplication layer 106. V _BI represents a built-in potential between the voltage control layer 105 and the second contact layer 107.

  According to the present invention having the above-described configuration, since the third electrode 123 is provided, the voltage application terminals to the multiplication layer 106 and the absorption layer 104 become independent. Each can produce an arbitrary electric field strength. Thus, the electric field control layer requiring high impurity concentration controllability, which is a problem in the conventional SAM structure, is not required in the present invention.

  In order to obtain the effect of the present invention more remarkably, it is desirable that the lateral width of the element determined by the multiplication layer 106 and the second contact layer 107 is 5 μm or less. The same effect can be obtained even when the voltage control layer 105 is provided in a light receiving element structure including an electric field control layer such as a conventional SAM structure. In this case, a large allowable range for the impurity concentration variation of the electric field control layer can be secured.

  By the way, as shown in FIG. 2, the operation principle of the light receiving element described above is that an electron (black circle in FIG. 2) photoexcited by the absorption layer 104 by the signal light is avalanche amplified by the multiplication layer 106, and becomes a weak optical signal. On the other hand, a large electric signal can be obtained. This is the same as the conventional APD, and the voltage applied to the voltage control layer 105 is constant regardless of the ON / OFF state of the signal, and the carrier travel path is extended by the extension of the depletion region of the voltage control layer 105. It is not a constriction.

Further, in the conventional APD, when the light intensity is increased, the electric field strength in the multiplication layer 106 is effectively reduced by the space charge effect, and as a result, the multiplication factor is lowered. For this reason, the linearity of the operating voltage with respect to the light intensity was not good. On the other hand, according to the present invention, it is possible to control the electric field strength in the multiplication layer 106 by applying the voltage V ₂ from the outside, so that the linearity of the APD operating voltage with respect to the light intensity is improved. Can do.

  As described above, according to Embodiment 1 of the present invention, high reproducibility can be obtained in the operating voltage while maintaining high speed and high sensitivity in the APD.

[Embodiment 2]
Next, Embodiment 2 of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view showing the configuration of the light receiving element according to the second embodiment of the present invention. This light receiving element includes an absorption layer 205 made of a semiconductor formed on the substrate 201, a multiplication layer 203 made of a semiconductor formed on the substrate 201, and between the absorption layer 205 and the multiplication layer 203. And a voltage control layer 204 made of a semiconductor or metal.

  In addition, the light receiving element includes a first contact layer 206 made of a first conductivity type semiconductor formed on the side of the absorption layer 205 opposite to the side on which the multiplication layer 203 is formed, and an absorption layer 205 of the multiplication layer 203. And a second contact layer 202 made of a second conductivity type semiconductor formed on the side opposite to the formation side. In addition, a first electrode 221 electrically connected to the first contact layer 206 and a second electrode 222 electrically connected to the second contact layer 202 are provided. In addition, a third electrode 223 that is electrically connected to the voltage control layer 204 is provided.

  In the second embodiment, the second contact layer 202, the multiplication layer 203, the voltage control layer 204, the absorption layer 205, and the first contact layer 206 are laminated on the substrate 201 in this order. Here, the multiplication layer 203 and the voltage control layer 204 form a first mesa, and the absorption layer 205 and the first contact layer 206 form a second mesa.

  The second mesa has a smaller area in plan view than the first mesa and is disposed inside the first mesa. Therefore, the shape of the side surface is a staircase shape. In this shape, the second electrode 222 is formed in contact with the upper surface of the second contact layer 202 around the first mesa. A third electrode 223 is formed in contact with the upper surface of the first mesa (voltage control layer 204) around the second mesa. The first electrode 221 is formed in contact with the upper surface of the first contact layer 206. In the second embodiment, the voltage control layer 204 is formed in the same area as the multiplication layer 203 disposed on the substrate 201 side.

  In the second embodiment, the first contact layer 206 is composed of an n-type semiconductor, and the second contact layer 202 is composed of a p-type semiconductor. Therefore, in the second embodiment, the first conductivity type is n-type, and the second conductivity type is p-type.

For example, on a substrate 201 made of InP, a p ⁺ -InGaAsP layer in which p-type impurities are introduced at a higher concentration, an InP layer, an n ⁻ -InP layer in which n-type impurities are introduced at a relatively low concentration, An i-InGaAs layer and an n ⁺ -InGaAsP layer doped with n-type impurities at a higher concentration are epitaxially grown by a well-known metal organic chemical vapor deposition method. The p ⁺ -InGaAsP layer becomes the second contact layer 202. Next, a first electrode 221 made of a metal such as Ti / Au is formed on the n ⁺ -InGaAsP layer by vapor deposition and lift-off.

Next, the i-InGaAs layer and the n ⁺ -InGaAsP layer are patterned by a known lithography technique and wet etching technique to form a second mesa composed of the absorption layer 205 and the first contact layer 206. Next, the first mesa including the multiplication layer 203 and the voltage control layer 204 is formed by patterning the InP layer and the n ⁻ -InP layer by a known lithography technique and wet etching technique.

  After forming each layer as described above, the second electrode 222 and the third electrode 223 made of metal such as Pt / Ti / Au are formed by vapor deposition and lift-off. Each mesa may be formed by dry etching instead of wet etching.

  The principle of operation of the light receiving element according to the second embodiment is that a hole optically excited in the absorption layer 205 by signal light is avalanche amplified in the multiplication layer 203, and a large electric signal can be obtained with respect to a weak optical signal. It is.

In the second embodiment, as in the first embodiment, the voltage control layer 204 is grounded, the voltage V ₁ is applied between the first contact layer 206 and the voltage control layer 204, and the voltage control layer 204 and the second contact are applied. By applying the voltage V ₂ between the layers 202, it is possible to apply different voltages of V ₁ to the absorption layer 205 and V ₂ + V _BI to the multiplication layer 203. Thereby, the avalanche breakdown can be selectively generated only in the multiplication layer 203. For this reason, the configuration of the second embodiment does not require an electric field control layer that requires high impurity concentration controllability, which was a problem with the conventional SAM structure. Further, even when the light receiving element structure including the electric field control layer like the conventional SAM structure is provided with the voltage control layer, the same effect can be obtained. In this case, a large allowable range for the impurity concentration variation of the electric field control layer can be taken.

Similar to the first embodiment, the operation principle of the light receiving element of the second embodiment is that the holes photoexcited in the absorption layer 205 by the signal light are avalanche amplified in the multiplication layer 203, and a large electric signal is generated for a weak optical signal. A signal can be obtained. The voltage applied to the voltage control layer 204 is constant regardless of the ON / OFF state of the signal, and does not narrow the carrier travel path due to the extension of the depleted region of the voltage control layer 204. In addition, also in the second embodiment, since the electric field strength in the multiplication layer 203 can be controlled by applying the voltage V ₂ from the outside, the linearity of the operating voltage of the APD with respect to the light intensity is improved. be able to.

  As described above, also in Embodiment 2 of the present invention, high reproducibility can be obtained in the operating voltage while maintaining high speed and high sensitivity in the APD.

[Embodiment 3]
Next, Embodiment 3 of the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional view showing the configuration of the light receiving element according to Embodiment 3 of the present invention. This light receiving element includes an absorption layer 304 made of a semiconductor formed on the substrate 301, a multiplication layer 306 made of a semiconductor formed on the substrate 301, and between the absorption layer 304 and the multiplication layer 306. And a voltage control layer 305 made of a semiconductor or metal.

  The light receiving element includes a first contact layer 302 made of a first conductivity type semiconductor formed on the side of the absorption layer 304 opposite to the side where the multiplication layer 306 is formed, and an absorption layer 304 of the multiplication layer 306. And a second contact layer 307 made of a second conductivity type semiconductor formed on the side opposite to the formation side. In addition, a first electrode 321 electrically connected to the first contact layer 302 and a second electrode 322 electrically connected to the second contact layer 307 are provided. In addition, a third electrode 323 that is electrically connected to the voltage control layer 305 is provided.

  In the third embodiment, a first contact layer 302, an etch stop layer 303, an absorption layer 304, a voltage control layer 305, a multiplication layer 306, and a second contact layer 307 are laminated on the substrate 301 in this order. Yes. Here, a first mesa is formed by the etch stop layer 303, the absorption layer 304, and the voltage control layer 305, and a second mesa is formed by the multiplication layer 306 and the second contact layer 307.

  The second mesa has a smaller area in plan view than the first mesa and is disposed inside the first mesa. Therefore, the shape of the side surface is a staircase shape. In this shape, the first electrode 321 is formed in contact with the upper surface of the first contact layer 302 around the first mesa. A third electrode 323 is formed in contact with the upper surface of the first mesa (voltage control layer 305) around the second mesa. The second electrode 322 is formed in contact with the upper surface of the second contact layer 307. In Embodiment 3, the voltage control layer 305 is formed in the same area as the absorption layer 304 disposed on the substrate 301 side.

  In the third embodiment, the first contact layer 302 is made of a p-type semiconductor, and the second contact layer 307 is made of an n-type semiconductor. Therefore, in the third embodiment, the first conductivity type is p-type and the second conductivity type is n-type.

For example, a p ⁺ -InGaAsP layer, an InP layer, and an i-InGaAs layer into which p-type impurities are introduced at a higher concentration are formed on a substrate 301 made of InP by a well-known metal organic chemical vapor deposition method. Epitaxial growth. In addition, a first metal layer made of Au is formed on the i-InGaAs layer by electron beam evaporation or sputtering. The first metal layer may be about several nm thick.

  On the other hand, an n-Si layer and an i-Si layer into which an n-type impurity is introduced are grown on another substrate made of single crystal silicon (not shown) by a well-known molecular beam epitaxy method. In addition, a second metal layer made of Au is formed on the i-Si layer by electron beam evaporation or sputtering. The second metal layer may also be about several nm thick.

Next, the substrate 301 and another substrate are bonded together by atomic diffusion bonding (metal-metal bonding) between the first metal layer and the second metal layer (see Non-Patent Document 2). After bonding, the other substrate is removed. For example, the other substrate may be removed by well-known polishing, etching, or the like. As a result, a p ⁺ -InGaAsP layer, an InP layer, an i-InGaAs layer, an Au layer, an i-Si layer, and an n-Si layer are stacked on the substrate 301 in this order. Is obtained. The p ⁺ -InGaAsP layer becomes the first contact layer 302.

  Next, a second electrode 322 made of a metal such as Ti / Au is formed on the n-Si layer by vapor deposition and lift-off.

  Next, the second mesa including the multiplication layer 306 and the second contact layer 307 is formed by patterning the i-Si layer and the n-Si layer by a known lithography technique and etching technique.

  Next, a layer made of InP, i-InGaAs, and Au is patterned by a known lithography technique and a predetermined etching technique to form a first mesa made up of an etch stop layer 303, an absorption layer 304, and a voltage control layer 305. To do. In the third embodiment, the voltage control layer 305 is made of Au. Each of the layers made of Au formed by bonding the first metal layer and the second metal layer each having a thickness of several nm has a thickness of about 4 to 6 nm and less than 10 nm. Therefore, the voltage control layer 305 composed of a layer made of Au has a thickness of about 4 to 6 nm and less than 10 nm.

  After forming each layer as described above, the first electrode 321 and the third electrode 323 made of metal such as Pt / Ti / Au are formed by vapor deposition and lift-off.

  Here, when voltage is applied, the absorption layer 304 is depleted and has an electric field strength of several tens to several hundreds kV / cm. For this reason, photocarriers (electrons) generated by light absorption have high kinetic energy while traveling through the absorption layer 304, and are in a so-called hot carrier state. Furthermore, the mean free path of electrons in Au used for the voltage control layer 305 is said to be about several tens of nm (see Non-Patent Document 3). Therefore, the above-described photocarrier is injected into the multiplication layer 306 with almost no influence of Au in the voltage control layer 305 having a thickness of less than 10 nm.

  Also in the third embodiment, since different voltages can be applied to the absorption layer 304 and the multiplication layer 306 as in the first and second embodiments, the avalanche breakdown is selectively generated only in the multiplication layer 306. be able to. For this reason, the electric field control layer requiring high impurity concentration controllability, which is a problem in the conventional SAM structure, is not required in the configuration of the present embodiment.

  Further, even when the light receiving element structure including the electric field control layer such as the conventional SAM structure is provided with the voltage control layer, the same effect can be obtained. In this case, a large allowable range for the impurity concentration variation of the electric field control layer can be taken.

Similar to the first embodiment, the operation principle of the light receiving element of the third embodiment is that an electron photoexcited by the absorption layer 304 by the signal light is avalanche amplified by the multiplication layer 306, and a large electric signal is generated for a weak optical signal. A signal can be obtained. The voltage applied to the voltage control layer 305 is constant regardless of ON / OFF of the signal, and does not narrow the carrier travel path due to the extension of the depletion region of the voltage control layer 305. In addition, in the third embodiment, since the electric field strength in the multiplication layer 306 can be controlled by applying the voltage V ₁ from the outside, the linearity of the operating voltage of the APD with respect to the light intensity is improved. be able to.

  As described above, also in Embodiment 3 of the present invention, high reproducibility can be obtained in the operating voltage while maintaining high speed and high sensitivity in the APD.

[Embodiment 4]
Next, Embodiment 4 of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view showing the configuration of the light receiving element according to Embodiment 4 of the present invention. This light receiving element includes an absorption layer 404 made of a semiconductor formed on the substrate 401, a multiplication layer 407 made of a semiconductor formed on the substrate 401, and between the absorption layer 404 and the multiplication layer 407. And a voltage control layer 406 made of a semiconductor or metal.

  Further, the light receiving element includes a first contact layer 402 made of a first conductivity type semiconductor formed on a side of the absorption layer 404 opposite to the side where the multiplication layer 407 is formed, and an absorption layer 404 of the multiplication layer 407. And a second contact layer 408 made of a second conductivity type semiconductor formed on the side opposite to the formation side. In addition, a first electrode 421 that is electrically connected to the first contact layer 402 and a second electrode 422 that is electrically connected to the second contact layer 408 are provided. In addition, a third electrode 423 that is electrically connected to the voltage control layer 406 is provided.

  In the fourth embodiment, the first contact layer 402, the first etch stop layer 403, the absorption layer 404, the second etch stop layer 405, the voltage control layer 406, the multiplication layer 407, and the second contact layer are formed on the substrate 401. 408 are stacked in this order. Here, the first mesa is formed by the first etch stop layer 403 and the absorption layer 404, the second mesa is formed by the second etch stop layer 405 and the voltage control layer 406, and the third mesa is formed by the multiplication layer 407. A fourth mesa is formed by the second contact layer 408.

  The fourth mesa has a smaller area in plan view than the third mesa and is disposed inside the third mesa. The third mesa has a smaller area in plan view than the second mesa and is disposed inside the second mesa. The second mesa has a smaller area in plan view than the first mesa and is disposed inside the first mesa. Therefore, the shape of the side surface is a staircase shape. In this shape, the first electrode 421 is formed in contact with the upper surface of the first contact layer 402 around the first mesa. A third electrode 423 is formed in contact with the upper surface of the second mesa (voltage control layer 406) around the third mesa. The second electrode 422 is formed in contact with the upper surface of the second contact layer 408 constituting the fourth mesa.

  As described above, the fourth embodiment is characterized in that the voltage control layer 406 is formed in an area smaller than the absorption layer 404 disposed on the substrate 401 side. In the fourth embodiment, the first contact layer 402 is made of a p-type semiconductor, and the second contact layer 408 is made of an n-type semiconductor. Therefore, in the fourth embodiment, the first conductivity type is p-type and the second conductivity type is n-type.

For example, on a substrate 401 made of InP, a p ⁺ -InGaAsP layer, an InP layer, an i-InGaAs layer, an InP layer into which a p-type impurity is introduced at a higher concentration, and a p-type impurity at a relatively low concentration. ^p was introduced - -InGaAsP layer, i-InP layer, the more layers of the high-concentration n ⁺ -InGaAsP doped with n type impurities, the well-known MOCVD epitaxial growth. The p ⁺ -InGaAsP layer becomes the first contact layer 402. Next, a second electrode 422 made of a metal such as Ti / Au is formed on the n ⁺ -InGaAsP layer by vapor deposition and lift-off.

Next, the n ⁺ -InGaAsP layer is patterned by a known lithography technique and wet etching technique to form a fourth mesa made of the second contact layer 408. Next, the i-InP layer is patterned by a known lithography technique and wet etching technique to form a third mesa composed of the multiplication layer 407.

Next, a second mesa composed of the second etch stop layer 405 and the voltage control layer 406 is formed by patterning the InP, p ⁻ -InGaAsP layer by a known lithography technique and wet etching technique. Next, the first mesa including the first etch stop layer 403 and the absorption layer 404 is formed by patterning the InP layer and the i-InGaAs layer by a known lithography technique and wet etching technique.

  By using the first etch stop layer 403 and the second etch stop layer 405 and using the hydrochloric acid-based etchant and the sulfuric acid-based etchant separately in the same manner as in the first embodiment, by using the selectivity for the etchant between the respective layers, In the formation of each mesa by wet etching, the etching can be automatically stopped in the lower layer of each mesa. In each mesa formation, the pattern shape of the etching mask formed by the lithography technique may be a larger area than the pattern shape of the etching mask in the mesa formation disposed on the mesa.

  After forming each layer as described above, the first electrode 421 and the third electrode 423 made of a metal such as Pt / Ti / Au are formed by vapor deposition and lift-off. Each mesa may be formed by dry etching instead of wet etching. In this case, an etch stop layer is not necessary.

  The absorption layer 404 and the multiplication layer 407 cause an increase in surface dark current by applying an electric field to the side surface of the mesa. On the other hand, in the fourth embodiment, the mesa diameter of the voltage control layer 406 is smaller than that of the absorption layer 404, and the mesa diameter of the second contact layer 408 is smaller than that of the multiplication layer 407. The voltage applied to is reduced, and the surface dark current is suppressed.

  The operation principle of the light receiving element of the fourth embodiment is that the electrons photoexcited in the absorption layer 404 by the signal light are avalanche amplified in the multiplication layer 407, and a large electric signal can be obtained with respect to the weak optical signal. It is.

  In the fourth embodiment, as in the first embodiment, different voltages can be applied to the absorption layer 404 and the multiplication layer 407. Therefore, the avalanche breakdown can be selectively generated only in the multiplication layer 407. it can. For this reason, the electric field control layer requiring high impurity concentration controllability, which is a problem in the conventional SAM structure, is not required in the configuration of the present embodiment.

  Further, even if the voltage control layer 406 is provided in the light receiving element structure including the electric field control layer like the conventional SAM structure, the same effect can be obtained. In this case, a large allowable range for the impurity concentration variation of the electric field control layer can be secured.

As in the first embodiment, during avalanche amplification, the voltage applied to the voltage control layer 406 is constant regardless of the ON / OFF state of the signal, and carriers are expanded by extension of the depletion region of the voltage control layer 406. It does not narrow the travel route. In addition, also in the fourth embodiment, it is possible to control the electric field strength in the multiplication layer 407 by applying the voltage V ₁ from the outside, so that the linearity of the operating voltage of the APD with respect to the light intensity is improved. be able to.

  As described above, according to the fourth embodiment of the present invention, high reproducibility of the operating voltage can be obtained while maintaining high speed and high sensitivity of the APD.

[Embodiment 5]
Next, Embodiment 5 of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view showing the configuration of the light receiving element in the fifth embodiment of the present invention. This light receiving element includes an absorption layer 504 made of a semiconductor formed on a substrate 501, a multiplication layer 507 made of a semiconductor formed on the substrate 501, and between the absorption layer 504 and the multiplication layer 507. And a first voltage control layer 505 made of a formed semiconductor.

  The light receiving element includes a first contact layer 502 made of a first conductivity type semiconductor formed on the opposite side of the absorption layer 504 from the side where the multiplication layer 507 is formed, and an absorption layer 504 of the multiplication layer 507. And a second contact layer 512 made of a second conductivity type semiconductor formed on the opposite side to the formation side. In addition, a first electrode 521 that is electrically connected to the first contact layer 502 and a second electrode 522 that is electrically connected to the second contact layer 512 are provided. In addition, a third electrode 523 a electrically connected to the first voltage control layer 505 is provided.

  In addition to the above-described configuration, in the fifth embodiment, the second voltage control layer 509 and the traveling layer 511 are provided on the multiplication layer 507 when viewed from the substrate 501 side. The second voltage control layer 509 and the traveling layer 511 are provided between the multiplication layer 507 and the second contact layer 512. In addition, a fourth electrode 523 b that is electrically connected to the second voltage control layer 509 is provided.

  In the fifth embodiment, the first contact layer 502, the first etch stop layer 503, the absorption layer 504, the first voltage control layer 505, the second etch stop layer 506, the multiplication layer 507, the third layer are formed on the substrate 501. The etch stop layer 508, the second voltage control layer 509, the fourth etch stop layer 510, the running layer 511, and the second contact layer 512 are laminated in this order.

  The first mesa is formed by the first etch stop layer 503 and the absorption layer 504, the second mesa is formed by the first voltage control layer 505, and the third mesa is formed by the second etch stop layer 506 and the multiplication layer 507. A fourth mesa is formed by the third etch stop layer 508 and the second voltage control layer 509, a fifth mesa is formed by the fourth etch stop layer 510 and the running layer 511, and a sixth mesa is formed by the second contact layer 512. Is formed.

  The sixth mesa has a smaller area in plan view than the fifth mesa and is disposed inside the fifth mesa. The fifth mesa has a smaller area in plan view than the fourth mesa and is disposed inside the fourth mesa. The fourth mesa has a smaller area in plan view than the third mesa and is disposed inside the third mesa. The third mesa has a smaller area in plan view than the second mesa and is disposed inside the second mesa. The second mesa has a smaller area in plan view than the first mesa and is disposed inside the first mesa. Therefore, the shape of the side surface is a staircase shape.

  In this shape, the first electrode 521 is formed in contact with the upper surface of the first contact layer 502 around the first mesa. A third electrode 523a is formed in contact with the upper surface of the second mesa (first voltage control layer 505) around the third mesa. The fourth electrode 523b is formed in contact with the upper surface of the fourth mesa (second voltage control layer 509) around the fifth mesa. The second electrode 522 is formed in contact with the upper surface of the second contact layer 512 constituting the sixth mesa.

  As described above, the fifth embodiment is characterized in that the traveling layer 511 is provided, and the first voltage control layer 505 and the second voltage control layer 509 are provided. Also in the fifth embodiment, the first voltage control layer 505 is formed in an area smaller than the absorption layer 504 disposed on the substrate 501 side. On the other hand, the second voltage control layer 509 is formed in a smaller area than the multiplication layer 507 disposed on the substrate 501 side. In the fifth embodiment, the first contact layer 502 is composed of a p-type semiconductor, and the second contact layer 512 is composed of an n-type semiconductor. Therefore, in the fifth embodiment, the first conductivity type is p-type and the second conductivity type is n-type.

For example, on a substrate 501 made of InP, a p ⁺ -InGaAsP layer doped with p-type impurities at a high concentration, a p ⁺ -InP layer doped with p-type impurities at a high concentration, an i-InGaAs layer, specifically low concentration of introducing a p-type impurity into the ^p - layer of -InGaAs, a layer of p-InGaAsP introduced with p-type impurity, i-InP layer, a relatively low concentration of n-type impurities are introduced ⁿ - -InGaAsP Layer, n-InP layer, i-InGaAsP layer, i-InP layer, and n ⁺ -InGaAsP layer doped with a high concentration of n-type impurities are epitaxially grown by a well-known metal organic chemical vapor deposition method. To do. The p ⁺ -InGaAsP layer becomes the first contact layer 502.

Next, a sixth mesa composed of the second contact layer 512 is formed by patterning the n ⁺ -InGaAsP layer by a known lithography technique and wet etching technique. Next, the i-InGaAsP layer and the i-InP layer are patterned by a known lithography technique and wet etching technique to form a fifth mesa including the fourth etch stop layer 510 and the traveling layer 511.

  Next, on the upper surface of the second contact layer 512 and the n-InP layer around the fifth mesa, the second electrode 522 made of a metal such as Ti / Au and the fourth electrode are formed by vapor deposition and lift-off. 523b is formed.

Next, by patterning the n ⁻ -InGaAsP layer and the n-InP layer by a known lithography technique and wet etching technique, a fourth mesa including the third etch stop layer 508 and the second voltage control layer 509 is formed. To do. Next, the p-InGaAsP layer and the i-InP layer are patterned by a known lithography technique and wet etching technique to form a third mesa including the second etch stop layer 506 and the multiplication layer 507.

Next, a second mesa including the first voltage control layer 505 is formed by patterning the p ⁻ -InGaAs layer by a known lithography technique and wet etching technique. Next, the p ⁺ -InP layer and the i-InGaAs layer are patterned by a known lithography technique and wet etching technique to form a first mesa including the first etch stop layer 503 and the absorption layer 504.

  Using the first etch stop layer 503, the second etch stop layer 506, the third etch stop layer 508, and the fourth etch stop layer 510, the hydrochloric acid etchant and the sulfuric acid etchant are selectively used as in the first embodiment. By using the selectivity to the etchant between the layers, in the formation of each mesa by wet etching, the etching can be automatically stopped in the lower layer of each mesa.

  For example, wet etching stops at the traveling layer 511 because there is selectivity between the InGaAsP of the second contact layer 512 and the InP of the traveling layer 511 regarding the sulfuric acid-based etchant. In addition, wet etching stops at the second voltage control layer 509 because there is selectivity between the InGaAsP of the fourth etch stop layer 510 and the InP of the second voltage control layer 509 regarding the sulfuric acid-based etchant.

  In addition, wet etching stops at the multiplication layer 507 because there is selectivity with respect to the hydrochloric acid-based etchant between the InGaAsP of the third etch stop layer 508 and the InP of the multiplication layer 507. In addition, wet etching stops at the first voltage control layer 505 because there is selectivity between the InGaAsP of the second etch stop layer 506 and the InP of the first voltage control layer 505 with respect to the sulfuric acid-based etchant.

  In addition, wet etching stops at the absorption layer 504 because there is selectivity between the InP of the first voltage control layer 505 and the InGaAs of the absorption layer 504 with respect to a hydrochloric acid-based etchant. In addition, wet etching stops at the first contact layer 502 because there is selectivity between the InP of the first etch stop layer 503 and the InGaAsP of the first contact layer 502 with respect to the hydrochloric acid-based etchant.

  In each mesa formation, the pattern shape of the etching mask formed by the lithography technique may be a larger area than the pattern shape of the etching mask in the mesa formation disposed on the mesa.

  After forming each layer as described above, the first electrode 521 and the third electrode 523a made of metal such as Pt / Ti / Au are formed by vapor deposition and lift-off. Each mesa may be formed by dry etching instead of wet etching. In this case, an etch stop layer is not necessary.

  Although the element capacity of the light receiving element depends on the depletion layer width and the element diameter, the element capacity can be reduced by depleting the traveling layer 511 formed of a non-doped semiconductor as in the fifth embodiment. it can. Further, the traveling layer 511 is arranged between the multiplication layer 507 and the second contact layer 512, so that traveling carriers can be limited to electrons, leading to higher speed. However, in order to avoid breakdown in the traveling layer 511, it is important that an electric field strength lower than that of the multiplication layer 507 is applied. For this reason, the second voltage control layer 509 is provided between the traveling layer 511 and the multiplication layer 507. This makes it possible to control the electric field strength without using an electric field control layer that requires high doping controllability.

  In the fifth embodiment, the mesa diameter of the first voltage control layer 505 is smaller than that of the absorption layer 504, and the mesa diameter of the second contact layer 512 is smaller than that of the multiplication layer 507. Thereby, the voltage applied to each mesa side surface is reduced, and the surface dark current is suppressed.

  The operating principle of the light receiving element of the fifth embodiment is that the electrons photoexcited in the absorption layer 504 by the signal light are avalanche amplified in the multiplication layer 507, and a large electric signal can be obtained with respect to the weak optical signal. It is.

  In the fifth embodiment, as in the first embodiment, different voltages can be applied to the absorption layer 504 and the multiplication layer 507, so that only an avalanche breakdown can be generated only in the multiplication layer 507. it can. For this reason, the electric field control layer requiring high impurity concentration controllability, which is a problem in the conventional SAM structure, is not required in the configuration of the present embodiment.

  The same effect can be obtained even if the first voltage control layer 505 is provided in a light receiving element structure including an electric field control layer such as a conventional SAM structure. In this case, a large allowable range for the impurity concentration variation of the electric field control layer can be secured.

  As described above, according to Embodiment 5 of the present invention, high reproducibility can be obtained in the operating voltage while maintaining high speed and high sensitivity in the APD.

  As described above, according to the present invention, since the voltage control layer is provided between the absorption layer and the multiplication layer, an avalanche photodiode capable of realizing high-speed and high-sensitivity operation can be more easily manufactured. become able to.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious.

  For example, the case where the multiplication layer is made of InP has been described above as an example. However, the present invention is not limited to this, and the multiplication layer is made of other semiconductor materials such as InAlAs, InAs, HgCdTe, Si, GaN, and SiC. May be. The multiplication layer may be composed of a superlattice structure such as InGaAs / InP.

  In addition, although the structure in which the voltage control layer is bonded by atomic diffusion bonding as an example of a configuration made of metal has been described, a surface activation process or the like may be performed after forming a metal thin film. Further, a structure in which amorphous layers such as a-Si and a-Ge are used as a multiplication layer and an absorption layer, respectively, without using a bonding technique, and these are deposited on a voltage control layer made of metal may be used. . Although the description has been given using the p-type semiconductor as the absorption layer, an n-type semiconductor may be used. Further, gradient doping that lowers the doping concentration from the absorption layer toward the bonding surface may be used. Further, as a manufacturing method, other crystal growth methods such as a molecular beam epitaxy method may be used. A guard ring or the like may be used to prevent edge breakdown.

  Furthermore, in order to realize higher sensitivity of the element, the incident surface is mirror-finished, the coupling loss at the light incident end is reduced by the formation of an antireflection film by a dielectric multilayer film, etc., and the mirror, waveguide structure and Even if a device such as DBR is used to increase the optical path length, it is a general design matter performed for a normal APD or photodiode, and the generality of the present invention is not lost.

  DESCRIPTION OF SYMBOLS 101 ... Substrate, 102 ... First contact layer, 103 ... Etch stop layer, 104 ... Absorption layer, 105 ... Voltage control layer, 106 ... Multiplication layer, 107 ... Second contact layer, 121 ... First electrode, 122 ... First 2 electrodes, 123 ... 3rd electrode.

Claims (2)

An absorption layer made of a semiconductor formed on a substrate;
A multiplication layer made of a semiconductor formed on a substrate;
A voltage control layer made of a semiconductor or metal formed between the absorption layer and the multiplication layer;
A first contact layer made of a semiconductor of a first conductivity type formed on the opposite side of the absorption layer from the side on which the multiplication layer is formed;
A second contact layer made of a semiconductor of a second conductivity type formed on the opposite side of the multiplication layer from the absorption layer;
A first electrode electrically connected to the first contact layer;
A second electrode electrically connected to the second contact layer;
A third electrode electrically connected to the voltage control layer ,
The voltage control layer, a light receiving element characterized that you have formed a smaller area than the multiplication layer, wherein the absorbent layer, or is disposed on a side of the substrate are arranged on the side of the substrate. The light receiving element according to claim 1,
The voltage control layer is composed of a semiconductor having a conductivity type.

Images